Memory device and reading method of memory device

Abstract

A memory device comprises a plurality of strings connected between a bit line and a source line, wherein each of the plurality of strings includes a drain select transistor connected to a corresponding drain select line, memory cells connected to a plurality of word lines, and a source select transistor connected to a corresponding source select line, wherein the memory cell array comprises: a plurality of strings; and a peripheral circuit configured to apply a sub-threshold gate voltage to a source select line connected to a non-selected string while applying a turn-off voltage to a drain select line connected to a non-selected string among the plurality of strings during at least a portion of a read section in which a read pass voltage is applied to non-selected word lines among the plurality of word lines.

Description

Technology Field

[0001] The present invention relates to a memory device. Background Technology

[0002] Semiconductor devices are core components of electronic devices and have various applications in the modern world; for example, they can be utilized in technologies such as computing, communication, artificial intelligence, and memory. Semiconductor devices can be composed of transistors, diodes, integrated circuits (ICs), etc.

[0003] The read performance of a semiconductor memory device plays a critical role in the processing speed and efficiency of a memory system and can also affect the maintenance of data reliability. If a high channel voltage is repeatedly applied to a memory cell during a read operation, the stress applied to the memory cell can degrade data retention characteristics and cause a shortened cell lifespan. Therefore, a technical solution that simultaneously considers read performance improvement and data stability may be required. The problem to be solved

[0004] An embodiment of the present invention provides a memory device and a method for reading the memory device that provide improved read performance. means of solving the problem

[0005] A memory device according to an embodiment of the present invention may include a memory cell array comprising a plurality of strings connected between a bit line and a source line, wherein each of the plurality of strings comprises a drain select transistor connected to a corresponding drain select line, memory cells connected to a plurality of word lines, and a source select transistor connected to a corresponding source select line; and a peripheral circuit configured to apply a sub-threshold gate voltage to a source select line connected to a non-selected string while applying a turn-off voltage to a drain select line connected to a non-selected string among the plurality of strings during at least a portion of a read section in which a read pass voltage is applied to non-selected word lines among the plurality of word lines.

[0006] A memory device according to an embodiment of the present invention may include a memory cell array comprising a plurality of strings connected between a bit line and a source line, wherein each of the plurality of strings comprises a drain select transistor connected to a corresponding drain select line, memory cells connected to a plurality of word lines, and a source select transistor connected to a corresponding source select line; and a peripheral circuit configured to reduce the voltage level of a channel of an unselected string among the plurality of strings to a level higher than the ground voltage during a channel voltage adjustment section in a read operation.

[0007] A method of operation of a memory device according to an embodiment of the present invention may include: an operation of applying a turn-on voltage to a drain selection line connected to a non-selected string among a plurality of strings and a source selection line connected to the non-selected string in a first section; an operation of applying a turn-off voltage to the drain selection line and the source selection line in a second section following the first section; and an operation of applying a sub-threshold gate voltage to the source selection line while applying the turn-off voltage to the drain selection line in at least a portion of a third section following the second section. Effects of the invention

[0008] A memory device and a read method for a memory device according to an embodiment of the present invention can provide improved read performance. Brief explanation of the drawing

[0009] FIG. 1 is a block diagram illustrating a memory device according to an embodiment, FIG. 2 is a circuit diagram illustrating a memory block included in a memory cell array according to an embodiment, FIG. 3 is a timing diagram of a read operation according to an embodiment, FIG. 4 is a timing diagram of a read operation according to an embodiment, FIG. 5 is a timing diagram of a read operation according to an embodiment, FIG. 6 is a flowchart of the read operation of a memory device according to an embodiment. Specific details for implementing the invention

[0010] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[0011] FIG. 1 is a block diagram illustrating a memory device (100) according to an embodiment.

[0012] Referring to FIG. 1, the memory device (100) can operate under the control of an external controller (not shown). The memory device (100) can store data (DATA) received from the controller by performing a program operation, and can output the stored data (DATA) to the controller by performing a read operation.

[0013] The memory device (100) may include peripheral circuits (120) and a memory cell array (120).

[0014] The peripheral circuit (120) can store data (DATA) in the memory cell array (120) and read data (DATA) from the memory cell array (120). The peripheral circuit (120) may include a control circuit (111), a voltage generation circuit (112), a buffer circuit (113), and a decoder (114).

[0015] The control circuit (111) can control the operation of the voltage generation circuit (112), the buffer circuit (113), and the decoder (114) in response to an external signal (CTR) received from the controller, in order to perform internal operations of the memory device (100), such as program operation, read operation, erase operation, etc. For example, the control circuit (111) can generate a voltage control signal (VCS) and output it to the voltage generation circuit (112) to control the voltage generation circuit (112). Additionally, the control circuit (111) can generate a buffer control signal (BCS) and output it to the buffer circuit (113) to control the buffer circuit (113). Additionally, the control circuit (111) can generate a decoder control signal (DCS) and output it to the decoder (114) to control the decoder (114).

[0016] A voltage generation circuit (112) can generate various voltages (not shown) in response to a voltage control signal (VCS) and transmit the voltages to a buffer circuit (113), a decoder (114), and other circuits of a memory device (100). Voltages output from the voltage generation circuit (112) may include a logic voltage transmitted to a control circuit (111), voltages transmitted to a buffer circuit (113) (bitline voltage and erase voltage, etc.), voltages transmitted to a decoder (114) (program voltage, program pass voltage, read voltage, read pass voltage (VP), turn-on voltage, and sub-threshold gate voltage, etc.), a data read pass voltage (VP) supplied to a data pass, a pump voltage supplied to a pump circuit, and various reference voltages.

[0017] The buffer circuit (113) can be connected to the memory cell array (120) via bit lines (BL1 to BLm). The buffer circuit (113) may include buffers (BF1 to BFm) each connected to the bit lines (BL1 to BLm). The buffers (BF1 to BFm) can be connected to memory cells (not shown) included in the memory cell array (120) via bit lines (BL1 to BLm). The buffers (BF1 to BFm) can receive and store data (DATA) to be stored in the memory cells from the controller. The buffers (BF1 to BFm) can store data (DATA) read from the memory cells to output to the controller. The buffers (BF1 to BFm) can operate simultaneously in response to a buffer control signal (BCS), and thus, the memory cells each connected to the bit lines (BL1 to BLm) can be accessed simultaneously.

[0018] The decoder (114) can be connected to the memory cell array (120) via low lines (RL). The decoder (114) can apply voltages to the low lines (RL) in response to a decoder control signal (DCS). The low lines (RL) may include drain select lines, word lines, and source select lines, as described below.

[0019] The memory cell array (120) may include a plurality of memory blocks (MB). Each memory block (MB) may include memory cells in which data (DATA) is stored. The memory cells may be selectively accessed through row lines (RL) and bit lines (BL1~BLm).

[0020] The peripheral circuit (120) can apply one or more read voltages to selected word lines connected to memory cells where read operations are performed. While applying one or more read voltages to the selected word lines, the peripheral circuit (120) can apply a read pass voltage (VP) to non-selected word lines that are not selected word lines. As described below, during the period in which the read pass voltage (VP) is applied to the non-selected word lines, the voltage level of the channel of the non-selected string among a plurality of strings connected between the bit line and the source line can be maintained at a high level. According to the present invention, the peripheral circuit (120) can reduce the voltage level of the channel of the non-selected string to a level higher than the ground voltage in at least a portion of the period in which the read pass voltage (VP) is applied to the non-selected word lines. Therefore, by advancing the boosting section that raises the voltage levels of multiple word lines to the lead pass voltage (VP), even if the voltage level of the channel of the unselected string is excessively boosted, the occurrence of Hot Carrier Injection (HCI) in the channel of the unselected string can be suppressed, and as a result, data stability and lead performance can be improved.

[0021] FIG. 2 is a circuit diagram illustrating a memory block (MB) included in a memory cell array (120) according to an embodiment. The memory cell array (120) may include one or more memory blocks configured similarly to the memory block (MB).

[0022] Referring to FIG. 2, a memory block (MB) may contain strings (ST11~ST1m, ST21~ST2m). Each of the strings (ST11~ST1m, ST21~ST2m) may extend along the vertical direction (Z direction). Within the memory block (MB), m strings may be arranged in the row direction (X direction). FIG. 2 is illustrated as having two strings arranged in the column direction (Y direction), but for convenience of explanation, three or more strings may be arranged in the column direction (Y direction).

[0023] Strings (ST11~ST1m, ST21~ST2m) can be configured identically. For example, string (ST11) may include a source select transistor (SST1), memory cells (MC1~MCn), and a drain select transistor (DST1) connected in series between a source line (SL) and a bit line (BL1). The source of the source select transistor (SST1) may be connected to the source line (SL), and the drain of the drain select transistor (DST1) may be connected to the bit line (BL1). Memory cells (MC1~MCn) may be connected in series between the source select transistor (SST1) and the drain select transistor (DST1). According to an embodiment, a plurality of source select transistors may be connected in series between the source line (SL) and the memory cell (MC1). According to an embodiment, a plurality of drain select transistors may be connected in series between the bit line (BL1) and the memory cell (MCn).

[0024] Source select transistors located at the same position in the vertical direction can be configured as follows. Specifically, the gates of source select transistors of strings arranged in the same row can be connected to the same source select line. For example, the gates of source select transistors of strings (ST11–ST1m) in the first row can be connected to the source select line (SSL1). For example, the gates of source select transistors of strings (ST21–ST2m) in the second row can be connected to the source select line (SSL2).

[0025] According to an embodiment, source selection transistors of strings of two or more rows may be commonly connected to a single source selection line. For example, source selection transistors of strings of the first and second rows (ST11~ST1m, ST21~ST2m) may be commonly connected to a single source selection line, and source selection transistors of strings of the third and fourth rows may be commonly connected to a single source selection line.

[0026] Drain select transistors located at the same position in the vertical direction can be configured as follows. Specifically, the gates of the drain select transistors of strings arranged in the same row can be connected to the same drain select line. For example, the gates of the drain select transistors of the strings (ST11–ST1m) of the first row can be connected to the drain select line (DSL1). For example, the gates of the drain select transistors of the strings (ST21–ST2m) of the second row can be connected to the drain select line (DSL2).

[0027] Strings arranged in the same column can be connected to the same bit line. For example, strings in the first column (ST11, ST21) can be connected to bit line (BL1). For example, strings in the mth column (ST1m, ST2m) can be connected to bit line (BLm).

[0028] The gates of memory cells located at the same position in the vertical direction can be connected to the same word line. For example, in strings (ST11~ST1m, ST21~ST2m), memory cells located at the same position in the vertical direction as memory cell (MC1) can be connected to word line (WL1).

[0029] Among the memory cells, memory cells connected to the same word line in the same row can form a single memory region. For example, memory cells connected to word line (WL1) in the first row can form a single memory region (MR11). For example, memory cells connected to word line (WL1) in the second row can form a single memory region (MR12). For example, memory cells connected to word line (WL2) in the first row can form a single memory region (MR21). Depending on the number of rows, each word line can be connected to multiple memory regions. Memory cells forming a single memory region can be accessed simultaneously.

[0030] According to an embodiment, the memory block (MB) may be further connected to one or more dummy word lines other than the word lines (WL1 to WLn). In this case, the memory block (MB) may further include dummy memory cells connected to the dummy word lines.

[0031] Figure 3 is a timing diagram of a lead operation according to an embodiment.

[0032] In the following, the drain select line (DSL_SEL) connected to the selected string and the source select line (SSL_SEL) connected to the selected string may be the drain select line and the source select line, respectively, connected to the drain select transistor and the source select transistor included in the selected string. The drain select line (DSL_UNSEL) connected to the unselected string and the source select line (SSL_UNSEL) connected to the unselected string may be the drain select line and the source select line, respectively, connected to the drain select transistor and the source select transistor included in the unselected string. The selected string is a string containing a memory cell where a read operation is performed among strings connected to a certain bit line, and the unselected string may be a string that is not the selected string among the strings connected to the corresponding bit line. The selected word line (WL_SEL) may be a word line connected to a target memory cell where a read operation is performed among the memory cells included in the selected string. The unselected word lines (WL_UNSEL) may be word lines connected to memory cells other than the target memory cells among the memory cells included in the selected string.

[0033] For example, when the target memory cell where the read operation is performed in FIG. 2 is memory cell (MC1), the selected string may be string (ST11) and the unselected string may be string (ST21). Also, the selected word line (WL_SEL) may be word line (WL1) and the unselected word lines (WL_UNSEL) may be word lines (WL2~WLn). Also, the drain selection line (DSL_SEL) connected to the selected string and the source selection line (SSL_SEL) connected to the selected string may be the drain selection line (DSL1) and the source selection line (SSL1). Also, the drain selection line (DSL_UNSEL) connected to the unselected string and the source selection line (SSL_UNSEL) connected to the unselected string may be the drain selection line (DSL2) and the source selection line (SSL2).

[0034] Referring to FIG. 3, in the interval (P11) (or initialization interval) and the interval (P12) (or boosting interval), voltage may be applied to the unselected word lines (WL_UNSEL) and the selected word line (WL_SEL) so that the voltage levels of the unselected word lines (WL_UNSEL) and the selected word line (WL_SEL) rise to the lead pass voltage (VP). The voltage levels of the unselected word lines (WL_UNSEL) and the selected word line (WL_SEL) may rise stepwise or gradually to the lead pass voltage (VP).

[0035] In the section (P13) (or, lead section), the voltage levels of the unselected word lines (WL_UNSEL) and the selected word line (WL_SEL) reach the lead pass voltage (VP), and while the lead pass voltage (VP) is applied to the unselected word lines (WL_UNSEL), lead voltages (VR1, VR2) may be sequentially applied to the selected word line (WL_SEL). Depending on the embodiment, the number of lead voltages applied in the section (P13) may differ from this.

[0036] In the interval (P14) (or, equalization interval), an equalization voltage (VE) may be applied to the unselected word lines (WL_UNSEL) and the selected word line (WL_SEL) to equalize the voltage levels of the unselected word lines (WL_UNSEL) and the selected word line (WL_SEL).

[0037] In the interval (P15) (or, discharge interval), the unselected word lines (WL_UNSEL) and the selected word line (WL_SEL) can be discharged to the ground voltage (VSS).

[0038] In section (P11), a turn-on voltage (VT) may be applied to the drain select line (DSL_SEL) connected to the selected string and the source select line (SSL_SEL) connected to the selected string. The turn-on voltage (VT) may be a voltage capable of turning on the drain select transistor and the source select transistor, respectively, connected to the drain select line (DSL_SEL) connected to the selected string and the source select line (SSL_SEL) connected to the selected string. Accordingly, in section (P11), the drain select transistor and the source select transistor, respectively, connected to the drain select line (DSL_SEL) connected to the selected string and the source select line (SSL_SEL) connected to the selected string are turned on, and the channel of the selected string may be connected between the corresponding bit line and source line. Consequently, in section (P11), the channel of the selected string may be initialized by being discharged. In the intervals (P12, P13), the drain select line (DSL_SEL) connected to the selected string and the source select line (SSL_SEL) connected to the selected string can continue to receive the turn-on voltage (VT) for the lead operation.

[0039] In intervals (P14, P15), the drain select line (DSL_SEL) connected to the selected string and the source select line (SSL_SEL) connected to the selected string can be discharged. Accordingly, in intervals (P14, P15), the drain select transistor and the source select transistor connected to the drain select line (DSL_SEL) connected to the selected string and the source select line (SSL_SEL) connected to the selected string, respectively, are turned off, and the channel of the selected string can be separated from the corresponding bit line and source line.

[0040] In section (P11), a turn-on voltage (VT) can be applied to the drain select line (DSL_UNSEL) connected to the unselected string and the source select line (SSL_UNSEL) connected to the unselected string. Accordingly, in section (P11), the drain select transistor and the source select transistor connected to the drain select line (DSL_UNSEL) connected to the unselected string and the source select line (SSL_UNSEL) connected to the unselected string, respectively, are turned on, and the channel (CH_UNSEL) of the unselected string can be connected between the corresponding bit line and source line. Consequently, in section (P11), the channel (CH_UNSEL) of the unselected string can be initialized by being discharged. According to an embodiment, the turn-on voltage applied to the drain selection line (DSL_SEL) connected to the selected string and the source selection line (SSL_SEL) connected to the selected string may be different from the turn-on voltage applied to the drain selection line (DSL_UNSEL) connected to the unselected string and the source selection line (SSL_UNSEL) connected to the unselected string.

[0041] In the intervals (P12–P15), the drain select line (DSL_UNSEL) connected to the unselected string and the source select line (SSL_UNSEL) connected to the unselected string can be discharged to ground voltage (VSS). Accordingly, in the intervals (P12–P15), the drain select transistor and the source select transistor connected to the drain select line (DSL_UNSEL) connected to the unselected string and the source select line (SSL_UNSEL) connected to the unselected string, respectively, are turned off, and the channel (CH_UNSEL) of the unselected string can be separated from the corresponding bit line and source line.

[0042] Consequently, at the end point (T11) of the interval (P11), as the channel (CH_UNSEL) of the unselected string is separated from the corresponding bit line and source line, the capacitance between the channel (CH_UNSEL) of the unselected string and the word lines can be reduced. Thus, in the interval (P12), the rate of rise of the voltage levels of the unselected word lines (WL_UNSEL) and the selected word line (WL_SEL) increases, so that the voltage levels of the unselected word lines (WL_UNSEL) and the selected word line (WL_SEL) can reach the lead pass voltage (VP) quickly. Additionally, in the interval (P13), the channel (CH_UNSEL) of the unselected string is at a boosted voltage level and can be subjected to less stress due to the lead operation.

[0043] According to an embodiment, a predetermined turn-off voltage may be applied instead of a ground voltage (VSS) to a drain select line (DSL_SEL) connected to a selected string, a source select line (SSL_SEL) connected to a selected string, a drain select line (DSL_UNSEL) connected to a non-selected string, and a source select line (SSL_UNSEL) connected to a non-selected string. The turn-off voltage may be a voltage capable of turning off the drain select transistor and the source select transistor.

[0044] FIG. 4 is a timing diagram of a lead operation according to an embodiment. The waveforms indicated by dotted lines in FIG. 4 may correspond to the operation of the embodiment described with reference to FIG. 3. Any operation not described below in relation to FIG. 4 may be performed similarly to the operation described with reference to FIG. 3.

[0045] Referring to FIG. 4, in section (P22), the drain select line (DSL_UNSEL) connected to the unselected string and the source select line (SSL_UNSEL) connected to the unselected string can be discharged to ground voltage (VSS). Accordingly, in section (P22), the drain select transistor and the source select transistor connected to the drain select line (DSL_UNSEL) connected to the unselected string and the source select line (SSL_UNSEL) connected to the unselected string, respectively, are turned off, and the channel (CH_UNSEL) of the unselected string can be separated from the corresponding bit line and source line.

[0046] Consequently, at the end point (T21) of the interval (P21), as the channel (CH_UNSEL) of the unselected string is separated from the corresponding bit line and source line, the capacitance between the channel (CH_UNSEL) of the unselected string and the word lines can be reduced. Thus, in the interval (P22), the rate of rise of the voltage levels of the unselected word lines (WL_UNSEL) and the selected word line (WL_SEL) increases, so that the voltage levels of the unselected word lines (WL_UNSEL) and the selected word line (WL_SEL) can reach the lead pass voltage (VP) quickly. Additionally, in the interval (P22), the channel (CH_UNSEL) of the unselected string is at a boosted voltage level and can be subjected to less stress due to the lead operation.

[0047] Here, the interval of the interval (P21) may be shorter than the interval of the interval (P11) according to the embodiment of FIG. 3. In other words, the time point (T21) at which the drain select transistor and the source select transistor connected to the drain select line (DSL_UNSEL) connected to the unselected string and the source select line (SSL_UNSEL) connected to the unselected string are turned off, and the channel (CH_UNSEL) of the unselected string is separated from the corresponding bit line and source line, may be earlier than the time point (T11) according to the embodiment of FIG. 3.

[0048] Accordingly, in the interval (P22), the point at which the voltage levels of the unselected word lines (WL_UNSEL) and the selected word lines (WL_SEL) reach the read pass voltage (VP) can be brought forward compared to the embodiment of FIG. 3. As a result, the time of the entire read operation can be shortened, and the read performance of the memory device (100) can be improved.

[0049] However, in section (P22), the increase in voltage levels of the unselected word lines (WL_UNSEL) and the selected word lines (WL_SEL) may be greater than in section (P12) according to the embodiment of FIG. 3. Accordingly, in sections (P22, P23), the channel (CH_UNSEL) of the unselected string may be boosted to a higher voltage level than in the embodiment of FIG. 3. As a result, HCI may occur in the channel (CH_UNSEL) of the unselected string, and performance degradation and reliability degradation of the memory cell in the unselected string may be induced.

[0050] FIG. 5 is a timing diagram of a lead operation according to an embodiment. The waveforms indicated by dotted lines in FIG. 5 can correspond to the operation of the embodiment described with reference to FIG. 4.

[0051] Referring to FIG. 5, in the intervals (P31–P35), the unselected word lines (WL_UNSEL), the selected word line (WL_SEL), the drain selection line (DSL_SEL) connected to the selected string, the source selection line (SSL_SEL) connected to the selected string, and the drain selection line (DSL_UNSEL) connected to the unselected string can be controlled and operated similarly to the intervals (P21–P25) of FIG. 4. Accordingly, the operation of the source selection line (SSL_UNSEL) connected to the unselected string will be described primarily below.

[0052] The section (P33) may include the section (P36) (or, the channel voltage adjustment section).

[0053] In the interval (P36), the subthreshold gate voltage (VST) of the source select transistor may be applied to the source select line (SSL_UNSEL) connected to the unselected string. The start time (T32) of the interval (P36) may be after the voltage levels of the unselected word lines (WL_UNSEL) and the selected word line (WL_SEL) have reached the lead pass voltage (VP). The start time (T32) of the interval (P36) may be before the lead voltages (VR1, VR2) are applied to the selected word line (WL_SEL). The end time (T33) of the interval (P36) may be before the start time (T34) of the interval (P34).

[0054] According to an embodiment, the channel voltage adjustment section may include a plurality of discontinuous sections in section (P33).

[0055] The subthreshold gate voltage (VST) may be a voltage between the ground voltage (VSS) (or the turn-off voltage of the source select transistor) and the threshold voltage of the source select transistor. Accordingly, the source select transistor of the unselected string is weakly turned on in response to the subthreshold gate voltage (VST), and the voltage level of the channel (CH_UNSEL) of the unselected string may be reduced in the channel voltage regulation period (P36). As a result, HCI generation in the channel (CH_UNSEL) of the unselected string may be suppressed.

[0056] In summary, as HCI generation in the channel (CH_UNSEL) of the unselected string is suppressed and the rise characteristic of the read pass voltage (VP) is improved compared to the embodiment of FIG. 3, the time of the entire read operation is shortened, so the read performance of the memory device (100) can be improved.

[0057] FIG. 6 is a flowchart of the read operation of a memory device (100) according to an embodiment.

[0058] Referring together with FIG. 6, in operation (S110), the peripheral circuit (120) can apply a turn-on voltage (VT) to a drain selection line (DSL_UNSEL) connected to an unselected string and a source selection line (SSL_UNSEL) connected to an unselected string among a plurality of strings connected between a bit line and a source line in the first section (or initialization section).

[0059] In operation (S120), the peripheral circuit (120) can apply a turn-off voltage to the drain select line (DSL_UNSEL) connected to the unselected string and the source select line (SSL_UNSEL) connected to the unselected string in the second section (or boosting section) following the first section. The peripheral circuit (120) can raise the voltage levels of the multiple word lines to a lead pass voltage (VP) in the first and second sections.

[0060] In operation (S130), the peripheral circuit (120) may apply a subthreshold gate voltage (VST) to a source select line (SSL_UNSEL) connected to an unselected string while applying a turn-off voltage to a drain select line (DSL_UNSEL) connected to an unselected string during at least a portion of a third section (or lead section) (or channel voltage control section) following the second section. The peripheral circuit (120) may apply one or more lead voltages (VR1, VR2) to a selected word line (WL_SEL) while applying a lead pass voltage (VP) to unselected word lines (WL_UNSEL) during the third section.

[0061] The foregoing description is merely an illustrative explanation of the technical concept of the present invention, and those skilled in the art to which the present invention pertains will be able to make various modifications and variations within the scope of the essential characteristics of the present invention. Furthermore, the embodiments disclosed in the present invention are intended to explain, not limit, the technical concept of the present invention, and thus the scope of the technical concept of the present invention is not limited by these embodiments. The scope of protection of the present invention shall be interpreted by the claims below, and all technical concepts within an equivalent scope shall be interpreted as being included within the scope of rights of the present invention. Explanation of the symbols

[0062] 100: Memory device 110: Peripheral circuit 111: Control circuit 112: Voltage generation circuit 113: Buffer circuit BF1~BFm: Buffers 114: Decoder 120: Memory cell array MB: Memory blocks

Claims

Claim 1 A memory device comprising: a plurality of strings connected between a bit line and a source line, wherein each of the plurality of strings comprises a drain select transistor connected to a corresponding drain select line, memory cells connected to a plurality of word lines, and a source select transistor connected to a corresponding source select line; and a peripheral circuit configured to apply a sub-threshold gate voltage to a source select line connected to a non-selected string while applying a turn-off voltage to a drain select line connected to a non-selected string among the plurality of strings during at least a portion of a read section in which a read pass voltage is applied to non-selected word lines among the plurality of word lines. Claim 2 A memory device according to claim 1, wherein the peripheral circuit raises the voltage levels of the plurality of word lines to the read pass voltage in the initialization section and boosting section prior to the read section. Claim 3 A memory device according to paragraph 2, wherein the peripheral circuit applies a turn-on voltage to the drain selection line connected to the unselected string and the source selection line connected to the unselected string during the initialization section. Claim 4 A memory device according to paragraph 2, wherein the peripheral circuit applies the turn-off voltage to the drain selection line connected to the unselected string and the source selection line connected to the unselected string in the boosting section. Claim 5 A memory device according to paragraph 2, wherein the peripheral circuit applies a turn-on voltage to a drain selection line connected to a selected string among the plurality of strings and a source selection line connected to the selected string in the initialization section, the boosting section, and the lead section. Claim 6 A memory device according to claim 1, wherein the peripheral circuit applies one or more read voltages to a selected word line among the plurality of word lines in the read section. Claim 7 A memory device according to claim 1, wherein the peripheral circuit equalizes the voltage levels of the plurality of word lines in an equalization section following the lead section. Claim 8 A memory device according to claim 7, wherein the end time of at least a portion of the above section is earlier than the start time of the above equalization section. Claim 9 In claim 7, the memory device, wherein the peripheral circuit applies the turn-off voltage to drain selection lines connected to each of the plurality of strings and source selection lines connected to each of the plurality of strings in the equalization section. Claim 10 A memory device according to claim 1, wherein at least some sections include a plurality of discontinuous sections in the read section. Claim 11 A memory cell array comprising a plurality of strings connected between a bit line and a source line, wherein each of the plurality of strings comprises a drain select transistor connected to a corresponding drain select line, memory cells connected to a plurality of word lines, and a source select transistor connected to a corresponding source select line; and a peripheral circuit configured to reduce the voltage level of a channel of an unselected string among the plurality of strings to a level higher than the ground voltage during a channel voltage regulation period in a read operation. Claim 12 A memory device according to claim 11, wherein the peripheral circuit controls the channel to allow a sub-threshold current to flow to the source line while isolating the channel of the unselected string from the bit line, thereby reducing the voltage level of the channel to the level higher than the ground voltage. Claim 13 In claim 11, the memory device wherein the peripheral circuit separates the channel of the unselected string from the bit line and the source line in a boosting section prior to the channel voltage regulation section. Claim 14 A memory device according to claim 13, wherein the peripheral circuit discharges the voltage levels of the channels to the ground voltage by connecting the channels of the plurality of strings to the bit line and the source line in an initialization section prior to the boosting section. Claim 15 In claim 14, the memory device wherein the peripheral circuit raises the voltage levels of the plurality of word lines to a read pass voltage in the initialization section and the boosting section. Claim 16 A memory device according to claim 11, wherein the channel voltage adjustment section is included in a read section in which one or more read voltages are applied to a selected word line among the plurality of word lines while a read pass voltage is applied to a non-selected word line among the plurality of word lines. Claim 17 A read method for a memory device comprising: an operation of applying a turn-on voltage to a drain selection line connected to a non-selected string among a plurality of strings and a source selection line connected to the non-selected string in a first section; an operation of applying a turn-off voltage to the drain selection line and the source selection line in a second section following the first section; and an operation of applying a sub-threshold gate voltage to the source selection line while applying the turn-off voltage to the drain selection line in at least a portion of a third section following the second section. Claim 18 A read method for a memory device according to claim 17, further comprising the operation of raising the voltage levels of a plurality of word lines to a read pass voltage in the first section and the second section. Claim 19 A read method for a memory device according to claim 18, wherein the start time of at least a portion of the above interval is after the voltage levels of the plurality of word lines have reached the read pass voltage. Claim 20 A read method for a memory device according to claim 17, further comprising the operation of applying the turn-on voltage to a drain selection line connected to a selected string among the plurality of strings and a source selection line connected to the selected string in the first to third sections. Claim 21 A reading method for a memory device according to claim 17, further comprising, in the third section, applying one or more read voltages to selected word lines while applying a read pass voltage to unselected word lines. Claim 22 A read method for a memory device according to claim 17, further comprising an operation to equalize the voltage levels of a plurality of word lines in a fourth section following the third section. Claim 23 A method for reading a memory device according to claim 22, wherein the end time of at least some section is earlier than the start time of the fourth section. Claim 24 A read method for a memory device according to claim 22, further comprising, in the fourth section, the operation of applying the turn-off voltage to drain selection lines connected to each of the plurality of strings and source selection lines connected to each of the plurality of strings. Claim 25 A method for reading a memory device according to claim 17, wherein at least some sections include multiple sections that are discontinuous in the third section.

Images