Conductive stack and semiconductor device including the same

Abstract

A conductive laminate and a semiconductor device including the same are provided. The conductive laminate comprises a lower conductive layer, a barrier conductive layer on the lower conductive layer, an insertion layer on the barrier conductive layer comprising a silicide nitride of a first metal element, a first upper conductive layer on the insertion layer comprising a first metal element, and a second upper conductive layer on the first upper conductive layer comprising a second metal element different from the first metal element.

Description

Technology Field

[0001] The present invention relates to a conductive laminate and a semiconductor device including the same. Background Technology

[0002] As semiconductor devices become increasingly highly integrated, tungsten (W) and molybdenum (Mo) are being studied as materials used for wiring in semiconductor devices. In addition, when high fusion point metals such as tungsten (W) and molybdenum (Mo) are used as wiring, a barrier conductive layer can be used to prevent the diffusion of metal elements. However, there is a problem in that the barrier conductive layer is damaged during the process of depositing tungsten (W) and molybdenum (Mo) on the barrier conductive layer by physical vapor deposition (PVD) or the like, which increases the electrical resistance of the wiring. The problem to be solved

[0003] The technical problem that the present invention aims to solve is to provide a conductive laminate with reduced electrical resistance.

[0004] Another technical problem that the present invention aims to solve is to provide a semiconductor device comprising a conductive laminate with reduced electrical resistance.

[0005] The technical problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0006] A conductive laminate according to some embodiments for achieving the above technical problem comprises a lower conductive layer, a barrier conductive layer on the lower conductive layer, an insert layer on the barrier conductive layer comprising a silicide nitride of a first metal element, a first upper conductive layer on the insert layer comprising a first metal element, and a second upper conductive layer on the first upper conductive layer comprising a second metal element different from the first metal element.

[0007] A conductive laminate according to some embodiments for achieving the above technical problem comprises a lower conductive layer comprising polysilicon (poly-Si), a barrier conductive layer comprising titanium (Ti) on the lower conductive layer, an insertion layer comprising tungsten silicide nitride (WSiN) on the barrier conductive layer, a first upper conductive layer comprising tungsten (W) on the insertion layer, and a second upper conductive layer comprising molybdenum (Mo) on the first upper conductive layer.

[0008] A semiconductor device according to some embodiments for achieving the above other technical objectives comprises an active pattern, a bit line connected to a first portion of the active pattern, a capacitor structure connected to a second portion of the active pattern, and a word line intersecting the active pattern between the first portion and the second portion, wherein the bit line comprises a lower conductive layer connected to the active pattern, a barrier conductive layer on the lower conductive layer, an insertion layer comprising tungsten silicide nitride (WSiN) on the barrier conductive layer, a first upper conductive layer comprising tungsten (W) on the insertion layer, and a second upper conductive layer comprising molybdenum (Mo) on the first upper conductive layer.

[0009] Specific details of other embodiments are included in the detailed description and drawings. Brief explanation of the drawing

[0010] FIG. 1 is a cross-sectional view illustrating a conductive laminate according to some embodiments. FIG. 2 is a graph illustrating the penetration depth of tungsten ions in a conductive laminate according to some embodiments. FIGS. 3a to 3c are graphs illustrating changes in characteristics according to the nitrogen concentration of the insertion layer in a conductive laminate according to some embodiments. FIG. 4 is a cross-sectional view illustrating a conductive laminate according to some embodiments. FIGS. 5A and 5B are graphs illustrating changes in properties according to the nitrogen concentration of the insertion layer in a conductive laminate according to some embodiments. FIG. 6 is a layout diagram for explaining a semiconductor device according to some embodiments. Figure 7 is a cross-sectional view taken along AA of Figure 6. Figures 8 and 9 are various enlarged views to illustrate the R1 region of Figure 7. Figure 10 is a cross-sectional view taken along BB of Figure 6. FIG. 11 is a layout diagram for illustrating a semiconductor device according to some embodiments. Figure 12 is a cross-sectional view taken along CC of Figure 11. Figures 13 and 14 are various enlarged views to illustrate the R2 region of Figure 12. FIG. 15 is a cross-sectional view taken along DD of FIG. 11. Specific details for implementing the invention

[0011] Hereinafter, a conductive laminate according to exemplary embodiments is described with reference to FIGS. 1 to 5b.

[0012] FIG. 1 is a cross-sectional view illustrating a conductive laminate according to some embodiments. FIG. 2 is a graph showing the penetration depth of tungsten ions according to ion energy in a conductive laminate according to some embodiments. FIG. 3a to 3c are graphs illustrating the change in properties according to the nitrogen concentration of the insertion layer in a conductive laminate according to some embodiments.

[0013] Referring to FIGS. 1 to 3c, a conductive laminate according to some embodiments includes a lower conductive layer (21), a barrier conductive layer (22), an insertion layer (23), a first upper conductive layer (24), and a second upper conductive layer (25) that are sequentially laminated on a first substrate (10).

[0014] The first substrate (10) may be a semiconductor substrate such as a silicon wafer. The first substrate (10) may have a structure in which a base substrate and an epitaxial layer are stacked, but is not limited thereto. The first substrate (10) may be a silicon substrate, a gallium arsenide substrate, a silicon germanium substrate, or a Semiconductor On Insulator (SOI) substrate. For example, the first substrate (10) is described below as being a silicon substrate.

[0015] The lower conductive layer (21) may be formed on the first substrate (10). The lower conductive layer (21) may be in direct contact with the first substrate (10) or spaced apart from the first substrate (10). The lower conductive layer (21) may include a conductive material, for example, a metal such as tungsten (W), molybdenum (Mo), ruthenium (Ru), cobalt (Co), nickel (Ni), or a semiconductor material such as silicon, but is not limited thereto.

[0016] In some embodiments, the lower conductive layer (21) may comprise polysilicon (poly-Si). For example, the lower conductive layer (21) may be a polysilicon film doped with n-type impurities (e.g., P, Sb, or As) and / or p-type impurities (e.g., boron (B), indium (In), gallium (Ga), or aluminum (Al)).

[0017] A barrier conductive layer (22) may be formed on a lower conductive layer (21). For example, the barrier conductive layer (22) may be laminated directly on the lower conductive layer (21) and in contact with the lower conductive layer (21). The barrier conductive layer (22) may be interposed between the lower conductive layer (21) and the insertion layer (23). The barrier conductive layer (22) may include a metal or a metal nitride to prevent a metal element (hereinafter referred to as the first metal element) contained in the insertion layer (23) and / or the first upper conductive layer (24) from diffusing into the lower conductive layer (21). For example, the barrier conductive layer (22) may include at least one of titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), cobalt (Co), platinum (Pt), alloys thereof, or nitrides thereof, but is not limited thereto.

[0018] In some embodiments, the barrier conductive layer (22) may include titanium (Ti). For example, the barrier conductive layer (22) may include at least one of a titanium film (Ti), a titanium nitride film (TiN), a titanium silicide nitride film (TiSiN), or a combination thereof.

[0019] An insert layer (23) may be formed on the barrier conductive layer (22). For example, the insert layer (23) may be laminated directly on the barrier conductive layer (22) and in contact with the barrier conductive layer (22). The insert layer (23) may be interposed between the barrier conductive layer (22) and the first upper conductive layer (24). The insert layer (23) may include a silicide nitride of the first metal element. The first metal element may be, for example, one of aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), cobalt (Co), and ruthenium (Ru), but is not limited thereto.

[0020] In some embodiments, the first metal element may be tungsten (W). That is, the insert layer (23) may include tungsten silicide nitride (WSiN).

[0021] In some embodiments, in the silicide nitride of the insertion layer (23), the ratio of silicon atoms to metal atoms may be about 0.5 or more, about 1.0 or more, or about 1.5 or more, and about 3.0 or less, about 4.0 or less, or about 5.0 or less. For example, when the insertion layer (23) is a tungsten silicide nitride film (WSiN), the ratio of silicon (Si) atoms to tungsten (W) atoms may be about 0.5 to about 3.0.

[0022] The first upper conductive layer (24) may be formed on the insertion layer (23). For example, the first upper conductive layer (24) may be laminated directly on the insertion layer (23) and in contact with the insertion layer (23). The first upper conductive layer (24) may be interposed between the insertion layer (23) and the second upper conductive layer (25). The first upper conductive layer (24) may include the first metal element. For example, the first upper conductive layer (24) may include one of aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), cobalt (Co), and ruthenium (Ru), but is not limited thereto. For example, when the insertion layer (23) is a tungsten silicide nitride film (WSiN), the first upper conductive layer (24) may be a tungsten film (W).

[0023] In some embodiments, the tungsten film (W) of the first upper conductive layer (24) may include a {110} crystal plane.

[0024] A second upper conductive layer (25) may be formed on the first upper conductive layer (24). For example, the second upper conductive layer (25) may be laminated directly on the first upper conductive layer (24) and in contact with the first upper conductive layer (24). The second upper conductive layer (25) may include a second metal element different from the first metal element. The second metal element may be, for example, one of aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), cobalt (Co), and ruthenium (Ru), but is not limited thereto. The first upper conductive layer (24) may be provided as an incubation layer for forming the second upper conductive layer (25).

[0025] In some embodiments, the electrical conductivity of the second metal element may be greater than the electrical conductivity of the first metal element. For example, the first metal element may be tungsten (W) and the second metal element may be molybdenum (Mo).

[0026] In some embodiments, the grain size of the first upper conductive layer (24) may be larger than the grain size of the second upper conductive layer (25). In this case, the grain size of the second upper conductive layer (25) may be increased compared to a single layer of the second upper conductive layer (25) where the first upper conductive layer (24) is not provided, thereby reducing the electrical resistance of the second upper conductive layer (25). For example, when the first upper conductive layer (24) is a tungsten film (W), the second upper conductive layer (25) may be a molybdenum film (Mo).

[0027] In some embodiments, the molybdenum film (Mo) of the second upper conductive layer (25) may include a {110} crystal plane.

[0028] In some embodiments, the thickness (T1) of the insertion layer (23) may be about 25 Å or more. For example, the thickness (T1) of the insertion layer (23) may be about 25 Å to about 100 Å, about 30 Å to about 100 Å, about 35 Å to about 100 Å, or about 40 Å to about 100 Å. Within these ranges, the insertion layer (23) can prevent damage to the barrier conductive layer (22) caused by the penetration of the first metal element (e.g., tungsten (W)) during the deposition process of the first upper conductive layer (24) and / or the second upper conductive layer (25).

[0029] For example, FIG. 2 shows the penetration depth of tungsten ions (W ions) penetrating into the tungsten silicide nitride film (WSiN) in the process of forming a tungsten film (W) as a first upper conductive layer (24) on a tungsten silicide nitride film (WSiN) as an insertion layer (23) using a physical vapor deposition (PVD) process. As shown in FIG. 2, when the ion energy is 100 eV (or 200 eV, or 500 eV, or 1000 eV), the penetration depth of the majority of tungsten ions (W ions) may be about 25 Å or less (or about 30 Å or less, or about 35 Å or less, or about 40 Å or less). Therefore, it can be confirmed that when the thickness of the insertion layer (23) is about 25 Å or more (or about 30 Å or more, or about 35 Å or more, or about 40 Å or more), damage to the barrier conductive layer (22) due to the penetration of tungsten ions can be effectively prevented.

[0030] In some embodiments, in the silicide nitride of the insertion layer (23), the nitrogen concentration may be about 20 atomic percent or more and about 35 atomic percent or less. In this range, the orientation of the first upper conductive layer (24) and / or the orientation of the second upper conductive layer (25) may be improved so that the electrical resistance of the first upper conductive layer (24) and / or the electrical resistance of the second upper conductive layer (25) may be reduced.

[0031] For example, in FIG. 3a, the x-axis represents the nitrogen concentration of the tungsten silicide nitride film (WSiN) as the insertion layer (23), and the y-axis represents the XRD (X-ray diffraction) peak intensity corresponding to the (110) crystal plane of the tungsten film (W) as the first upper conductive layer (24). As shown in FIG. 3a, when the nitrogen concentration of the insertion layer (23) (tungsten silicide nitride film (WSiN)) is about 24 atomic%, it can be seen that the orientation of the first upper conductive layer (24) (tungsten film (W)) is improved compared to when the nitrogen concentration is about 0 atomic% (e.g., no nitrogen is included) or when the nitrogen concentration is about 35 atomic%.

[0032] For example, in FIG. 3b, the x-axis represents the nitrogen concentration of the tungsten silicide nitride film (WSiN) as the insertion layer (23), and the y-axis represents the XRD (X-ray diffraction) peak intensity corresponding to the (110) crystal plane of the molybdenum film (Mo) as the second upper conductive layer (25). As shown in FIG. 3b, when the nitrogen concentration of the insertion layer (23) (tungsten silicide nitride film (WSiN)) is about 24 atomic%, it can be seen that the orientation of the second upper conductive layer (25) (molybdenum film (Mo)) is improved compared to when the nitrogen concentration is about 0 atomic% (e.g., no nitrogen is included) or when the nitrogen concentration is about 35 atomic%.

[0033] In FIG. 3c, the x-axis represents the nitrogen concentration of the tungsten silicide nitride film (WSiN) as the insertion layer (23), and the y-axis represents the sheet resistance of the molybdenum film (Mo) as the second upper conductive layer (25). Accordingly, as shown in FIG. 3c, when the nitrogen concentration of the insertion layer (23) (tungsten silicide nitride film (WSiN)) is about 24 atomic%, it can be confirmed that the second upper conductive layer (25) (molybdenum film (Mo)) has reduced sheet resistance.

[0034] In some embodiments, the thickness (T2) of the first upper conductive layer (24) may be from about 10 Å to about 200 Å or less. Within this range, the first upper conductive layer (24) may be provided as an incubation layer for forming the second upper conductive layer (25).

[0035] FIG. 4 is a cross-sectional view illustrating a conductive laminate according to some embodiments. FIG. 5a and FIG. 5b are graphs illustrating changes in characteristics according to the nitrogen concentration of the insertion layer in a conductive laminate according to some embodiments. For convenience of explanation, parts that overlap with those described above using FIG. 1 to FIG. 3c are briefly explained or omitted.

[0036] Referring to FIGS. 4 to 5b, in a conductive laminate according to some embodiments, the insertion layer (23) includes a first sub-insertion layer (23a) and a second sub-insertion layer (23b).

[0037] The first sub-insertion layer (23a) and the second sub-insertion layer (23b) may be stacked sequentially on the barrier conductive layer (22). For example, the first sub-insertion layer (23a) may be stacked directly on the barrier conductive layer (22) and may come into contact with the barrier conductive layer (22). The first sub-insertion layer (23a) may be interposed between the barrier conductive layer (22) and the second sub-insertion layer (23b). For example, the first upper conductive layer (24) may be stacked directly on the second sub-insertion layer (23b) and may come into contact with the second sub-insertion layer (23b). The second sub-insertion layer (23b) may be interposed between the first sub-insertion layer (23a) and the first upper conductive layer (24).

[0038] The first sub-insertion layer (23a) and the second sub-insertion layer (23b) may each include a silicide nitride of the first metal element. For example, the first sub-insertion layer (23a) and the second sub-insertion layer (23b) may each include tungsten silicide nitride (WSiN).

[0039] The first sub-insertion layer (23a) and the second sub-insertion layer (23b) may have different nitrogen concentrations. In some embodiments, the nitrogen concentration of the first sub-insertion layer (23a) may be lower than the nitrogen concentration of the second sub-insertion layer (23b).

[0040] In some embodiments, the nitrogen concentration of the first sub-insertion layer (23a) may be less than about 35 atomic percent. For example, the nitrogen concentration of the first sub-insertion layer (23a) may be about 0 atomic percent or more and less than about 35 atomic percent, about 0 atomic percent to about 30 atomic percent, about 0 atomic percent to about 20 atomic percent, or about 0 atomic percent to about 10 atomic percent. Preferably, the nitrogen concentration of the first sub-insertion layer (23a) may be about 24 atomic percent or less. Alternatively, the first sub-insertion layer (23a) may not contain nitrogen. Within these ranges, the first sub-insertion layer (23a) may provide reduced electrical resistance.

[0041] For example, in FIG. 5a, the x-axis represents the nitrogen concentration of the tungsten silicide nitride film (WSiN) as the first sub-insertion layer (23a), and the y-axis represents the sheet resistance of the tungsten silicide nitride film (WSiN) as the first sub-insertion layer (23a). As shown in FIG. 5a, when the nitrogen concentration of the first sub-insertion layer (23a) (tungsten silicide nitride film (WSiN)) is less than 35 atomic percent, it can be confirmed that the first sub-insertion layer (23a) has reduced sheet resistance.

[0042] In some embodiments, the nitrogen concentration of the second sub-insertion layer (23b) may be about 40 atomic% to about 65 atomic%, or about 43 atomic% to about 65 atomic%. Preferably, the nitrogen concentration of the second sub-insertion layer (23b) may be about 45 atomic% to about 65 atomic%. In the above range, the orientation of the first upper conductive layer (24) and / or the orientation of the second upper conductive layer (25) may be improved so that the electrical resistance of the first upper conductive layer (24) and / or the electrical resistance of the second upper conductive layer (25) may be reduced.

[0043] For example, in FIG. 5b, the x-axis represents the nitrogen concentration of the tungsten silicide nitride film (WSiN) as the second sub-insertion layer (23b), and the y-axis represents the sheet resistance of the molybdenum film (Mo) as the second upper conductive layer (25). As shown in FIG. 5b, when the nitrogen concentration of the second sub-insertion layer (23b) (tungsten silicide nitride film (WSiN)) is 45 atomic% or more, it can be seen that the second upper conductive layer (25) (molybdenum film (Mo)) has reduced sheet resistance.

[0044] In FIG. 4, only the thickness (T1a) of the first sub-insertion layer (23a) and the thickness (T1b) of the second sub-insertion layer (23b) are shown as being the same, but this is merely illustrative. Of course, unlike what is shown, the thickness (T1a) of the first sub-insertion layer (23a) and the thickness (T1b) of the second sub-insertion layer (23b) may be different from each other.

[0045] As semiconductor devices become increasingly highly integrated, tungsten (W) and molybdenum (Mo) are being studied as materials used for wiring in semiconductor devices. In addition, when high fusion point metals such as tungsten (W) and molybdenum (Mo) are used as wiring, a barrier conductive layer can be used to prevent the diffusion of metal elements. However, there is a problem in that the barrier conductive layer is damaged during the process of depositing tungsten (W) and molybdenum (Mo) on the barrier conductive layer by physical vapor deposition (PVD) or the like, which increases the electrical resistance of the wiring.

[0046] A conductive laminate according to some embodiments may provide reduced electrical resistance by utilizing an insert layer (23). Specifically, as described above, the insert layer (23) is interposed between the barrier conductive layer (22) and the first upper conductive layer (24) to prevent damage to the barrier conductive layer (22) caused by the penetration of the first metal element (e.g., tungsten (W)) during the deposition process of the first upper conductive layer (24) and / or the second upper conductive layer (25). Additionally, as described above, the insert layer (23) may reduce the sheet resistance of the second upper conductive layer (25) by improving the orientation of the first upper conductive layer (24) and / or the orientation of the second upper conductive layer (25). Through this, a conductive laminate with reduced electrical resistance may be provided.

[0047] Hereinafter, a semiconductor device according to exemplary embodiments is described with reference to FIGS. 1 to 15. In FIGS. 6 to 15, a Dynamic Random-Access Memory (DRAM) is described as an example of a semiconductor device, but this is merely illustrative. A person skilled in the art to which the present invention pertains will understand that the technical concept of the present invention can also be applied to various other semiconductor devices including a conductive laminate, such as system LSI (large scale integration), flash memory, SRAM, EEPROM, PRAM, MRAM or RERAM, image sensors such as CIS (CMOS imaging sensor), MEMS (micro-electro-mechanical system), active devices, passive devices, etc.

[0048] FIG. 6 is a layout diagram for explaining a semiconductor device according to some embodiments. FIG. 7 is a cross-sectional view taken along AA of FIG. 6. FIG. 8 and FIG. 9 are various enlarged views for explaining the R1 region of FIG. 7. FIG. 10 is a cross-sectional view taken along BB of FIG. 6. For convenience of explanation, parts that overlap with those described above using FIG. 1 to 5b are briefly explained or omitted.

[0049] Referring to FIGS. 6 to 10, a semiconductor device according to some embodiments includes a second substrate (100), a device isolation pattern (102), a first gate dielectric film (105), a first gate electrode (110), a first capping pattern (115), a base insulating film (120), a first conductive pattern (130), a second capping pattern (137), a direct contact (DC), a spacer structure (140), a first contact pattern (BC1), a first landing pad (LP1), and a first data storage structure (190).

[0050] Since the second substrate (100) may be similar to the first substrate (10) described above using FIG. 1, a detailed description below is omitted.

[0051] The second substrate (100) may include a plurality of first active patterns (AR). The plurality of first active patterns (AR) may be defined by a device isolation pattern (102) within the second substrate (100). As the design rule of the semiconductor memory device decreases, each first active pattern (AR) may be formed in the shape of a diagonal bar. For example, as shown in FIG. 6, each first active pattern (AR) may be in the shape of a bar extending in a plane in which the first direction (X) and the second direction (Y) extend, and in a third direction (W) different from the first direction (X) and the second direction (Y).

[0052] The first active patterns (AR) may be in the form of multiple bars extending in directions parallel to each other. In some embodiments, the center of one of the first active patterns (AR) may be positioned adjacent to the end of another of the first active patterns (AR).

[0053] Each of the first active patterns (AR) may include different first parts (e.g., a center) and second parts (e.g., both ends). The first part and the second part may each be provided as source / drain regions containing impurities. In some embodiments, the first part (e.g., a center) may be connected to the first conductive pattern (130) via a direct contact (DC), and the second part (e.g., both ends) may be connected to the first data storage structure (190) via a first contact pattern (BC1) and / or a first landing pad (LP1).

[0054] A first gate electrode (110) may be formed on a second substrate (100) and a device isolation pattern (102). The first gate electrode (110) may intersect with first active patterns (AR) and a first conductive pattern (130). For example, the first gate electrode (110) may be extended in a second direction (Y) parallel to the upper surface of the second substrate (100), so as to obliquely cross the first active patterns (AR) and vertically cross the first conductive pattern (130). A plurality of first gate electrodes (110) may be spaced apart from each other and arranged along a first direction (X).

[0055] The first gate electrode (110) may cross the first active patterns (AR) between the direct contact (DC) and the first contact pattern (BC1). For example, the first gate electrode (110) may cross the region of the first active patterns (AR) interposed between the first part of the first active patterns (AR) (e.g., the central part) and the second part of the first active patterns (AR) (e.g., both ends). The first gate electrode (110) may be provided as a word line of a semiconductor memory device according to some embodiments.

[0056] The first gate electrode (110) may be a single film, but may also be a multiple film as illustrated in FIG. 10. For example, the first gate electrode (110) may include a first electrode layer (111) and a second electrode layer (112) that are sequentially stacked on the second substrate (100) and the device isolation pattern (102). The first electrode layer (111) and the second electrode layer (112) may each include, for example, at least one of a metal, polysilicon, or a combination thereof, but are not limited thereto. For example, the first electrode layer (111) may include titanium nitride (TiN), and the second electrode layer (112) may include polysilicon doped with n-type impurities.

[0057] A first gate dielectric film (105) may be interposed between a first gate electrode (110) and a second substrate (100) (or, first active patterns (AR)). The first gate dielectric film (105) may comprise, for example, at least one of silicon oxide, silicon oxynitride, silicon nitride, and a high-k material having a dielectric constant greater than that of silicon oxide, but is not limited thereto.

[0058] A first capping pattern (115) may be formed on a first gate electrode (110). The first capping pattern (115) may extend along the upper surface of the first gate electrode (110). The first capping pattern (115) may include at least one insulating material, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or a combination thereof, but is not limited thereto. The first capping pattern (115) may be a single film or a multi-film composed of a combination of various types of insulating materials.

[0059] In some embodiments, the first gate electrode (110) may be embedded within the second substrate (100). For example, the second substrate (100) and the device isolation pattern (102) may include a gate trench (WT) that extends in a second direction (Y). The first gate dielectric film (105) may extend along the profile of the gate trench (WT). The first gate electrode (110) may fill a portion of the gate trench (WT) on the first gate dielectric film (105). The first capping pattern (115) may fill another portion of the gate trench (WT) on the first gate electrode (110). In this case, the upper surface of the first gate electrode (110) may be formed lower than the upper surface of the second substrate (100).

[0060] A base insulating film (120) may be formed on a second substrate (100) and a device isolation pattern (102). The base insulating film (120) may be interposed between the second substrate (100) and the first conductive pattern (130) and between the device isolation pattern (102) and the first conductive pattern (130).

[0061] The base insulating film (120) may be a single film, but may also be a multiple film as shown in FIGS. 7 and FIGS. 10. For example, the base insulating film (120) may include a first insulating film (122), a second insulating film (124), and a third insulating film (126) that are stacked sequentially on the second substrate (100) and the device isolation pattern (102). For example, the first insulating film (122) may include a silicon oxide film, the second insulating film (124) may include a silicon nitride film, and the third insulating film (126) may include a silicon oxide film.

[0062] A first conductive pattern (130) may be formed on a second substrate (100), a device isolation pattern (102), and a base insulating film (120). The first conductive pattern (130) may intersect with first active patterns (AR) and a first gate electrode (110). For example, the first conductive pattern (130) may be extended in a first direction (X) to obliquely cross the first active patterns (AR) and vertically cross the first gate electrode (110). A plurality of first conductive patterns (130) may be spaced apart from each other and arranged along a second direction (Y). The first conductive pattern (130) may be provided as a bit line of a semiconductor memory device according to some embodiments.

[0063] The first conductive pattern (130) may be a conductive laminate formed by stacking a plurality of conductive layers. For example, the first conductive pattern (130) may include a first conductive layer (131), a second conductive layer (132), a third conductive layer (133), a fourth conductive layer (134), and a fifth conductive layer (135) that are stacked sequentially on the first active patterns (AR) and / or the base insulating film (120).

[0064] In some embodiments, the conductive laminate of FIG. 1 may be provided as a first conductive pattern (130). For example, as shown in FIG. 8, the first conductive layer (131), the second conductive layer (132), the third conductive layer (133), the fourth conductive layer (134), and the fifth conductive layer (135) may correspond to the lower conductive layer (21), the barrier conductive layer (22), the insertion layer (23), the first upper conductive layer (24), and the second upper conductive layer (25) of FIG. 1, respectively. For example, the first conductive layer (131) may include a polysilicon film (poly-Si), the second conductive layer (132) may include titanium (Ti), the third conductive layer (133) may include a tungsten silicide nitride film (WSiN), the fourth conductive layer (134) may include a tungsten film (W), and the fifth conductive layer (135) may include a molybdenum film (Mo).

[0065] In some embodiments, as illustrated in FIG. 9, the third conductive layer (133) may include a first sub-conductive layer (133a) and a second sub-conductive layer (133b). The first sub-conductive layer (133a) and the second sub-conductive layer (133b) may have different nitrogen concentrations. For example, the first sub-conductive layer (133a) and the second sub-conductive layer (133b) may correspond to the first sub-insertion layer (23a) and the second sub-insertion layer (23b) of FIG. 1, respectively.

[0066] A second capping pattern (137) may be formed on the first conductive pattern (130). The second capping pattern (137) may extend along the upper surface of the first conductive pattern (130). The second capping pattern (137) may be a single film, but may also be a multiple film as illustrated. For example, the second capping pattern (137) may include a first capping layer (138) and a second capping layer (139) that are sequentially stacked on the first conductive pattern (130). The first capping layer (138) and the second capping layer (139) may each include an insulating material, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or a combination thereof, but are not limited thereto. For example, the first capping layer (138) and the second capping layer (139) may each include silicon nitride.

[0067] A direct contact (DC) may be formed on the first active patterns (AR). The direct contact (DC) may connect the first active patterns (AR) and the first conductive pattern (130). For example, the second substrate (100) may include a first contact trench (CT1) that penetrates the base insulating film (120) to expose the first portion (e.g., center) of the first active patterns (AR). The direct contact (DC) may be formed within the first contact trench (CT1) to electrically connect the first portion (e.g., center) of the first active patterns (AR) and the first conductive pattern (130). In some embodiments, the first conductive layer (131) of the first conductive pattern (130) may be connected to the first portion (e.g., center) of the first active patterns (AR) through the direct contact (DC).

[0068] The direct contact (DC) may comprise at least one of a conductive material, for example, polysilicon, TiN, TiSiN, tungsten, tungsten silicide, or a combination thereof, but is not limited thereto. In some embodiments, the direct contact (DC) may be formed at the same level as the first conductive layer (131). In this specification, "same level" means formed by the same manufacturing process. For example, the first conductive layer (131) and the direct contact (DC) may have the same material composition.

[0069] A spacer structure (140) may be formed on the side of the first conductive pattern (130). The spacer structure (140) may extend along the side of the first conductive pattern (130) and the side of the second capping pattern (137).

[0070] The spacer structure (140) may include at least one insulating material, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or a combination thereof, but is not limited thereto.

[0071] In some embodiments, the spacer structure (140) may be a multilayer made of a combination of various types of insulating materials. For example, the spacer structure (140) may include a base spacer (141), a first buried spacer (142), a second buried spacer (143), a first side spacer (144), and a second side spacer (145).

[0072] A base spacer (141) may be formed on the side of the first conductive pattern (130). For example, the base spacer (141) may be conformally extended along the profile of at least a portion of the side of the first conductive pattern (130) and the side of the second capping pattern (137).

[0073] The first buried spacer (142) may be formed on the base spacer (141) within the first contact trench (CT1). For example, the first buried spacer (142) may be conformally extended along the profile of the base spacer (141) within the first contact trench (CT1).

[0074] The second buried spacer (143) may be formed on the first buried spacer (142) within the first contact trench (CT1). For example, the second buried spacer (143) may fill the area of ​​the first contact trench (CT1) remaining after the base spacer (141) and the first buried spacer (142) are formed.

[0075] The first side spacer (144) may be formed on the outer surface of the base spacer (141). Additionally, the first side spacer (144) may be formed on the first buried spacer (142) and the second buried spacer (143). For example, the first side spacer (144) may extend conformally along a portion of the side of the second capping pattern (137) and the profile of the side of the first conductive pattern (130).

[0076] A second side spacer (145) may be formed on the outer surface of the first side spacer (144). Additionally, the first side spacer (144) may be formed on the second embedded spacer (143). For example, the second side spacer (145) may extend conformally along a portion of the side of the second capping pattern (137) and the profile of the side of the first conductive pattern (130).

[0077] A first contact pattern (BC1) may be formed on a second substrate (100), a device isolation pattern (102), and a spacer structure (140). The first contact pattern (BC1) may be spaced apart from the first conductive pattern (130) and connected to the first active patterns (AR). For example, the second substrate (100) may include a second contact trench (CT2) that penetrates the base insulating film (120) to expose the second portion (e.g., both ends) of the first active patterns (AR). The first contact pattern (BC1) may be formed within the second contact trench (CT2) and connected to the second portion (e.g., both ends) of the first active patterns (AR).

[0078] A first contact pattern (BC1) may be formed on the side of the first conductive pattern (130). Additionally, the first contact pattern (BC1) may be spaced apart from the first conductive pattern (130) by a spacer structure (140). For example, as shown in FIG. 7, the first contact pattern (BC1) may extend along a portion of the outer surface of the spacer structure (140). In some embodiments, the upper surface of the first contact pattern (BC1) may be formed lower than the upper surface of the second capping pattern (137).

[0079] The first contact pattern (BC1) can form a plurality of isolated regions spaced apart from each other. For example, as shown in FIG. 6, a plurality of first contact patterns (BC1) may be interposed between a plurality of first conductive patterns (130) and between a plurality of first gate electrodes (110) in a planar view. In some embodiments, the plurality of first contact patterns (BC1) may be arranged in a lattice structure.

[0080] The first contact pattern (BC1) may include at least one of a conductive material, for example, polysilicon, TiN, TiSiN, tungsten, tungsten silicide, or a combination thereof, but is not limited thereto. For example, the first contact pattern (BC1) may include polysilicon.

[0081] A first landing pad (LP1) may be formed on a first contact pattern (BC1). The first landing pad (LP1) may be connected to the first contact pattern (BC1). In some embodiments, the first landing pad (LP1) may be positioned to overlap at least a portion of the first contact pattern (BC1) in a fourth direction (Z) that intersects the upper surface of the second substrate (100). For example, a portion of the first landing pad (LP1) may overlap the first contact pattern (BC1), and another portion of the first landing pad (LP1) may overlap a portion of the spacer structure (140) and a portion of the second capping pattern (137).

[0082] The first landing pad (LP1) may include at least one of a conductive material, for example, polysilicon, TiN, TiSiN, tungsten, tungsten silicide, or a combination thereof, but is not limited thereto. For example, the first landing pad (LP1) may include tungsten (W).

[0083] The first landing pad (LP1) may form a plurality of isolated regions spaced apart from one another. For example, a pad trench (PT) defining a plurality of first landing pads (LP1) may be formed. The pad trench (PT) may extend from the upper surface of the first landing pad (LP1) and may be formed such that its lower surface is lower than the upper surface of the spacer structure (140). Additionally, at least a portion of the pad trench (PT) may be positioned to overlap with at least a portion of the spacer structure (140). For example, the pad trench (PT) may overlap with a portion of the spacer structure (140) and a portion of the second capping pattern (137). Through this, the plurality of first landing pads (LP1) may be separated from one another by the pad trench (PT).

[0084] In some embodiments, a separation pattern (180) filling the pad trench (PT) may be formed. The separation pattern (180) may include at least one of an insulating material, for example, silicon oxide, silicon oxynitride, silicon nitride, and a low-dielectric (low-k) material having a dielectric constant smaller than that of silicon oxide, but is not limited thereto. A plurality of first landing pads (LP1) may be electrically separated from each other by the separation pattern (180).

[0085] In some embodiments, a plurality of first landing pads (LP1) may be arranged in a honeycomb structure. The first landing pads (LP1) arranged in a honeycomb structure can further improve the integration density of the semiconductor memory device.

[0086] A first data storage structure (190) may be formed on a separation pattern (180) and a first landing pad (LP1). The first data storage structure (190) may be connected to the upper surface of the first landing pad (LP1). For example, the separation pattern (180) may be patterned to expose at least a portion of the upper surface of the first landing pad (LP1). The first data storage structure (190) may be connected to at least a portion of the upper surface of the first landing pad (LP1) exposed by the separation pattern (180). The first data storage structure (190) may be electrically connected to the first contact pattern (BC1) and the first landing pad (LP1) with the second portion (e.g., both ends) of the first active patterns (AR).

[0087] The first data storage structure (190) can store data by being controlled by a first gate electrode (110) provided as a word line and a first conduction pattern (130) provided as a bit line.

[0088] In some embodiments, the first data storage structure (190) may include a first lower electrode (192), a first capacitor dielectric film (194), and a first upper electrode (196) that are sequentially stacked on the first landing pad (LP1). The first data storage structure (190) may store charge within the first capacitor dielectric film (194) using the potential difference generated between the first lower electrode (192) and the first upper electrode (196).

[0089] The first lower electrode (192) and the first upper electrode (196) may each comprise, for example, doped polysilicon, a metal, or a metal nitride, but are not limited thereto. Additionally, the first capacitor dielectric film (194) may comprise, for example, silicon oxide or a high dielectric constant material having a dielectric constant greater than that of silicon oxide, but is not limited thereto.

[0090] FIG. 11 is a layout diagram for explaining a semiconductor device according to some embodiments. FIG. 12 is a cross-sectional view taken along CC of FIG. 11. FIG. 13 and FIG. 14 are various enlarged views for explaining the R2 region of FIG. 12. FIG. 15 is a cross-sectional view taken along DD of FIG. 11. For convenience of explanation, parts that overlap with those described above using FIG. 1 to FIG. 5b are briefly explained or omitted.

[0091] Referring to FIGS. 11 to 15, a semiconductor device according to some embodiments includes a plurality of second active patterns (210), a second gate dielectric film (230), a back gate electrode (240), a second gate electrode (250), a second contact pattern (BC2), a second landing pad (LP2), a second data storage structure (280), an upper insulating film (290), a second conductive pattern (310), a third capping pattern (320), a liner film (340), a spacer film (345), a shield conductive film (350), and a lower insulating film (360).

[0092] A plurality of second active patterns (210) may be arranged two-dimensionally along a horizontal plane. For example, the second active patterns (210) may be arranged in a matrix form along a first direction (X) and a second direction (Y) that intersect each other.

[0093] Each of the second active patterns (210) may be extended in a vertical direction. For example, each of the second active patterns (210) may be extended in a fourth direction (Z) that intersects the first direction (X) and the second direction (Y). The height of each of the second active patterns (210) extending in the fourth direction (Z) may be greater than the width of each of the second active patterns (210) (e.g., width in the first direction (X) and / or width in the second direction (Y)). The height of each of the second active patterns (210) may be about 2 to about 10 times the width of each of the second active patterns (210), but is not limited thereto. Each of the second active patterns (210) may be provided as a channel region of a vertical channel transistor (VCT). The vertical channel transistor may refer to a structure in which the channel length of the channel layer extends in a vertical direction (e.g., the fourth direction (Z)).

[0094] In some embodiments, a plurality of second active patterns (210) may include a first column (210A) and a second column (210B). The first column (210A) and the second column (210B) may each include a first column of second active patterns (210) arranged along a second direction (Y). The first column (210A) and the second column (210B) may be arranged alternately along a first direction (X).

[0095] Each of the second active patterns (210) may include a semiconductor material. For example, each of the second active patterns (210) may include an elemental semiconductor material such as monocrystalline silicon (210), polycrystalline silicon (210), amorphous silicon (210), silicon germanium (SiGe), SGOI (silicon germanium on insulator), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Alternatively, for example, each of the second active patterns (210) may include a metal oxide semiconductor material such as IGZO (indium gallium zinc oxide) or ITZO (indium tin zinc oxide).

[0096] The second active patterns (210) may each comprise a single layer or a multilayer of the semiconductor material. In some embodiments, the second active patterns (210) may each comprise a single crystal semiconductor material. For example, the second active patterns (210) may each comprise single crystal silicon.

[0097] Each of the second active patterns (210) may include different third parts (e.g., lower) and fourth parts (e.g., upper). In some embodiments, the third part (e.g., lower) may be connected to the second conductive pattern (310), and the fourth part (e.g., upper) may be connected to the second data storage structure (280) through the second contact pattern (BC2) and / or the second landing pad (LP2).

[0098] The second gate dielectric film (230) may surround the sides of each of the second active patterns (210). In some embodiments, the second gate dielectric film (230) may include a first dielectric film (232) and a second dielectric film (234). The first dielectric film (232) and the second dielectric film (234) may each extend in a second direction (Y). The first dielectric film (232) may be interposed between the second active patterns (210) and the back gate electrode (240). The second dielectric film (234) may be interposed between the second active patterns (210) and the second gate electrode (250). The first dielectric film (232) and the second dielectric film (234) may each include, for example, at least one of silicon oxide, silicon oxynitride, and a high-k material with a dielectric constant higher than that of silicon oxide, or a combination thereof, but are not limited thereto.

[0099] A second gate electrode (250) may be formed on the side of each second active pattern (210). The second gate electrode (250) may be spaced apart from each second active pattern (210) by a second dielectric film (234).

[0100] The second gate electrode (250) may intersect with each of the second active patterns (210). For example, the second gate electrode (250) may be extended in the second direction (Y). A plurality of second gate electrodes (250) may be spaced apart from each other in the first direction (X) and extended side by side (or parallel) in the second direction (Y). The second gate electrode (250) may be provided as a word line of a semiconductor memory device according to some embodiments.

[0101] The second gate electrode (250) may comprise at least one of a conductive material, for example, doped polysilicon, a metal, a conductive metal nitride, a conductive metal silicide, a conductive metal oxide, or a combination thereof. For example, the second gate electrode (250) may comprise doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x , RuO x or may include at least one combination thereof, but is not limited thereto.

[0102] In some embodiments, the lower surface of the second gate electrode (250) may be formed higher than the lower surface of each of the second active patterns (210). For example, as shown in FIG. 12, a first lower spacer (252) may be formed on the lower surface of the second gate electrode (250). The second gate electrode (250) may be spaced apart from the second conductive pattern (310) in the fourth direction (Z) by the first lower spacer (252).

[0103] In some embodiments, the upper surface of the second gate electrode (250) may be formed lower than the upper surface of each of the second active patterns (210). For example, as shown in FIG. 12, a first upper spacer (254) may be formed on the upper surface of the second gate electrode (250). The second gate electrode (250) may be spaced apart from the second contact pattern (BC2) and / or the etch stop layer (262) in the fourth direction (Z) by the first upper spacer (254).

[0104] The first lower spacer (252) and the first upper spacer (254) may each comprise at least one insulating material, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or a combination thereof, but are not limited thereto. The first lower spacer (252) and the first upper spacer (254) may each be a single film made of one type of insulating material, or a multi-film made of a combination of several types of insulating materials.

[0105] In some embodiments, the second gate electrode (250) may include a first sub-gate electrode (250A) and a second sub-gate electrode (250B). The first sub-gate electrode (250A) may intersect with each of the second active patterns (210) of the first column (210A), and the second sub-gate electrode (250B) may intersect with each of the second active patterns (210) of the second column (210B). For example, the first sub-gate electrode (250A) may be placed on the side of the first column (210A) facing the second column (210B), and the second sub-gate electrode (250B) may be placed on the side of the second column (210B) facing the first column (210A).

[0106] The first sub-gate electrode (250A) and the second sub-gate electrode (250B) may be spaced apart from each other in the first direction (X). For example, as shown in FIG. 15, a separation spacer (256) may be formed between the first sub-gate electrode (250A) and the second sub-gate electrode (250B). The separation spacer (256) may be extended in the second direction (Y) to separate the first sub-gate electrode (250A) and the second sub-gate electrode (250B) in the first direction (X).

[0107] The back gate electrode (240) may be disposed on the side of each second active pattern (210). The back gate electrode (240) may be spaced apart from each second active pattern (210) by the first dielectric film (232).

[0108] The back gate electrode (240) may intersect with each of the second active patterns (210). For example, the back gate electrode (240) may be extended in the second direction (Y). A plurality of back gate electrodes (240) may be spaced apart from each other in the first direction (X) and extended side by side (or parallel) in the second direction (Y).

[0109] The back gate electrode (240) may comprise at least one of a conductive material, for example, doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof. For example, the back gate electrode (240) may comprise doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x , RuO x or may include at least one combination thereof, but is not limited thereto.

[0110] In some embodiments, the lower surface of the back gate electrode (240) may be formed higher than the lower surface of each of the second active patterns (210). For example, as shown in FIG. 15, a second lower spacer (242) may be formed on the lower surface of the back gate electrode (240). The back gate electrode (240) may be spaced apart from the second conductive pattern (310) in the fourth direction (Z) by the second lower spacer (242).

[0111] In some embodiments, the upper surface of the back gate electrode (240) may be formed lower than the upper surface of each of the second active patterns (210). For example, as shown in FIG. 15, a second upper spacer (244) may be formed on the upper surface of the back gate electrode (240). The back gate electrode (240) may be spaced apart from the second contact pattern (BC2) and / or the etch stop layer (262) in the fourth direction (Z) by the second upper spacer (244).

[0112] The second lower spacer (242) and the second upper spacer (244) may each comprise at least one insulating material, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or a combination thereof, but are not limited thereto. The second lower spacer (242) and the second upper spacer (244) may each be a single film made of one type of insulating material, or a multi-film made of a combination of several types of insulating materials.

[0113] In some embodiments, the first column (210A) and the second column (210B) may share a single back gate electrode (240). For example, the first column (210A) may be placed on one side of the back gate electrode (240), and the second column (210B) may be placed on the other side of the back gate electrode (240).

[0114] The second contact pattern (BC2) may be connected to the fourth portion (e.g., the upper portion) of each second active pattern (210). For example, the second contact pattern (BC2) may be formed on the upper surface of each second active pattern (210). For example, an etch stop layer (262) and a first interlayer insulating layer (264) may be stacked sequentially on the second active patterns (210). The second contact pattern (BC2) may penetrate the etch stop layer (262) and the first interlayer insulating layer (264) to contact the upper surface of each second active pattern (210).

[0115] The second contact pattern (BC2) may include at least one of a conductive material, for example, doped polysilicon, conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal silicide, conductive metal oxide, two-dimensional material, metal, or a combination thereof, but is not limited thereto.

[0116] A second landing pad (LP2) may be formed on the upper surface of a second contact pattern (BC2). The second landing pad (LP2) may be connected to the second contact pattern (BC2). For example, a second interlayer insulating film (266) may be laminated on the upper surface of a first interlayer insulating film (264). The second landing pad (LP2) may penetrate the second interlayer insulating film (266) and come into contact with the upper surface of the second contact pattern (BC2).

[0117] The second landing pad (LP2) may include at least one of a conductive material, for example, doped polysilicon, conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal silicide, conductive metal oxide, two-dimensional material, metal, or a combination thereof, but is not limited thereto.

[0118] The second data storage structure (280) may be formed on the upper surface of the second landing pad (LP2) and the upper surface of the second interlayer insulating film (266). The second data storage structure (280) may be connected to the second landing pad (LP2). The second data storage structure (280) may be electrically connected to the fourth portion (e.g., upper) of the second active patterns (210) through the second contact pattern (BC2) and the second landing pad (LP2).

[0119] The second data storage structure (280) can store data by being controlled by a second gate electrode (250) provided as a word line and a second conduction pattern (310) provided as a bit line.

[0120] In some embodiments, the second data storage structure (280) may include a second lower electrode (282), a second capacitor dielectric film (284), and a second upper electrode (286) that are sequentially stacked on the second landing pad (LP2). The second data storage structure (280) may store charge within the second capacitor dielectric film (284) using the potential difference generated between the second lower electrode (282) and the second upper electrode (286).

[0121] The second lower electrode (282) and the second upper electrode (286) may each comprise, for example, doped polysilicon, a metal, or a metal nitride, but are not limited thereto. Additionally, the second capacitor dielectric film (284) may comprise, for example, silicon oxide or a high dielectric constant material having a dielectric constant greater than that of silicon oxide, but is not limited thereto.

[0122] The upper insulating film (290) may be laminated on the second data storage structure (280). The upper insulating film (290) may cover at least a portion of the second data storage structure (280). The upper insulating film (290) may comprise, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or a combination thereof, but is not limited thereto.

[0123] A second conductive pattern (310) may be formed on the lower surface of each second active pattern (210). The second conductive pattern (310) may be connected to the third portion (e.g., the lower portion) of each second active pattern (210). The second conductive pattern (310) may intersect with the second gate electrode (250). For example, the second conductive pattern (310) may be extended in a first direction (X). A plurality of second conductive patterns (310) may be spaced apart from each other in the second direction (Y) and extended side by side (or parallel) in the first direction (X). Each second conductive pattern (310) may be connected in common with a row of second active patterns (210) arranged along the first direction (X). The second conductive pattern (310) may be provided as a bit line of a semiconductor memory device according to some embodiments.

[0124] The second conductive pattern (310) may be a conductive laminate formed by stacking a plurality of conductive layers. For example, the second conductive pattern (310) may include a sixth conductive layer (311), a seventh conductive layer (312), an eighth conductive layer (313), a ninth conductive layer (314), and a tenth conductive layer (315) that are stacked sequentially on the lower surface of the second active patterns (210).

[0125] In some embodiments, the conductive laminate of FIG. 1 may be provided as a second conductive pattern (310). For example, as shown in FIG. 13, the sixth conductive layer (311), the seventh conductive layer (312), the eighth conductive layer (313), the ninth conductive layer (314), and the tenth conductive layer (315) may correspond to the lower conductive layer (21), the barrier conductive layer (22), the insertion layer (23), the first upper conductive layer (24), and the second upper conductive layer (25) of FIG. 1, respectively. For example, the sixth conductive layer (311) may include a polysilicon film (poly-Si), the seventh conductive layer (312) may include titanium (Ti), the eighth conductive layer (313) may include a tungsten silicide nitride film (WSiN), the ninth conductive layer (314) may include a tungsten film (W), and the tenth conductive layer (315) may include a molybdenum film (Mo).

[0126] In some embodiments, the sixth conductive layer (311) of the second conductive pattern (310) may be in direct contact with the third portion (e.g., the lower portion) of the second active patterns (210).

[0127] In some embodiments, as illustrated in FIG. 14, the eighth conductive layer (313) may include a third sub-conductive layer (313a) and a fourth sub-conductive layer (313b). The third sub-conductive layer (313a) and the fourth sub-conductive layer (313b) may have different nitrogen concentrations. For example, the third sub-conductive layer (313a) and the fourth sub-conductive layer (313b) may correspond to the first sub-insertion layer (23a) and the second sub-insertion layer (23b) of FIG. 1, respectively.

[0128] The third capping pattern (320) may extend along the lower surface of the second conductive pattern (310). The third capping pattern (320) may extend in the first direction (X). The third capping pattern (320) may include an insulating material, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, and combinations thereof, but is not limited thereto.

[0129] The liner film (340) may be laminated under the second conductive pattern (310) and the third capping pattern (320). For example, the liner film (340) may be conformally extended along the profiles of the side and bottom of the third capping pattern (320), the side of the second conductive pattern (310), the bottom of the second gate dielectric film (230), the bottom of the first lower spacer (252), and the bottom of the second lower spacer (242).

[0130] The liner film (340) may include at least one insulating material, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, and combinations thereof, but is not limited thereto. For example, the liner film (340) may include a silicon nitride film.

[0131] A spacer membrane (345) can be laminated under a liner membrane (340). For example, the spacer membrane (345) can be conformally extended along the profiles of the side and bottom surfaces of the liner membrane (340).

[0132] The spacer film (345) may comprise at least one insulating material, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, and combinations thereof, but is not limited thereto. For example, the spacer film (345) may comprise a silicon oxide film.

[0133] A shield conductive film (350) may be laminated under a spacer film (345). At least a portion of the shield conductive film (350) may be interposed between second conductive patterns (310) arranged along a second direction (Y). For example, as shown in FIG. 12, the shield conductive film (350) may be formed to fill at least a portion of the area between one second conductive pattern (310) and another second conductive pattern (310). The shield conductive film (350) may be spaced apart from the second conductive patterns (310) by a liner film (340) and / or a spacer film (345).

[0134] The shield conductive film (350) may comprise at least one of a conductive material, for example, doped polysilicon, a metal, a conductive metal nitride, a conductive metal silicide, a conductive metal oxide, or a combination thereof. The shield conductive film (350) may reduce coupling noise between the second conductive patterns (310) in the second direction (Y). For example, a predetermined bias voltage (e.g., ground voltage) may be applied to the shield conductive film (350).

[0135] The lower insulating film (360) may be laminated below the shield conductive film (350). The lower insulating film (360) may cover at least a portion of the shield conductive film (350). The lower insulating film (360) may comprise, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or a combination thereof, but is not limited thereto.

[0136] Although embodiments of the present invention have been described above with reference to the attached drawings, the present invention is not limited to the above embodiments and can be manufactured in various different forms, and those skilled in the art will understand that the present invention can be implemented in other specific forms without changing the technical concept or essential features of the present invention. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0137] 10: First substrate 21: Lower conductive layer 22: Barrier Challenge Layer 23: Insertion layer 23a: First sub-insertion layer 23b: Second sub-insertion layer 24: First upper conductive layer 25: Second upper conductive layer

Claims

Claim 1 A conductive laminate comprising: a lower conductive layer; a barrier conductive layer on the lower conductive layer; an insert layer on the barrier conductive layer comprising a silicide nitride of a first metal element; a first upper conductive layer on the insert layer comprising the first metal element; and a second upper conductive layer on the first upper conductive layer comprising a second metal element different from the first metal element. Claim 2 A conductive laminate according to claim 1, wherein the thickness of the insertion layer is 25 Å to 100 Å. Claim 3 A conductive laminate according to claim 1, wherein the nitrogen concentration of the silicide nitride is 20 atomic% or more and less than 35 atomic%. Claim 4 A conductive laminate according to claim 1, wherein in the silicide nitride, the ratio of silicon atoms to metal atoms is 0.5 to 3.

0. Claim 5 A conductive laminate according to claim 1, wherein the electrical conductivity of the second metal element is greater than the electrical conductivity of the first metal element, and the electrical conductivity of the first metal element is such that the crystal grain size of the first upper conductive layer is greater than the crystal grain size of the second upper conductive layer. Claim 6 A conductive laminate according to claim 5, wherein the first metal element is tungsten (W) and the second metal element is molybdenum (Mo). Claim 7 A conductive laminate according to claim 1, wherein the insertion layer comprises a first sub-insertion layer and a second sub-insertion layer sequentially stacked on the barrier conductive layer, and the nitrogen concentration of the first sub-insertion layer is smaller than the nitrogen concentration of the second sub-insertion layer. Claim 8 A conductive laminate according to claim 7, wherein the nitrogen concentration of the first sub-insertion layer is less than 35 atomic% and the nitrogen concentration of the second sub-insertion layer is 45 atomic% to 65 atomic%. Claim 9 A conductive laminate comprising: a lower conductive layer comprising polysilicon (poly-Si); a barrier conductive layer comprising titanium (Ti) on the lower conductive layer; an insertion layer comprising tungsten silicide nitride (WSiN) on the barrier conductive layer; a first upper conductive layer comprising tungsten (W) on the insertion layer; and a second upper conductive layer comprising molybdenum (Mo) on the first upper conductive layer. Claim 10 A semiconductor memory device comprising: an active pattern; a bit line connected to a first portion of the active pattern; a capacitor structure connected to a second portion of the active pattern; and a word line intersecting the active pattern between the first portion and the second portion, wherein the bit line comprises a lower conductive layer connected to the active pattern; a barrier conductive layer on the lower conductive layer; an insertion layer comprising tungsten silicide nitride (WSiN) on the barrier conductive layer; a first upper conductive layer comprising tungsten (W) on the insertion layer; and a second upper conductive layer comprising molybdenum (Mo) on the first upper conductive layer.

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