display device

Abstract

A novel display device is provided. The first element layer has a first transistor. The first transistor has a semiconductor layer of silicon having a channel forming region. The second element layer has a second transistor. The second transistor has a semiconductor layer of metal oxide having a channel forming region. The first element layer is provided with a display driver and a processor circuit. The display driver has a latch circuit having a function of holding image data and an amplifier circuit having a function of outputting an analog voltage according to the image data. The processor circuit has an analog-to-digital conversion circuit that converts the analog voltage into a digital signal and an operation circuit that acquires a correction value according to the digital signal. The latch circuit has a function of correcting the analog voltage by adding the correction value to the image data.

Description

Technology Field

[0001] One embodiment of the present invention relates to a display device.

[0002] Furthermore, one embodiment of the present invention is not limited to the above technical fields. Examples of the technical fields of one embodiment of the present invention disclosed in this specification, etc. include semiconductor devices, display devices, light-emitting devices, capacitor devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, methods for driving the same, or methods for manufacturing the same. Background Technology

[0003] In recent years, there has been a demand for high-definition display devices. Devices requiring high-definition display devices include, for example, devices for Virtual Reality (VR), Augmented Reality (AR), Substitutional Reality (SR), or Mixed Reality (MR), which have been actively developed in recent years. VR, AR, SR, and MR are sometimes collectively referred to as xR.

[0004] In display devices used for xR, there is a demand for miniaturization along with high resolution. Examples of display devices for xR include light-emitting devices equipped with light-emitting elements such as organic EL (Electro-Luminescence) elements and light-emitting diodes (LEDs).

[0005] In a display device used for xR, a configuration that is multifunctional in addition to high resolution and miniaturization is proposed. For example, Patent Documents 1 and 2 disclose a configuration in which, in addition to a configuration for displaying an image such as a pixel circuit and a display driving circuit, a functional circuit having a function to perform computational processing such as image processing is integrally formed with the configuration of the pixel circuit and the display driving circuit. Prior art literature

[0006] International Publication WO2022 / 118141 International Publication WO2022 / 118151 The problem to be solved

[0007] In display devices used for xR, the pixel size per pixel is small. Therefore, the voltage of image data (analog voltage) applied to a single pixel is very small. If there is a large deviation in output voltage according to the input voltage between the amplifier circuits of each column that apply analog voltage to the signal line connected to the pixel circuit, a difference in potential occurs even if the analog voltage corresponds to the same grayscale level. As a result, there is a risk that the display quality of the display unit controlled by the analog voltage will be significantly degraded.

[0008] Regarding the correction of deviations between amplifier circuits, there is a configuration that provides capacitor and resistor elements to compensate for offset voltage. However, in a display device used for xR, there is a concern that the layout area may increase in a configuration where capacitor and resistor elements are provided in each column containing amplifier circuits. Furthermore, in a configuration that compensates for offset voltage, it is difficult to correct deviations between amplifier circuits in each column, for example, between amplifier circuits in adjacent columns.

[0009] One embodiment of the present invention has as its objective to provide a miniaturized display device. Alternatively, one embodiment of the present invention has as its objective to provide a display device with excellent display quality. Alternatively, one embodiment of the present invention has as its objective to provide a display device with excellent convenience. Alternatively, one embodiment of the present invention has as its objective to provide a novel display device.

[0010] Furthermore, the description of these problems does not interfere with the existence of other problems. Also, one embodiment of the present invention is not required to solve all of these problems. Additionally, problems other than these can be derived from the description in the specification, drawings, claims, etc. means of solving the problem

[0011] One embodiment of the present invention is a display device having a first element layer and a second element layer on the first element layer, wherein the first element layer has a first transistor, the first transistor has a semiconductor layer having a channel forming region made of silicon, the second element layer has a second transistor, the second transistor has a semiconductor layer having a channel forming region made of a metal oxide, and the first element layer is provided with a display driving unit and a processor circuit, the display driving unit has a latch circuit having a function of maintaining image data and an amplifier circuit having a function of outputting an analog voltage according to the image data, the processor circuit has an analog-to-digital conversion circuit that converts the analog voltage into a digital signal and an operation circuit that acquires a correction value according to the digital signal, and the latch circuit has a function of correcting the analog voltage by adding the correction value to the image data.

[0012] One embodiment of the present invention is a display device having a first element layer and a second element layer on the first element layer, wherein the first element layer has a first transistor, the first transistor has a semiconductor layer having a channel forming region made of silicon, the second element layer has a second transistor, and the second transistor has a semiconductor layer having a channel forming region made of a metal oxide, wherein the first element layer is provided with a display driving unit and a processor circuit, the display driving unit has a latch circuit having a function of maintaining image data and an amplifier circuit having a function of outputting an analog voltage according to the image data, the amplifier circuit is provided for each of a plurality of signal lines, and each of the plurality of signal lines is electrically connected to an analog-to-digital conversion circuit through a switch circuit, and the processor circuit has an analog-to-digital conversion circuit that converts an analog voltage into a digital signal and an operation circuit that acquires a correction value according to the digital signal, wherein the analog voltage is input to the analog-to-digital conversion circuit by sequentially turning on the switch circuit electrically connected to the plurality of signal lines, and the latch circuit has a function of correcting the analog voltage by adding the correction value to the image data.

[0013] In one embodiment of the present invention, the display driving unit preferably has a display device provided in an area overlapping with the display unit.

[0014] In one embodiment of the present invention, a display device is preferred in which the display driving unit has a gate line driving circuit and a source line driving circuit, and the processor circuit has a function of switching the driving frequency of the gate line driving circuit and the driving frequency of the source line driving circuit.

[0015] In one embodiment of the present invention, a display unit is provided on the second element layer, and the display unit has a pixel circuit that controls the light emission of a light-emitting element, and a display device is preferred in which the light-emitting element is provided on the second element layer.

[0016] In addition, other embodiments of the present invention other than those described above are described in the following embodiments and drawings. Effects of the invention

[0017] One embodiment of the present invention may provide a miniaturized display device. Alternatively, one embodiment of the present invention may provide a display device with excellent display quality. Alternatively, one embodiment of the present invention may provide a display device with excellent convenience. Alternatively, one embodiment of the present invention may provide a novel display device.

[0018] Furthermore, the description of these effects does not interfere with the existence of other effects. Also, one embodiment of the present invention does not necessarily have to possess all of these effects. Additionally, other effects may be derived from the description in the specification, drawings, claims, etc. Brief explanation of the drawing

[0019] Figure 1 (A) is a perspective view illustrating an example of the configuration of a display device, and Figure 1 (B) is a block diagram illustrating an example of the configuration of a display device. Figure 2 is a schematic diagram illustrating an example of the configuration of a display device. Figure 3 is a block diagram illustrating an example of the configuration of a display device. Figure 4 is a circuit diagram illustrating an example of the configuration of a display device. Figure 5 is a timing chart illustrating an example of the configuration of a display device. Figure 6 is a flowchart illustrating an example of the configuration of a display device. Figure 7 is a block diagram illustrating an example of the configuration of a display device. Figures 8 (A) to (C) are circuit diagrams illustrating examples of configurations of a display device. Figures 9 (A) to (C) are schematic diagrams illustrating examples of the configuration of a display device. Figures 10 (A) to (D) are circuit diagrams illustrating examples of configurations of a display device. Figures 11 (A) to (D) are circuit diagrams illustrating examples of configurations of a display device. Figures 12 (A) and (B) are circuit diagrams illustrating examples of the configuration of a display device. FIG. 13 is a block diagram illustrating an example of the configuration of a display device. FIG. 14 is a block diagram illustrating an example of the configuration of a display device. FIG. 15 is a schematic diagram illustrating an example of the configuration of a display device. Figures 16 (A) and (B) are block diagrams illustrating examples of the configuration of a display device. Figures 17 (A) to (C) are block diagrams illustrating examples of configurations of a display device. Figure 18 (A) is a perspective view illustrating an example of the configuration of a display device, and Figure 18 (B) is a block diagram illustrating an example of the configuration of a display device. FIG. 19 is a schematic diagram illustrating an example of the configuration of a display device. Figures 20 (A) to (H) are circuit diagrams illustrating examples of configurations of a display device. Figures 21 (A) and (B) are circuit diagrams illustrating examples of the configuration of a display device. Figure 22 (A) is a perspective view illustrating an example of the configuration of a display device, and Figure 22 (B) is a block diagram illustrating an example of the configuration of a display device. FIG. 23 is a schematic diagram illustrating an example of the configuration of a display device. Figures 24 (A) and (B) are schematic diagrams illustrating examples of the configuration of a display device. FIG. 25 is a cross-sectional schematic diagram illustrating an example of the configuration of a display device. FIG. 26 is a cross-sectional schematic diagram illustrating an example of the configuration of a display device. FIG. 27 is a cross-sectional schematic diagram illustrating an example of the configuration of a display device. FIG. 28 is a cross-sectional schematic diagram illustrating an example of the configuration of a display device. Figures 29 (A) to (E) are schematic diagrams illustrating examples of electronic devices. Specific details for implementing the invention

[0020] Embodiments are described below with reference to the drawings. However, it is readily understood by those skilled in the art that embodiments can be implemented in many different forms, and that their forms and details can be varied without departing from the intent and scope thereof. Therefore, the present invention is not to be interpreted as being limited to the description of the embodiments below.

[0021] In addition, the size, layer thickness, or area in the drawing may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. Also, the drawing is a schematic representation of an ideal example and is not limited to the shape or value shown in the drawing.

[0022] Furthermore, unless otherwise specifically stated in this specification, etc., off-current refers to the drain current when the transistor is in the off state (also referred to as the non-conducting state or cutoff state). Unless otherwise specifically stated, the off state refers to the voltage between the gate and source (V) in an n-channel transistor. gs ) is the threshold voltage (V th Lower than ) (in p-channel transistors, V th It refers to a higher state.

[0023] In this specification and other contexts, the term "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to simply as Oxide Semiconductors or OS), etc. For example, when a metal oxide is used in the active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. For example, when a transistor is described as an OS transistor, it may be rephrased as a transistor having a metal oxide or an oxide semiconductor.

[0024] (Embodiment 1)

[0025] A display device according to one embodiment of the present invention will be described.

[0026] <Configuration Example 1 of a Display Device>

[0027] FIG. 1 (A) and FIG. 2 are perspective views of a display device (100) according to one embodiment of the present invention. FIG. 1 (B) is a block diagram explaining the configuration of the display device (100). The display device (100) comprises a device layer (30) on a device layer (20) and a sealing substrate (40) on the device layer (30). Additionally, the device layer (30) comprises a display portion (31), and a light-emitting device layer (60) is provided between the sealing substrate (40) and the display portion (31). In FIG. 2, the device layer (20), the device layer (30), the light-emitting device layer (60), and the sealing substrate (40) are shown separately to make it easier to understand the configuration of the display device (100).

[0028] The element layer (20) is provided with, as an example, a display driving unit (22), a processor circuit unit (70), a memory unit (71), and a terminal unit (29).

[0029] The display driving unit (22), the processor circuit unit (70), and the memory unit (71) are composed of Si CMOS, for example, a transistor (Si transistor) having silicon in the channel forming region. The device layer (20) is a device layer having Si transistors. By configuring a plurality of circuits, such as the display driving unit (22), the processor circuit unit (70), and the memory unit (71), with Si transistors, each circuit, which is desirable for high integration density, can be provided to the device layer (20).

[0030] In addition, the device layer (20) can be configured to have various functional circuits, such as sensor circuits, communication circuits, and control circuits, by making the device layer (20) a device layer having Si transistors. In addition, by configuring the display driving unit (22), the processor circuit unit (70), and the memory unit (71) to be placed on the same layer, the processor circuit unit (70) and the memory unit (71) can be placed using the area of ​​the device layer (20) where the display driving unit (22) is not placed. Therefore, the degree of freedom of layout can be increased, such as by dispersing the processor circuit unit (70) and the memory unit (71) within the device layer (20).

[0031] For Si transistors, it is particularly desirable to use highly crystalline silicon, such as single-crystal or polycrystalline silicon, because this enables high field-effect mobility and allows for higher speed operation.

[0032] The display driving unit (22) provided in the device layer (20) is connected to the display unit (31) provided in the device layer (30). The display driving unit (22) has the function of supplying image data to the display unit (31). Various circuits such as a shift register circuit, a level shifter circuit, an inverter circuit, a latch circuit, an amplifier circuit, an analog switch circuit, or a logic circuit can be used in the display driving unit (22).

[0033] The latch circuit of the display driving unit (22) is a circuit that has the function of maintaining image data supplied to the display device (100). The amplifier circuit of the display driving unit (22) is a circuit that has the function of outputting an analog voltage based on image data supplied to the display unit (31) to the source line (signal line).

[0034] The latch circuit has a memory circuit that stores a correction value for correcting image data supplied to the display device (100). The correction value is data corresponding to the difference between the analog voltage output by the amplifier circuit based on the reference image data and the analog voltage output by supplying the reference image data to another amplifier circuit. The latch circuit has the function of correcting the analog voltage output by the amplifier circuit to the source line by correcting the image data supplied to the display device (100) according to the correction value. The correction value maintained in the memory circuit of the latch circuit is supplied from the processor circuit section (70).

[0035] A processor circuit (70) provided to the device layer (20) is connected to a memory unit (71) of the device layer (20) and has the function of executing processing based on a program and data maintained in the memory unit (71). The processor circuit (70) has an analog-to-digital conversion circuit for converting an analog voltage applied to the display unit (31) by the display driving unit (22) into digital data, and an operation circuit for obtaining a correction value to perform calculation processing based on the digital data and correct image data supplied to the display device (100).

[0036] The analog voltage input to the analog-digital circuit of the processor circuit (70) is the analog voltage that is the output of the amplifier circuit of the display driving unit (22). The amplifier circuit is provided in each column to apply an analog voltage based on image data to the pixel circuit. The analog voltage can be applied to the analog-digital circuit through the same wiring by turning the switch circuit on sequentially in each column. By applying analog voltages of different values ​​output from the amplifier circuits of each column to the analog-digital conversion circuit through the same wiring, conversion can be performed with reduced deviation due to the influence of the wiring.

[0037] In addition, in this specification, the direction in which source lines are provided is referred to as the column direction, and the direction in which gate lines are provided is referred to as the row direction. An amplifier circuit that applies an analog voltage to the source lines is provided in each column as described above.

[0038] In addition, in a configuration where different analog voltage values ​​output from each column's amplifier circuits are applied to an analog-to-digital conversion circuit, the analog voltage output from each column's amplifier circuit can be corrected based on a reference analog voltage. Therefore, deviations in output voltage between different columns' amplifier circuits can be corrected. Furthermore, in a configuration where different analog voltage values ​​output from each column's amplifier circuits are applied to an analog-to-digital conversion circuit, capacitors, resistors, etc., used to cancel offset voltage in the amplifier circuits can be reduced. Therefore, the circuit area required for the amplifier circuits can be reduced.

[0039] In the operation circuit of the processor circuit (70), a correction value is calculated based on digital data corresponding to the analog voltage output by the amplifier circuits of each column. The correction value is, for example, a value calculated as the difference between the digital data corresponding to the analog voltage output by the amplifier circuit that supplied the reference image data and the digital data corresponding to the analog voltage output by supplying the reference image data to another amplifier circuit. For example, the correction value for each column can be calculated by using the digital data corresponding to the analog voltage of the amplifier circuit of the first column as standard data and performing an operation on the difference between it and the digital data corresponding to the analog voltage of the amplifier circuits from the second column onwards. Alternatively, the operation circuit of the processor circuit (70) can calculate the average value of the analog voltage output by a plurality of amplifier circuits and perform an operation on the difference from the average value to calculate the correction value for each column. With the above configuration, correction can be performed even when the deviation of the analog voltage output from the amplifier circuits is small or large.

[0040] The correction value obtained from the operation circuit of the processor circuit (70) is supplied to the display driving unit (22) provided to the device layer (20) as described above, and by adding the correction value to the original image data, the image data can be corrected according to the deviation of the analog voltage between the amplifier circuits.

[0041] In one embodiment of the present invention, the image data in the display driving unit (22) can be corrected based on a correction value calculated by a processor circuit unit (70) provided within the display device (100). The correction value used for correcting the image data (output data) is calculated within the processor circuit unit (70) based on an analog voltage output by an amplifier circuit, and is maintained in a latch circuit of the display driving unit (22) provided in the same device layer (20) as the processor circuit unit (70). The above configuration can reduce the impact of signal delay compared to a configuration in which image data is corrected in a circuit outside the display device and then supplied to the display device. Furthermore, since the connection between the processor circuit unit (70) and the display driving unit (22) is performed through wiring within the same device layer (20), there is no influence from the bus width limitation that occurs when passing through an external circuit. Therefore, the data transmission rate regarding the correction value for the display driving unit (22) from the processor circuit unit (70) can be increased.

[0042] A memory unit (71) connected to a processor circuit unit (70) is equipped with a plurality of memory circuits (memory cells). Various types of memory devices can be used as the memory unit (71). For example, DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), Phase-Change Memory (PCM), Resistive Random Access Memory (ReRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FeRAM), Antiferroelectric Memory, etc., can be used.

[0043] The device layer (30) provided with the display portion (31) is a layer having an OS transistor. By configuring it as above, the display portion (31) having an OS transistor can be provided by stacking it with the device layer (20).

[0044] OS transistors have the characteristic of having very low off-current. Therefore, using OS transistors, especially as transistors supplied to pixel circuits, allows recorded data to be retained for a long period.

[0045] Metal oxides applied to OS transistors include In oxide, Zn oxide, Zn-Sn oxide, Ga-Sn oxide, In-Ga oxide, In-Zn oxide, In-M-Zn oxide (where M is Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf). In particular, when a metal oxide using Ga as M is adopted in an OS transistor, it is desirable because the transistor can be made with excellent electrical characteristics such as field-effect mobility by adjusting the ratio of the elements. In addition, the oxide containing indium and zinc may include one or more types selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.

[0046] In addition, a light-emitting element layer (60) is provided on the upper layer of the display portion (31) having the element layer (30), as shown in FIG. 2. The light-emitting element layer (60) has a plurality of light-emitting elements, and the light emission brightness is controlled by a pixel circuit (51) provided in the display portion (31). The light-emitting element layer (60) can also be considered as part of the display portion (31).

[0047] The display unit (31) is provided with a pixel (50) having a plurality of pixel circuits (51). The pixel (50) has a pixel circuit (51) and a light-emitting element (not shown) provided on a light-emitting element layer (60) above the pixel circuit (51). The pixel circuit (51) of the display unit (31) is configured to have an OS transistor. The pixel circuit (51) corresponds to a pixel circuit having a sub-pixel (sub-pixel) for performing color display. Detailed information regarding the pixel circuit (51) and the light-emitting element will be described later.

[0048] In addition, each of the three subpixels controls the amount of red light, green light, or blue light emitted. Furthermore, the color of light controlled by each of the three subpixels is not limited to a combination of red (R), green (G), and blue (B), but can be cyan (C), magenta (M), or yellow (Y). Also, the area of ​​each of the three subpixels does not have to be the same. If the luminous efficiency and reliability differ depending on the color of emission, the area of ​​the subpixel may be different for each color of emission.

[0049] Flexible printed circuits (FPCs), etc. are connected to the terminal portion (29). Although an example is shown in which the device layer (30) and the sealing substrate (40) are not formed in the area overlapping with the terminal portion (29), the terminal portion (29) may also be formed on the device layer (30).

[0050] In one embodiment of the present invention, a correction value is calculated in a processor circuit within a display device, and image data correction based on the correction value can be performed. Compared to a configuration in which an offset voltage is corrected in an amplifier circuit and an analog voltage output by the amplifier circuit is corrected, this configuration can reduce the layout area of ​​capacitor and resistor elements required for the configuration that corrects the offset voltage.

[0051] In addition, one embodiment of the present invention may be configured to calculate a correction value that corrects deviations between amplifier circuits in each column by sequentially converting the analog voltages output by the amplifier circuits in each column into digital data. In this case, for example, deviations in analog voltages output between adjacent amplifier circuits can be corrected. The configuration of one embodiment of the present invention is particularly effective in cases where the pixel size per pixel is small and the analog voltage applied to a single pixel is very small, such as in a display device used for xR devices. By one embodiment of the present invention, the display quality in a display unit controlled by analog voltage can be improved.

[0052] FIG. 3 is a block diagram illustrating an example configuration of a display driving unit (22), a processor circuit unit (70), and a display unit (31).

[0053] The display driving unit (22) has a gate line driving circuit (32) and a source line driving circuit (33). The circuit included in the gate line driving circuit (32) functions, for example, as a scan line driving circuit (gate line driving circuit). The circuit included in the source line driving circuit (33) functions, for example, as a signal line driving circuit (source line driving circuit). The gate line driving circuit (32) is a circuit that drives a gate line connected to a pixel circuit (51). The source line driving circuit (33) is a circuit that drives a source line connected to a pixel circuit (51).

[0054] As shown in FIG. 3, the source line driving circuit (33) has an LVDS (Low Voltage Differential Signaling) circuit (41), a series-to-parallel conversion circuit (42), a latch circuit (43), a level shifter circuit (44), a digital-to-analog conversion circuit (45), and an amplifier circuit (46).

[0055] The gate line driving circuit (32) of the display driving unit (22) is a circuit that outputs a timing signal to control the conduction state of a transistor whose gate is connected to the gate line in the pixel circuit.

[0056] The LVDS circuit (41) is a circuit for receiving data based on LVDS, which is a signal transmission means. LVDS is a communication technology capable of operating at a relatively high speed, and can reduce power consumption through small amplitude signals, reduce the number of wires, and mitigate the effects of noise. By receiving data via LVDS from outside the display device (100), it is possible to avoid being affected by noise such as EMI (Electro Magnetic Interference).

[0057] The serial-to-parallel conversion circuit (42) is connected to the LVDS circuit (41). The serial-to-parallel conversion circuit (42) can convert a single-ended signal from the LVDS circuit (41) into a parallel signal and supply it to the latch circuit (43).

[0058] The latch circuit (43) is a circuit for transmitting a signal supplied from the serial-to-parallel conversion circuit (42), for example, image data, to the level shifter circuit (44) as a certain data group. For example, the supplied image data is maintained sequentially, and one row of data from the display unit (31) is transmitted to the level shifter circuit (44) at the timing when the data is prepared.

[0059] The latch circuit (43) has a memory circuit (43M) that maintains data based on the correction value described above. The latch circuit (43) corrects the image data supplied to the latch circuit (43) according to the data maintained in the memory circuit (43M). The memory circuit (43M) can store data of the correction value according to the amplifier circuit (46) provided to each column. Correction of the image data can be performed, for example, by adding (or subtracting) the data of the correction value maintained in the memory circuit (43M) to the image data supplied to the latch circuit (43). The correction of the image data is based on the deviation of the analog voltage between the amplifier circuits of each column. Therefore, the signal transmitted from the latch circuit (43) to the level shifter circuit (44) can be image data with the deviation of the analog voltage between the amplifier circuits of each column corrected.

[0060] The level shifter circuit (44) is a circuit for increasing the signal level of image data output from the latch circuit (43), for example, the amplitude voltage of the signal. By the above configuration, the on or off state of the transistor in the subsequent digital-to-analog conversion circuit (45) can be controlled.

[0061] The digital-to-analog conversion circuit (45) is a circuit that converts digital image data into an analog voltage.

[0062] The amplifier circuit (46) is a circuit for amplifying the analog voltage supplied from the digital-to-analog conversion circuit (45). The amplifier circuit (46) supplies the analog voltage to the pixel circuit (51) through the wiring (SL) (also called the source line). Additionally, the amplifier circuit (46) supplies the analog voltage to the analog-to-digital conversion circuit (77) through the switch circuit (not shown) and the wiring (ACL).

[0063] The display unit (31) has a plurality of pixel circuits (51). A transistor, a capacitor, etc., can be used in the pixel circuit (51).

[0064] The processor circuit section (70) has an analog-to-digital conversion circuit (77) and an operation circuit (78). One terminal of the switch circuit is connected to the output terminal of the amplifier circuit (46) in each column. The other terminal of the switch circuit is connected to the wiring (ACL). The wiring (ACL) is connected to the analog-to-digital conversion circuit (77). Analog voltage is supplied to the analog-to-digital conversion circuit (77) through the switch circuit and the wiring (ACL). The analog-to-digital conversion circuit (77) converts the analog voltage into a digital signal and sequentially outputs it to the operation circuit (78). The operation circuit (78) calculates data (Dc) based on a correction value by performing calculations on the digital signal, and outputs and maintains the data (Dc) in the memory circuit (43M) described above.

[0065] FIG. 4 is a circuit diagram illustrating the connection between an analog-to-digital conversion circuit (77) and an amplifier circuit (46). FIG. 4 shows a digital-to-analog conversion circuit (45) (digital-to-analog conversion circuit (45_1 to 45_N)), an amplifier circuit (46) (amplifier circuit (46_1 to 46_N)), a switch circuit (47_1 to 47_N), a wiring (SL) (wiring (SL_1 to SL_N)), a wiring (ACL), a pixel circuit (51), a selection circuit (48), and an analog-to-digital conversion circuit (77) in a series of 1 to N (N is an integer greater than or equal to 2).

[0066] The selection circuit (48) is a circuit that outputs signals (SEL_1 to SEL_N) to sequentially turn on the switch circuits (47_1 to 47_N). In addition, although the switch circuits (47_1 to 47_N) in FIG. 4 are shown as analog switches as an example, other circuits that turn on or off the wiring (SL) and wiring (ACL) may also be used.

[0067] Additionally, FIG. 5 illustrates a timing chart to explain the operation of each circuit depicted in FIG. 4. FIG. 5 illustrates the signals (SEL_1, SEL_2, and SEL_N), the wiring (SL_1), the wiring (SL_2), the wiring (SL_N), and the signals or voltages of the wiring (ACL). Furthermore, signals (SEL_1) through (SEL_N) are described as being in the ON state at the H level and in the OFF state at the L level.

[0068] In the period from time (T00) to time (T01) shown in FIG. 5, the analog voltages of wiring (SL_1), wiring (SL_2), and wiring (SL_N) are each voltages (V SL_1 ), voltage (V SL_2 ), voltage (V SL_N It becomes.

[0069] During the period from time (T01) to time (T02) shown in FIG. 5, the signal (SEL_1) is set to the H level. The switch circuit (47_1) located between wiring (SL_1) and wiring (ACL) is turned on. The voltage of wiring (ACL) is the voltage (V) of wiring (SL_1). SL_1 ) becomes. Therefore, the voltage (V) in the analog-to-digital conversion circuit (77) is applied. SL_1 ) is supplied, and a digital signal according to the magnitude of the voltage is supplied to the operation circuit (78).

[0070] During the period from time (T02) to time (T03) shown in FIG. 5, the signal (SEL_2) is set to the H level. The switch circuit (47_2) located between the wiring (SL_2) and the wiring (ACL) is turned on. The voltage of the wiring (ACL) is the voltage (V) of the wiring (SL_2). SL_2 ) becomes. Therefore, the voltage (V) in the analog-to-digital conversion circuit (77) is applied. SL_2 ) is supplied, and a digital signal according to the magnitude of the voltage is supplied to the operation circuit (78). The operation circuit (78) is, for example, a voltage (V SL_1 ) and voltage (V SL_2 By calculating the difference of ), a correction value can be supplied to the latch circuit to correct the deviation of the analog voltage between the amplifier circuits (46_1, 46_2).

[0071] During the period from time (T04) to time (T05) shown in FIG. 5, the signal (SEL_N) is set to the H level. The switch circuit (47_N) located between the wiring (SL_N) and the wiring (ACL) is turned on. The voltage of the wiring (ACL) is the voltage (V) of the wiring (SL_N). SL_N ) becomes. Therefore, the voltage (V) in the analog-to-digital conversion circuit (77) is applied. SL_N ) is supplied, and a digital signal according to the magnitude of the voltage is supplied to the operation circuit (78).

[0072] In addition, FIG. 6 illustrates a flowchart explaining the operation of obtaining a correction value based on an analog voltage in the processor circuit (70) and maintaining it in the memory circuit (43M) of the latch circuit (43).

[0073] The step (S01) shown in FIG. 6 is the step of inputting standard data. Inputting standard data corresponds to supplying reference image data to the display device (100). The image data supplied to the display device (100) is data for the source line driving circuit (33) to output a predetermined analog voltage to the amplifier circuit of each column. Upon inputting the standard data, the wiring (SL) of each column is voltage (V SL It becomes.

[0074] The step (S02) shown in FIG. 6 is a step of sequentially outputting the analog voltages of the amplifier circuits from the first column to the Nth column. The voltage (V) output from the amplifier circuits (46) from the first column to the Nth column. SL ) has a deviation due to the performance of the amplifier circuit (46), etc. Therefore, V shown in FIG. 5 SL_1 , V SL_2 , V SL_N As shown, there is a variation in magnitude. Voltages with different values ​​are supplied to the analog-to-digital conversion circuit (77) sequentially through the wiring (ACL) from the first column by sequentially turning on the switch circuit (47) described in FIG. 4.

[0075] Step (S03) shown in FIG. 6 is a step of converting the analog voltages of amplifier circuits supplied sequentially into analog-to-digital data. The analog voltages of the amplifier circuits in the first to Nth column are sequentially converted into digital data and supplied to the operation circuit (78). Since the analog voltages output from other amplifier circuits (46) are supplied to the analog-to-digital conversion circuit (77) through the same wiring (ACL), the values ​​of the analog voltages of the amplifier circuits in other columns can be converted into digital data more accurately.

[0076] The step (S04) shown in FIG. 6 is a step for obtaining a correction value. Digital data corresponding to the analog voltages of the amplifier circuits in the first to Nth column can be used to calculate a correction value based on the deviation of the analog voltage between the amplifier circuits in the first to Nth column by calculating the difference between the reference data (e.g., digital data corresponding to the analog voltage of the amplifier circuit in the first column) and the digital data corresponding to the analog voltage of the amplifier circuits in the second column and beyond.

[0077] Step (S05) shown in FIG. 6 is a step of outputting a correction value to a latch circuit. The correction value, based on the deviation of the analog voltage between the first to Nth column amplifier circuits calculated by the operation circuit (78) of the processor circuit (70), is output to the latch circuit (43) within the display driving unit (22). Since the connection between the processor circuit (70) and the display driving unit (22) is performed through wiring within the same component layer (20), there is no influence from the bus width limitation that occurs when passing through an external circuit. Therefore, the data transmission rate regarding the correction value for the display driving unit (22) from the processor circuit (70) can be increased.

[0078] The step (S06) shown in FIG. 6 is a step of maintaining in the memory circuit of the latch circuit. The correction value is maintained in the memory circuit (43M) within the latch circuit (43). By the above configuration, the image data in the display driving unit (22) can be corrected based on the correction value calculated in the processor circuit unit (70) provided in the display device (100).

[0079] In addition, the configuration of one embodiment of the present invention is not limited to the configuration described in FIG. 1 (A) to FIG. 6. For example, it may be configured to output data based on a correction value calculated by the processor circuit to an external image data correction circuit.

[0080] In the display device (100) shown in FIG. 7, a configuration is illustrated in which data (Dc) based on a correction value calculated by an operation circuit (78) having a processor circuit (70) is output to an image data correction circuit (80) outside the display device (100) through a terminal (29).

[0081] The image data correction circuit (80) has the function of generating corrected image data based on data (Dc) based on a correction value supplied from the display device (100). The corrected image data can be supplied to the display device (100) through the terminal section (29).

[0082] In the configuration of FIG. 7, data (Dc) based on a correction value for correcting the deviation of the analog voltage output from the amplifier circuits (46) calculated within the display device (100) is output to an image data correction circuit (80) outside the display device (100). In the above configuration, although the data (Dc) based on the correction value is output to an external circuit, the effect of signal degradation is minimal because the data (Dc) is digital data. In addition, since the acquisition of the data (Dc) based on the correction value is performed at a timing such as when the display device (100) starts up, the frequency of acquisition is low. Therefore, the effect caused by outputting the data (Dc) based on the correction value to the image data correction circuit (80) outside the display device (100) can be said to be small.

[0083] In the configuration of FIG. 7, a correction value can be calculated in the processor circuit section inside the display device described in FIG. 1 (A) to FIG. 6, and image data correction can be performed according to the correction value. Compared to a configuration in which an offset voltage is corrected in an amplifier circuit and an analog voltage output by an amplifier circuit is corrected, the layout area of ​​capacitor and resistor elements required for the configuration that corrects the offset voltage can be reduced.

[0084] In addition, the configuration of FIG. 7 can be configured to calculate a correction value that corrects the deviation between the amplifier circuits in each column by sequentially converting the analog voltages output by the amplifier circuits in each column described in FIG. 1 (A) to FIG. 6 into digital data. In this case, for example, the deviation of the analog voltage output between adjacent amplifier circuits can be corrected. A configuration of one embodiment of the present invention is particularly effective in cases where the pixel size per pixel is small and the analog voltage applied to a single pixel is very small, such as in a display device used for xR devices. By one embodiment of the present invention, the display quality in a display unit controlled by analog voltage can be improved.

[0085] <Specific example of a display drive unit>

[0086] Figure 8 (A) is a schematic diagram illustrating the connection relationship between the display driving unit (22) and the display unit (31). As described above, in one embodiment of the present invention, the display driving unit (22) and the display unit (31) are provided on different layers, so the display unit (31) can be provided on the display driving unit (22).

[0087] As described above, the display driving unit (22) has a gate line driving circuit (32) and a source line driving circuit (33). The gate line driving circuit (32) is connected to the pixel circuit (51) of the display unit (31) provided above via a wire (GL) (gate line). The source line driving circuit (33) is connected to the pixel circuit (51) of the display unit (31) provided above via a wire (SL) (source line).

[0088] In the display driving unit (22), the gate line driving circuit (32) and the source line driving circuit (33) are each provided in a vertically elongated (or horizontally elongated) rectangular shape. In this case, it is preferable that the processor circuit unit (70) in the device layer (20) be positioned to fill the area within the display driving unit (22) where the gate line driving circuit (32) and the source line driving circuit (33) are not provided, as shown in (B) of FIG. 8. By configuring it as above, the area where the processor circuit unit (70) and the display driving unit (22) are provided in the device layer (20) can be positioned without dividing it.

[0089] The schematic diagram shown in FIG. 8 (C) is an example configuration in which a group of display units (31), gate line driving circuits (32), and source line driving circuits (33) shown in FIG. 8 (A) are arranged side by side. The display units (31), gate line driving circuits (32), and source line driving circuits (33) are each arranged on a matrix of m rows and n columns (m and n are each integers greater than or equal to 1). In the present specification, etc., a section of 1 row and 1 column is referred to as a display unit (31[1,1]), and a section of m rows and n columns is referred to as a display unit (31[m,n]). The display units (31[1,1]) and the display units (31[m,n]) can be combined to form a display unit (31). Additionally, the display units (31[1,1]) and the display units (31[m,n]) may each be referred to as sub-display units. The display unit (31) can display a single image by combining a plurality of sub-display units. Figure 8 (C) shows the case where m is 4 and n is 4. The display unit (31) is divided into 16 sections. Each of the divided display units (31[1,1]) to display units (31[m,n]) has a gate line driving circuit (32) connected to the wiring (GL) and a source line driving circuit (33) connected to the wiring (SL).

[0090] By providing the display unit (31) and the display driving unit (22) in an overlapping area, the connection distance (wiring length) between the pixel circuit and the peripheral driving circuit can be made very short. As a result, since wiring resistance and parasitic capacitance are reduced, the time required for charging and discharging is shortened, enabling high-speed driving. In addition, power consumption can be reduced. Furthermore, miniaturization and weight reduction can be achieved.

[0091] Additionally, the display unit (31) is configured to have a gate line driving circuit (32) and a source line driving circuit (33) for each display unit (31[1,1]) to each display unit (31[m,n]). Accordingly, the display unit (31) can perform image rewriting for each display unit (31[1,1]) to each display unit (31[m,n]). For example, image data can be rewritten only in the section of the display unit (31) where a change in the image occurs, and image data can be maintained in the section where there is no change, thereby realizing a reduction in power consumption. For example, the number of image rewriting cycles per unit time in any one of the sub-display units (31[1,1]) to the display unit (31[m,n]) can be made less than the number of image rewriting cycles per unit time in the other sub-display unit, thereby realizing a reduction in power consumption.

[0092] Additionally, the display device (100) can individually set the driving frequency (frame frequency, frame rate, or refresh rate, etc.) for image display for each display unit (31[1,1]) to display unit (31[m,n]). Therefore, by combining with eye measurement (eye tracking), etc., foveated rendering, which is a type of drawing that sets the frame rate for each area differently according to the user's gaze, can be applied. Therefore, it is possible to configure the device to output an image with low load and excellent display quality.

[0093] A display device of one embodiment of the present invention can achieve low power consumption by stacking a pixel circuit and a display driving unit and varying the driving frequency for each divided display unit (31). For example, the driving frequency for each divided display unit (31) is varied according to the movement of the gaze. In addition, information regarding the movement of the gaze (gaze point G) can be obtained using a gaze measurement (gaze tracking) method, such as the Pupil Center Corneal Reflection method or the Bright / Dark Pupil Effect method. Alternatively, it may be obtained using a gaze measurement method using a laser or ultrasound.

[0094] Figure 9 (A) shows a display section (31) divided into 4 rows and 8 columns, i.e., 32 sections. Also, Figure 9 (A) shows a first area (S1) to a third area (S3) centered on the viewing point G. The display section (31) distributes each of the divided display sections (31) into either a first section (29A) that overlaps with the first area (S1) or the second area (S2) or a second section (29B) that overlaps with the third area (S3). The display section (31) distributes each of the divided display sections (31) into a first section (29A) or a second section (29B). In this case, the first section (29A) that overlaps with the first area (S1) and the second area (S2) is a display part that includes an area that overlaps with the viewing point G, and the second section (29B) is a display part located outside the first section (29A) and far from the user's viewing point G (see (B) in FIG. 9).

[0095] The operation of the gate line driving circuit (32) and source line driving circuit (33) of each of the divided display sections (31) can be controlled individually. For example, the display section corresponding to the second section (29B) is a section that overlaps with the third area (S3), which includes a stable viewing field, a guiding field, and an auxiliary field, and is a section with low user identification ability. Therefore, when displaying an image, even if the number of image data rewrites per unit time (hereinafter also referred to as "image rewrite count") of the display section belonging to the second section (29B) is made less than that of the display section corresponding to the first section (29A), the degradation of the actual display quality perceived by the user (hereinafter also referred to as "actual display quality") is small. Even if the driving frequency of the display section corresponding to the second section (29B) is made lower than the driving frequency of the display section corresponding to the first section (29A), the degradation of the actual display quality is small.

[0096] Lowering the driving frequency can reduce the power consumption of the display device. On the other hand, lowering the driving frequency also degrades the display quality. In particular, the display quality degrades when displaying video. According to one embodiment of the present invention, by making the driving frequency of the display unit corresponding to the second section (29B) lower than the driving frequency of the display unit corresponding to the first section (29A), it is possible to reduce the power consumption of the section with low user visibility while suppressing the deterioration of the actual display quality. According to one embodiment of the present invention, it is possible to achieve both the maintenance of display quality and the reduction of power consumption.

[0097] The driving frequency of the display unit corresponding to the first section (29A) can be 30Hz or higher and 500Hz or lower, preferably 60Hz or higher and 500Hz or lower. The driving frequency of the display unit corresponding to the second section (29B) is preferably lower than or equal to the driving frequency of the first section (29A), more preferably lower than or equal to 1 / 2 of the driving frequency of the display unit corresponding to the first section (29A), and more preferably lower than or equal to 1 / 5 of the driving frequency of the display unit corresponding to the first section (29A).

[0098] In addition, the outer part of the second section (29B) among the display sections corresponding to the third area (S3) may be set as the third section (29C) (see (C) in FIG. 9), and the driving frequency of the display section corresponding to the third section (29C) may be lower than that of the display section corresponding to the second section (29B). The driving frequency of the display section corresponding to the third section (29C) is preferably less than or equal to the driving frequency of the display section corresponding to the second section (29B), more preferably less than or equal to 1 / 2 of the driving frequency of the display section corresponding to the second section (29B), and more preferably less than or equal to 1 / 5 of the driving frequency of the display section corresponding to the second section (29B). Power consumption can be further reduced by significantly reducing the number of image rewrite cycles. In addition, the rewriting of image data may be stopped as necessary. Power consumption can be further reduced by stopping the rewriting of image data.

[0099] When performing this driving method, it is suitable to use a transistor with a very low off-current for the transistor constituting the pixel circuit (51). For example, it is suitable to use an OS transistor for the transistor constituting the pixel circuit (51). Since the OS transistor has a significantly low off-current, the image data supplied to the pixel circuit (51) can be maintained for a long period of time by stopping the output signal output by the gate line driving circuit.

[0100] In addition, there are cases where an image is displayed that is significantly different in brightness, contrast, or hue from the previous image, such as when the image scene displayed on the display unit (31) changes. In such cases, there is a difference in the timing of image switching between the first section (29A) and the section with a lower driving frequency than the first section (29A), so the brightness, contrast, or hue is significantly different between the two sections, and there is a risk that the actual display quality will be degraded. In such cases where the image scene changes, it is preferable to first rewrite the image in the section other than the first section (29A) at the same driving frequency as the first section (29A), and then lower the driving frequency of the section other than the first section (29A).

[0101] In addition, if it is determined that the amount of variation of the viewing point G exceeds a certain amount, the display unit other than the display unit corresponding to the first section (29A) may also perform image re-recording at the same driving frequency as the display unit corresponding to the first section (29A), and if it is determined that the amount of variation is within a certain amount, the driving frequency of the display unit other than the display unit corresponding to the first section (29A) may be lowered. In addition, if it is determined that the amount of variation of the viewing point G is small, the driving frequency of the display unit other than the display unit corresponding to the first section (29A) may be lowered further.

[0102] In addition, the divided display sections constituting the display section (31) are not limited to three sections: the first section (29A), the second section (29B), and the third section (29C). Four or more sections may be set in the display section (31). By setting multiple sections in the display section (31) and gradually lowering the driving frequency, the actual degradation of the display quality can be further reduced.

[0103] In addition, high-speed rewriting can be realized by simultaneously performing the rewriting of image data, which is performed for each divided display unit (31), on all divided display units.

[0104] In addition, in the display device (100) exemplified in this embodiment, the display portion (31) is divided into 8 sections in the column direction ((A) to (C) of FIG. 9), so the length of the wiring (GL) connecting the gate line driving circuit and the pixel circuit is reduced to one-eighth. Therefore, since the resistance value and parasitic capacitance of the wiring (GL) are each reduced to one-eighth, signal degradation and delay are improved, making it easier to secure the re-writing time for image data.

[0105] According to one embodiment of the present invention, the display device (100) enables high-speed re-recording of the display image because the recording time of the image data is shortened. Therefore, a display device with high display quality can be realized. In particular, a display device excellent for displaying video can be realized.

[0106] In addition, according to one embodiment of the present invention, the output signal output by the gate line driving circuit can be controlled independently for each divided display part by the display device (100), so the shape or size of the divided display parts can be made different from each other. As a result, the display part (31) can be composed of display parts with different shapes or sizes. Therefore, the configuration is not limited to a rectangular shape display part (31), but can be a display part with excellent design, such as a circular shape.

[0107] <Specific example of a pixel circuit>

[0108] FIGS. 10 (A) to FIGS. 12 (B) illustrate examples of the configuration of a pixel circuit applicable to a pixel circuit (51) and a light-emitting element connected to the pixel circuit (51). In addition, in the following description, the light-emitting element is not limited to an organic EL element and can be a self-emissive light-emitting device such as an LED, micro LED, QLED (Quantum-dot Light Emitting Diode), or semiconductor laser.

[0109] In addition, the term "element" may be replaced with "device" in the present specification and other documents. For example, a display element and a light-emitting element may be replaced with a display device and a light-emitting device, respectively.

[0110] The pixel circuit (51A) shown in FIG. 10 (A) has a transistor (55A), a transistor (55B), and a capacitor (56). FIG. 10 (A) also shows a light-emitting element (61) connected to the pixel circuit (51A). FIG. 10 (A) also shows a wiring (SL), wiring (GL), power line (ANO), and power line (VCOM).

[0111] The gate of the transistor (55A) is connected to the wire (GL), one of the source and drain is connected to the wire (SL), and the other is connected to the gate of the transistor (55B) and one electrode of the capacitor (56). One of the source and drain of the transistor (55B) is connected to the power line (ANO), and the other is connected to the anode of the light-emitting element (61). The other electrode of the capacitor (56) is connected to the anode of the light-emitting element (61). The cathode of the light-emitting element (61) is connected to the power line (VCOM). Additionally, the anode and cathode of the light-emitting element (61) can be appropriately changed by changing the magnitude of the supplied potential.

[0112] The pixel circuit (51B) shown in (B) of FIG. 10 has a configuration in which a transistor (55C) is added to the pixel circuit (51A). The gate of the transistor (55C) is connected to the wiring (GL), one of the source and drain is connected to the anode of the light-emitting element (61), and the other is connected to the wiring (V0).

[0113] The pixel circuit (51C) shown in (C) of FIG. 10 is an example in which a transistor having a pair of gates is applied to the transistors (55A) and (55B) of the pixel circuit (51A). Also, the pixel circuit (51D) shown in (D) of FIG. 10 is an example in which the transistor is applied to the pixel circuit (51B). By doing so, the current that can be flowed by the transistor can be increased. In addition, although a transistor having a pair of gates is applied to all transistors here, it is not limited thereto. It is also acceptable to apply a transistor having a pair of gates and in which they are connected to different wirings. For example, reliability can be increased by using a transistor in which one of the gates is connected to the source.

[0114] The pixel circuit (51E) shown in (A) of FIG. 11 has a configuration in which a transistor (55D) is added to the pixel circuit (51B). In addition, three gate lines (wire (GL1), wire (GL2), and wire (GL3)) are connected to the pixel circuit (51E).

[0115] The gate of transistor (55D) is connected to the wire (GL3), and one of the source and drain is connected to the gate of transistor (55B), and the other is connected to the wire (V0). Additionally, the gate of transistor (55A) is connected to the wire (GL1), and the gate of transistor (55C) is connected to the wire (GL2).

[0116] By making transistors (55C) and (55D) simultaneously conductive, the source and gate of transistor (55B) become at the same potential, so that when the threshold voltage of transistor (55B) is greater than 0V, transistor (55B) can be made non-conductive. By doing so, the current flowing through the light-emitting element (61) can be forcibly cut off. This pixel circuit is suitable for use in a display method that alternately provides a display period and a extinguishing period.

[0117] The pixel circuit (51F) shown in (B) of FIG. 11 is an example in which a capacitor (56A) is added to the pixel circuit (51E). The capacitor (56A) functions as a storage capacitor.

[0118] The pixel circuit (51G) shown in (C) of FIG. 11 and the pixel circuit (51H) shown in (D) of FIG. 11 are examples in which a transistor having a pair of gates is applied to the pixel circuit (51E) or pixel circuit (51F), respectively. As transistors (55A), (55C), and (55D), transistors with a pair of gates connected are applied, and as transistor (55B), a transistor with one of the gates connected to a source is applied.

[0119] FIGS. 11 (A) to (D) illustrates a configuration example in which each transistor is configured with only OS transistors, which are n-channel type transistors, but the present invention is not limited thereto. For example, a pixel circuit configuration having OS transistors and Si transistors may be used. Specifically, in the case of the pixel circuit (51A) of FIG. 10 (A), it is preferable to make the transistor (55A) an OS transistor and the transistor (55B) a Si transistor.

[0120] In addition, (A) of FIG. 12 shows an example of a circuit configuration of a pixel circuit (pixel circuit (51J)). FIG. 12 (B) is a schematic diagram showing the upper and lower relationships of a device layer (20) having a display driving unit (22), a device layer (30) having a pixel circuit (51), and a light-emitting device layer (60) having a light-emitting device (61).

[0121] The pixel circuit (51J) shown as an example in (A) and (B) of FIG. 12 comprises a transistor (55A), a transistor (55B), a transistor (55C), and a capacitor (56). The transistors (55A), (55B), and (55C) can be configured as OS transistors. It is preferable that each OS transistor of transistors (55A), (55B), and (55C) be provided with a back gate electrode, and in this case, the back gate electrode may be configured to supply a signal the same as the gate electrode or a signal different from the gate electrode.

[0122] The transistor (55B) has a gate electrode connected to the transistor (55A), a first electrode connected to the light-emitting element (61), and a second electrode connected to a power line (ANO). The power line (ANO) is a wire for supplying a potential to supply current to the light-emitting element (61).

[0123] The transistor (55A) has a first electrode connected to the gate electrode of the transistor (55B), a second electrode connected to a wire (SL) that functions as a source line, and a gate electrode that has the function of controlling a conductive state or a non-conductive state based on the potential of the wire (GL1) that functions as a gate line.

[0124] The transistor (55C) has a first electrode connected to the wiring (V0), a second electrode connected to the light-emitting element (61), and a gate electrode having the function of controlling a conducting state or a non-conducting state based on the potential of the wiring (GL2) which functions as a gate line. The wiring (V0) is a wiring for supplying a reference potential and a wiring for outputting the current flowing through the pixel circuit (51) to the display driving unit (22).

[0125] The capacitor (56) has a conductive film connected to the gate electrode of the transistor (55B) and a conductive film connected to the second electrode of the transistor (55C).

[0126] The light-emitting element (61) has a first electrode connected to the first electrode of the transistor (55B) and a second electrode connected to the power line (VCOM). The power line (VCOM) is a wire for supplying a potential to supply current to the light-emitting element (61).

[0127] Accordingly, the intensity of light emitted by the light-emitting element (61) can be controlled according to the image signal supplied to the gate electrode of the transistor (55B). In addition, the deviation in the gate-source potential of the transistor (55B) can be suppressed by the reference potential of the wiring (V0) supplied through the transistor (55C).

[0128] Additionally, a current value that can be used to set pixel parameters can be output from the wiring (V0). More specifically, the wiring (V0) can function as a monitor line for outputting the current flowing through the transistor (55B) or the current flowing through the light-emitting element (61) to the outside. The current output to the wiring (V0) may be converted into a voltage by a source follower circuit, etc.

[0129] In addition, in the configuration example shown in (B) of FIG. 12, the wiring connecting the pixel circuit (51J) and the display driving unit (22) can be shortened, so the wiring resistance of the wiring can be reduced. Also, the parasitic capacitance of the wiring can be reduced. Therefore, data recording can be performed at high speed, and the display unit (31) can be driven at high speed. As a result, even if the number of pixel circuits (51) is large, a sufficient frame period can be secured, so the pixel density of the display unit (31) can be increased. Also, by increasing the pixel density of the display unit (31), the detail of the image displayed on the display unit (31) can be increased. For example, the pixel density of the display unit (31) can be 1000 ppi or more, 5000 ppi or more, or 7000 ppi or more. Therefore, the display device (100) can be used in an xR display device such as AR or VR, for example. A display device (100) according to one embodiment of the present invention can be suitably applied to electronic devices such as HMDs, where the distance between the display part and the user is close.

[0130] As described above, a display device (100) of one form of the present invention has a stacked configuration comprising a device layer having a display unit (31) and a memory unit (71), and a device layer having a display driving unit (22) and a processor circuit unit (70). By stacking the device layers provided with each circuit, the display device (100) can be miniaturized. In addition, by providing the display driving unit (22) overlapping with the display unit (31), the width of the bezel around the display unit (31) can be made very narrow, thereby allowing the area of ​​the display unit (31) to be expanded. Therefore, the resolution of the display unit (31) can be increased. Thus, the display quality of the display device (100) can be improved.

[0131] In addition, when the resolution of the display unit (31) is constant, the occupied area per pixel can be expanded. Thus, the luminous brightness of the display unit (31) can be increased. In addition, the aperture ratio of the pixel can be increased. For example, the aperture ratio of the pixel can be 40% or more and less than 100%, preferably 50% or more and less than 95%, and more preferably 60% or more and less than 95%. In addition, by expanding the occupied area per pixel, the current density supplied to the pixel can be reduced. Thus, the load applied to the pixel is reduced, and the reliability of the display device (100) can be increased.

[0132] In addition, by stacking a device layer having a display unit (31) and a memory unit (71) and a device layer having a display driving unit (22) and a processor circuit unit (70), the wiring connecting each can be shortened. Therefore, wiring resistance and parasitic capacitance are reduced, and the operating speed of the display device (100) can be increased. In addition, the power consumption of the display device (100) is reduced.

[0133] The configuration examples and corresponding drawings, etc. exemplified in this embodiment may be appropriately combined with at least a part thereof with other configuration examples or drawings, etc.

[0134] (Embodiment 2)

[0135] In this embodiment, a display device having different configurations and functions in the display driving unit (22) and processor circuit unit (70) described in the previous embodiment 1 is described. Since the processor circuit unit (70) described in the previous embodiment 1 can perform general-purpose computation processing, it can execute the functions described in this embodiment in addition to the functions described in the previous embodiment 1. Furthermore, in this embodiment, repetitive descriptions of configurations assigned the same symbols as in the previous embodiment may be omitted.

[0136] <Configuration Example 2 of a Display Device>

[0137] FIG. 13 is a block diagram illustrating the configuration of a display device (100_X1) according to one embodiment of the present invention. The display device (100_X1) shown in FIG. 13 has a display driving unit (22), a processor circuit unit (70), and a display unit (31), similar to (B) in FIG. 1. The circuits of the processor circuit unit (70) and the display driving unit (22) can be connected through a bus unit (37).

[0138] In addition, FIG. 13 illustrates an image data comparison circuit (200) that supplies control data (EN_I) to an interface (39) of a display device (100_X1) and supplies image data (EN_V) to a video interface (39_V) of a display device (100_X1). The processor circuit (70) and the interface (39) can be connected through a bus (37).

[0139] The interface (39) has the function of an interface to which control data (EN_I) is supplied for computational processing in the processor circuit (70). The video interface (39_V) has the function of an interface to which image data (EN_V) is supplied from outside the display device (100_X1).

[0140] The display driving unit (22) has a plurality of timing controllers. A plurality of timing controllers may be provided according to the number of sections of the display unit (31). In FIG. 13, timing controllers (34_1 to 34_4) are shown as an example. The processor circuit unit (70) and the timing controllers (34_1 to 34_4) can be connected through the bus unit (37).

[0141] The display driving unit (22) has a plurality of gate line driving circuits controlled by a plurality of timing controllers. The plurality of gate line driving circuits can be provided according to the plurality of timing controllers. In FIG. 13, gate line driving circuits (32_1 to 32_4) are shown as an example.

[0142] The display driving unit (22) has a controller (35) having a frame memory (36). The frame memory (36) has the function of maintaining image data (EN_V) supplied to the video interface (39_V). The controller (35) is connected to the video interface (39_V).

[0143] The display driving unit (22) has a plurality of source line driving circuits controlled by a controller (35). The plurality of source line driving circuits can be provided according to the number of sections of the display unit (31). In FIG. 13, source line driving circuits (33_1 to 33_4) are shown as an example. The processor circuit unit (70) and the controller (35) are connected through a bus unit (37).

[0144] The display section (31) is shown divided into multiple sections. As an example, FIG. 13 is shown divided into 16 display sections (31[1,1] to 31[4,4]) in 4 rows and 4 columns.

[0145] One of the gate line driving circuits (32_1 to 32_4) corresponds to a row-direction section of the display unit (31[1,1] to 31[4,4]). One of the source line driving circuits (33_1 to 33_4) corresponds to a column-direction section of the display unit (31[1,1] to 31[4,4]). The display unit (31[1,1]) is controlled, for example, by the gate line driving circuit (32_1) and the source line driving circuit (33_1). The display unit (31[4,4]) is controlled, for example, by the gate line driving circuit (32_4) and the source line driving circuit (33_4).

[0146] The processor circuit section (70) has the function of switching the driving frequency for driving the gate line driving circuit (32) (gate line driving circuit (32_1 to 32_4)) and the source line driving circuit (33) (source line driving circuit (33_1 to 33_4)) by controlling the settings of the controller (35) and the timing controller (34_1 to 34_4) according to the calculation result obtained by processing the control data (EN_I) supplied to the interface (39).

[0147] The image data comparison circuit (200) compares image data of a continuous frame period that performs display, for example, on the display unit (31), and outputs control data (EN_I) according to the comparison result. The control data (EN_I) is data for switching the operation of the gate line driving circuit and the source line driving circuit corresponding to the section when there is a section that performs display based on the same image data in the image data of a continuous frame period. The image data (EN_V) is image data based on control by the control data (EN_I).

[0148] FIG. 14 is a block diagram illustrating an example configuration of an image data comparison circuit (200) that outputs control data (EN_I) and image data (EN_V) to a display device (100_X1). The image data comparison circuit (200) has a comparison circuit (201), a frame memory (202), and a control circuit (203).

[0149] The comparison circuit (201) is a circuit for comparing image data between different frames. For example, when image data (VD1) and image data (VD2) of different frames are input consecutively to the image data comparison circuit (200), the comparison circuit (201) compares the image data (VD1) (image data of the previous frame) and the image data (VD2) (image data of the input frame) in sections of the display unit (31). The image data (VD1) is maintained in the frame memory (202) and can be read into the comparison circuit (201) under the control of the control circuit (203). The reading of the image data of the previous frame from the frame memory (202) to the comparison circuit (201) continues as long as the image data being compared matches, and terminates when the image data being compared does not match.

[0150] If there is no change in the section compared in the image data between different frames, the control circuit (203) transmits control data (EN_I). In this case, the control data (EN_I) is data for switching the operation of the gate line driving circuit and the source line driving circuit corresponding to the section, as described above. Therefore, the source line driving circuit and the gate line driving circuit can be controlled so that the image data update is not performed in the section according to the result of the operation in the processor circuit (70). As a result, the power required to drive the source line driving circuit and the gate line driving circuit required for the update of the image data in the section can be reduced.

[0151] In addition, if there is no change in the section compared in the image data between different frames, the image data (EN_V) corresponding to the section, i.e., the data of the image data (VD2), is not transmitted to the display device (100_X1). Therefore, since the frequency of updating the image data can be reduced, the frequency of the clock signal for driving the source line driving circuit and the gate line driving circuit can be lowered. In addition, the application of power voltage to the amplifier circuit of the source line driving circuit can be stopped, and the clock signal for the gate line driving circuit can be stopped. As a result, the power required for transmitting the image data can be reduced.

[0152] As described above, an OS transistor can be applied to the pixel circuit (51) of the display unit (31). The OS transistor has a very small off-current. Therefore, by lowering the frequency of the clock signal for driving the source line driving circuit and the gate line driving circuit, the refresh frequency when displaying a still image in the display unit (31) can be reduced. In the present specification and other sources, the technique for reducing the refresh frequency described above is sometimes referred to as "idling stop driving" or "IDS driving." In the display device (100_X1), the power consumption required for driving the display unit (31) can be reduced by applying IDS driving to each section.

[0153] If there is a change in the section compared in the image data between different frames, the control circuit (203) transmits control data (EN_I). In this case, the control data (EN_I) is data for updating the image data by the operation of the gate line driving circuit and the source line driving circuit. Therefore, the source line driving circuit and the gate line driving circuit can be controlled to perform the updating of the image data in the said section according to the result of the operation in the processor circuit section (70).

[0154] Additionally, if there is a change in the section compared in the image data between different frames, the control circuit (203) transmits the image data (EN_V), i.e., the data contained in the image data (VD2), to the display device (100_X1). The display unit (31) in the display device (100_X1) is updated from a display based on the image data (VD2) to a display based on the image data (VD1).

[0155] FIG. 15 is a timing chart explaining the operation of the display device (100_X1) illustrated in FIG. 13. In the timing chart illustrated in FIG. 15, the operation is explained by dividing it into periods (P0 to P4).

[0156] The period (P0) represents the period for performing normal operation, which performs image updating in all sections. The interface (39) and the processor circuit (70) are configured to perform normal operation. The processor circuit (70) configures the timing controllers (34_1 to 34_4) so ​​that they are configured for normal operation, for example, to perform operation at a driving frequency of 90Hz (indicated as 90Hz_DV in the drawing). Although not illustrated, the controller (35) is configured in the same way. Depending on the configuration of the timing controllers (34_1 to 34_4) and the controller (35), the gate line driving circuits (32_1 to 32_4) and the source line driving circuits (33_1 to 33_4) are configured for normal operation (indicated as 90Hz in the drawing). In the display unit (31), image data updating is performed at 90Hz in the display unit (31[1,1] to 31[4,4]) (normal operation).

[0157] Period (P1) represents the period during which control data (EN_I) is supplied from an external image data comparison circuit (200) to the interface (39), specifically, as an example, control data (EN_I) for switching the update frequency of image data of the display unit (31[2,2]). During this period, the processor circuit (70) is set to perform normal operation. Therefore, in the display unit (31), the update of image data in the display unit (31[1,1] to 31[4,4]) is performed at 90Hz continuously from period (P0) (normal operation).

[0158] Period (P2) represents the period during which control data (EN_I) is supplied from the interface (39) to the processor circuit (70) and computational processing based on the control data (EN_I) is performed. During this period, the processor circuit (70) is set to perform normal operation. Therefore, in the display unit (31), the updating of image data in the display unit (31[1,1] to 31[4,4]) is performed at 90Hz continuously from period (P1) (normal operation).

[0159] Period (P3) represents a period of control in which the settings of the timing controller (34_2) and the controller (35) that update the image data of the display unit (31[2,2]) are switched as the processing of the control data (EN_I) is performed in the processor circuit unit (70). The timing controller (34_2) that controls the gate line driving circuit (32_2) corresponding to the display unit (31[2,2]) becomes the low-frequency driving switching setting (IDS_EN). Similarly, the controller (35) that controls the source line driving circuit (33_2) also has its settings switched. During this period, the processor circuit unit (70) is set to perform normal driving. Therefore, in the display unit (31), the updating of image data in the display unit (31[1,1] to 31[4,4]) is performed at 90Hz continuously from period (P0) (normal driving).

[0160] Period (P4) is the period during which the timing controller (34_2) switches through the low-frequency drive switching setting (IDS_EN) to a setting for low-frequency drive that performs driving at a driving frequency of, for example, 1Hz (indicated as 1Hz_DV in the drawing). As the timing controller (34_2) switches to the low-frequency drive switching setting (IDS_EN), the gate line driving circuit (32_2) and source line driving circuit (33_2) corresponding to the display unit (31[2,2]) are set to IDS driving (indicated as 1Hz in the drawing). Additionally, the gate line driving circuit (32_1, 32_3, and 32_4) and source line driving circuit (33_1, 33_3, and 33_4) are sections where image data updates are performed and continue normal operation (indicated as 90Hz in the drawing).

[0161] As explained above, since the processor circuit of the present embodiment can perform general-purpose computation processing, in addition to the functions described in the previous embodiment 1, it can perform computation processing on data for switching the operation of the gate line driving circuit and the source line driving circuit corresponding to the section of the display unit, and perform setting switching according to the computation processing. Therefore, since the setting of normal driving or IDS driving can be switched for each section in the display unit, low power consumption can be achieved.

[0162] <Configuration Example 3 of a Display Device>

[0163] FIG. 16 (A) is a block diagram illustrating the configuration of a display device (100_X2) according to one embodiment of the present invention. The display device (100_X2) shown in FIG. 16 (A) has a display driving unit (22), a processor circuit unit (70), and a display unit (31) (not shown), similar to FIG. 1 (B).

[0164] The display device (100_X2) illustrated in (A) of FIG. 16 has a display driving unit (22) and a processor circuit unit (70). The processor circuit unit (70) illustrated in (A) of FIG. 16 can execute a Built-in Self Test (BIST) program. Additionally, the processor circuit unit (70) illustrated in (A) of FIG. 16 can perform verification of the operation of the display driving unit (22) based on the BIST program.

[0165] The signal (70_OUT) output by the processor circuit unit (70) includes information on the result of computational processing based on a BIST program for verifying the operation of the processor circuit unit (70). The signal (70_OUT) is input to the processor circuit unit (70) and can perform verification of the normal operation of the processor circuit unit (70). The determination of the normal operation of the processor circuit unit (70) can be output externally as a signal (BIST_OUT) by comparing the signal (70_OUT) with the expected value in the processor circuit unit (70).

[0166] Additionally, the signal (70_OUT) is input to the display driver (22). The display driver (22) outputs a signal (22_OUT) based on the signal for BIST that the signal (70_OUT) possesses. The signal (22_OUT) output by the display driver (22) includes information on the result of computational processing based on a BIST program for verifying the operation of the display driver (22). The signal (22_OUT) is input to the processor circuit (70) and can perform verification of the normal operation of the display driver (22). The determination of the normal operation of the display driver (22) can be output externally as a signal (BIST_OUT) by comparing the signal (70_OUT) with the expected value in the processor circuit (70).

[0167] FIG. 16 (B) is a diagram explaining the operation of the BIST of the processor circuit section (70) and the display driving section (22). In FIG. 16 (B), the operation is explained by dividing it into periods (P11 to P16).

[0168] The period (P11) indicates the power-off state. The display drive unit (22) and the processor circuit unit (70) are power-off (P_OFF).

[0169] The period (P12) indicates the power-on state. The display drive unit (22) and the processor circuit unit (70) are turned on (P_ON).

[0170] The period (P13) indicates the initialization state. The display drive unit (22) and the processor circuit unit (70) are initialized (INI).

[0171] The period (P14) indicates the BIST operation of the processor circuit unit (70). The processor circuit unit (70) performs operation verification based on the BIST program for the processor circuit unit (70). The display driving unit (22) continues the initialization (INI).

[0172] The period (P15) indicates the BIST operation of the display driver (22). The processor circuit (70) supplies a signal (70_OUT) based on the BIST program (BIST_22) of the display driver (22) to the display driver (22). The display driver (22) outputs a signal (22_OUT) based on the BIST program to the processor circuit (70), and operation verification is performed in the processor circuit (70).

[0173] The period (P16) indicates the output period of the operation verification result. The processor circuit unit (70) outputs a signal (BIST_OUT) indicating the determination of normal operation of the display driving unit (22) and the processor circuit unit (70) to the outside. As a result, normal operation or faulty operation of the display driving unit (22) and the processor circuit unit (70) can be determined.

[0174] The processor circuit (70) described in the preceding embodiment 1 can perform general-purpose computation processing. Therefore, the processor circuit (70) can execute a BIST program. In order to improve the quality of the operation test, it is necessary to prepare various test patterns for BIST, but if executed on dedicated hardware inside the chip, the circuit size tends to increase. On the other hand, in a display device (100_X2) having a processor circuit (70) capable of executing a BIST program, computation processing based on other programs in addition to BIST is possible, so the processor circuit (70) can be effectively utilized. Furthermore, when designing dedicated hardware inside the chip, the test patterns that can be generated are fixed, but since the processor circuit (70) capable of executing a BIST program can generate new test patterns by updating the program, the test patterns can be flexibly changed.

[0175] <Configuration Example 4 of a Display Device>

[0176] FIG. 17 (A) is a block diagram illustrating the configuration of a display device (100_X3) according to one embodiment of the present invention. The display device (100_X3) shown in FIG. 17 (A) has a display driving unit (22), a processor circuit unit (70), and a display unit (31) (not shown), similar to FIG. 1 (B).

[0177] The display device (100_X3) illustrated in (A) of FIG. 17 has a memory controller (73) in addition to the display driving unit (22) and the processor circuit unit (70). The processor circuit unit (70) and the memory controller (73) can be connected via a bus unit (37). The display driving unit (22) is illustrated with a controller (35) having the frame memory (36) described above and a source line driving circuit (33).

[0178] The processor circuit (70) illustrated in (A) of FIG. 17 has the function of controlling the memory controller (73) to update the address value of the image data maintained in the frame memory. By configuring it as above, the image data maintained in the frame memory (36) can be reused. Therefore, the amount of image data supplied from outside the display device (100_X3) can be reduced.

[0179] The processor circuit (70) has the function of controlling the controller (35) and the memory controller (73) according to the calculation result obtained by processing the control data (EN_I) supplied to the interface (not shown). Here, the control data (EN_I) supplied to the processor circuit (70) is information regarding image data with different addresses between different frames. Image data with different addresses between different frames can be used repeatedly by updating the address.

[0180] The memory controller (73) has the function of updating the address value of an area that can be repeatedly used within the image data between different frames. For example, it can update the address of the image data (VD) of the previous frame and control the display to be performed as image data combined with separately supplied image data (EN_V).

[0181] FIG. 17 (B) and (C) are schematic diagrams illustrating an example of updating the address value of an area that can be repeatedly used within image data between different frames. FIG. 17 (B) is a schematic diagram of the image data (VD) of the preceding frame. FIG. 17 (C) is a schematic diagram of the image data (EN_V) supplied separately. In the schematic diagrams of the image data (VD) and image data (EN_V), there is an area (99) (hatched area) of the same image data with different addresses.

[0182] The memory controller (73) changes the address of the image data in the area (99) of the image data (VD) when, for example, it is "ADDR_1 to ADDR_k (k is an integer greater than or equal to 2)". Specifically, it changes the address of the image data in the area (99) of the image data (EN_V) so that, for example, it is "ADDR_1+x to ADDR_k+x (x is an integer greater than or equal to 1)". By changing the address in this way, a portion of the image data (VD) of the previous frame can be used when displaying the image data (EN_V). Since the image data (EN_V) supplied from the outside can be data excluding the image data of the area (99), the amount of data supplied from the outside can be reduced.

[0183] The processor circuit (70) described in the preceding embodiment 1 can perform general-purpose computation processing. Therefore, the processor circuit (70) can be configured to receive the result of comparing image data between different frames and execute a process to change the address of the image data. By changing the address of the image data, a portion of the image data of the preceding frame can be utilized. With the above configuration, the amount of image data supplied from the outside can be reduced.

[0184] (Embodiment 3)

[0185] In this embodiment, variations of the configuration of a display device according to one form of the present invention are described. Additionally, in this embodiment, repetitive descriptions of configurations given the same reference numerals as in the preceding embodiment may be omitted.

[0186] FIG. 18 (A) and FIG. 19 are perspective views of a display device (100A) according to one embodiment of the present invention. FIG. 18 (B) is a block diagram explaining the configuration of the display device (100A). The display device (100A) comprises a device layer (30) on a device layer (20) and a sealing substrate (40) on the device layer (30). Additionally, the device layer (30) comprises a display portion (31) and a memory portion (71), and a light-emitting device layer (60) is provided between the sealing substrate (40) and the display portion (31). In FIG. 19, the device layer (20), the device layer (30), the light-emitting device layer (60), and the sealing substrate (40) are shown separately to make it easier to understand the configuration of the display device (100A).

[0187] In this embodiment, the configuration is such that a part or all of the memory portion (71) of the processor circuit portion (70) provided to the device layer (20) is provided to the device layer (30). The description of the other device layer (20) is the same as in the preceding embodiment 1.

[0188] In the device layer (30), a display unit (31) is provided, similar to the preceding embodiment 1. Additionally, as described above, a memory unit (71) is provided in the device layer (30). The memory unit (71) provided in the device layer (30) comprises a plurality of memory circuits (72). In the configuration of the display device (100A), the display unit (31) and the memory unit (71) are each provided in the device layer (30).

[0189] The memory unit (71) has the function of storing programs or data used in the processor circuit unit (70). The memory unit (71) can be provided by overlapping with the processor circuit unit (70). Since some of the circuits provided to the processor circuit unit (70) can be placed in a different element layer (30) than the element layer (20), the processor circuit unit (70) can be made smaller in area. Since the layout area of ​​the memory unit (71) provided in the element layer (30) (the area of ​​the region where the memory circuit (72) is placed) can be made larger than the layout area of ​​the memory unit (71) provided within the processor circuit unit (70), the memory capacity for storing programs or data used in the processor circuit unit (70) can be increased. In addition, the memory circuit (72) of the memory unit (71) and the pixel circuit (51) of the display unit (31) are both configured to have OS transistors.

[0190] NOSRAM (Nonvolatile Oxide Semiconductor Random Access Memory) or DOSRAM (Dynamic Oxide Semiconductor Random Access Memory) can be used as the memory unit (71).

[0191] NOSRAM refers to a memory in which the memory cell is a 2-transistor type (2T) or 3-transistor type (3T) gain cell and the access transistor is an OS transistor. The OS transistor has a very small leakage current, which is the current flowing between the source and drain in the off state. NOSRAM can read retained data without destroying it (non-destructive reading).

[0192] DOSRAM refers to a RAM having a 1T (transistor) 1C (capacitance element) type memory cell. Like NOSRAM, DOSRAM is a memory that utilizes the low off-current of the OS transistor.

[0193] NOSRAM and DOSRAM are types of memory devices that use OS transistors.

[0194] The memory circuit (72) of the memory unit (71) and the pixel circuit (51) of the display unit (31) are configured to have OS transistors. By configuring as above, the display unit (31) and the memory unit (71) can be arranged in the device layer (30). By configuring the memory unit (71) and the display unit (31) to be arranged in the same layer, the memory unit (71) can be arranged using the area of ​​the device layer (30) where the display unit (31) is not arranged.

[0195] In the configuration shown in FIG. 19, the memory unit (71) is provided in an area that overlaps with the processor circuit unit (70) around the area where the display unit (31) is provided. Additionally, the memory unit (71) may be configured to be provided in at least a portion of the area around the display unit (31). By configuring it as above, the memory unit (71) can be placed so as to fill the area where the display unit (31) is not provided in the device layer (30). Therefore, the memory unit (71) can be placed to increase the memory capacity without degrading the display quality, such as by reducing the area of ​​the display unit (31).

[0196] In addition, the memory unit (71) connected to the processor circuit unit (70) may be used as a memory unit for backing up programs or data used in the processor circuit unit (70). In this way, a normally off CPU (also called "Noff-CPU") can be realized by combining a memory unit using an OS transistor with a processor circuit. Also, a Noff-CPU is an integrated circuit that includes a normally off type transistor that is in a non-conducting state (also called an off state) even when the gate voltage is 0V.

[0197] The Noff-CPU can stop the power supply to circuits within the Noff-CPU that do not require operation, thereby placing said circuits in a standby state. Since no power is consumed by circuits in a standby state when the power supply is stopped, the Noff-CPU can minimize power consumption. Furthermore, the Noff-CPU can maintain information necessary for operation, such as setting conditions, for an extended period even when the power supply is stopped. To return from the standby state, it is sufficient to simply restart the power supply to said circuits, and rewriting settings such as setting conditions is unnecessary. For example, it can return from the standby state at high speed. In this way, the Noff-CPU can reduce power consumption without significantly lowering the operating speed.

[0198] In addition, in the configuration of FIG. 19, the memory capacity of the memory unit (71) connected to the processor circuit unit (70) can be increased, so the memory unit (71) is suitable for maintaining data (weight data) corresponding to weight parameters used in the product-sum operation of the neural network. In this case, the processor circuit unit (70) can execute the product-sum operation using the weight data of the memory unit (71). By configuring the processor circuit unit (70) to perform parallel processing of the product-sum operation of the neural network, for example, a large amount of input data can be processed simultaneously, thereby enabling data processing in a short time.

[0199] Next, examples of configurations of memory cells having OS transistors will be described with reference to FIGS. 20 (A) to (H). In addition, memory cells using OS transistors, such as the memory circuits (72A to 72H) shown in FIGS. 20 (A) to (H), can be broadly divided into NOSRAM ( FIGS. 20 (A) to (F)) and DOSRAM ( FIGS. 20 (G) and (H)).

[0200] Figure 20 (A) shows an example of a circuit configuration applicable to a memory circuit (72). Here, the memory circuit (72A) is a 2-transistor type (2T) gain cell. The memory circuit (72A) has transistors (MW1, MR1) and a capacitor (CS1). Transistor (MW1) is a write transistor, and transistor (MR1) is a read transistor. The back gates of transistors (MW1, MR1) are connected to a wire (BGL).

[0201] Since the read transistor is configured with an OS transistor, the memory circuit (72A) does not consume power for data retention. Therefore, the memory circuit (72A) is a low-power memory cell capable of retaining data for a long period, and the memory unit (71) can be used as a non-volatile memory device.

[0202] The memory circuit (72B) shown in (B) of FIG. 20 is a 3T type gain cell and has transistors (MW2, MR2, MS2) and a capacitor (CS2). The transistors (MW2, MR2, MS2) are a write transistor, a read transistor, and a select transistor, respectively. The back gates of the transistors (MW2, MR2, MS2) are connected to the wiring (BGL). The memory circuit (72B) is connected to the word lines (RWL, WWL), bit lines (RBL, WBL), capacitance lines (CDL), and power lines (PL2). For example, a voltage (GND) (low-level side power voltage) is input to the capacitance lines (CDL) and power lines (PL2).

[0203] Other configuration examples of a 2T type gain cell are shown in FIG. 20 (C) and (D). In the memory circuit (72C) shown in FIG. 20 (C), the read transistor is configured as an n-channel type Si transistor. In the memory circuit (72D) shown in FIG. 20 (D), the read transistor is configured as a p-channel type Si transistor. As shown in FIG. 20 (C) and (D), the transistors within the memory cell may be configured as a combination of OS transistors and Si transistors.

[0204] Since the metal oxide applied to the OS transistor is an N-type (n-channel type), such as In-Ga-Zn oxide, a CMOS (Complementary Metal Oxide Semiconductor) circuit can be constructed by combining it with a Si transistor to form a memory cell. Therefore, compared to the case where a memory cell is constructed using only n-channel types, it is possible to realize a circuit that combines features such as high driving capability due to the use of Si transistors and low power consumption due to the low off-current of the OS transistor. In addition, since there is no need to form N-type (n-channel type) and P-type (p-channel type) Si transistors separately, the process cost of the transistor can be reduced.

[0205] Other configuration examples of a 3T type gain cell are shown in (E) and (F) of FIG. 20. In the memory circuit (72E) shown in FIG. 20 (E), the read transistor and the select transistor are composed of n-channel Si transistors. In the memory circuit (72F) shown in FIG. 20 (F), the read transistor and the select transistor are composed of p-channel Si transistors. In the example of FIG. 20 (F), a voltage (Vdd) (high-level side power supply voltage) is input to the power line (PL2).

[0206] In the gain cell described above, a bit line serving as both a read bit line (RBL) and a write bit line (WBL) may be provided.

[0207] Examples of 1T1C (capacitance) type memory cells are shown in FIG. 20 (G) and (H). The memory circuit (72G) shown in FIG. 20 (G) is connected to the word line (WL), bit line (BL), capacitance line (CDL), and wiring (BGL). The memory circuit (72G) has a transistor (MW3) and a capacitor (CS3). The back gate of the transistor (MW3) is connected to the wiring (BGL). In addition, the memory circuit (72H) shown in FIG. 20 (H) has the configuration of a ferroelectric memory using a capacitance element (FE1) having a ferroelectric material in the capacitor (CS3). For example, HfZrO is used as the ferroelectric material. x You can use .

[0208] The circuit configuration of the memory circuit (72) of the memory unit (71) can be configured in a circuit configuration consisting only of OS transistors, or a circuit configuration combined with Si transistors.

[0209] In addition, FIG. 21 (A) shows an example of a circuit configuration of a memory cell (memory circuit (72E)). FIG. 21 (B) is a schematic diagram showing the upper and lower relationships of a device layer (20) having a processor circuit part (70), a device layer (30) having a memory circuit (72), and a light-emitting device layer (60). In addition, although the configuration of the light-emitting device layer (60) in the memory part (71) where the memory circuit (72E) is provided is not shown, for example, a light-emitting device (61) may be provided in the light-emitting device layer (60).

[0210] The memory circuit (72E) shown as an example in (A) and (B) of FIG. 21 is equipped with transistors (MW2, MR2, MS2) and a capacitor (CS2). The transistor (MW2) can be composed of an OS transistor, and the transistors (MR2, MS2) can be composed of Si transistors. For example, as shown in (B) of FIG. 21, the transistors (MR2, MS2) are provided in the device layer (20), and the transistor (MW2) is provided in the device layer (30). Also, although the capacitor (CS2) is shown in the device layer (30), it may be provided in the device layer (20). Additionally, each wiring (word line (RWL, WWL), bit line (RBL, WBL)), etc., is shown in the device layer (20), but may be provided in the device layer (30).

[0211] As described above, the display device (100A) of the present embodiment has a stacked configuration having a device layer having a display unit (31) and a memory unit (71), and a device layer having a display driving unit (22) and a processor circuit unit (70). By stacking layers provided with each circuit, the display device (100A) can be miniaturized. In addition, since the display driving unit (22) can be provided by overlapping with the display unit (31), the area of ​​the display unit (31) can be expanded. Therefore, the resolution of the display unit (31) can be increased, and the display quality of the display device (100A) can be improved.

[0212] In addition, by stacking a device layer having a memory section (71) and a device layer having a processor circuit section (70), the wiring connecting each can be shortened. Therefore, wiring resistance and parasitic capacitance are reduced, and the operating speed of the processor circuit section (70) can be increased. In addition, the power consumption of the display device (100A) is reduced.

[0213] (Embodiment 4)

[0214] In this embodiment, variations of the configuration of a display device according to one form of the present invention are described. Additionally, in this embodiment, repetitive descriptions of configurations given the same reference numerals as in the preceding embodiment may be omitted.

[0215] FIG. 22 (A) and FIG. 23 are perspective views of a display device (100B) according to one embodiment of the present invention. FIG. 22 (B) is a block diagram illustrating the configuration of the display device (100B). The display device (100B) comprises a device layer (30A) on a device layer (20), a device layer (30B) on the device layer (30A), and a sealing substrate (40) on the device layer (30B). Additionally, the device layer (30B) comprises a display portion (31), and a light-emitting device layer (60) is provided between the sealing substrate (40) and the display portion (31). Additionally, the device layer (30A) comprises a memory portion (71). In FIG. 23, the device layer (20), device layer (30A), device layer (30B), light-emitting device layer (60), and sealing substrate (40) are shown separately to make it easier to understand the configuration of the display device (100B).

[0216] The description of the element layer (20) is the same as in the previous embodiment 1.

[0217] The memory unit (71) provided in the device layer (30A) is equipped with a plurality of memory circuits (72). For an example of the configuration of the memory circuit (72) of the memory unit (71), it is recommended to refer to the description in Embodiment 3. In the configuration of the display device (100B), the display unit (31) and the memory unit (71) are provided in different layers, namely the device layer (30A) and the device layer (30B), respectively. Therefore, it is possible to realize a large area of ​​the display unit (31) and a large capacity of the memory unit (71). In addition, the memory circuit (72) of the memory unit (71) and the pixel circuit (51) of the display unit (31) are provided in different layers, but they are all configured to have OS transistors.

[0218] In one embodiment of the present invention, the memory unit (71) may be provided in a device layer (30A), which is a different device layer from the device layer (30B) where the display unit (31) is provided. Therefore, the display area can be increased while increasing the memory capacity of the display device (100B). The memory unit (71) can be used as a memory circuit that stores programs or data used in the processor circuit unit (70).

[0219] As described above, a display device (100B) of one form of the present invention has a stacked configuration comprising a device layer having a display portion (31), a device layer having a memory portion (71), and a device layer having a display driving portion (22) and a processor circuit portion (70). By stacking layers provided with each circuit, the display device (100B) can be miniaturized. In addition, since the display driving portion (22) can be provided by overlapping with the display portion (31), the area of ​​the display portion (31) can be expanded. Therefore, the resolution of the display portion (31) can be increased, thereby improving the display quality of the display device (100B).

[0220] In addition, by stacking a device layer having a display portion (31), a device layer having a memory portion (71), and a device layer having a display driving portion (22) and a processor circuit portion (70), the wiring connecting each can be shortened. Accordingly, wiring resistance and parasitic capacitance are reduced, and the operating speed of the display device (100B) can be increased. In addition, the power consumption of the display device (100B) is reduced.

[0221] The configuration examples and corresponding drawings, etc. exemplified in this embodiment may be appropriately combined with at least a part thereof with other configuration examples or drawings, etc.

[0222] (Embodiment 5)

[0223] In this embodiment, an example of the configuration of a display module to which a display device of one form of the present invention can be applied is described.

[0224] The display device of the present embodiment may be a fixed display panel. For example, a display device of one form of the present invention may be used as a display unit of an information terminal (wearable device) such as a wristwatch type and a bracelet type, and as a display unit of a wearable device that can be mounted on the head, such as a VR device such as a head-mounted display and a glasses-type AR device.

[0225] [Display Module]

[0226] A perspective view of a display module (980) is shown in FIG. 24 (A). The display module (980) has a display device (200A) and an FPC (990). In addition, the display panel of the display module (980) is not limited to the display device (200A) and may be the display device (200B) described later.

[0227] The display module (980) has a substrate (991) and a substrate (992). The display module (980) has a display section (981). The display section (981) is an area for displaying an image.

[0228] FIG. 24 (B) is a schematic perspective view showing the configuration of the substrate (991). A circuit section (982), a display section (983) on the circuit section (982), and a pixel section (984) on the display section (983) are stacked on the substrate (991). Additionally, a terminal section (985) for connecting to an FPC (990) is provided in a portion that does not overlap with the pixel section (984) on the substrate (991). The terminal section (985) and the circuit section (982) are connected by a wiring section (986) composed of multiple wires.

[0229] In the layer having the circuit portion (982), circuits of each configuration of the element layer (20) described in the preceding embodiment 1, etc. can be applied. In the layer having the display portion (983), in addition to the pixel circuit (983a), circuits of the memory portion, etc. of the element layer (30) described in the preceding embodiment 1, etc. can be applied. Furthermore, by appropriately increasing the number of layers providing elements, circuits of each configuration of the element layer (20) described in the preceding embodiment 1, etc. can be applied.

[0230] The pixel section (984) has a plurality of pixels (984a) arranged periodically. An enlarged view of one pixel (984a) is shown on the right side of (B) in FIG. 24. The pixel (984a) has a light-emitting device (410R) that emits red light, a light-emitting device (410G) that emits green light, and a light-emitting device (410B) that emits blue light.

[0231] The display unit (983) has a plurality of pixel circuits (983a) arranged periodically. One pixel circuit (983a) is a circuit that controls the light emission of three light-emitting devices having one pixel (984a). As described in the preceding embodiment 1, a memory unit (not shown) may be provided in the layer where the display unit (983) is provided. Alternatively, the pixel circuit (983a) may provide a memory cell (not shown) having a memory unit within the pixel circuit (983a). One pixel circuit (983a) may be configured to have three circuits that control the light emission of one light-emitting device. For example, the pixel circuit (983a) may be configured to have at least one select transistor, one current control transistor (driving transistor), and a capacitance element for each light-emitting device. At this time, a gate signal is input to the gate of the select transistor, and a source signal is input to the source. By this, an active matrix type display panel is realized.

[0232] The circuit section (982) has a circuit that drives each pixel circuit (983a) of the display section (983). For example, it is preferable to have one or both of a gate line driving circuit and a source line driving circuit. In addition, it may have at least one of an operation circuit, a memory circuit, and a power circuit. Furthermore, a transistor provided to the circuit section (982) may form part of the pixel circuit (983a). For example, the pixel circuit (983a) may be composed of a transistor of the display section (983) and a transistor of the circuit section (982).

[0233] The FPC (990) functions as a wiring for supplying video signals and power voltage, etc., from the outside to the circuit section (982). Additionally, an IC may be mounted on the FPC (990).

[0234] Since the display module (980) can be configured such that a layer having a display portion (983) and a layer having a circuit portion (982) are stacked below the pixel portion (984), the aperture ratio (effective display area ratio) of the display portion (981) can be made very high. For example, the aperture ratio of the display portion (981) can be 40% or more and less than 100%, preferably 50% or more and less than 95%, and more preferably 60% or more and less than 95%. In addition, pixels (984a) can be arranged at a very high density, and the precision of the display portion (981) can be made very high. For example, it is preferable that pixels (984a) be arranged in the display portion (981) with a precision of 2000 ppi or more, preferably 3000 ppi or more, more preferably 5000 ppi or more, and more preferably 6000 ppi or more.

[0235] Since this display module (980) has very high resolution, it can be used in VR devices such as head-mounted displays or glasses-type AR devices. For example, even if the display portion of the display module (980) is viewed through a lens, the display module (980) has a display portion (981) with very high resolution, so pixels are not visible even when the display portion is magnified by the lens, allowing for a highly immersive display. Furthermore, the display module (980) is not limited to this and can be used in electronic devices having a relatively small display portion. For example, it can be used in the display portion of a wearable electronic device such as a wristwatch.

[0236] [Display device (200A)]

[0237] The display device (200A) shown in FIG. 25 has a configuration in which a transistor (810) having a channel formed on a substrate (801) and a transistor (820) including a metal oxide on a semiconductor layer having a channel formed are stacked.

[0238] The substrate (801) corresponds to the substrate (991) in (A) and (B) of FIG. 24.

[0239] The transistor (810) is a transistor having a channel forming region on a substrate (801). As the substrate (801), a semiconductor substrate, such as a single-crystal silicon substrate, may be used. The transistor (810) has a portion of the substrate (801), a conductive layer (811), a low-resistance region (812), an insulating layer (813), and an insulating layer (814). The conductive layer (811) functions as a gate electrode. The insulating layer (813) is located between the substrate (801) and the conductive layer (811) and functions as a gate insulating layer. The low-resistance region (812) is a region on the substrate (801) doped with impurities and functions as either a source or a drain. The insulating layer (814) is provided by covering the side of the conductive layer (811).

[0240] In addition, a device isolation layer (815) is provided between two adjacent transistors (810) so as to be embedded in the substrate (801).

[0241] An insulating layer (961) is provided over the transistor (810), and a conductive layer (951) is provided on the insulating layer (961). Additionally, an insulating layer (962) is provided over the conductive layer (951), and a conductive layer (952) is provided on the insulating layer (962). The conductive layer (951) and the conductive layer (952) each function as wiring. Additionally, an insulating layer (963) and an insulating layer (832) are provided over the conductive layer (952), and a transistor (820) is provided on the insulating layer (832).

[0242] The transistor (820) is a transistor (OS transistor) in which a metal oxide (also called an oxide semiconductor) is applied to the semiconductor layer where the channel is formed.

[0243] The transistor (820) has a semiconductor layer (821), an insulating layer (823), a conductive layer (824), a pair of conductive layers (825), an insulating layer (826), and a conductive layer (827).

[0244] An insulating layer (832) is provided on top of an insulating layer (963). The insulating layer (832) functions as a barrier layer to prevent impurities, such as water or hydrogen, from diffusing from the insulating layer (963) to the transistor (820), and to prevent oxygen from escaping from the semiconductor layer (821) to the insulating layer (832). As the insulating layer (832), a film that is more difficult for hydrogen or oxygen to diffuse than a silicon oxide film, such as an aluminum oxide film, a hafnium oxide film, or a silicon nitride film, may be used.

[0245] A conductive layer (827) is provided on an insulating layer (832), and an insulating layer (826) is provided over the conductive layer (827). The conductive layer (827) functions as the first gate electrode of the transistor (820), and a portion of the insulating layer (826) functions as the first gate insulating layer. It is preferable to use an oxide insulating film, such as a silicon oxide film, in the portion of the insulating layer (826) that contacts at least the semiconductor layer (821). It is preferable that the upper surface of the insulating layer (826) be flattened.

[0246] A semiconductor layer (821) is provided on an insulating layer (826). The semiconductor layer (821) preferably has a metal oxide film (also called an oxide semiconductor) that exhibits semiconductor properties. A pair of conductive layers (825) are provided in contact with the semiconductor layer (821) and function as a source electrode and a drain electrode.

[0247] An insulating layer (828) is provided by covering the upper and side surfaces of a pair of conductive layers (825) and the side surface of a semiconductor layer (821), and an insulating layer (964) is provided on top of the insulating layer (828). The insulating layer (828) functions as a barrier layer to prevent impurities such as water or hydrogen from diffusing from the insulating layer (964) to the semiconductor layer (821), and to prevent oxygen from escaping from the semiconductor layer (821). As the insulating layer (828), an insulating film such as the insulating layer (832) can be used.

[0248] An opening reaching the semiconductor layer (821) is provided in the insulating layer (828) and the insulating layer (964). Inside the opening, an insulating layer (823) in contact with the upper surface of the semiconductor layer (821) and a conductive layer (824) are embedded. The conductive layer (824) functions as a second gate electrode, and the insulating layer (823) functions as a second gate insulating layer.

[0249] The upper surface of the conductive layer (824), the upper surface of the insulating layer (823), and the upper surface of the insulating layer (964) are each flattened so that their heights match or substantially match, and the insulating layer (829) and the insulating layer (965) are provided over them.

[0250] The insulating layer (964) and the insulating layer (965) function as interlayer insulating layers. The insulating layer (829) functions as a barrier layer that prevents impurities, such as water or hydrogen, from diffusing from the insulating layer (965) and the like into the transistor (820). As the insulating layer (829), an insulating film such as the insulating layer (828) and the insulating layer (832) can be used.

[0251] A plug (974) connected to one of a pair of conductive layers (825) is provided to be embedded in an insulating layer (965), an insulating layer (829), and an insulating layer (964). Here, it is preferable that the plug (974) be configured such that a portion of the side of the opening of each of the insulating layer (965), the insulating layer (829), the insulating layer (964), and the insulating layer (828), as well as a portion of the upper surface of the conductive layer (825), are covered by the conductive layer. At this time, it is preferable to use a conductive material that is resistant to the diffusion of hydrogen and oxygen as the conductive layer covering the plug (974).

[0252] Additionally, a capacitive element (840) is provided on the insulating layer (965). The capacitive element (840) and the transistor (820) are connected by a plug (974).

[0253] The transistor (820) can be used as a transistor that constitutes a pixel circuit. Additionally, the transistor (810) can be used as a transistor that constitutes a pixel circuit or as a transistor that constitutes a driving circuit (gate line driving circuit, source line driving circuit) for driving the pixel circuit. Furthermore, the transistor (810) and the transistor (820) can be used as transistors that constitute various circuits, such as memory cells.

[0254] A capacitive element (840) has a conductive layer (941), a conductive layer (945), and an insulating layer (943) located between them. The conductive layer (941) functions as one electrode of the capacitive element (840), the conductive layer (945) functions as the other electrode of the capacitive element (840), and the insulating layer (943) functions as a dielectric of the capacitive element (840).

[0255] A conductive layer (941) is provided on an insulating layer (961) and embedded in an insulating layer (954). The conductive layer (941) is connected to one of the source and drain of a transistor (810) by a plug (971) embedded in an insulating layer (961). An insulating layer (943) is provided covering the conductive layer (941). A conductive layer (945) is provided in an area overlapping the conductive layer (941) with the insulating layer (943) interposed therein.

[0256] An insulating layer (955a) is provided over the capacitive element (840), an insulating layer (955b) is provided on top of the insulating layer (955a), and an insulating layer (955c) is provided on top of the insulating layer (955b).

[0257] Inorganic insulating films may be suitably used for each of the insulating layer (955a), insulating layer (955b), and insulating layer (955c). For example, it is preferable to use a silicon oxide film for the insulating layer (955a) and insulating layer (955c), and a silicon nitride film for the insulating layer (955b). By doing so, the insulating layer (955b) can function as an etching protective film. In this embodiment, an example is shown in which a portion of the insulating layer (955c) is etched to form a concave portion, but the insulating layer (955c) does not need to have a concave portion provided.

[0258] A light-emitting device (410R), a light-emitting device (410G), and a light-emitting device (410B) are provided on an insulating layer (955c).

[0259] Since the display device (200A) forms a separate light-emitting device for each light-emitting color, the change in color between light emission at low brightness and light emission at high brightness is small. In addition, since the organic layers (412R, 412G, 412B) are spaced apart from each other, the occurrence of crosstalk between adjacent subpixels can be suppressed even in a high-definition display panel. Therefore, a display panel with high precision and high display quality can be realized.

[0260] An insulating layer (425), a resin layer (426), and a layer (428) are provided in the region between adjacent light-emitting devices.

[0261] The pixel electrodes (411R), (411G), and (411B) of the light-emitting device are connected to one of the source and drain of the transistor (810) by means of a plug (956) embedded in an insulating layer (955a), an insulating layer (955b), and an insulating layer (955c), a conductive layer (941) embedded in an insulating layer (954), and a plug (971) embedded in an insulating layer (961). The height of the upper surface of the insulating layer (955c) and the height of the upper surface of the plug (956) are equal or substantially equal. Various conductive materials may be used for the plug. Additionally, the pixel electrodes (411R), (411G), and (411B) are collectively referred to as the pixel electrode (411).

[0262] Additionally, a protective layer (421) is provided on the light-emitting devices (410R, 410G, and 410B). A substrate (470) is bonded to the protective layer (421) with an adhesive layer (471).

[0263] An insulating layer covering the upper end of the pixel electrode (411) is not provided between two adjacent pixel electrodes (411). Therefore, the distance between adjacent light-emitting devices can be made very narrow. Thus, it can be made into a display device with high precision or high resolution.

[0264] By configuring it in this way, not only the pixel circuit but also the driving circuit can be formed directly below the light-emitting device, so the display panel can be miniaturized compared to the case where the driving circuit is provided around the display area.

[0265] [Display device (200B)]

[0266] The display device (200B) shown in FIG. 26 has a stacked configuration in which a transistor (820A) containing a metal oxide in a semiconductor layer where a channel is formed and a transistor (820B) containing a metal oxide in a semiconductor layer where a channel is formed are stacked. By having the above configuration, transistors with different compositions of constituent elements in the metal oxide of the semiconductor layer can be used. Therefore, the display device can be made using OS transistors with different transistor characteristics. For example, the upper transistor (820A) can be used as a transistor of a pixel circuit that drives a light-emitting device, and the lower transistor (820B) can be used as a transistor of a memory cell.

[0267] By making this configuration, the circuit provided directly below the light-emitting device can be placed at a higher density, so the display panel can be miniaturized compared to when the driving circuit is provided around the display area.

[0268] [Display device (200C, 200D)]

[0269] The display device (200C) shown in FIG. 27 is configured by adding an insulating layer (423) and a lens (424) to the display device (200A). Also, the display device (200D) shown in FIG. 28 is configured by adding an insulating layer (423) and a lens (424) to the display device (200B).

[0270] In one embodiment of the present invention, a display device preferably has a lens array (e.g., a microlens array) at a position overlapping with a light-emitting device. By providing a lens array at a position overlapping with the light-emitting device, light emitted from the light-emitting device can be utilized efficiently. Accordingly, a highly reliable display device can be realized.

[0271] FIG. 27 illustrates an example in which a lens (424) is provided by interposing a protective layer (421) and an insulating layer (423) on a light-emitting device (410R, 410G, and 410B). By directly forming the lens (424) on the substrate on which the light-emitting device is formed, the alignment precision of the light-emitting device and the lens array can be increased.

[0272] FIG. 27 illustrates an example in which a layer having a flattening function is used as the insulating layer (423). For example, it is preferable to use an inorganic material for the protective layer (421) and an organic material for the insulating layer (423). Alternatively, the insulating layer (423) may not be used, and the lens (424) may be provided directly on the protective layer (421).

[0273] The convex side of the lens (424) may face the substrate (470) or the light-emitting device.

[0274] The lens (424) may be formed using at least one of an inorganic material and an organic material. For example, a material containing a resin may be used for the lens. Additionally, a material containing at least one of an oxide and a sulfide may be used for the lens. The lens (424) may be formed directly on a substrate or on a light-emitting device, or a separately formed lens array may be bonded.

[0275] This embodiment may be implemented by appropriately combining at least a part thereof with other embodiments described in this specification.

[0276] (Embodiment 6)

[0277] In this embodiment, an electronic device to which a display device according to one form of the present invention can be applied is described.

[0278] A display device according to one embodiment of the present invention can be applied to the display portion of an electronic device. Accordingly, an electronic device with high display quality can be realized. Alternatively, an electronic device with very high precision can be realized. Alternatively, an electronic device with high reliability can be realized.

[0279] An electronic device using a display device, etc., according to one embodiment of the present invention, comprising: a display device such as a television or monitor; a lighting device; a desktop or laptop-type personal computer; a word processor; an image playback device for playing still images or video stored on a recording medium such as a DVD (Digital Versatile Disc); a portable CD player; a radio; a tape recorder; a headphone stereo; a stereo; a desk clock; a wall clock; a cordless telephone; a transceiver; a car phone; a mobile phone; a portable information terminal; a tablet-type terminal; a portable game console; a stationary game console such as a pachinko machine; an electronic desktop calculator; an electronic notebook; an e-book reader; an electronic translator; a voice input device; a video camera; a digital still camera; a high-frequency heating device such as an electric shaver or microwave oven; an electric rice cooker; an electric washing machine; an electric vacuum cleaner; a water heater; a fan; a hair dryer; an air conditioning system such as an air conditioner; a humidifier; a dehumidifier; a dishwasher; a dish dryer; a clothes dryer; a duvet dryer; an electric refrigerator; an electric freezer; an electric freezer / refrigerator; a freezer for DNA storage; a flashlight; and a chain. Examples include tools such as saws, smoke detectors, and medical devices such as dialysis machines. Additionally, examples include industrial equipment such as guide lights, signal lights, belt conveyors, elevators, escalators, industrial robots, power storage systems, and storage devices for power leveling and smart grids. Furthermore, vehicles propelled by fuel-powered engines or electric motors powered by batteries may also fall under the category of electronic devices. Examples of such vehicles include electric vehicles (EVs), hybrid vehicles (HVs) combining internal combustion engines and electric motors, plug-in hybrid vehicles (PHVs), tracked vehicles with their wheels modified to caterpillar tracks, motorized bicycles including electric assist bicycles, automatic two-wheeled vehicles, electric wheelchairs, golf carts, small or large vessels, submarines, helicopters, aircraft, rockets, satellites, space probes, planetary probes, and spacecraft.

[0280] An electronic device according to one embodiment of the present invention may have a secondary battery, and it is preferable that the secondary battery can be charged using non-contact power transmission.

[0281] Examples of secondary batteries include lithium-ion secondary batteries, nickel-hydrogen batteries, nickel-cadmium batteries, organic radical batteries, lead-acid batteries, air secondary batteries, nickel-zinc batteries, silver-zinc batteries, etc.

[0282] An electronic device according to one embodiment of the present invention may have an antenna. By receiving a signal with the antenna, images and information, etc., can be displayed on a display unit. In addition, if the electronic device has an antenna and a secondary battery, the antenna may be used for non-contact power transmission.

[0283] An electronic device according to one embodiment of the present invention may have a sensor (including the function of detecting, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, inclination, vibration, odor, or infrared radiation).

[0284] An electronic device according to one embodiment of the present invention may have various functions. For example, it may have a function of displaying various information (still images, video, text images, etc.) on a display unit, a touch panel function, a function of displaying a calendar, date, or time, a function of executing various software (programs), a wireless communication function, and a function of reading programs or data recorded on a recording medium.

[0285] Furthermore, in an electronic device having multiple display units, the device may have a function of primarily displaying image information on a part of the display unit and primarily displaying text information on another part, or a function of displaying a three-dimensional image by displaying an image that takes parallax into account on multiple display units. In addition, in an electronic device having an image receiving unit, the device may have a function of capturing a still image or a video, a function of automatically or manually correcting the captured image, a function of storing the captured image on a recording medium (external or embedded in the electronic device), and a function of displaying the captured image on the display unit. Furthermore, the functions of an electronic device of one embodiment of the present invention are not limited to these and may have various functions.

[0286] A display device according to one embodiment of the present invention can display high-definition images. Therefore, it can be particularly suitable for use in portable electronic devices, wearable electronic devices, and e-book terminals. For example, it can be suitable for use in xR devices such as VR devices or AR devices.

[0287] Figure 29 (A) shows the exterior of a head-mounted display (710). The head-mounted display (710) has a mounting part (711), a lens (712), a main body (713), a display part (714), a cable (715), etc. Additionally, a battery (716) is built into the mounting part (711). A display device according to one embodiment of the present invention can be applied to the display part (714).

[0288] The cable (715) supplies power to the main body (713) from the battery (716). The main body (713) is equipped with a wireless receiver, etc., and can display image information, such as received image data, on the display unit (714). Additionally, the movement of the user's eyeball and / or eyelid is detected by a camera provided in the main body (713), and the user's gaze is calculated based on that information, thereby allowing the user's gaze to be used as an input means.

[0289] Additionally, the mounting portion (711) may be provided with multiple electrodes at a position that contacts the user. The main body (713) may have a function of recognizing the user's gaze by detecting the current flowing through the electrodes according to the movement of the user's eyeball. Additionally, it may have a function of monitoring the user's pulse by detecting the current flowing through the electrodes. Furthermore, the mounting portion (711) may have various sensors such as a temperature sensor, a pressure sensor, and an accelerometer, and may have a function of displaying the user's biometric information on the display portion (714). Additionally, it may detect the movement of the user's head and change the image displayed on the display portion (714) according to that movement.

[0290] Figure 29 (B) shows the appearance of a head-mounted display (720). The head-mounted display (720) is a goggle-type information processing device.

[0291] The head-mounted display (720) has a housing (721), an operation button (723), a band-shaped fastener (724), and two display units (722). By having two display units (722), the user can view one display unit per eye. Therefore, high-resolution images can be displayed even when performing three-dimensional displays using parallax. Additionally, a battery (725) is provided in the fastener (724). While it is possible to provide the battery (725) in the housing (721), providing it in the fastener (724) is suitable because it allows the center of gravity of the head-mounted display (720) to be positioned towards the rear, thereby improving the user's sense of mounting. In addition to the battery (725), a driving circuit that operates the display units (722) may also be provided in the fastener (724) to adjust the center of the head-mounted display (720).

[0292] The control button (723) has functions such as a power button. It may also have buttons other than the control button (723).

[0293] A display device according to one embodiment of the present invention can be applied to the display unit (722). Since the display device according to one embodiment of the present invention has a very high degree of precision, pixels are difficult for the user to perceive, and can display an image with a higher sense of realism.

[0294] Figure 29 (C) shows the appearance of a camera (730) equipped with a finder (740).

[0295] The camera (730) has a housing (731), a display (732), an operation button (733), a shutter button (734), etc. Additionally, the camera (730) is equipped with a detachable lens (736).

[0296] Here, the camera (730) is configured so that the lens (736) can be detached from the housing (731) and replaced, but the lens (736) and the housing may be formed as a single unit.

[0297] The camera (730) can take a picture by pressing the shutter button (734). Additionally, the display unit (732) functions as a touch panel, and can also take a picture by touching the display unit (732).

[0298] The housing (731) of the camera (730) has a mount having electrodes, and can connect a strobe device, etc., in addition to the finder (740).

[0299] The finder (740) has a housing (741), a display (742), a button (743), etc.

[0300] The housing (741) has a mount that is coupled to the mount of the camera (730), and can mount the finder (740) to the camera (730). In addition, the mount has an electrode, and can display images received from the camera (730) on the display unit (742) through the electrode.

[0301] The button (743) functions as a power button. The on / off status of the display unit (742) can be switched by the button (743).

[0302] A display device according to one embodiment of the present invention can be applied to the display portion (732) of the camera (730) and the display portion (742) of the finder (740).

[0303] In addition, in (C) of FIG. 29, the camera (730) and the finder (740) are separate electronic devices and are configured to be detachable, but a finder having a display device according to one embodiment of the present invention may be built into the housing (731) of the camera (730).

[0304] The information terminal (750) shown in (D) of FIG. 29 has a housing (751), a display unit (752), a microphone (757), a speaker unit (754), a camera (753), and an operation switch (755), etc. A display device according to one embodiment of the present invention may be applied to the display unit (752). In addition, the display unit (752) has a function as a touch panel. In addition, the information terminal (750) is equipped with an antenna, a battery, etc. inside the housing (751). The information terminal (750) can be used as, for example, a smartphone, a mobile phone, a tablet-type information terminal, a tablet-type personal computer, an e-book terminal, etc.

[0305] Figure 29 (E) shows an example of a wristwatch-type information terminal. The information terminal (760) is equipped with a housing (761), a display unit (762), a band (763), a buckle (764), an operation switch (765), an input / output terminal (766), etc. Additionally, the information terminal (760) is equipped with an antenna and a battery, etc. inside the housing (761). The information terminal (760) can execute various applications such as mobile phone, email, text viewing and writing, music playback, internet communication, and computer games.

[0306] Additionally, the display unit (762) is equipped with a touch sensor and can be operated by touching the screen with a finger or a stylus. For example, an application can be launched by touching an icon (767) displayed on the display unit (762). The operation switch (765) may have various functions in addition to setting the time, such as turning the power on and off, turning wireless communication on and off, enabling and disabling silent mode, and enabling and disabling power saving mode. For example, the functions of the operation switch (765) may be set by an operating system provided to the information terminal (760).

[0307] Additionally, the information terminal (760) can perform standardized short-range wireless communication. For example, it can make hands-free calls by communicating with a headset capable of wireless communication. Additionally, the information terminal (760) is equipped with an input / output terminal (766) and can transmit and receive data with another information terminal through the input / output terminal (766). It can also perform charging through the input / output terminal (766). Additionally, the charging operation may be performed by wireless power supply without using the input / output terminal (766).

[0308] In addition, an electronic device capable of applying a display device according to one embodiment of the present invention shown in FIG. 29 (A) to (E) may be connected to an external server via a network. Furthermore, processing requiring high computational power may not be performed on the electronic device, but rather on a server connected via a network. Such processing is also referred to as a so-called thin client, and the processing scale of the client-side terminal (here, the electronic device) can be reduced by performing only limited processing on the user-side (client-side) terminal and performing advanced processing, such as the execution and management of applications, on the server side. As a result, since there is no need to use a computing device with high computational performance on the electronic device, it is easy to reduce costs, lighten weight, and miniaturize. In addition, in an electronic device of one embodiment of the present invention, processing requiring high computational power may be performed by combining the thin client and the electronic device side.

[0309] The configuration described in this embodiment can be used in appropriate combination with the configurations shown in other embodiments, etc.

[0310] <Notes on the Description in this Specification, etc.>

[0311] The preceding embodiment and the description of each component in the embodiment are added below.

[0312] The configurations described in each embodiment can be appropriately combined with the configurations described in other embodiments to form one form of the present invention. In addition, when multiple configuration examples are described in one embodiment, the configuration examples can be appropriately combined.

[0313] In addition, the contents described in any one embodiment (may be only a part of the contents) may be applied, combined, or substituted, etc. with other contents described in that embodiment (may be only a part of the contents) and / or contents described in one or more other embodiments (may be only a part of the contents).

[0314] In addition, the content described in the embodiments refers to the content described using various drawings in each embodiment or the content described using sentences written in the specification.

[0315] In addition, the drawings described in any one embodiment (may be partial) may comprise more drawings by combining other parts of the drawings, other drawings described in that embodiment (may be partial), and / or drawings described in one or more other embodiments (may be partial).

[0316] Furthermore, in the block diagrams described in this specification and others, components are classified by function and represented as independent blocks. However, in actual circuits, it is difficult to classify components by function, and there may be cases where multiple functions are involved in a single circuit, or where a single function is involved in multiple circuits. Therefore, the blocks in the block diagram are not limited to the components described in the specification and can be appropriately rephrased.

[0317] In addition, in the drawings, the size, layer thickness, or area is shown in arbitrary sizes for convenience of explanation. Therefore, it is not necessarily limited to that scale. Also, the drawings are shown schematically for clarity and are not limited to the shapes or values ​​shown in the drawings. For example, it may include deviations in signal, voltage, or current caused by noise, or deviations in signal, voltage, or current caused by timing misalignment.

[0318] When describing the connection relationship of a transistor in the present specification, etc., notations such as "one of the source and drain (or the first electrode or the first terminal)" and "the other of the source and drain (or the second electrode or the second terminal)" are used. This is because the source and drain of the transistor change depending on the structure or operating conditions of the transistor. In addition, the terms source and drain of the transistor can be appropriately changed to source (drain) terminal or source (drain) electrode.

[0319] Furthermore, the terms "electrode" or "wiring" in this specification and others do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Additionally, the terms "electrode" or "wiring" include cases where multiple "electrodes" or "wiring" are integrally formed.

[0320] In addition, voltage and potential may be appropriately interchanged in this specification and others. Voltage refers to the potential difference from a reference potential, and for example, if the reference potential is ground voltage, voltage may be interchanged with potential. Ground potential does not necessarily mean 0V. Furthermore, potential is relative, and depending on the reference potential, the potential supplied to wiring, etc. may change.

[0321] Additionally, expressions such as "film" and "layer" in this specification are interchangeable. For example, the term "conductive layer" may be changed to the term "conductive film." Or, for example, the term "insulating film" may be changed to the term "insulating layer."

[0322] In the present specification, etc., the term "switch" refers to a device having the function of controlling whether to conduct current by becoming in a conducting state (on state) or a non-conducting state (off state). Alternatively, the term "switch" refers to a device having the function of selecting and switching the path through which current flows.

[0323] In the present specification and others, channel length refers to, for example, the distance between the source and the drain in the region where the semiconductor (or the part of the semiconductor through which current flows when the transistor is in the ON state) and the gate overlap in the top view of the transistor, or in the region where the channel is formed.

[0324] In the present specification, etc., channel width refers to, for example, the length of the region where the semiconductor (or the part of the semiconductor through which current flows when the transistor is in the ON state) and the gate electrode overlap, or the region where the source and drain face each other in the region where the channel is formed.

[0325] In the present specification and others, the "on state" of a transistor refers to a state in which, for example, the source and drain of the transistor can be considered to be short-circuited. For example, in an n-channel transistor, the state in which the voltage between the gate and the source is higher than the threshold voltage, or in a p-channel transistor, the state in which the voltage between the gate and the source is lower than the threshold voltage, is referred to as the "on state." Furthermore, the "on state" of a transistor refers to a state in which current can flow between the source and the drain. Therefore, the "on state" of a transistor is sometimes referred to as the "conduction state" of the transistor.

[0326] In the present specification and other documents, the "off state" of a transistor refers to a state in which the source and drain of the transistor can be considered to be cut off. For example, in an n-channel transistor, a state in which the voltage between the gate and the source is lower than the threshold voltage, or in a p-channel transistor, a state in which the voltage between the gate and the source is higher than the threshold voltage, is referred to as the "off state." Additionally, the "off state" of a transistor may be referred to as the "non-conducting state" of the transistor.

[0327] In the present specification and other documents, the voltage between the gate and the source (gate-source) may be referred to as "gate voltage," the voltage between the drain and the source (drain-source) may be referred to as "drain voltage," and the voltage between the back gate and the source (back gate-source) may be referred to as "back gate voltage." Additionally, the current flowing from the drain to the source may be referred to as "drain current."

[0328] In this specification and others, the term "off-current of a transistor" refers to the drain current when the transistor is in the off state, unless otherwise specifically stated. Additionally, in this specification and others, the term "leakage current" may refer to the off-current and the current flowing from the gate to the source and drain (also referred to as gate leakage current).

[0329] In this specification, "connection" includes, by way of example, "electrical connection." Furthermore, when the term "electrical connection" is used to define the connection relationship of circuit elements as an object, "electrical connection" includes, by way of example, "direct connection" and "indirect connection." "A and B are directly connected" means, by way of example, that A and B are connected without passing through a circuit element (e.g., a transistor or a switch, and wiring is not a circuit element). On the other hand, "A and B are indirectly connected" means, by way of example, that A and B are connected through one or more circuit elements.

[0330] Here, when defined as "A and B are indirectly connected," it refers to the following connection relationships as an example. That is, assuming the circuit is operating, if there is a timing during the circuit's operation period when the exchange of electrical signals or potential interaction occurs between A and B, such a circuit can be defined as "A and B are indirectly connected" as an object. Furthermore, even if there is a timing during which no electrical signal exchange or potential interaction occurs between A and B, if there is a timing during the circuit's operation period when such exchange occurs, it can be defined as "A and B are indirectly connected." Additionally, "A and B are indirectly connected" refers to defining the connection relationship of circuit elements as an object. Therefore, for example, even when power voltage is not supplied to the circuit and the circuit does not operate, the circuit can be defined as an object in which "A and B are indirectly connected" (provided, as an example, that power voltage is supplied to the circuit and the circuit operates, and the exchange of electrical signals or interaction of potentials between A and B occurs during the period of operation of the circuit).

[0331] Specific examples of "indirect connection" are described below. First, examples of cases where "A and B are indirectly connected" include cases where A and B are connected through the sources and drains of one or more transistors. Other examples of cases where "A and B are indirectly connected" include cases where A and B are connected through one or more switches. In cases where "A and B are indirectly connected," assuming the circuit is operating, there is at least one timing when one transistor between A and B is in an ON state, a conducting state, or a state where current can flow. Furthermore, cases where "A and B are indirectly connected" include cases where one transistor between A and B is in an OFF state or a non-conducting state. In cases where "A and B are indirectly connected", if multiple transistors are connected between A and B, assuming the circuit is operating, there is at least one timing when each of the multiple transistors between A and B is in an ON state, a conducting state, or a state where current can flow. That is, in the case where "A and B are indirectly connected," it is not necessary for all of the multiple transistors to be simultaneously in an ON state, a conducting state, or a state where current can flow. Therefore, the case where "A and B are indirectly connected" includes a timing in which multiple transistors between A and B become OFF or non-conducting at the same time or at different timings. As another example, if A and C are connected through the source and drain of transistor (TrP) and B and C are connected through the source and drain of transistor (TrQ), it can be defined as "A and C are indirectly connected," "B and C are indirectly connected," or "A and B are indirectly connected."However, as described below, when a constant potential V is supplied to C from a power source or GND, it may be said that "A and C are indirectly connected" or "B and C are indirectly connected," but it is not said that "A and B are indirectly connected."

[0332] Although examples of cases that can be considered "indirect connection" and those that cannot have been have been explained as above, I will now explain another example of a case where it cannot be considered "indirect connection." Even if the exchange of electrical signals or potential interaction occurs between A and B during the operation of the circuit, there are exceptional cases where it cannot be said that "A and B are indirectly connected." An example of such an exceptional case is when A and B are connected through an insulator. In other words, if A and B are connected through an insulator, it is considered that "A and B are indirectly connected." A specific example of a case where A and B are connected through an insulator is when a capacitive element is connected between A and B. Another example of a case where A and B are connected through an insulator is when the gate insulating film of a transistor is interposed between A and B. In this case, it is not considered that "A (the gate of the transistor) and B (the source or drain of the transistor) are indirectly connected."

[0333] Another example of a case where it cannot be said that "A and B are indirectly connected" is when there is no timing for the exchange of electrical signals or potential interaction between A and B. An example of this is when multiple transistors are connected through their sources and drains in the path from A to B, and a constant potential V is supplied to the node between the transistors from a power source or GND. In this case, it cannot be said that "A and B are indirectly connected," but it can be said that "A and V are indirectly connected" or "B and V are indirectly connected." Additionally, when A and C are connected through the source and drain of a transistor (TrP) and B and C are connected through the source and drain of a transistor (TrQ), and a constant potential V is supplied to C from a power source or GND, it cannot be said that "A and B are indirectly connected," but it can be said that "A and C are indirectly connected" or "B and C are indirectly connected."

[0334] Although examples of "indirect connection" have been explained as such, as an example, since the provisions regarding "indirect connection" are included within the provisions regarding "electrical connection," in the case where "A and B are indirectly connected," it can be said that "A and B are electrically connected."

[0335] Next, specific examples of "direct connection" will be explained. An example of a case where "A and B are directly connected" is when A and B are connected without passing through circuit elements. Furthermore, if A and B are connected to a power source or GND that supplies a constant potential V without passing through circuit elements, it can be said that "A and B are directly connected," "A and V are directly connected," or "B and V are directly connected." Additionally, if A (or B) is connected to a constant potential V through the source and drain of a transistor, it can also be said that "A and B are directly connected." Furthermore, since A and V or B and V are connected through the source and drain of a transistor, they cannot be considered a direct connection, and it can be said that "A and V are indirectly connected" or "B and V are indirectly connected."

[0336] Although examples of "direct connection" have been explained as such, as an example, since the provisions for "direct connection" are included in the provisions for "electrical connection," in the case where "A and B are directly connected," it can be said that "A and B are electrically connected." Explanation of the symbols

[0337] 20: Device layer, 22: Display driver, 29: Terminal, 30: Device layer, 31: Display, 32: Gate line driver circuit, 33: Source line driver circuit, 40: Sealing substrate, 41: LVDS circuit, 42: Serial-to-parallel conversion circuit, 43: Latch circuit, 43M: Memory circuit, 44: Level shifter circuit, 45: Digital-to-analog conversion circuit, 46: Amplifier circuit, 47: Switch circuit, 48: Select circuit, 50: Pixel, 51: Pixel circuit, 60: Light-emitting element layer, 61: Light-emitting element, 70: Processor circuit, 71: Memory, 72: Memory circuit, 77: Analog-to-digital conversion circuit, 78: Arithmetic circuit, 80: Image data correction circuit, 100: Display device

Claims

Claim 1 A display device having a first element layer and a second element layer on the first element layer, wherein the first element layer has a first transistor, the first transistor has a semiconductor layer having a channel forming region made of silicon, the second element layer has a second transistor, the second transistor has a semiconductor layer having a channel forming region made of a metal oxide, and the first element layer is provided with a display driving unit and a processor circuit, wherein the display driving unit has a latch circuit having a function of maintaining image data and an amplifier circuit having a function of outputting an analog voltage according to the image data, the processor circuit has an analog-to-digital conversion circuit that converts the analog voltage into a digital signal and an operation circuit that acquires a correction value according to the digital signal, and the latch circuit has a function of correcting the analog voltage by adding the correction value to the image data. Claim 2 A display device according to claim 1, wherein a display portion is provided in the second element layer, and the display driving portion is provided in an area overlapping with the display portion. Claim 3 A display device according to claim 1 or 2, wherein the second element layer is provided with a display portion, the display portion has a pixel circuit that controls the light emission of a light-emitting element, and the light-emitting element is provided on the second element layer. Claim 4 A display device according to claim 1, wherein the display driving unit has a gate line driving circuit and a source line driving circuit, and the processor circuit unit has a function of switching the driving frequency of the gate line driving circuit and the driving frequency of the source line driving circuit. Claim 5 A display device having a first element layer and a second element layer on the first element layer, wherein the first element layer has a first transistor, the first transistor has a semiconductor layer having a channel forming region made of silicon, the second element layer has a second transistor, the second transistor has a semiconductor layer having a channel forming region made of metal oxide, and the first element layer is provided with a display driving unit and a processor circuit, the display driving unit has a latch circuit having a function of maintaining image data and an amplifier circuit having a function of outputting an analog voltage according to the image data, the processor circuit has an analog-to-digital conversion circuit that converts the analog voltage into a digital signal and an operation circuit that acquires a correction value according to the digital signal, the amplifier circuit is provided for each of a plurality of signal lines, and each of the plurality of signal lines is electrically connected to the analog-to-digital conversion circuit through a switch circuit, the analog voltage is input to the analog-to-digital conversion circuit by sequentially turning on the switch circuit electrically connected to the plurality of signal lines, and the latch circuit adds the correction value to the image data to the analog voltage A display device having a correction function. Claim 6 In claim 5, a display device wherein a display portion is provided in the second element layer, and the display driving portion is provided in an area overlapping with the display portion. Claim 7 A display device according to claim 5 or 6, wherein the second element layer is provided with a display portion, the display portion has a pixel circuit that controls the light emission of a light-emitting element, and the light-emitting element is provided on the second element layer. Claim 8 In claim 5, the display driving unit has a gate line driving circuit and a source line driving circuit, and the processor circuit unit has a function of switching the driving frequency of the gate line driving circuit and the driving frequency of the source line driving circuit, a display device.

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