Copper Diffusion Barrier Film Comprising Tungsten Disulfide Layer And Manufacturing Method Thereof

Abstract

The copper diffusion barrier of the present invention is formed by forming a tungsten disulfide ultrathin film layer on a silicon substrate, and the surface roughness of the tungsten disulfide ultrathin film layer is low, resulting in fewer defects; and it is composed of a crystalline phase having semiconductor properties; thus, not only is the copper diffusion barrier performance excellent, but it also exhibits low stress and bending; copper electroplating is easy; and it shows excellent adhesion to electroplated copper; and since it has excellent durability, it has the advantage of being usable in next-generation advanced packaging by replacing conventional copper diffusion barriers.

Description

Technology Field

[0001] The present invention relates to a copper diffusion barrier film comprising a tungsten disulfide layer and a method for manufacturing the same. More specifically, the invention relates to a copper diffusion barrier film applicable to advanced packaging and heterogeneous integration technologies comprising an ultrathin tungsten disulfide layer and a method for manufacturing the same. Background Technology

[0003] As electronic devices become smaller and more high-performance, there is an increasing demand for technologies that reduce the dimensions of electronic circuits and integrate more circuits and transistors. Aluminum (Al) has been proposed as a material for interconnecting multifunction microprocessors; however, using aluminum has the problem of degrading device performance due to increased resistance-capacitance (RC) latency. To address this issue, technology to replace aluminum with copper is being developed. Copper has the advantage of reducing RC latency due to its high conductivity when interconnected in the back-end-of-line (BEOL) layer. However, copper has the problem of causing device failure and performance degradation due to high levels of copper ions or atoms diffusing into the intermetal dielectric and its surroundings.

[0004] To address the aforementioned problems with copper, research is being conducted on copper diffusion barriers (DBs) that prevent the diffusion of copper ions or copper atoms. Tantalum (Ta) / tantalum nitride (TaN), ruthenium (Ru), manganese (Mn), and titanium (Ti) are being studied as materials for these copper diffusion barriers. However, these materials have limitations in that they are difficult to apply to advanced packaging and heterogeneous integration (HI) technologies because their copper diffusion barrier effects are low due to their complex crystal structures and grain boundary (GB) diffusion pathways.

[0005] The patent documents and references mentioned in this specification are incorporated by reference into this specification to the same extent that each document is individually and clearly identified by reference. Prior art literature

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[0008] The objective of the present invention is to solve the problem of conventional copper diffusion barrier films having low copper diffusion prevention effects due to complex crystal structures and grain diffusion pathways, etc., by forming a tungsten disulfide ultrathin film on a silicon substrate, thereby providing excellent copper diffusion prevention performance; exhibiting low stress and bending; facilitating copper electroplating; and showing excellent adhesion to electroplated copper, thereby providing a copper diffusion barrier film and a method for manufacturing the same that can replace conventional copper diffusion barrier films and be used in next-generation advanced packaging.

[0009] Other objects and technical features of the present invention are more specifically presented by the following detailed description of the invention, claims, and drawings. means of solving the problem

[0011] The present invention provides a copper diffusion barrier film comprising: a silicon substrate; and a tungsten disulfide layer formed on the silicon substrate, the thickness of which is 0.3 to 10 nm.

[0012] The copper diffusion barrier film is characterized by a surface roughness of 0.1 to 0.7 nm; and an interface trap density of 0.3 to 2.5 x 10⁻⁶ 11 cm -2 eV -1 It is characterized by having a breakdown voltage of 5 to 12 MV / cm.

[0013] The present invention provides a method for manufacturing a copper diffusion barrier film, comprising: a first step of manufacturing a tungsten-silicon substrate by depositing tungsten on a silicon substrate; and a second step of manufacturing a copper diffusion barrier film by sulfidating the tungsten-silicon substrate to form a tungsten disulfide layer. Effects of the invention

[0015] The copper diffusion barrier of the present invention is formed by forming a tungsten disulfide ultrathin film layer on a silicon substrate, and the surface roughness of the tungsten disulfide ultrathin film layer is low, resulting in fewer defects; and it is composed of a crystalline phase having semiconductor properties; thus, not only is the copper diffusion barrier performance excellent, but it also exhibits low stress and bending; copper electroplating is easy; and it shows excellent adhesion to electroplated copper; and since it has excellent durability, it has the advantage of being usable in next-generation advanced packaging by replacing conventional copper diffusion barriers. Brief explanation of the drawing

[0017] Figure 1 shows the results of an atomic force microscope (AFM) analysis of a copper diffusion barrier film comprising a tungsten disulfide layer of the present invention. Figure 2 shows the transmission electron microscope (TEM) analysis results for a copper diffusion barrier film including a tungsten disulfide layer of the present invention. Figure 3 shows the results of X-ray diffraction (XRD) analysis for a copper diffusion barrier film comprising a tungsten disulfide layer of the present invention. Figure 4 shows the results of Raman spectroscopy analysis for the tungsten disulfide film of the present invention. Figure 5 shows the X-ray photoelectron spectroscopy (XPS) results for the tungsten disulfide layer of the present invention. Figure 6 shows the current-voltage (JE) measurement results for a MOS structure manufactured using a copper diffusion barrier film including a tungsten disulfide layer of the present invention and a MOS structure manufactured using silicon oxide. Figure 7 shows the capacitance-voltage (CV) measurement results for a MOS structure manufactured using silicon oxide and a copper diffusion barrier film including a tungsten disulfide layer of the present invention. Figure 8 shows the interfacial charge trapping density for a MOS structure manufactured using a copper diffusion barrier film including a tungsten disulfide layer of the present invention and a MOS structure manufactured using silicon oxide. Figure 9 shows the current-voltage (JE) measurement results according to temperature (22 to 400°C) of a MOS structure manufactured using a copper diffusion barrier film including a tungsten disulfide layer of Example 1 of the present invention. Figure 10 shows the current-voltage (JE) measurement results according to temperature (-200 to 22°C) of a MOS structure manufactured using a copper diffusion barrier film including a tungsten disulfide layer of Example 1 of the present invention. Figure 11 shows the results of measuring the degree of warpage of a MOS structure manufactured using a copper diffusion barrier film including a tungsten disulfide layer of the present invention. Figure 12 shows the result of performing copper electroplating on a copper diffusion barrier film including a tungsten disulfide layer of the present invention. Specific details for implementing the invention

[0018] The present invention provides a copper diffusion barrier film comprising: a silicon substrate; and a tungsten disulfide layer formed on the silicon substrate, the thickness of which is 0.3 to 10 nm.

[0019] The silicon substrate may be a silicon substrate made of one or a mixture of silicon (Si) or silicon oxide (SiO2), and preferably is a silicon oxide (SiO2) substrate. The tungsten disulfide (WS2) layer is characterized by being formed by depositing tungsten (W) onto the silicon substrate and then sulfidating the tungsten. The tungsten disulfide layer is characterized by being in the form of an ultrathin film with a thickness of nanometers, and preferably, the thickness of the tungsten disulfide layer is 0.3 to 10 nm. If the thickness of the tungsten disulfide layer is less than 0.2 nm, there is a problem with difficulty in deposition, and if it exceeds 10 nm, there is a problem with reduced copper diffusion prevention performance. More preferably, the thickness of the tungsten disulfide layer is 0.5 to 7 nm, and more preferably, 0.7 to 4.5 nm.

[0020] The copper diffusion barrier of the present invention is characterized by having a surface roughness of 0.1 to 0.7 nm. The surface roughness reflects surface defects in the tungsten disulfide layer, and as the surface roughness increases, defects in the tungsten disulfide layer increase, forming diffusion pathways for copper, which leads to a problem where the copper diffusion barrier effect is reduced. Preferably, the copper diffusion barrier is characterized by having a surface roughness of 0.2 to 0.6 nm, and more preferably, the copper diffusion barrier is characterized by having a surface roughness of 0.3 to 0.55 nm.

[0021] The copper diffusion barrier of the present invention has an interface trap density of 0.3 to 2.5 x 10⁻⁶ 11 cm -2 eV -1It is characterized by the following. The interface-trapped charge density refers to the total amount of charge present in a certain area or volume between the silicon substrate and the tungsten disulfide layer, and a high interface-trapped charge density implies high mobility of charge carriers. Preferably, the interface-trapped charge density of the copper diffusion barrier of the present invention is 0.45 to 2.5 x 10⁻⁶. 11 cm -2 eV -1 and; more preferably 0.6 to 2.3 x 10 11 cm -2 eV -1 am.

[0022] The copper diffusion barrier of the present invention is characterized by having a breakdown voltage of 5 to 12 MV / cm. The breakdown voltage refers to the voltage at which electrical resistance is destroyed and current flows when a reverse electromotive force is applied. Since a low breakdown voltage implies that electrical resistance is easily destroyed and current flows, a higher breakdown voltage implies that the diffusion inhibition effect of a carrier such as copper is superior. Preferably, the copper diffusion barrier of the present invention is characterized by having a breakdown voltage of 6 to 12 MV / cm; more preferably, the copper diffusion barrier of the present invention is characterized by having a breakdown voltage of 6.5 to 10 MV / cm.

[0023] The present invention provides a method for manufacturing a copper diffusion barrier film, comprising: a first step of manufacturing a tungsten-silicon substrate by depositing tungsten on a silicon substrate; and a second step of manufacturing a copper diffusion barrier film by sulfidating the tungsten-silicon substrate to form a tungsten disulfide layer.

[0024] The present invention will be explained in detail through the following examples.

[0026] Examples

[0028] 1. Experimental Method

[0029] 1) Copper diffusion barrier containing a tungsten disulfide layer

[0030] The present invention relates to a copper diffusion barrier (DB) comprising a tungsten disulfide (WS2) layer. The copper diffusion barrier comprising a tungsten disulfide layer according to the present invention was manufactured by a manufacturing method comprising: a first step of manufacturing a tungsten-silicon substrate by depositing tungsten on a silicon substrate; and a second step of forming a tungsten disulfide layer by sulfidating the tungsten-silicon substrate.

[0031] A silicon substrate (silicon (Si) or silicon oxide (SiO2) substrate) was washed with acetone and methanol, dried with nitrogen (N2) gas, and tungsten (W, 99.95%) was deposited on the dried silicon substrate using sputtering technology. Prior to the main deposition, a pre-deposition was performed for 20 minutes to remove contaminants. The tungsten deposition was performed at a base pressure of 4.1 x 10⁻⁶ -7 The distance between the tungsten anode target and the silicon oxide (SiO2) sample (substrate) was set to 10 cm and a 20 sccm argon-plasma (Ar-Plasma) atmosphere; 80 W forward power; and 30 mTorr working pressure were used to perform deposition for 10 seconds (Example 1), 30 seconds (Example 2), 60 seconds (1 minute, Example 3), 300 seconds (5 minutes, Example 4), 600 seconds (10 minutes, Example 5), or 1800 seconds (30 minutes, Example 6). The tungsten-silicon substrate prepared through the above deposition was sulfidated using sulfur powder for 1 hour in a vacuum furnace at 400°C in an argon (Ar) atmosphere to produce a copper diffusion barrier film containing a tungsten disulfide layer.

[0032] For the copper diffusion barrier films comprising a tungsten disulfide layer of Examples 1 to 6 prepared by varying the tungsten deposition time (sputter time) above, the thickness of the tungsten disulfide layer (WS2Thickness, nm); surface roughness (Surface Roughness, nm); XPS binding energy (XPS binding energy, eV); and interface trap density (D it , 10 11 cm -2 eV -1 ); and Breakdown Voltage (V B , MV / cm); was analyzed (see Table 1).

[0033] Examples 1 2 3 4 5 6 Sputter(W) Time(sec) 10 30 60 300 600 1800 WS2Thickness(nm) 0.7 2.2 4.5 21 38.6 50.2 Surface Roughness (nm) 0.34 0.42 0.51 0.85 1.50 3.57 XPS binding energy (eV) W 5p 3 / 2 37.90 37.85 37.72 37.45 37.42 37.06 In 4f 5 / 2 34.35 34.30 34.11 34.10 34.07 34.30 In 4f 7 / 2 32.23 32.10 31.92 31.92 31.91 33.13 Interface Trap Density(D it , 10 11 ㎝ -2 eV -1 ) 0.61 1.1 2.3 2.7 4.1 8.9 Breakdown Voltage(V B , MV / ㎝) 9.7 to 10 7.1 6.5 5.8 2.7 1

[0035] 2) Metal oxide semiconductor structure

[0036] A metal oxide semiconductor (MOS) structure was fabricated by depositing a copper / aluminum (Cu / Al) electrode on a copper diffusion barrier film comprising a tungsten disulfide layer according to the present invention. The deposition was performed using a thermal evaporation technique (E-Vac). To form a dot structure on the MOS structure, a shadow mask (150x150㎛) was used. 2 ) was used, and the copper (Cu, 60 nm) and aluminum (Al, 40 nm) passivation layers were evaporation chambers (3.4 x 10⁻⁶). -6 It was manufactured by evaporation in Pa). The electrical characteristics of the MOS structure manufactured above were analyzed using a MOS capacitor.

[0038] 2. Experimental Results

[0039] 1) Analysis of physical properties of a copper diffusion barrier containing a tungsten disulfide layer

[0040] A copper diffusion barrier film comprising a tungsten disulfide layer according to the present invention was manufactured, and its physical properties were analyzed.

[0041] (1) Results of atomic microscope analysis

[0042] FIG. 1 shows the results of atomic force microscope (AFM) analysis of a copper diffusion barrier film comprising a tungsten disulfide layer of the present invention. Panel a) shows the results of AFM analysis for Example 1; panel b) shows the results of AFM analysis for Example 2; panel c) shows the results of AFM analysis for Example 3; panel d) shows the results of AFM analysis for Example 4; panel e) shows the results of AFM analysis for Example 5; and panel f) shows the results of AFM analysis for Example 6.

[0043] Analysis results confirmed that the shorter the tungsten deposition time, the better the surface uniformity of the tungsten disulfide film. In Example 1, where tungsten deposition was performed for 10 seconds, the roughness of the tungsten disulfide layer was 0.34 nm, whereas in Example 2, where tungsten deposition was performed for 30 seconds, the roughness of the tungsten disulfide layer was 0.42 nm. Additionally, in the example where tungsten deposition was performed for more than 30 seconds, the roughness increased further and crystals were observed; this is judged to be because grain formation was strengthened as the tungsten deposition time increased. When the above grain boundaries are formed, copper (Cu) diffusion through the grain path increases, which may lead to a problem where the copper diffusion prevention performance is degraded.

[0045] (2) Transmission electron microscope analysis results

[0046] FIG. 2 shows the transmission electron microscope (TEM) analysis results for a copper diffusion barrier film comprising a tungsten disulfide layer of the present invention. Panel a) shows the TEM analysis results for Example 1; panel b) shows the TEM analysis results for Example 2; and panel c) shows the TEM analysis results for Example 6.

[0047] Analysis results confirmed that the thickness of the tungsten disulfide layer increased as the tungsten deposition time increased. The thickness of the tungsten disulfide layer in Example 1 was confirmed to be 0.7 nm; the thickness of the tungsten disulfide layer in Example 2 was confirmed to be 2.2 nm; and the thickness of the tungsten disulfide layer in Example 6 was confirmed to be 50.2 nm. These results are supported by Energy Dispersive X-ray Spectrometer (EDX) results.

[0049] (3) X-ray diffraction analysis results

[0050] FIG. 3 shows the X-ray diffraction (XRD) analysis results for a copper diffusion barrier film comprising a tungsten disulfide layer of the present invention. i) shows the XRD analysis results of Example 1; ii) shows the XRD analysis results of Example 2; and iii) shows the XRD analysis results of Example 6.

[0051] As a result of the analysis, peaks 004, 100, 101, 105, 110, and 117 were identified in the copper diffusion barrier containing the tungsten disulfide layer of Examples 1 and 2, which means that the tungsten disulfide layer of Examples 1 and 2 has a hexagonal (2H) crystal system. In contrast, peaks 006, 101, 012, 104, 015, 107, 018, 110, and 103 were identified in the copper diffusion barrier containing the tungsten disulfide layer of Example 6, which means that the tungsten disulfide layer of the copper diffusion barrier containing the tungsten disulfide layer of Example 6 exists in a state where the hexagonal (2H phase) crystal structure and the rhombohedral (3R phase) crystal structure are mixed.

[0052] The above XRD analysis results indicate that the growth process of the tungsten disulfide layer is controlled by a complex and sensitive mechanism. It is determined that the complexity of the crystal structure of the tungsten disulfide layer is proportional to the deposition time, and this is related to the energy level applied during deposition.

[0053] It is known that copper diffusion barriers exhibit superior copper diffusion inhibition performance as their electrical conductivity decreases. Tungsten disulfide with a 2H-phase crystal structure possesses semiconductor properties, resulting in lower electrical conductivity than tungsten disulfide with a 2R-phase crystal structure and greater stability than tungsten disulfide with a 3R-phase crystal structure. Therefore, it is determined that the copper diffusion inhibition performance of the copper diffusion barrier containing the tungsten disulfide layer of Examples 1 and 2 is superior to that of the copper diffusion barrier containing the tungsten disulfide layer of Example 6.

[0055] (4) Raman spectroscopic analysis results

[0056] FIG. 4 shows the results of Raman spectroscopy analysis of the tungsten disulfide film of the present invention. (i) shows the results of Raman spectroscopy analysis of Example 1; (ii) shows the results of Raman spectroscopy analysis of Example 2; and (iii) shows the results of Raman spectroscopy analysis of Example 6.

[0057] Raman spectroscopic analysis result A 1 g Peak (420 to 435 cm) -1 ) and E 1 2g Peak (360cm) -1 It was confirmed that the intensity of ) is proportional to the thickness of the tungsten disulfide layer, and that said thickness increases the shift of the v peak. As the thickness of the tungsten disulfide layer increases, the strain effect and the quality of the crystal structure increase, and the degree of sulfur treatment on the surface of the tungsten layer increases, which is related to Raman spectroscopy, particularly A 1 g Peak (420 to 435 cm) -1 It is determined that it increases the signal strength and movement of ).

[0059] (5) X-ray photoelectron spectroscopy analysis results

[0060] FIG. 5 shows the X-ray Photoelectron Spectroscopy (XPS) results for the tungsten disulfide layer of the present invention. Panel a) shows the XPS analysis results of Example 1 at 10 sec WS2; the XPS analysis results of Example 2 at 30 sec WS2; and the XPS analysis results of Example 6 at 30 min WS2. Panel b) shows the XPS W core-level spectroscopic analysis results of Example 1 (10 sec WS2); Panel c) shows the XPS W core-level spectroscopic analysis results of Example 2 (30 sec WS2); and Panel d) shows the XPS W core-level spectroscopic analysis results of Example 6 (30 min WS2).

[0061] Analysis results confirmed tungsten (W), sulfur (S), oxygen (O), nitrogen (N), and carbon (C) peaks in all examples (see Panel a of Fig. 5). XPS W core-level spectroscopic analysis revealed that the W 4f core profile was mainly W 5p 3 / 2 , W 4f 5 / 2 and W 4f 7 / 2 It was confirmed to consist of peaks. In the case of Example 1, W 5p 3 / 2 It was confirmed to have a binding energy of 37.90 eV; W 4f 5 / 2 It was confirmed to have a binding energy of 34.35 eV; W 4f 7 / 2 It was confirmed to have a binding energy of 32.23 eV (see Panel b of Fig. 5 and Table 1). The tungsten disulfide layers of Examples 1 and 2 were confirmed to have a 2H phase crystal structure, and it was confirmed that a blue shift appears as the thickness of the tungsten disulfide layer increases. The difference in binding energy and the observation of the blue shift are considered to be caused by phase transitions and structural changes in the crystal structure. In the case of Example 6, where the tungsten deposition time exceeds 30 seconds, W + A peak is identified, which is determined to be due to an increase in thickness and surface sulfidation levels. Additionally, in the case of Example 6, a new peak (Defects peak) is identified at a binding energy of 28 to 29 eV, which is determined to be due to defects associated with the bulk structure of tungsten disulfide (see Panel d of Fig. 5).

[0063] 2) Analysis of electrical characteristics of a copper diffusion barrier containing a tungsten disulfide layer

[0064] A MOS structure was manufactured using a copper diffusion barrier film containing a tungsten disulfide layer of the present invention, and its electrical characteristics were analyzed.

[0065] (1) Current-voltage measurement results

[0066] FIG. 6 shows the current-voltage (JE) measurement results for a MOS structure prepared using a copper diffusion barrier film containing a tungsten disulfide layer of the present invention and a MOS structure prepared using silicon oxide. SiO2 represents the JE measurement result of the MOS structure prepared using a silicon oxide film; 10 sec represents the JE measurement result of the MOS structure prepared using a copper diffusion barrier film containing a tungsten disulfide layer of Example 1; 30 sec represents the JE measurement result of the MOS structure prepared using a copper diffusion barrier film containing a tungsten disulfide layer of Example 2; 1 min represents the JE measurement result of the MOS structure prepared using a copper diffusion barrier film containing a tungsten disulfide layer of Example 3; and 5 min represents the JE measurement result of the MOS structure prepared using a copper diffusion barrier film containing a tungsten disulfide layer of Example 4. 10 Min refers to the JE measurement result of a MOS structure prepared using a copper diffusion barrier film including a tungsten disulfide layer of Example 5; and 30 Min refers to the JE measurement result of a MOS structure prepared using a copper diffusion barrier film including a tungsten disulfide layer of Example 6.

[0067] The MOS structure using the copper diffusion barrier film comprising a tungsten disulfide layer according to the present invention includes the tungsten disulfide layer of Examples 1 to 6 and has a structure of aluminum (Al) / copper (Cu) / tungsten disulfide (WS2) / silicon oxide (SiO2) / silicon (Si) / aluminum (Al). The MOS structure manufactured using the silicon oxide film is a structure manufactured without a tungsten disulfide layer. The JE measurement was performed under conditions of a voltage range of 0 to 100 V and a specified current of 100 μ.

[0068] As a result of the analysis, the MOS structure using the copper diffusion barrier film including a tungsten disulfide layer according to the present invention shows that as the thickness of the tungsten disulfide layer decreases from 50 nm to 0.7 nm, the breakdown voltage (Breakdown Voltage, V) B It was confirmed that ) increases. Specifically, the MOS structure including the tungsten disulfide layer (0.7 nm) of Example 1, which has the thinnest thickness, V B It was confirmed that the value had the largest value of 9.7 to 10 MV / cm, and V B The smallest amount of current up to (10 -10 to 10 -9 A / cm 2 It was confirmed that ) flows. In contrast, the MOS structure including the tungsten disulfide layer (50 nm) of Example 6 and the MOS structure manufactured using silicon oxide had a breakdown voltage (Breakdown Voltage, V B It was confirmed that ) has a very small value of less than 1 MV / cm, and the current is also 10 -4 A / cm 2 It was confirmed that it flows to a certain level. The above result means that copper was easily diffused in the MOS structure containing the tungsten disulfide layer (50 nm) of Example 6 and the MOS structure prepared using silicon oxide.

[0069] The MOS structure using a copper diffusion barrier film (thickness 2.2 nm) including a tungsten disulfide layer of Example 2 of the present invention V B It was confirmed that the value was ~6.8 to 7.1 MV / cm, indicating excellent copper diffusion prevention performance.

[0070] The above results indicate that copper diffusion in the copper diffusion barrier is carried out by diffusion paths within the layer or between layers. According to the analysis results, it was confirmed that the copper diffusion barrier comprising the tungsten disulfide layer of Example 1, which has the thinnest thickness (0.7 nm), showed uniform growth of the 2H phase crystal structure without defects. Therefore, in the MOS structure using the copper diffusion barrier comprising the ultrathin film (thickness 0.7 nm) tungsten disulfide layer of the present invention, copper diffusion was effectively suppressed, thus having the largest V B It is judged that the above results showed a value. The surface roughness increased, and the MOS structure using a tungsten disulfide copper diffusion barrier of another embodiment, in which the crystal structure is composed of a mixed phase of 2H-phase and 3R-phase crystal structures, exhibited a small V due to copper diffusion. B This is supported by the results showing the value. The increase in the surface roughness is due to defects in the copper diffusion barrier film. Therefore, it is considered natural to interpret the increase in surface defects as a decrease in copper diffusion barrier performance. In addition, while the 2H phase crystal structure exhibits the most stable semiconductor properties, the mixed phase crystal structure of the 2H and 3R phases possesses both metallic and semiconductor properties, so it is judged that copper diffusion is freer.

[0072] (2) Capacitance-voltage measurement results

[0073] FIG. 7 shows the capacitance-voltage (CV) measurement results for a MOS structure prepared using a copper diffusion barrier film containing a tungsten disulfide layer of the present invention and a MOS structure prepared using silicon oxide. SiO2 / Cu shows the CV measurement results of the MOS structure prepared using a silicon oxide film; 10 sec shows the CV measurement results of the MOS structure prepared using a copper diffusion barrier film containing a tungsten disulfide layer (thickness 0.7 nm) of Example 1; 30 sec shows the CV measurement results of the MOS structure prepared using a copper diffusion barrier film containing a tungsten disulfide layer (thickness 2.2 nm) of Example 2; and 1 min shows the CV measurement results of the MOS structure prepared using a copper diffusion barrier film containing a tungsten disulfide layer (thickness 4.5 nm) of Example 3. 30Min shows the CV measurement results of a MOS structure prepared using a copper diffusion barrier film (thickness 50.2 nm) containing a tungsten disulfide layer of Example 6.

[0074] Analysis results confirmed that hysteresis due to general defects was observed in the MOS structure fabricated using a silicon oxide film. It was confirmed that the CV curve of the MOS structure fabricated using a copper diffusion barrier film containing a tungsten disulfide layer in Examples 1, 2, and 3 shifted in the positive direction without hysteresis compared to the MOS structure fabricated using a silicon oxide film. However, it was confirmed that the MOS structure fabricated using a copper diffusion barrier film containing a tungsten disulfide layer in Example 6 shifted in the negative direction more than the MOS structure fabricated using a silicon oxide film.

[0075] The shift in the above CV curve moves in the negative direction as the thickness of the copper diffusion barrier containing the tungsten disulfide layer increases, which is determined to be caused by the diffusion of positive charges. This is because when positive charges become dominant, an electric field is formed, and a negative gate voltage is generated to compensate for this. It was confirmed that the minority charge in the low-frequency region was larger in the MOS structure manufactured using the copper diffusion barrier containing the tungsten disulfide layer of Example 2 than in the MOS structure manufactured using the copper diffusion barrier containing the tungsten disulfide layer of Example 1. The above minority charge can lead to a diffusion current, which can be interpreted as a degradation of the copper diffusion barrier performance.

[0077] (3) Measurement of interfacial charge capture density

[0078] Interface trap densities (D) from the CV curves for a MOS structure prepared using the copper diffusion barrier film including a tungsten disulfide layer of the present invention and a MOS structure prepared using silicon oxide it ) was analyzed.

[0079] Figure 8 shows the interfacial charge trapping density for a MOS structure manufactured using a copper diffusion barrier film including a tungsten disulfide layer of the present invention and a MOS structure manufactured using silicon oxide.

[0080] As a result of the analysis, the interfacial charge trapping density of the MOS structure prepared using the copper diffusion barrier film containing the tungsten disulfide layer of Examples 1 to 6 is 0.61 to 8.9 x 10⁻⁶. 11 cm -2 eV -1 It was confirmed that the MOS structure prepared using the copper diffusion barrier film (thickness 0.7 nm) containing the tungsten disulfide layer of Example 1 had the lowest interfacial charge trapping density (0.61 x 10⁻⁶). 11 cm -2 eV-1 It was confirmed that it has ) and that the interfacial charge capture density increases as the thickness of the tungsten disulfide layer increases. The increase in the interfacial charge capture density accelerates the movement of charge carriers. Therefore, it is determined that the copper diffusion barrier film containing the tungsten disulfide layer of Example 1, which has the lowest interfacial charge capture density, exhibits the best copper diffusion prevention effect.

[0082] 3) Reliability Evaluation

[0083] (1) Analysis of changes in copper diffusion prevention performance according to temperature

[0084] Figure 9 shows the current-voltage (JE) measurement results according to temperature (22 to 400°C) of a MOS structure prepared using a copper diffusion barrier film including a tungsten disulfide layer of Example 1 of the present invention. The JE measurement results were analyzed by maintaining the structure at 22°C (room temperature), 150°C, and 400°C for 5 hours.

[0085] Analysis results show that under room temperature conditions, the breakdown voltage (Breakdown Voltage, V B While ) was confirmed at around 10 MV / cm, it was confirmed at around 8 MV / cm under 150℃ conditions and at around 6.5 MV / cm under 400℃ conditions. The above results indicate that the copper diffusion barrier film containing the tungsten disulfide layer of the present invention has a reduced copper diffusion effect as the temperature increases. This is because, as the temperature increases, structural changes occur in the tungsten disulfide layer, resulting in voids or gaps, and phase transitions occur, forming grain boundaries, which is believed to reduce dielectric performance.

[0086] Figure 10 shows the current-voltage (JE) measurement results according to temperature (-200 to 22°C) of a MOS structure prepared using a copper diffusion barrier film including a tungsten disulfide layer of Example 1 of the present invention. The JE measurement results were analyzed by maintaining the structure at 22°C (room temperature), -50°C, -100°C, -150°C, and -400°C for 5 hours.

[0087] As a result of the analysis, the MOS structure prepared using the copper diffusion barrier film including the tungsten disulfide layer of Example 1 of the present invention V under room temperature conditions B It was at the level of 10 MV / cm, but at -50℃ V B At the level of 11 MV / cm, V at -100℃ B At the level of 12.5 MV / cm, and at -150℃, V B At the level of 13.2 MV / cm, V at -200℃ B It was confirmed that it gradually increased to a level of 14.8 MV / cm.

[0089] (2) Analysis of bending degree

[0090] FIG. 11 shows the results of measuring the degree of warpage of a MOS structure manufactured using a copper diffusion barrier film including a tungsten disulfide layer of the present invention. SiO2 shows the results of measuring the degree of warpage of a MOS structure manufactured using a silicon oxide film; W shows the results of measuring the degree of warpage of a MOS structure manufactured using tungsten (W); 0.7 nm WS2 shows the results of measuring the degree of warpage of a MOS structure manufactured using the tungsten disulfide copper diffusion barrier film (thickness 0.7 nm) of Example 1; and 2.2 nm WS2 shows the results of measuring the degree of warpage of a MOS structure manufactured using the tungsten disulfide copper diffusion barrier film (thickness 2.2 nm) of Example 2. 38.6 nm WS2 shows the result of measuring the degree of bending of a MOS structure manufactured using the tungsten copper disulfide diffusion barrier film (thickness 38.6 nm) of Example 5.

[0091] Analysis results confirmed that as the thickness increases, the tensile stress increases, leading to an increase in the degree of bending. As tensile stress increases, cracks and fractures are more likely to occur. Therefore, it is determined that the thinner the thickness, the higher the durability. The above results are supported by the findings from the atomic force microscopy and X-ray photoelectron spectroscopy analysis, which showed that surface roughness and defects increase as the thickness increases.

[0093] (3) Copper electroplating analysis

[0094] Copper electroplating holds high potential in the field of advanced packaging due to its diverse creativity in interconnection, low-temperature processing, precise control over deposition, high deposition rates, and the ability to plate through photoresist patterns. In particular, the method of directly depositing copper onto a copper diffusion barrier is a highly recommended technique in advanced semiconductor packaging. Directly plating copper onto a diffusion barrier offers the advantage of eliminating the seed layer, excellent adhesion, improved barrier performance, reduced resistivity, and enhanced compatibility.

[0095] FIG. 12 shows the results of performing copper electroplating on a copper diffusion barrier film containing a tungsten disulfide layer according to the present invention. Panel a) shows the results of performing direct copper electroplating on a copper diffusion barrier film (thickness 0.7 nm) containing a tungsten disulfide layer according to Example 1 of the present invention, and Panel b) shows the results of performing a tape test on copper dots plated on a copper diffusion barrier film (WS2, thickness 0.7 nm) containing a tungsten disulfide layer according to Example 1 and a copper diffusion barrier film (SiO2) not containing a tungsten disulfide layer. A1 shows the results immediately after copper plating, A2 shows the results after 10 tape tests, and A3 shows the results after 20 tape tests. The copper electroplating was performed using a thermal evaporation technique and a shadow mask.

[0096] Analysis results confirmed that copper was uniformly plated on the copper diffusion barrier film containing a tungsten disulfide layer of the present invention. The above results indicate that the copper diffusion barrier film containing a tungsten disulfide layer of the present invention exhibits excellent liner characteristics that enable copper electroplating without a seed layer or an adhesive layer containing tantalum (Ta) or titanium (Ti).

[0097] As a result of the analysis, when a tape test was performed 10 times on a copper diffusion barrier (SiO2) that did not contain a tungsten disulfide layer, surface peeling was confirmed in 4 of the plated copper dots, and when a tape test was performed 20 times, surface peeling was confirmed in 6 of the plated copper dots. In contrast, when a tape test was performed more than 20 times on a copper diffusion barrier containing a tungsten disulfide layer, no surface peeling of the copper dots was confirmed.

[0098] The above results indicate that the copper diffusion barrier film comprising the tungsten disulfide layer of the present invention has excellent adhesion to copper electroplating and excellent durability.

[0099] In summary, the copper diffusion barrier film comprising a tungsten disulfide layer according to the present invention has the advantages of low stress and bending when the tungsten disulfide layer is manufactured by ultra-thin deposition; easy electroplating; and excellent adhesion, so it can be used as a copper diffusion barrier film for advanced packaging.

[0101] 3. Conclusion

[0102] In advanced packaging, copper diffusion barriers that prevent copper diffusion and electrical movement are very important. To solve the problems of conventional tantalum (Ta) / tantalum nitride (TaN) dual-liner copper diffusion barriers, the present invention provides a copper diffusion barrier comprising an ultrathin tungsten disulfide layer as a new copper diffusion barrier.

[0103] According to an embodiment of the present invention, a copper diffusion barrier film comprising an ultrathin tungsten disulfide layer of the present invention has a high breakdown voltage (Breakdown Voltage, V B Exhibiting ); low interface trap density (D itIt was confirmed to exhibit ); low stress and bending; easy electroplating; and excellent adhesion.

[0104] Therefore, it is believed that the copper diffusion barrier film comprising the ultra-thin tungsten disulfide layer of the present invention can be used as a copper diffusion barrier film for next-generation advanced packaging by replacing the conventional tantalum (Ta) / tantalum nitride (TaN) dual liner copper diffusion barrier film.

[0105] The specific embodiments described herein represent preferred embodiments or examples of the invention and do not limit the scope of the invention. It is evident to those skilled in the art that variations and other uses of the invention do not deviate from the scope of the invention as described in the claims of this specification.

Claims

Claim 1 A copper diffusion barrier comprising: a silicon substrate; and a tungsten disulfide layer formed on the silicon substrate, the thickness of which is 0.3 to 10 nm. Claim 2 A copper diffusion barrier according to claim 1, characterized in that the copper diffusion barrier has a surface roughness of 0.1 to 0.7 nm. Claim 3 In claim 1, the copper diffusion barrier has an interface trap density of 0.3 to 2.5 x 10⁻⁶ 11 cm -2 eV -1 Copper diffusion barrier characterized by being. Claim 4 A copper diffusion barrier according to claim 1, characterized in that the copper diffusion barrier has a breakdown voltage of 5 to 12 MV / cm. Claim 5 A method for manufacturing a copper diffusion barrier film, comprising: a first step of manufacturing a tungsten-silicon substrate by depositing tungsten on a silicon substrate; and a second step of manufacturing a copper diffusion barrier film by sulfidating the tungsten-silicon substrate to form a tungsten disulfide layer.

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