Semiconductor device and method for fabricating the same

Abstract

A semiconductor device is provided. A semiconductor device comprises a substrate, an active pattern extending in a first horizontal direction on the upper surface of the substrate, first and second nanosheets containing silicon (Si) stacked sequentially spaced apart in a direction perpendicular to the upper surface of the active pattern, third and fourth nanosheets containing silicon (Si) stacked sequentially spaced apart in a direction perpendicular to the upper surface of the active pattern, spaced apart from each of the first and second nanosheets in a first horizontal direction, respectively, a first channel doping layer spaced apart in a direction perpendicular to the upper surface of the active pattern, connecting the first and third nanosheets, contacting the sidewalls of each of the first and third nanosheets in a first horizontal direction, and doped with a first impurity in silicon (Si), a second channel doping layer spaced apart in a direction perpendicular to the upper surface of the first channel doping layer, connecting the second and fourth nanosheets, contacting the sidewalls of each of the second and fourth nanosheets in a first horizontal direction, and doped with a first impurity in silicon (Si), extending in a second horizontal direction different from the first horizontal direction on the upper surface of the active pattern, It includes a first gate electrode surrounding the first and second nanosheets, a second gate electrode extending in a second horizontal direction on the upper surface of the active pattern and spaced apart from the first gate electrode in a first horizontal direction and surrounding the third and fourth nanosheets, and a source / drain region disposed between the first gate electrode and the second gate electrode on the upper surface of the active pattern and surrounding the first and second channel doping layers.

Description

Technology Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same. Specifically, the present invention relates to an MBCFET TM The present invention relates to a semiconductor device including a Multi-Bridge Channel Field Effect Transistor and a method for manufacturing the same. Background Technology

[0002] As one of the scaling techniques to increase the density of integrated circuit devices, a multi-gate transistor has been proposed in which a silicon body in the shape of a fin or nanowire is formed on a substrate and a gate is formed on the surface of the silicon body.

[0003] Since these multi-gate transistors utilize a three-dimensional channel, they are easy to scale. In addition, current control capability can be improved without increasing the gate length of the multi-gate transistor. Furthermore, the short channel effect (SCE), in which the potential of the channel region is affected by the drain voltage, can be effectively suppressed. The problem to be solved

[0004] The problem that the present invention aims to solve is to provide a semiconductor device and a method for manufacturing a semiconductor device that improve electrical characteristics by improving the reliability of the source / drain region.

[0005] The problems that the present invention aims to solve are not limited to those mentioned above, and other unmentioned problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0006] Some embodiments of a semiconductor device according to the technical concept of the present invention for solving the above problem include: a substrate; an active pattern extending in a first horizontal direction on the upper surface of the substrate; first and second nanosheets containing silicon (Si) stacked sequentially spaced apart in a direction perpendicular to the upper surface of the active pattern; third and fourth nanosheets containing silicon (Si) stacked sequentially spaced apart in a direction perpendicular to the upper surface of the active pattern, spaced apart in a first horizontal direction from each of the first and second nanosheets; a first channel doping layer spaced perpendicular to the upper surface of the active pattern, connecting the first and third nanosheets, contacting the first horizontal sidewalls of each of the first and third nanosheets, and doped with a first impurity in silicon (Si); a second channel doping layer spaced perpendicular to the upper surface of the first channel doping layer, connecting the second and fourth nanosheets, contacting the first horizontal sidewalls of each of the second and fourth nanosheets, and doped with a first impurity in silicon (Si); and the upper surface of the active pattern It includes a first gate electrode extending in a second horizontal direction different from the first horizontal direction and surrounding the first and second nanosheets, a second gate electrode extending in a second horizontal direction on the upper surface of the active pattern and spaced apart from the first gate electrode in the first horizontal direction and surrounding the third and fourth nanosheets, and a source / drain region disposed between the first gate electrode and the second gate electrode on the upper surface of the active pattern and surrounding the first and second channel doping layers.

[0007] Some embodiments of a method for manufacturing a semiconductor device according to the technical concept of the present invention for solving the above problem include forming a stacked structure comprising a first semiconductor layer and a second semiconductor layer alternately stacked on an active pattern extending in a first horizontal direction, wherein the first semiconductor layer comprises silicon germanium (SiGe) and the second semiconductor layer comprises silicon (Si), forming first and second dummy gates that are each extended in a second horizontal direction different from the first horizontal direction and are spaced apart from each other in the first horizontal direction on the stacked structure, and doping a first impurity into a part of the stacked structure formed between the first and second dummy gates, wherein a part of the first semiconductor layer doped with the first impurity is defined as a sacrificial doping layer and a part of the second semiconductor layer doped with the first impurity is defined as a channel doping layer, and another part of the second semiconductor layer not doped with the first impurity below the first dummy gate is defined as a first and second nanosheet spaced apart in the vertical direction, and another part of the second semiconductor layer not doped with the first impurity below the second dummy gate is a third and fourth nanosheet spaced apart in the vertical direction Defined as a nanosheet, the method comprises etching a sacrificial doping layer to form a source / drain trench, forming a source / drain region surrounding a channel doping layer inside the source / drain trench, etching a first semiconductor layer and a first dummy gate to form a first gate trench, etching a first semiconductor layer and a second dummy gate to form a second gate trench, and forming a first gate electrode surrounding the first and second nanosheets inside the first gate trench, and forming a second gate electrode surrounding the third and fourth nanosheets inside the second gate trench.

[0008] Other specific details of the present invention are included in the detailed description and drawings. Brief explanation of the drawing

[0009] FIG. 1 is a schematic layout diagram for explaining a semiconductor device according to some embodiments of the present invention. Figure 2 is a cross-sectional view taken along the line AA' of Figure 1. Figure 3 is a cross-sectional view taken along the line BB' of Figure 1. Figure 4 is a cross-sectional view taken along the CC' line of Figure 1. FIGS. 5 to 23 are intermediate step drawings for explaining a method for manufacturing a semiconductor device according to some embodiments of the present invention. FIG. 24 is a cross-sectional view illustrating a semiconductor device according to some other embodiments of the present invention. FIGS. 25 to 27 are intermediate step drawings for explaining a method for manufacturing a semiconductor device according to several other embodiments of the present invention. Specific details for implementing the invention

[0010] Hereinafter, a semiconductor device according to several embodiments of the present invention will be described with reference to FIGS. 1 to 4.

[0011] FIG. 1 is a schematic layout diagram for illustrating a semiconductor device according to some embodiments of the present invention. FIG. 2 is a cross-sectional view taken along line AA' of FIG. 1. FIG. 3 is a cross-sectional view taken along line BB' of FIG. 1. FIG. 4 is a cross-sectional view taken along line CC' of FIG. 1.

[0012] Referring to FIGS. 1 to 4, a semiconductor device according to some embodiments of the present invention comprises a substrate (100), an active pattern (101), a field insulating film (105), first to sixth nanosheets (NW1 to NW6), first to third channel doping layers (111, 112, 113), first and second gate electrodes (G1, G2), first and second gate spacers (121, 122), first and second gate insulating films (131, 132), first and second capping patterns (141, 142), a source / drain region (SD), an etch stop film (150), an interlayer insulating film (160), a source / drain contact (CA), a silicide layer (SL), and a gate contact (CB).

[0013] The substrate (100) may be a silicon substrate or a silicon-on-insulator (SOI). Alternatively, the substrate (100) may include silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but the technical concept of the present invention is not limited thereto. In the following, the first horizontal direction (DR1) and the second horizontal direction (DR2) may each be defined as a direction parallel to the upper surface of the substrate (100). The second horizontal direction (DR2) may be defined as a direction different from the first horizontal direction (DR1). The vertical direction (DR3) may be defined as a direction perpendicular to the first horizontal direction (DR1) and the second horizontal direction (DR2), respectively. That is, the vertical direction (DR3) may be defined as a direction perpendicular to the upper surface of the substrate (100).

[0014] An active pattern (101) may be disposed on the upper surface of a substrate (100). The active pattern (101) may protrude in a vertical direction (DR3) from the upper surface of the substrate (100). For example, the active pattern (101) may be part of the substrate (100) or may include an epitaxial layer grown from the substrate (100). A field insulating film (105) may be disposed on the upper surface of the substrate (100). The field insulating film (105) may surround the sidewalls of the active pattern (101). For example, the upper surface of the field insulating film (105) may be formed on the same plane as the upper surface of the active pattern (101). However, the technical concept of the present invention is not limited thereto. For example, the field insulating film (105) may include an oxide film, a nitride film, an oxynitride film, or a combination thereof.

[0015] The first to third plurality of nanosheets (NW1, NW2, NW3) may be stacked sequentially spaced apart in a vertical direction (DR3) on the upper surface of the active pattern (101). For example, the first nanosheet (NW1) may be spaced apart in a vertical direction (DR3) from the upper surface of the active pattern (101). The second nanosheet (NW2) may be spaced apart in a vertical direction (DR3) from the upper surface of the first nanosheet (NW1). The third nanosheet (NW3) may be spaced apart in a vertical direction (DR3) from the upper surface of the second nanosheet (NW2). The fourth to sixth plurality of nanosheets (NW4, NW5, NW6) may be stacked sequentially spaced apart in a vertical direction (DR3) on the upper surface of the active pattern (101). The fourth to sixth plurality of nanosheets (NW4, NW5, NW6) may be spaced apart from the first to third plurality of nanosheets (NW1, NW2, NW3) in the first horizontal direction (DR1). For example, the fourth nanosheet (NW4) may be spaced apart in the vertical direction (DR3) from the upper surface of the active pattern (101). The fifth nanosheet (NW5) may be spaced apart in the vertical direction (DR3) from the upper surface of the fourth nanosheet (NW4). The sixth nanosheet (NW6) may be spaced apart in the vertical direction (DR3) from the upper surface of the fifth nanosheet (NW5).

[0016] For example, the first nanosheet (NW1) and the fourth nanosheet (NW4) may be placed at the same vertical level. The fourth nanosheet (NW4) may be spaced apart from the first nanosheet (NW1) in the first horizontal direction (DR1). The second nanosheet (NW2) and the fifth nanosheet (NW5) may be placed at the same vertical level. The fifth nanosheet (NW5) may be spaced apart from the second nanosheet (NW2) in the first horizontal direction (DR1). The third nanosheet (NW3) and the sixth nanosheet (NW6) may be placed at the same vertical level. The sixth nanosheet (NW6) may be spaced apart from the third nanosheet (NW3) in the first horizontal direction (DR1). For example, each of the first to sixth plurality of nanosheets (NW1 to NW6) may contain silicon (Si). In FIGS. 2 and 3, three nanosheets are shown stacked sequentially spaced apart in the vertical direction (DR3) on the upper surface of the active pattern (101), but the technical concept of the present invention is not limited thereto. In some other embodiments, three nanosheets may be stacked sequentially spaced apart in the vertical direction (DR3) on the upper surface of the active pattern (101).

[0017] The first to third channel doping layers (111) may be stacked sequentially spaced apart in a vertical direction (DR3) on the upper surface of the active pattern (101). For example, the first channel doping layer (111) may be spaced apart in a vertical direction (DR3) from the upper surface of the active pattern (101). The second channel doping layer (112) may be spaced apart in a vertical direction (DR3) from the upper surface of the first channel doping layer (111). The third channel doping layer (113) may be spaced apart in a vertical direction (DR3) from the upper surface of the second channel doping layer (112). The first to third channel doping layers (111) may be placed between the first to third nanosheets (NW1, NW2, NW3) and the fourth to sixth nanosheets (NW4, NW5, NW6). For example, the first channel doping layer (111) may be placed at the same vertical level as the first nanosheet (NW1) and the fourth nanosheet (NW4), respectively. The second channel doping layer (112) may be placed at the same vertical level as the second nanosheet (NW2) and the fifth nanosheet (NW5), respectively. The third channel doping layer (113) may be placed at the same vertical level as the third nanosheet (NW3) and the sixth nanosheet (NW6), respectively.

[0018] For example, the first channel doping layer (111) may be placed between the first nanosheet (NW1) and the fourth nanosheet (NW4). The first channel doping layer (111) may connect the first nanosheet (NW1) and the fourth nanosheet (NW4). Both sidewalls of the first channel doping layer (111) in the first horizontal direction (DR1) may be in contact with the first nanosheet (NW1) and the fourth nanosheet (NW4). The second channel doping layer (112) may be placed between the second nanosheet (NW2) and the fifth nanosheet (NW5). The second channel doping layer (112) may connect the second nanosheet (NW2) and the fifth nanosheet (NW5). Both sidewalls of the second channel doping layer (112) in the first horizontal direction (DR1) may be in contact with the second nanosheet (NW2) and the fifth nanosheet (NW5). The third channel doping layer (113) may be placed between the third nanosheet (NW3) and the sixth nanosheet (NW6). The third channel doping layer (113) may connect the third nanosheet (NW3) and the sixth nanosheet (NW6). Both sidewalls of the third channel doping layer (113) in the first horizontal direction (DR1) may be in contact with the third nanosheet (NW3) and the sixth nanosheet (NW6).

[0019] For example, the first channel doping layer (111) does not come into contact with the second nanosheet (NW2), the third nanosheet (NW3), the fifth nanosheet (NW5), and the sixth nanosheet (NW6), respectively. The second channel doping layer (112) does not come into contact with the first nanosheet (NW1), the third nanosheet (NW3), the fourth nanosheet (NW4), and the sixth nanosheet (NW6), respectively. The third channel doping layer (113) does not come into contact with the first nanosheet (NW1), the second nanosheet (NW2), the fourth nanosheet (NW4), and the fifth nanosheet (NW5), respectively. For example, each of the first to third channel doping layers (111, 112, 113) may comprise a material in which a first impurity is doped into silicon (Si). For example, the first impurity may comprise arsenic (As). For example, each of the first to sixth nanosheets (NW1 to NW6) and the first to third channel doping layers (111, 112, 113) comprises silicon (Si), but each of the first to third channel doping layers (111, 112, 113) is doped with the first impurity, and each of the first to sixth nanosheets (NW1 to NW6) is not doped with the first impurity. As a result, the first to third channel doping layers (111, 112, 113) can be distinguished from the first to sixth nanosheets (NW1 to NW6).

[0020] For example, the first nanosheet (NW1), the first channel doping layer (111), and the fourth nanosheet (NW2) can function as the first channel layer. The second nanosheet (NW2), the second channel doping layer (112), and the fifth nanosheet (NW5) can function as the second channel layer. The third nanosheet (NW3), the third channel doping layer (113), and the sixth nanosheet (NW6) can function as the third channel layer.

[0021] The first gate electrode (G1) may extend in a second horizontal direction (DR2) on the upper surface of each of the active pattern (101) and the field insulating film (105). The first gate electrode (G1) may surround the first to third nanosheets (NW1, NW2, NW3). The second gate electrode (G2) may extend in a second horizontal direction (DR2) on the upper surface of each of the active pattern (101) and the field insulating film (105). The second gate electrode (G2) may be spaced apart from the first gate electrode (G1) in a first horizontal direction (DR1). The second gate electrode (G2) may surround the fourth to sixth nanosheets (NW4, NW5, NW6).

[0022] For example, the first and second gate electrodes (G1, G2) each comprise titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), It may include at least one of molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), and combinations thereof. Each of the first and second gate electrodes (G1, G2) may include a conductive metal oxide, a conductive metal oxynitride, etc., and may include an oxidized form of the above-described material.

[0023] The first gate spacer (121) may extend in a second horizontal direction (DR2) along both sidewalls of the first gate electrode (G1) on the upper surface of the third nanosheet (NW3) and the upper surface of the field insulating film (105). The second gate spacer (122) may extend in a second horizontal direction (DR2) along both sidewalls of the second gate electrode (G2) on the upper surface of the sixth nanosheet (NW6) and the upper surface of the field insulating film (105). For example, each of the first and second gate spacers (121, 122) may include at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron nitride (SiOBN), silicon carbonate (SiOC), and combinations thereof. However, the technical concept of the present invention is not limited thereto.

[0024] A source / drain region (SD) may be disposed between the first gate electrode (G1) and the second gate electrode (G2) on the upper surface of the active pattern (101). The source / drain region (SD) may surround each of the first to third channel doping layers (111, 112, 113). For example, the source / drain region (SD) may be in contact with the sidewalls in the first horizontal direction (DR1) of each of the first to sixth nanosheets (NW1 to NW6). For example, the source / drain region (SD) may be in contact with the upper and lower surfaces of each of the first to third channel doping layers (111, 112, 113). For example, the source / drain region (SD) may be in contact with both sidewalls in the second horizontal direction (DR2) of each of the first to third channel doping layers (111, 112, 113). For example, the source / drain region (SD) does not come into contact with both side walls in the first horizontal direction (DR1) of each of the first to third channel doping layers (111, 112, 113). For example, the upper surface of the source / drain region (SD) may be formed higher than the upper surface of each of the third nanosheet (NW3), the third channel doping layer (113), and the sixth nanosheet (NW6).

[0025] A first gate insulating film (131) may be disposed between a first gate electrode (G1) and an active pattern (101). A first gate insulating film (131) may be disposed between a first gate electrode (G1) and a field insulating film (105). A first gate insulating film (131) may be disposed between a first gate electrode (G1) and a first gate spacer (121). A first gate insulating film (131) may be disposed between a first gate electrode (G1) and each of a first to third plurality of nanosheets (NW1, NW2, NW3). A first gate insulating film (131) may be disposed between a first gate electrode (G1) and a source / drain region (SD).

[0026] The second gate insulating film (132) may be disposed between the second gate electrode (G2) and the active pattern (101). The second gate insulating film (132) may be disposed between the second gate electrode (G2) and the field insulating film (105). The second gate insulating film (132) may be disposed between the second gate electrode (G2) and the second gate spacer (122). The second gate insulating film (132) may be disposed between the second gate electrode (G2) and each of the fourth to sixth plurality of nanosheets (NW4, NW5, NW6). The second gate insulating film (132) may be disposed between the second gate electrode (G2) and the source / drain region (SD).

[0027] For example, each of the first and second gate insulating films (131, 132) may include at least one of silicon oxide, silicon oxynitride, silicon nitride, or a high dielectric constant material having a dielectric constant greater than that of silicon oxide. High dielectric constant materials may include, for example, one or more of hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

[0028] A semiconductor device according to some other embodiments may include a negative capacitance (NC) FET using a negative capacitor. For example, each of the first and second gate insulating films (131, 132) may include a ferroelectric material film having ferroelectric properties and a paraelectric material film having paraelectric properties.

[0029] Ferroelectric film materials can have negative capacitance, while paraelectric film materials can have positive capacitance. For example, if two or more capacitors are connected in series and each capacitor has a positive capacitance, the total capacitance will be smaller than the capacitance of each individual capacitor. Conversely, if at least one of the capacitances of the two or more capacitors connected in series has a negative value, the total capacitance will have a positive value and may be greater than the absolute value of each individual capacitance.

[0030] When a ferroelectric material film having negative capacitance and a paraelectric material film having positive capacitance are connected in series, the total capacitance value of the series-connected ferroelectric material film and paraelectric material film can increase. By utilizing the increase in the total capacitance value, a transistor containing a ferroelectric material film can have a subthreshold swing (SS) of less than 60 mV / decade at room temperature.

[0031] Ferroelectric material films may have ferroelectric properties. Ferroelectric material films may include, for example, at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanium oxide. Here, as an example, hafnium zirconium oxide may be a material in which zirconium (Zr) is doped into hafnium oxide. As another example, hafnium zirconium oxide may be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

[0032] The ferroelectric material film may further include a doped dopant. For example, the dopant may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin (Sn). Depending on which ferroelectric material the ferroelectric material film contains, the type of dopant included in the ferroelectric material film may vary.

[0033] When the ferroelectric material film contains hafnium oxide, the dopant included in the ferroelectric material film may include, for example, at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and yttrium (Y).

[0034] When the dopant is aluminum (Al), the ferroelectric material film may contain 3 to 8 at% (atomic %) of aluminum. Here, the ratio of the dopant may be the ratio of aluminum to the sum of hafnium and aluminum.

[0035] When the dopant is silicon (Si), the ferroelectric material film may contain 2 to 10 at% silicon. When the dopant is yttrium (Y), the ferroelectric material film may contain 2 to 10 at% yttrium. When the dopant is gadolinium (Gd), the ferroelectric material film may contain 1 to 7 at% gadolinium. When the dopant is zirconium (Zr), the ferroelectric material film may contain 50 to 80 at% zirconium.

[0036] The paraelectric material film may have paraelectric properties. The paraelectric material film may include, for example, at least one of silicon oxide and a metal oxide having a high dielectric constant. The metal oxide included in the paraelectric material film may include, for example, at least one of hafnium oxide, zirconium oxide, and aluminum oxide, but is not limited thereto.

[0037] Ferroelectric and paraelectric film layers may contain the same material. Ferroelectric film layers possess ferroelectric properties, whereas paraelectric film layers may not. For example, if both ferroelectric and paraelectric film layers contain hafnium oxide, the crystal structure of the hafnium oxide contained in the ferroelectric film layer is different from the crystal structure of the hafnium oxide contained in the paraelectric film layer.

[0038] The ferroelectric material film may have a thickness that exhibits ferroelectric properties. The thickness of the ferroelectric material film may be, for example, 0.5 to 10 nm, but is not limited thereto. Since the critical thickness at which ferroelectric properties are exhibited may vary for each ferroelectric material, the thickness of the ferroelectric material film may vary depending on the ferroelectric material.

[0039] For example, each of the first and second gate insulating films (131, 132) may include a single ferroelectric material film. For another example, each of the first and second gate insulating films (131, 132) may include a plurality of ferroelectric material films spaced apart from each other. Each of the first and second gate insulating films (131, 132) may have a stacked film structure in which a plurality of ferroelectric material films and a plurality of paraelectric material films are alternately stacked.

[0040] The etch stop layer (150) may be disposed on the sidewall of the first horizontal direction (DR1) of each of the first and second gate spacers (121, 122). The etch stop layer (150) may be disposed on the upper surface of the source / drain region (SD). The etch stop layer (150) may be disposed on the upper surface of the field insulating film (105). The etch stop layer (150) may be disposed on the sidewall of the second horizontal direction (DR2) of the source / drain region (SD). For example, the etch stop layer (150) may be formed conformally. For example, the etch stop layer (150) may include at least one of aluminum oxide, aluminum nitride, hafnium oxide, zirconium oxide, silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material.

[0041] The first capping pattern (141) may extend in a second horizontal direction (DR2) on each of the first gate spacer (121), the first gate insulating film (131), and the first gate electrode (G1). The second capping pattern (142) may extend in a second horizontal direction (DR2) on each of the second gate spacer (122), the second gate insulating film (132), and the second gate electrode (G2). For example, the lower surface of each of the first and second capping patterns (141, 142) may be in contact with the etch stop film (150). However, the technical concept of the present invention is not limited thereto. In some other embodiments, the sidewalls of each of the first and second capping patterns (141, 142) may be in contact with the etch stop film (150). For example, each of the first and second capping patterns (141, 142) may include at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and combinations thereof. However, the technical concept of the present invention is not limited thereto.

[0042] An interlayer insulating film (160) may be disposed on an etch stop film (150). An interlayer insulating film (160) may be disposed on the sidewalls of each of the first and second capping patterns (141, 142). An interlayer insulating film (160) may cover a source / drain region (SD) on a field insulating film (105). For example, the upper surface of the interlayer insulating film (160) may be formed coplanar with the upper surface of each of the first and second capping patterns (141, 142). For example, the interlayer insulating film (160) may comprise at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material.

[0043] A source / drain contact (CA) may be disposed on the upper surface of a source / drain region (SD). The source / drain contact (CA) may be electrically connected to the source / drain region (SD) by penetrating the interlayer insulating film (160) in the vertical direction (DR3). The source / drain contact (CA) may include a conductive material. A silicide layer (SL) may be disposed along the interface between the source / drain region (SD) and the source / drain contact (CA). For example, the silicide layer (SL) may include a metal silicide material. A gate contact (CB) may be connected to a first gate electrode (G1) by penetrating the first capping pattern (141) in the vertical direction (DR3). The gate contact (CB) may include a conductive material.

[0044] Hereinafter, a method for manufacturing a semiconductor device according to some embodiments of the present invention will be described with reference to FIGS. 2 to 23.

[0045] FIGS. 5 to 23 are intermediate step drawings for explaining a method for manufacturing a semiconductor device according to some embodiments of the present invention.

[0046] Referring to FIGS. 5 and 6, a stacked structure (10) may be formed on the upper surface of a substrate (100). For example, a stacked structure (10) may be formed on the upper surface of an active pattern (101). Specifically, the stacked structure (10) may include a first semiconductor layer (11) and a second semiconductor layer (12) alternately stacked on the upper surface of the substrate (100). For example, the first semiconductor layer (11) may be formed at the bottom of the stacked structure (10), and the second semiconductor layer (12) may be formed at the top of the stacked structure (10). However, the technical concept of the present invention is not limited thereto. For example, the first semiconductor layer (11) may include silicon germanium (SiGe), and the second semiconductor layer (12) may include silicon (Si).

[0047] Subsequently, a portion of the stacked structure (10) may be etched. While the stacked structure (10) is being etched, a portion of the substrate (100) may also be etched. Through this etching process, an active pattern (101) may be defined on the lower portion of the stacked structure (10) on the upper surface of the substrate (100). That is, it may be defined as forming the stacked structure (10) on the upper surface of the active pattern (101). The active pattern (101) may protrude in a vertical direction (DR3) from the upper surface of the substrate (100). The active pattern (101) may extend in a first horizontal direction (DR1). For example, the active pattern (101) may include silicon (Si).

[0048] Next, a field insulating film (105) may be formed on the upper surface of the substrate (100). The field insulating film (105) may surround the sidewall of the active pattern (101). For example, the upper surface of the field insulating film (105) may be formed on the same plane as the upper surface of the active pattern (101). Next, a pad oxide film (20) may be formed to cover the upper surface of the field insulating film (105), the sidewall of the stacked structure (10), and the upper surface. For example, the pad oxide film (20) may be formed conformally. For example, the pad oxide film (20) may include silicon oxide (SiO2).

[0049] Referring to FIGS. 7 and 8, first and second dummy gates (DG1, DG2) and first and second dummy capping patterns (DC1, DC2) extending in a second horizontal direction (DR2) can be formed on a pad oxide film (20) on a stacked structure (10) and a field insulating film (105). For example, the second dummy gate (DG2) may be spaced apart from the first dummy gate (DG1) in the first horizontal direction (DR1). The first dummy capping pattern (DC1) may be placed on the first dummy gate (DG1). The second dummy capping pattern (DC2) may be placed on the second dummy gate (DG2). While the first and second dummy gates (DG1, DG2) and the first and second dummy capping patterns (DC1, DC2) are being formed, the remaining pad oxide film (20) can be removed on the substrate (100), excluding the portion that overlaps with each of the first and second dummy gates (DG1, DG2) in the vertical direction (DR3).

[0050] Subsequently, a spacer material layer (SM) may be formed on each of the sidewalls of the first and second dummy gates (DG1, DG2), each of the sidewalls and top surfaces of the first and second dummy capping patterns (DC1, DC2), each of the sidewalls and top surfaces of the exposed stacked structure (10), and each of the top surface of the field insulating film (105). For example, the spacer material layer (SM) may be formed conformally. For example, the spacer material layer (SM) may include at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron nitride (SiOBN), silicon carbonitride (SiOC), and combinations thereof.

[0051] Referring to FIGS. 9 through 11, an etch back etching process may be performed to etch a portion of the spacer material layer (SM in FIGS. 7 and 8). After performing the etch back etching process, the upper surface of each of the first and second dummy capping patterns (DC1, DC2) may be exposed. Additionally, after performing the etch back etching process, the sidewall and upper surface of the stacked structure (10) formed between the first gate spacer (121) and the second gate spacer (122) may be exposed. That is, by etching a portion of the spacer material layer (SM in FIGS. 7 and 8), a portion of the stacked structure (10) formed between the first dummy gate (DG1) and the second dummy gate (DG2) may be exposed. For example, the spacer material layer (SM in FIG. 7 and 8) remaining on the sidewalls of the first and second dummy capping patterns (DC1, DC2) and the first and second dummy gates (DG1, DG2), respectively, can be defined as the first and second gate spacers (121, 122).

[0052] Referring to FIGS. 12 and 13, a first impurity may be doped into a portion of a stacked structure (10) formed between a first dummy gate (DG1) and a second dummy gate (DG2). For example, the first impurity may be arsenic (As). For example, the first impurity may be doped into each of the first semiconductor layer (11) and the second semiconductor layer (12 in FIGS. 9 to 11) formed between the first dummy gate (DG1) and the second dummy gate (DG2). For example, a portion of the first semiconductor layer (11) doped with the first impurity may be defined as first to third sacrificial doping layers (31, 32, 33). The first to third sacrificial doping layers (31, 32, 33) may be spaced apart sequentially in the vertical direction (DR3). For example, a portion of the second semiconductor layer (12 in FIGS. 9 to 11) doped with the first impurity may be defined as first to third channel doping layers (111, 112, 113). The first to third channel doping layers (111, 112, 113) may be spaced apart sequentially in the vertical direction (DR3).

[0053] For example, another part of the second semiconductor layer (12 in FIGS. 9 to 11) that is not doped with the first impurity at the bottom of the first dummy gate (DG1) may be defined as first to third nanosheets (NW1, NW2, NW3) sequentially spaced apart in the vertical direction (DR3). Additionally, another part of the second semiconductor layer (12 in FIGS. 9 to 11) that is not doped with the first impurity at the bottom of the second dummy gate (DG2) may be defined as fourth to sixth nanosheets (NW4, NW5, NW6) sequentially spaced apart in the vertical direction (DR3). For example, each of the first to sixth nanosheets (NW1 to NW6) may comprise silicon (Si) that is not doped with the first impurity, and each of the first to third channel doping layers (111, 112, 113) may comprise silicon (Si) doped with the first impurity. For example, the first semiconductor layer (11) comprises silicon germanium (SiGe) that is not doped with the first impurity, and each of the first to third sacrificial doping layers (31, 32, 33) may comprise silicon germanium (SiGe) with the first impurity.

[0054] Referring to FIGS. 14 and 15, the first to third sacrificial doping layers (31, 32, and 33 in FIGS. 12 and 13) can be etched. For example, the first to third sacrificial doping layers (31, 32, and 33 in FIGS. 12 and 13) can be etched through a wet etching process. For example, the first to third sacrificial doping layers (31, 32, and 33 in FIGS. 12 and 13) doped with the first impurity can be selectively etched by an etching selectivity ratio. That is, in order to selectively etch the first to third sacrificial doping layers (31, 32, and 33 in FIGS. 12 and 13), the first impurity is doped into the second semiconductor layer (12 in FIGS. 9 to 11). The portions where the first to third sacrificial doping layers (31, 32, and 33 in FIG. 12 and FIG. 13) are etched can be defined as source / drain trenches (ST).

[0055] In FIGS. 14 and 15, it is shown that after the first to third sacrificial doping layers (31, 32, 33 in FIGS. 12 and 13) are etched, each of the first to third channel doping layers (111, 112, 113) is not etched at all, but the technical concept of the present invention is not limited thereto. In some other embodiments, after the first to third sacrificial doping layers (31, 32, 33 in FIGS. 12 and 13) are etched, a portion of the exposed surface of each of the first to third channel doping layers (111, 112, 113) may be etched.

[0056] Referring to FIGS. 16 and 17, a source / drain region (SD) may be formed inside a source / drain trench (ST in FIG. 14). For example, the source / drain region (SD) may surround each of the first to third channel doping layers (111, 112, 113). For example, the source / drain region (SD) may be in contact with both side walls in the second horizontal direction (DR2) of each of the first to third channel doping layers (111, 112, 113).

[0057] Referring to FIGS. 18 and 19, an etch stop layer (150) may be formed on the upper surface of the exposed field insulating layer (105), the sidewalls of each of the exposed first and second gate spacers (121, 122), the upper surfaces of each of the exposed first and second dummy capping patterns (DC1, DC2 in FIG. 16), and the surface of the exposed source / drain region (SD). Subsequently, an interlayer insulating layer (160) may be formed on the etch stop layer (150). Subsequently, a planarization process may be performed so that the upper surfaces of each of the first and second dummy gates (DG1, DG2) may be exposed.

[0058] Referring to FIGS. 20 and 21, the first and second dummy gates (DG1 and DG2 of FIG. 18), the pad oxide film (20 of FIG. 18), and the first semiconductor layer (11 of FIG. 18) can each be etched. The portion where the first dummy gate (DG1 of FIG. 18), the pad oxide film (20 of FIG. 18), and the first semiconductor layer (11 of FIG. 18) are etched can be defined as the first gate trench (GT1). Additionally, the portion where the second dummy gate (DG2 of FIG. 18), the pad oxide film (20 of FIG. 18), and the first semiconductor layer (11 of FIG. 18) are etched can be defined as the second gate trench (GT2).

[0059] Referring to FIGS. 22 and 23, a first gate insulating film (131), a first gate electrode (G1), and a first capping pattern (141) may each be sequentially formed inside a first gate trench (GT1 in FIG. 20). Additionally, a second gate insulating film (132), a second gate electrode (G2), and a second capping pattern (142) may each be sequentially formed inside a second gate trench (GT2 in FIG. 20). For example, the first gate electrode (G1) may surround first to third nanosheets (NW1, NW2, NW3). The second gate electrode (G2) may surround fourth to sixth nanosheets (NW4, NW5, NW6).

[0060] Referring to FIGS. 2 to 4, a gate contact (CB1) connected to a first gate electrode (G1) can be formed by penetrating the first capping pattern (141) in the vertical direction (DR3). Additionally, a source / drain contact (CA) electrically connected to a source / drain region (SD) can be formed by penetrating the interlayer insulating film (160) and the etch stop film (150) in the vertical direction (DR3). Furthermore, a silicide layer (SL) can be formed on the interface between the source / drain region (SD) and the source / drain contact (CA). Through this manufacturing process, a semiconductor device illustrated in FIGS. 2 to 4 can be manufactured.

[0061] For example, when a dry etching process is performed to form a source / drain region (SD), a portion of the upper part of the active pattern (101) may be etched, and at least a portion of the source / drain region (SD) may extend into the interior of the active pattern (101). As a result, a short circuit may occur between adjacent source / drain regions (SD), which may cause problems with electrical characteristics. Additionally, for example, when a dry etching process is performed to form a source / drain region (SD), the silicon (Si) layer in the portion where the source / drain region (SD) is formed may be etched. In this case, as the source / drain region (SD) is formed by epitaxial growth from an exposed nanosheet, a problem may arise where defects or air gaps are formed inside the source / drain region (SD), which may cause problems with electrical characteristics.

[0062] A method for manufacturing a semiconductor device according to some embodiments of the present invention may form first to third channel doping layers (111, 112, 113) and first to third sacrificial doping layers (31, 32, 33) by doping a first impurity in the portion where the source / drain region (SD) is formed before the source / drain region (SD) is formed. The first to third sacrificial doping layers (31, 32, 33) doped with the first impurity may be selectively etched by an etching selectivity ratio. The first to third sacrificial doping layers (31, 32, 33) may be etched by a wet etching process. The source / drain region (SD) may be formed in the portion where the first to third sacrificial doping layers (31, 32, 33) are etched. As a result, the source / drain region (SD) does not extend into the interior of the active pattern (101), thereby preventing a short circuit between adjacent source / drain regions (SD), and thus improving the electrical characteristics of the semiconductor device. In addition, a method for manufacturing a semiconductor device according to some embodiments of the present invention can improve the electrical characteristics of the semiconductor device by preventing defects or air gaps from being formed inside the source / drain region (SD) by forming the source / drain region (SD) to surround the first to third channel doping layers (111, 112, 113).

[0063] Hereinafter, a semiconductor device according to several other embodiments of the present invention will be described with reference to FIG. 24. The description will focus on the differences from the semiconductor device illustrated in FIG. 1 to 4.

[0064] FIG. 24 is a cross-sectional view illustrating a semiconductor device according to some other embodiments of the present invention.

[0065] Referring to FIG. 24, a semiconductor device according to some other embodiments of the present invention may have a first internal spacer (271) disposed between a first gate electrode (G1) and a source / drain region (SD), and a second internal spacer (272) disposed between a second gate electrode (G2) and a source / drain region (SD).

[0066] For example, the first internal spacer (271) may be positioned between the upper surface of the active pattern (101) and the lower surface of the first nanosheet (NW1), between the upper surface of the first nanosheet (NW1) and the lower surface of the second nanosheet (NW2), and between the upper surface of the second nanosheet (NW2) and the lower surface of the third nanosheet (NW3). The first internal spacer (271) may be in contact with the first gate insulating film (131) and the source / drain region (SD), respectively. For example, the second internal spacer (272) may be positioned between the upper surface of the active pattern (101) and the lower surface of the fourth nanosheet (NW4), between the upper surface of the fourth nanosheet (NW4) and the lower surface of the fifth nanosheet (NW5), and between the upper surface of the fifth nanosheet (NW5) and the lower surface of the sixth nanosheet (NW6). The second internal spacer (272) can be in contact with the second gate insulating film (132) and the source / drain region (SD), respectively.

[0067] For example, each of the first and second internal spacers (271, 272) may include at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron nitride (SiOBN), silicon carbonitride (SiOC), and combinations thereof. However, the technical concept of the present invention is not limited thereto.

[0068] Hereinafter, a method for manufacturing a semiconductor device according to several other embodiments of the present invention will be described with reference to FIGS. 24 to 27. The description will focus on the differences from the method for manufacturing a semiconductor device illustrated in FIGS. 5 to 23.

[0069] FIGS. 25 to 27 are intermediate step drawings for explaining a method for manufacturing a semiconductor device according to several other embodiments of the present invention.

[0070] Referring to FIG. 25, after the manufacturing process illustrated in FIG. 5 to FIG. 15 is performed, a portion of the first horizontal direction (DR1) sidewall of the first semiconductor layer (11) exposed through the source / drain trench (ST) may be etched. As a result, the remaining first horizontal direction (DR1) sidewall of the first semiconductor layer (11) may be formed concavely toward the center of each of the first and second dummy gates (DG1, DG2).

[0071] Referring to FIG. 26, first and second internal spacers (271, 272) may each be formed on the sidewall in the first horizontal direction (DR1) of the remaining first semiconductor layer (11). For example, a first internal spacer (271) may be formed on the sidewall in the first horizontal direction (DR1) of the first semiconductor layer (11) remaining below the first dummy gate (DG1), and a second internal spacer (272) may be formed on the sidewall in the first horizontal direction (DR1) of the first semiconductor layer (11) remaining below the second dummy gate (DG2).

[0072] Referring to FIG. 27, a source / drain region (SD) may be formed inside the source / drain trench (ST in FIG. 26). For example, the source / drain region (SD) may surround each of the first to third channel doping layers (111, 112, 113). For example, the source / drain region (SD) may be in contact with each of the first and second internal spacers (271, 272).

[0073] Referring to FIG. 24, after additionally performing the manufacturing process illustrated in FIG. 18 to FIG. 23, a gate contact (CB1), a source / drain contact (CA), and a silicide layer (SL) can each be formed. Through this manufacturing process, a semiconductor device illustrated in FIG. 24 can be manufactured.

[0074] Although embodiments according to the technical concept of the present invention have been described above with reference to the attached drawings, the present invention is not limited to the above embodiments and can be manufactured in various different forms, and those skilled in the art will understand that the present invention can be implemented in other specific forms without changing the technical concept or essential features of the present invention. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0075] 100: Substrate 101: Active Pattern 105: Field insulation film NW1 to NW6: 1st to 6th nanosheets 111, 112, 113: 1st to 3rd channel doping layers G1, G2: First and second gate electrodes 121, 122: First and second gate insulating films 131, 132: First and second gate insulating films 141, 142: First and second capping patterns SD: Source / Drain Area 150: Etching stop layer 160: Interlayer insulation film CA: Source / Drain Contact SL: Silicide layer CB: Gate Contact 271, 272: 1st and 2nd inner spacers

Claims

Claim 1 Substrate; an active pattern extending in a first horizontal direction on the upper surface of the substrate; first and second nanosheets containing silicon (Si) stacked sequentially spaced apart in a vertical direction from the upper surface of the active pattern; third and fourth nanosheets containing silicon (Si) stacked sequentially spaced apart in a vertical direction from the upper surface of the active pattern, spaced apart in a first horizontal direction from each of the first and second nanosheets; a first channel doping layer spaced apart in a vertical direction from the upper surface of the active pattern, connecting the first and third nanosheets, in contact with the sidewalls in the first horizontal direction of each of the first and third nanosheets, and doped with a first impurity in silicon (Si); a second channel doping layer spaced apart in a vertical direction from the upper surface of the first channel doping layer, connecting the second and fourth nanosheets, in contact with the sidewalls in the first horizontal direction of each of the second and fourth nanosheets, and doped with the first impurity in silicon (Si); the upper surface of the active pattern A semiconductor device comprising: a first gate electrode extending in a second horizontal direction different from the first horizontal direction and surrounding the first and second nanosheets; a second gate electrode extending in the second horizontal direction on the upper surface of the active pattern, spaced apart from the first gate electrode in the first horizontal direction, and surrounding the third and fourth nanosheets; and a source / drain region disposed between the first gate electrode and the second gate electrode on the upper surface of the active pattern and surrounding the first and second channel doping layers. Claim 2 A semiconductor device according to claim 1, wherein the source / drain region is in contact with both sidewalls in the second horizontal direction of each of the first and second channel doping layers. Claim 3 In claim 1, each of the first to fourth nanosheets is a semiconductor device that is not doped with the first impurity. Claim 4 A semiconductor device according to claim 1, wherein the first channel doping layer does not come into contact with each of the second and fourth nanosheets, and the second channel doping layer does not come into contact with each of the first and third nanosheets. Claim 5 A semiconductor device according to claim 1, further comprising: a first internal spacer disposed between the first nanosheet and the second nanosheet, and between the first gate electrode and the source / drain region; and a first internal spacer disposed between the third nanosheet and the fourth nanosheet, and between the second gate electrode and the source / drain region. Claim 6 A stacked structure comprising a first semiconductor layer and a second semiconductor layer alternately stacked on an active pattern extending in a first horizontal direction, wherein the first semiconductor layer comprises silicon germanium (SiGe) and the second semiconductor layer comprises silicon (Si); first and second dummy gates are formed on the stacked structure, each extending in a second horizontal direction different from the first horizontal direction and spaced apart from each other in the first horizontal direction; a first impurity is doped into a portion of the stacked structure formed between the first and second dummy gates, wherein a portion of the first semiconductor layer doped with the first impurity is defined as a sacrificial doping layer and a portion of the second semiconductor layer doped with the first impurity is defined as a channel doping layer, and another portion of the second semiconductor layer not doped with the first impurity below the first dummy gate is defined as a first and second nanosheet spaced apart in the vertical direction, and another portion of the second semiconductor layer not doped with the first impurity below the second dummy gate is defined as a third and fourth nanosheet spaced apart in the vertical direction. A method for manufacturing a semiconductor device comprising: defining; etching the sacrificial doping layer to form a source / drain trench; forming a source / drain region surrounding the channel doping layer inside the source / drain trench; etching the first semiconductor layer and the first dummy gate to form a first gate trench, and etching the first semiconductor layer and the second dummy gate to form a second gate trench; and forming a first gate electrode surrounding the first and second nanosheets inside the first gate trench, and forming a second gate electrode surrounding the third and fourth nanosheets inside the second gate trench. Claim 7 A method for manufacturing a semiconductor device in which, in claim 6, the first impurity is arsenic (As). Claim 8 A method for manufacturing a semiconductor device according to claim 6, further comprising: forming a spacer material layer on the upper surface and sidewall of the first and second dummy gates and the upper surface and sidewall of the stacked structure, respectively, before doping a portion of the stacked structure with the first impurity; and etching a portion of the spacer material layer to expose a portion of the stacked structure formed between the first and second dummy gates. Claim 9 A method for manufacturing a semiconductor device according to claim 6, wherein the channel doping layer comprises: a first channel doping layer spaced vertically apart from the upper surface of the active pattern, connecting between the first and third nanosheets, and in contact with the first horizontal sidewalls of each of the first and third nanosheets; and a second channel doping layer spaced vertically apart from the upper surface of the first channel doping layer, connecting between the second and fourth nanosheets, and in contact with the first horizontal sidewalls of each of the second and fourth nanosheets. Claim 10 A method for manufacturing a semiconductor device according to claim 6, further comprising etching a portion of the first horizontal sidewall of the first semiconductor layer exposed through the source / drain trench before forming the source / drain region; and forming an internal spacer on the remaining first horizontal sidewall of the first semiconductor layer.

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