Display device

Abstract

A display device according to one embodiment comprises: a substrate including a display area including a plurality of pixels and a non-display area surrounding the display area; a first high-voltage line surrounding the display area in the non-display area on the substrate; and a second high-voltage line having one end and the other end connected to the first high-voltage line and connected to a first pixel row including the pixels arranged along a first direction, wherein one end and the other end of the second high-voltage line are each connected to the first high-voltage line in the non-display area.

Description

Technology Field

[0001] This specification relates to a display device. Background Technology

[0002] As the information society develops, there is an increasing demand for display devices that display images, and various types of display devices, such as Liquid Crystal Displays and Organic Light Emitting Diode Displays, are being utilized.

[0003] The display device includes a plurality of pixels and is equipped with a plurality of switching elements to drive and control the pixels. The problem to be solved

[0004] The embodiments of the present specification have the technical objective of providing a display device capable of improving the aperture ratio.

[0005] The embodiments of the present specification have the technical objective of providing a display device that can improve the ease of wiring design.

[0006] The embodiments of the present specification have the technical objective of providing a low-power display device.

[0007] The problems of this specification are not limited to those mentioned above, and other technical problems may be inferred from the following embodiments. means of solving the problem

[0008] A display device according to one embodiment for solving the above problem comprises: a substrate including a display area comprising a plurality of pixels and a non-display area surrounding the display area; a first high-voltage line surrounding the display area in the non-display area on the substrate; and a second high-voltage line having one end and the other end connected to the first high-voltage line and connected to a first pixel row comprising the pixels arranged along a first direction, wherein one end and the other end of the second high-voltage line are each connected to the first high-voltage line in the non-display area.

[0009] A display device according to another embodiment for solving the above problem comprises: a substrate including a first pixel row comprising a plurality of pixels arranged along a first direction, and a non-display area surrounding the display area; a first conductive layer; a buffer layer on the first conductive layer; a semiconductor layer on the buffer layer; a first insulating layer on the semiconductor layer; a second conductive layer on the first insulating layer; a second insulating layer on the second conductive layer; and a third conductive layer on the second insulating layer, and further comprises a high-voltage line connected to the first pixel row and extending along the first direction, wherein the high-voltage line is disposed on the first conductive layer, the second conductive layer, or the third conductive layer, and the high-voltage line extends to the non-display area.

[0010] Specific details of other embodiments are included in the detailed description and drawings. Effects of the invention

[0011] A display device according to the embodiments of the present specification can improve the aperture ratio by changing the arrangement of high-voltage lines so that a plurality of pixels share high-voltage lines.

[0012] The display device according to the embodiments of the present specification may further arrange a conductive layer to improve the ease of wiring design.

[0013] The display device according to the embodiments of the present specification can achieve low power consumption by reducing power consumption through an improved aperture ratio of the display device.

[0014] However, the effects obtainable in this specification are not limited to those mentioned above, and other unmentioned effects will be clearly understood by those skilled in the art to which this specification belongs from the description below. Brief explanation of the drawing

[0015] FIG. 1 is a schematic diagram showing a display device according to one embodiment. FIG. 2 is a plan view showing the back of a display device according to one embodiment. FIG. 3 is an example diagram of a circuit constituting a pixel in a display device according to one embodiment. FIG. 4 is a plan view showing a display panel according to one embodiment. FIG. 5 is a plan view showing a display panel according to one embodiment. Figure 6 is a cross-sectional view taken along the line AA' of Figure 5. Figure 7 is a cross-sectional view taken along the BB' line of Figure 5. FIG. 8 is a cross-sectional view taken along the BB' line of a display panel according to another embodiment. FIG. 9 is a plan view showing a display panel according to another embodiment. Figure 10 is a cross-sectional view taken along the CC' line of Figure 9. FIG. 11 is a cross-sectional view taken along the CC' line of a display panel according to another embodiment. Specific details for implementing the invention

[0016] Hereinafter, embodiments will be described with reference to the drawings.

[0017] Identical reference numerals denote identical components. Additionally, in the drawings, the thickness, proportion, and dimensions of components may be exaggerated to effectively illustrate the technical content. The scale of the components depicted in the drawings differs from the actual scale for the convenience of explanation and is therefore not limited to the scale depicted in the drawings.

[0018] In this specification, where it is stated that any component (or region, layer, part, etc.) is "on," "connected," or "joined" to another component, it means that it may be directly connected / joined to the other component or that a third component may be placed between them.

[0019] "And / or" includes all one or more combinations that the associated configurations can define.

[0020] Terms such as "first," "second," etc., may be used to describe various components, but said components are not limited by said terms. These terms are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present embodiments, the first component may be named the second component, and similarly, the second component may be named the first component. A singular expression includes a plural expression unless the context clearly indicates otherwise.

[0021] Terms such as "below," "lower," "above," and "upper" are used to describe the relationships between components depicted in the drawings. These terms are relative concepts and are described based on the directions indicated in the drawings. For example, unless "immediately" or "directly" is used, one or more other parts may be located between two parts. Spatially relative terms such as "below" or "beneath," "lower," "above," and "upper" may be used to easily describe the correlation between one element or component and another element or component as depicted in the drawings. Spatially relative terms should be understood as terms that include different directions of the element during use or operation in addition to the directions depicted in the drawings. For example, if an element depicted in the drawings is flipped, an element described as "below" or "beneath" another element may be placed "above" of that other element. Therefore, the exemplary term "below" can include both the downward and upward directions.

[0022] Terms such as "include" or "have" are intended to indicate the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0023] The features of each of the various embodiments of this specification may be combined or combined with one another, either partially or wholly, and may technically enable various interlocking and operation. Each embodiment may be implemented independently of one another or may be implemented together in an associated relationship.

[0024] The display device of this specification is described below through the attached drawings and embodiments.

[0025] FIG. 1 is a schematic diagram showing a display device according to one embodiment.

[0026] Referring to FIG. 1, a display device (10) according to one embodiment may include a display panel (100) having a plurality of gate lines (GL) and data lines (DL) connected and a plurality of pixels (PX) arranged therein, a gate driving circuit (200) that provides a signal to a plurality of gate lines (GL), a first circuit board (300) that supplies a data voltage through a plurality of data lines (DL), and a timing controller (400) that controls the gate driving circuit (200) and the first circuit board (300).

[0027] In the embodiments, the first direction (DR1) and the second direction (DR2) are different directions and intersect each other, for example, representing directions that intersect perpendicularly in a plan view. The third direction (DR3) is a direction that intersects the plane on which the first direction (DR1) and the second direction (DR2) are placed, for example, representing a direction that intersects perpendicularly to both the first direction (DR1) and the second direction (DR2). In FIG. 1, the first direction (DR1) is the same as the extension direction of the long sides of the display panel (100), the second direction (DR2) is the same as the extension direction of the short sides of the display panel (100), and the third direction (DR3) may be the same as the stacking direction of the data line (see DL in FIG. 6), the scan line (see SL in FIG. 7), and the second high voltage line (see DVL_2 in FIG. 7). However, the directions mentioned in the embodiments should be understood as referring to relative directions, and the embodiments are not limited to the mentioned directions.

[0028] The display panel (100) displays an image based on a scan signal transmitted from a gate driving circuit (200) through a plurality of gate lines (GL) and a data voltage transmitted from a first circuit board (300) through a plurality of data lines (DL).

[0029] In the case of a liquid crystal display, the display panel (100) includes a liquid crystal layer formed between two substrates and may operate in any known mode, such as a TN (Twisted Nematic) mode, a VA (Vertical Alignment) mode, an IPS (In Plane Switching) mode, or an FFS (Fringe Field Switching) mode. On the other hand, in the case of an organic light-emitting display, the display panel (100) may be implemented in a top emission method, a bottom emission method, or a dual emission method.

[0030] The display panel (100) may include a plurality of pixels (PX), each pixel (PX) may be composed of pixels (PX) of different colors, for example, a white subpixel, a red subpixel, a green subpixel, and a blue subpixel, and each pixel (PX) may be defined by a plurality of data lines (DL) and a plurality of gate lines (GL).

[0031] A single pixel (PX) may include a thin film transistor (TFT) placed in an area formed by a data line (DL) and a gate line (GL), a light-emitting element such as a light-emitting diode that emits light according to a data voltage, and a storage capacitor electrically connected to the light-emitting element to maintain the voltage.

[0032] For example, if a display device (10) having a resolution of 2,600 X 3,840 is composed of four pixels (PX) of white (W), red (R), green (G), and blue (B), a total of 3,840 X 4 = 15,360 data lines (DL) can be provided by 2,600 gate lines (GL) and 3,840 data lines (DL) connected to each of the four subpixels (WRGB), and pixels (PX) will be placed in the areas formed by these gate lines (GL) and data lines (DL).

[0033] The gate driving circuit (200) is controlled by a timing controller (400) and controls the driving timing for a plurality of pixels (PX) by sequentially outputting scan signals to a plurality of gate lines (GL) arranged on a display panel (100).

[0034] In a display device (10) having a resolution of 2,600 x 3,840, a case in which a scan signal is output sequentially from the first gate line to the 2,600th gate line for 2,600 gate lines (GL) can be called 2,600-phase driving. Alternatively, a case in which a scan signal is output sequentially in units of 4 gate lines (GL), such as sequentially outputting a scan signal from the first gate line to the 4th gate line and then sequentially outputting a scan signal from the 5th gate line to the 8th gate line, is called 4-phase driving. That is, a case in which a scan signal is output sequentially for every N gate lines (GL) can be called N-phase driving.

[0035] At this time, the gate driving circuit (200) may include one or more gate driving integrated circuits (GDICs), and depending on the driving method, it may be located on only one side of the display panel (100) or on both sides. Alternatively, the gate driving circuit (200) may be implemented in the form of a GIP (Gate In Panel) directly formed in the bezel area of ​​the display panel (100).

[0036] The first circuit board (300) receives digital image data (DATA) from the timing controller (400) and converts the received digital image data (DATA) into an analog data voltage. Then, by outputting the data voltage to each data line (DL) in accordance with the timing at which a scan signal is applied through the gate line (GL), each pixel (PX) connected to the data line (DL) displays a light emission signal of brightness corresponding to the data voltage.

[0037] Likewise, the first circuit board (300) may include one or more source driving integrated circuits (SDICs), and the source driving integrated circuits (SDICs) may be connected to a bonding pad of the display panel (100) or placed directly on the display panel (100) using a tape-automated bonding (TAB) method or a chip-on-glass (COG) method.

[0038] In some cases, each source driving integrated circuit (SDIC) may be integrated and placed on the display panel (100). Additionally, each source driving integrated circuit (SDIC) may be implemented using a COF (Chip On Film) method, in which case each source driving integrated circuit (SDIC) may be mounted on a circuit film and electrically connected to a data line (DL) of the display panel (100) through the circuit film.

[0039] The timing controller (400) supplies various control signals to the gate driving circuit (200) and the first circuit board (300) and controls the operation of the gate driving circuit (200) and the first circuit board (300). That is, the timing controller (400) controls the gate driving circuit (200) to output a scan signal according to the timing implemented in each frame, and on the other hand, transmits digital image data (DATA) received from the outside to the first circuit board (300).

[0040] At this time, the timing controller (400) receives various timing signals from an external source (e.g., a host system), including a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a data enable signal (DE), and a main clock (MCLK), along with digital image data (DATA). Accordingly, the timing controller (400) generates a control signal using the various timing signals received from the external source and transmits it to the gate driving circuit (200) and the first circuit board (300).

[0041] For example, the timing controller (400) outputs various gate control signals, including a Gate Start Pulse (GSP), a Gate Clock (GCLK), and a Gate Output Enable signal (GOE), to control the gate driving circuit (200). Here, the Gate Start Pulse (GSP) controls the timing at which one or more Gate Driving Integrated Circuits (GDICs) constituting the gate driving circuit (200) begin operation. Additionally, the Gate Clock (GCLK) is a clock signal commonly input to one or more Gate Driving Integrated Circuits (GDICs) and controls the shift timing of the scan signal. Additionally, the Gate Output Enable signal (GOE) specifies the timing information of one or more Gate Driving Integrated Circuits (GDICs).

[0042] Additionally, the timing controller (400) outputs various data control signals, including a Source Start Pulse (SSP), a Source Sampling Clock (SCLK), and a Source Output Enable Signal (SOE), to control the first circuit board (300). Here, the Source Start Pulse (SSP) controls the timing at which one or more source driving integrated circuits (SDICs) constituting the first circuit board (300) begin data sampling. The Source Sampling Clock (SCLK) is a clock signal that controls the timing of data sampling by the source driving integrated circuits (SDICs). The Source Output Enable Signal (SOE) controls the output timing of the first circuit board (300).

[0043] Such a display device (10) may further include a power management integrated circuit that supplies various voltages or currents to a display panel (100), a gate driving circuit (200), a first circuit board (300), etc., or controls various voltages or currents to be supplied.

[0044] Meanwhile, a light-emitting element may be placed in each pixel (PX). For example, an organic light-emitting display device includes a light-emitting element, such as a light-emitting diode, in each pixel (PX), and can display an image by controlling the current flowing through the light-emitting element according to the data voltage.

[0045] FIG. 2 is a plan view showing the back of a display device according to one embodiment.

[0046] Referring to FIG. 2, a display device (10) according to one embodiment is shown in which a source driving integrated circuit (SDIC) included in a first circuit board (300) is implemented in a COF (Chip On Film) manner among various methods (TAB, COG, COF, etc.), and a gate driving circuit (200) is implemented in a GIP (Gate In Panel) form among various methods (TAB, COG, COF, GIP, etc.).

[0047] When the gate driving circuit (see 200 in FIG. 1) is implemented in the form of a GIP, a plurality of gate driving integrated circuits (GDICs) included in the gate driving circuit (200) can be directly formed in the bezel area of ​​the display panel (100). At this time, the gate driving integrated circuits (GDICs) can receive various signals (clock signal, gate high signal, gate low signal, etc.) required for generating a scan signal (SCAN) through a gate driving related signal line placed in the bezel area.

[0048] Likewise, one or more source driving integrated circuits (SDICs) included in the first circuit board (300) may each be mounted on a source film (SF), and one side of the source film (SF) may be electrically connected to a display panel (100). Additionally, lines for electrically connecting the source driving integrated circuit (SDIC) and the display panel (100) may be arranged on the upper side of the source film (SF).

[0049] For circuit connections between a plurality of source driving integrated circuits (SDICs) and other devices, such a display device (10) may include at least one source printed circuit board (SPCB) (or a second circuit board) and a control printed circuit board (CPCB) (or a third circuit board) for mounting control components and various electrical devices.

[0050] At this time, the other side of a source film (SF) on which a source driving integrated circuit (SDIC) is mounted can be connected to at least one source printed circuit board (SPCB). That is, one side of the source film (SF) on which the source driving integrated circuit (SDIC) is mounted can be electrically connected to a display panel (100), and the other side can be electrically connected to a source printed circuit board (SPCB). For example, a plurality of source films (SF) may be connected to a single source printed circuit board (SPCB), but are not limited thereto.

[0051] A timing controller (400) and a power management IC (PMIC, 500) may be mounted on a control printed circuit board (CPCB). The timing controller (400) can control the operation of the first circuit board (300) and the gate driving circuit (200). The power management circuit (500) may supply a driving voltage or current to the display panel (100), the first circuit board (300), and the gate driving circuit (200), and may control the supplied voltage or current.

[0052] At least one source printed circuit board (SPCB) and a control printed circuit board (CPCB) may be circuitously connected through at least one connecting member, and the connecting member may be, for example, a flexible printed circuit (FPC), a flexible flat cable (FFC), etc. For example, there may be multiple source printed circuit boards (SPCB), and multiple source printed circuit boards (SPCB) may be connected to one control printed circuit board (CPCB). In this case, one source printed circuit board (SPCB) may be connected to the control printed circuit board (CPCB) through multiple flexible flat cables (FFC).

[0053] The display device (10) may further include a set board (700) electrically connected to a control printed circuit board (CPCB). In this case, the set board (700) may also be referred to as a power board. The set board (700) may contain a main power management circuit (M-PMC, 600) that manages the total power of the display device (10). The main power management circuit (600) may be linked with a power management circuit (500).

[0054] In the case of a display device (10) configured as described above, the driving voltage is generated in the set board (700) and transmitted to the power management circuit (500) within the control printed circuit board (CPCB). The power management circuit (500) transmits the driving voltage required for display driving or characteristic value sensing to the source printed circuit board (SPCB) via the flexible printed circuit (FPC) or flexible flat cable (FFC). The driving voltage transmitted to the source printed circuit board (SPCB) is supplied to emit or sense a specific pixel (PX) within the display panel (100) via the source driving integrated circuit (SDIC).

[0055] Although not illustrated, the driving voltage can be supplied to the pixel (PX) along the high voltage lines (see DVL_P, SB, DVL_1, DVL_2 in FIG. 4).

[0056] At this time, each pixel (PX) arranged in the display panel (100) within the display device (10) may be composed of a light-emitting element and a circuit element such as a driving transistor for driving it.

[0057] The type and number of circuit elements constituting each pixel (PX) can be determined in various ways depending on the provided functions and design methods.

[0058] FIG. 3 is an example diagram of a circuit constituting a pixel in a display device according to one embodiment.

[0059] Referring to FIG. 3, in a display device (10) according to one embodiment, a pixel (PX) may include one or more transistors and a capacitor, and an organic light-emitting diode may be disposed as a light-emitting element (ED).

[0060] For example, a pixel (PX) may include a driving transistor (DRT), a switching transistor (SWT), a sensing transistor (SENT), a storage capacitor (Cst), and a light-emitting element (ED).

[0061] The driving transistor (DRT) has a first node (N1), a second node (N2), and a third node (N3). The first node (N1) of the driving transistor (DRT) may be a gate node to which a data voltage (Vdata) is applied from the first circuit board (300) through a data line (DL) when the switching transistor (SWT) is turned on. The second node (N2) of the driving transistor (DRT) may be electrically connected to the anode electrode of the light-emitting element (ED) and may be a source node or a drain node. The third node (N3) of the driving transistor (DRT) may be electrically connected to a driving voltage line (DVL) to which a driving voltage (EVDD) is applied and may be a drain node or a source node.

[0062] At this time, during the display driving period, the driving voltage (EVDD) required to display the image can be supplied through the driving voltage line (DVL), for example, the driving voltage (EVDD) required to display the image can be 27V.

[0063] The switching transistor (SWT) is electrically connected between the first node (N1) of the driving transistor (DRT) and the data line (DL), and the gate line (GL) is connected to the gate node and operates according to the scan signal (SCAN) supplied through the gate line (GL). In addition, when the switching transistor (SWT) is turned on, the operation of the driving transistor (DRT) is controlled by transmitting the data voltage (Vdata) supplied through the data line (DL) to the gate node of the driving transistor (DRT).

[0064] The sensing transistor (SENT) is electrically connected between the second node (N2) of the driving transistor (DRT) and the reference voltage line (RVL), and the gate line (GL) is connected to the gate node and operates according to the sense signal (SENSE) supplied through the gate line (GL). When the sensing transistor (SENT) is turned on, the sensing reference voltage (Vref) supplied through the reference voltage line (RVL) is delivered to the second node (N2) of the driving transistor (DRT).

[0065] That is, by controlling the switching transistor (SWT) and the sensing transistor (SENT), the voltage at the first node (N1) and the voltage at the second node (N2) of the driving transistor (DRT) are controlled, thereby enabling the supply of current to drive the light-emitting element (ED).

[0066] The gate nodes of the switching transistor (SWT) and the sensing transistor (SENT) may be connected together to a single gate line (GL) or to different gate lines (GL). Here, a structure in which the switching transistor (SWT) and the sensing transistor (SENT) are connected to different gate lines (GL) is shown as an example, and in this case, the switching transistor (SWT) and the sensing transistor (SENT) can be controlled independently by the scan signal (SCAN) and the sense signal (SENSE) transmitted through the different gate lines (GL).

[0067] On the other hand, when the switching transistor (SWT) and the sensing transistor (SENT) are connected to a single gate line (GL), the switching transistor (SWT) and the sensing transistor (SENT) can be controlled simultaneously by a scan signal (SCAN) or sense signal (SENSE) transmitted through the single gate line (GL), and the aperture ratio of the pixel (PX) can be increased.

[0068] Meanwhile, the transistors placed in the pixel (PX) can consist of not only n-type transistors but also p-type transistors; however, the case composed of n-type transistors is shown here as an example.

[0069] The storage capacitor (Cst) is electrically connected between the first node (N1) and the second node (N2) of the driving transistor (DRT) and maintains the data voltage (Vdata) for one frame.

[0070] These storage capacitors (Cst) may be connected between the first node (N1) and the third node (N3) of the driving transistor (DRT) depending on the type of driving transistor (DRT). The anode electrode of the light-emitting element (ED) may be electrically connected to the second node (N2) of the driving transistor (DRT), and a base voltage (EVSS) may be applied to the cathode electrode of the light-emitting element (ED).

[0071] Here, the base voltage (EVSS) may be a ground voltage or a voltage higher or lower than the ground voltage. Additionally, the electromotive force voltage (EVSS) may vary depending on the driving state, for example, the base voltage (EVSS) at the time of display driving and the base voltage (EVSS) at the time of sensing driving may be set differently from each other.

[0072] The structure of the pixel (PX) described above as an example is a 3T (Transistor) 1C (Capacitor) structure, which is merely an example for illustrative purposes, and may include one or more additional transistors, or in some cases, one or more additional capacitors. Alternatively, each of the multiple pixels (PX) may have the same structure, or some of the multiple pixels (PX) may have different structures.

[0073] A display device (10) according to one embodiment may use a method of measuring the current flowing by the voltage charged to the storage capacitor (Cst) in the characteristic value sensing section of the driving transistor (DRT) in order to effectively sense the characteristic value of the driving transistor (DRT), for example, threshold voltage or mobility, and this is called current sensing.

[0074] That is, by measuring the current flowing due to the voltage charged in the storage capacitor (Cst) during the characteristic value sensing period of the driving transistor (DRT), the characteristic value of the driving transistor (DRT) within the pixel (PX) or the change in the characteristic value can be determined.

[0075] In this case, the reference voltage line (RVL) not only serves to transmit the reference voltage (Vref) but also acts as a sensing line to sense the characteristic value of the driving transistor (DRT) within the pixel (PX); therefore, the reference voltage line (RVL) can be referred to as a sensing line.

[0076] FIG. 4 is a plan view showing a display panel according to one embodiment.

[0077] Referring to FIG. 4, the display panel (100) may include a display area (DA) and a non-display area (NDA) surrounding the display area (DA), and the display area (DA) may include a plurality of pixels (PX).

[0078] The driving voltage (EVDD) delivered to the first circuit board (see 300 in FIG. 2) can be applied to each pixel (PX) of the display area (DA) through the pad high voltage line (DVL_P), the shorting bar (SB), the first high voltage line (DVL_1), and the second high voltage line (DVL_2).

[0079] Multiple pad high voltage lines (DVL_P) may be provided. One side of the multiple pad high voltage lines (DVL_P) may be connected to the first circuit board (see 300 in FIG. 2) in the pad area (PA), and the other side may be connected to the shorting bar (SB). Accordingly, the multiple pad high voltage lines (DVL_P) can transmit the driving voltage (EVDD) transmitted from the first circuit board (see 300 in FIG. 2) to the shorting bar (SB).

[0080] The shorting bar (SB) can be arranged in a form that extends along the first direction (DR1) from a non-display area (NDA) located on one side of the second direction (DR2) of the display panel (100).

[0081] One side of the first high voltage line (DVL_1) may be connected to one side of a shorting bar (SB) extended in the first direction (DR1), and the connected first high voltage line (DVL_1) may be placed in a non-display area (NDA) and may be arranged to surround a display area (DA) along the non-display area (NDA). The other side of the first high voltage line (DVL_1) surrounding the display area (DA) may be connected to the other side of a shorting bar (SB) extended in the first direction (DR1).

[0082] The second high voltage line (DVL_2) may be provided in multiple numbers, and one side and the other side of the multiple second high voltage lines (DVL_2) may be electrically connected to the first high voltage line (DVL_1) located in the non-display area (NDA) extended along the second direction (DR2). That is, the second high voltage lines (DVL_2) may be extended in the first direction (DR1) and placed in the display area (DA), and one side and the other side of the second high voltage line (DVL_2) in the first direction (DR1) may each be extended to the non-display area (NDA) and may be electrically connected to the first high voltage line (DVL_1) extended in the second direction from the non-display area (NDA).

[0083] Multiple pixels (PX) placed in a display area (DA) can be arranged in a matrix manner along a first direction (DR1) and a second direction (DR2). Accordingly, adjacent multiple pixels (PX) arranged along the first direction (DR1) can form a pixel row, and adjacent multiple pixels (PX) arranged along the second direction (DR2) can form a pixel column. That is, pixel rows can be arranged repeatedly along the second direction (DR2), and pixel columns can be arranged repeatedly along the first direction (DR1). However, the arrangement method of the multiple pixels (PX) in the embodiments of this specification may be a method other than the matrix method described above.

[0084] The second high voltage lines (DVL_2) can be arranged in overlap with the pixel row along the first direction (DR1), and thus can be connected to each pixel (PX) included in the pixel row.

[0085] FIG. 5 is a plan view showing a display panel according to one embodiment.

[0086] Referring to FIG. 5, a pixel (PX) may include a first subpixel (PX1), a second subpixel (PX2), and a third subpixel (PX3). The first subpixel (PX1) may include a first light-emitting region (EA1) and a first non-light-emitting region (NEA1) around the first light-emitting region (EA1), the second subpixel (PX2) may include a second light-emitting region (EA2) and a second non-light-emitting region (NEA2) around the second light-emitting region (EA2), and the third subpixel (PX3) may include a third light-emitting region (EA3) and a third non-light-emitting region (NEA3) around the third light-emitting region (EA3). That is, each non-light-emitting region (NEA1, NEA2, NEA3) may correspond to the boundary of adjacent subpixels (PX1, PX2, PX3).

[0087] An anode electrode (AND1, AND2, AND3) may be disposed in each subpixel (PX1, PX2, PX3). The anode electrode (AND1, AND2, AND3) may be disposed across the entire light-emitting region (EA1, EA2, EA3) and may also be partially disposed in the non-light-emitting region (NEA1, NEA2, NEA3). The area of ​​the anode electrode disposed in the light-emitting region (EA1, EA2, EA3) may be larger than the area of ​​the anode electrode disposed in the non-light-emitting region (NEA1, NEA2, NEA3).

[0088] Between each anode electrode (AND1, AND2, AND3), a data line (DL1, DL2, DL3) extending in a second direction (DR2) and a reference voltage line (RVL1, RVL2) extending in a second direction (DR2) may be arranged.

[0089] Reference voltage lines (RVL1, RVL2) and data lines (DL1, DL2, DL3) can be placed in the non-emissive regions (NEA1, NEA2, NEA3) of each subpixel (PX1, PX2, PX3).

[0090] A first reference voltage line (RVL1) may be disposed on one side of the first direction (DR1) of the first anode electrode (AND1), and a first data line (DL1) and a second data line (DL2) may be disposed on the other side. A first data line (DL1) and a second data line (DL2) may be disposed on one side of the first direction (DR1) of the second anode electrode (AND2), and a third data line (DL3) may be disposed on the other side. A third data line (DL3) may be disposed on one side of the first direction (DR1) of the third anode electrode (AND3), and a second reference voltage line (RVL2) may be disposed on the other side.

[0091] That is, a first data line (DL1) and a second data line (DL2) may be disposed between the first anode electrode (AND1) and the second anode electrode (AND2), and a third data line (DL3) may be disposed between the second anode electrode (AND2) and the third anode electrode (AND3). The first data line (DL1) may be disposed between the second data line (DL2) and the first anode electrode (AND1), and the second data line (DL2) may be disposed between the second anode electrode (AND2) and the first data line (DL1).

[0092] A second high-voltage line (DVL_2) may be disposed on one side of the second direction (DR2) of each anode electrode (AND1, AND2, AND3). The second high-voltage line (DVL_2) may be extended to the first direction (DR1) and thus may be electrically connected to the anode electrodes (AND1, AND2, AND3) disposed along the first direction (DR1) in the non-luminous regions (NEA1, NEA2, NEA3). Further details will be described later in FIG. 7.

[0093] A scan line (SL) extending to the first direction (DR1) may be disposed on one side of the second direction (DR2) of the second high voltage line (DVL_2). That is, the second high voltage line (DVL_2) may be disposed between each anode electrode (AND1, AND2, AND3) and the scan line (SL). The scan line (SL) may be a type of gate line (see GL in FIG. 1) and may be a wiring that transmits a scan signal. The second high voltage line (DVL_2) and the scan line (SL) may be disposed across the non-luminous regions (NEA1, NEA2, NEA3) of each subpixel (PX1, PX2, PX3).

[0094] Figure 6 is a cross-sectional view taken along the line AA' of Figure 5.

[0095] Referring to FIG. 6, the display panel (100) may include a substrate (110), a first conductive layer, a buffer layer (120), a first insulating layer (140), a second insulating layer (150), a third insulating layer (160), color filters (CF1, CF2), a flattening layer (OC), an anode electrode (AND1, AND2), an organic layer (170), and a cathode electrode (180).

[0096] The substrate (110) may be made of a material such as glass or plastic. In particular, in an organic light-emitting display device with a back-side light-emitting structure, the substrate (110) may be made of a transparent material so that light passing through the color filter (CF) is emitted to the outside, but the embodiments of the present specification are not limited thereto.

[0097] The first conductive layer may be disposed on a substrate (110). The first conductive layer may be a single layer or a multilayer composed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof, but the embodiments of the present specification are not limited thereto.

[0098] The first conductive layer may include a first data line (DL1) and a second data line (DL2). The first data line (DL1) may be placed in a first non-luminous region (NEA1), and the second data line (DL2) may be placed in a second non-luminous region (NEA2). Although not illustrated, a third data line (see DL3 in FIG. 5) may be placed in a third non-luminous region (see NEA3 in FIG. 5).

[0099] A buffer layer (120) may be disposed on the first conductive layer. The buffer layer (120) may minimize or delay the diffusion of moisture or oxygen penetrating the substrate (110) and may prevent a short circuit between the first conductive layer and the semiconductor layer (see 133 in FIG. 7) to be described later. The buffer layer (120) may be formed by stacking silicon nitride (SiNx) and silicon oxide (SiOx) alternately at least once, but the embodiments of the present specification are not limited thereto.

[0100] The first insulating layer (140) may be disposed on the buffer layer (120). The first insulating layer (140) can prevent short circuits between the semiconductor layer (see 133 in FIG. 7) to be described later and other components of the thin-film transistor (see 131, 132, 134 in FIG. 7). The first insulating layer (140) may be made of the same material as the buffer layer (120), but the embodiments of this specification are not limited thereto. For example, the first insulating layer (140) may be made of an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx), but the embodiments of this specification are not limited thereto.

[0101] A second insulating layer (150) may be disposed on the first insulating layer (140). The second insulating layer (150) may be formed by alternately stacking silicon nitride (SiNx) and silicon oxide (SiOx) at least once, but the embodiments of the present specification are not limited thereto.

[0102] A third insulating layer (160) may be disposed on the second insulating layer (150). The third insulating layer (160) may be made of the same material as the first insulating layer (140) or the second insulating layer (150), but the embodiments of this specification are not limited thereto.

[0103] Color filters (CF1, CF2) may be placed on the third insulating layer (160). The first color filter (CF1) may be placed on the first subpixel (PX1), and the second color filter (CF2) may be placed on the second subpixel (PX2). Although not illustrated, a third color filter may be placed on the third subpixel (see PX3 in FIG. 5).

[0104] Color filters (CF1, CF2) can block specific colors of light emitted from the light-emitting regions (EA1, EA2) of each subpixel (PX1, PX2). The first color filter (CF1) may be configured to block light of colors other than red (R) light. In this case, the first color filter (CF1) may be configured as a red color filter. The second color filter (CF2) may be configured to block light of colors other than green (G) light. In this case, the second color filter (CF2) may be configured as a green color filter. Although not illustrated, a color filter configured in the third subpixel (see PX3 in FIG. 5) may be configured to block light of colors other than blue (B) light, and in this case, the color filter may be configured as a blue color filter. However, the embodiments of this specification are not limited thereto.

[0105] Each color filter (CF1, CF2) may overlap in the thickness direction (e.g., third direction (DR)) at the boundary of adjacent subpixels (PX1, PX2). However, the embodiments of this specification are not limited thereto and may be spaced apart.

[0106] A flattening layer (OC) can be placed on the color filters (CF1, CF2). The flattening layer (OC) can perform the function of flattening the step formed by the color filters (CF1, CF2). The flattening layer (OC) may include an organic insulating material.

[0107] Anode electrodes (AND1, AND2) may be disposed on a planarization layer (OC). The first anode electrode (AND1) may be disposed in a first pixel (PX1), and more specifically, in a first light-emitting region (EA1). The second anode electrode (AND2) may be disposed in a second pixel (PX2), and more specifically, in a second light-emitting region (EA2). The anode electrodes (AND1, AND2) may be transparent electrodes that transmit light, but the embodiments of this specification are not limited thereto. For example, the anode electrodes (AND1, AND2) may include a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide) or a metal that transmits visible light, but the embodiments of this specification are not limited thereto.

[0108] The organic layer (170) may be disposed across the anode electrodes (AND1, AND2) and the planarization layer (OC) where the anode electrodes (AND1, AND2) are not disposed. The organic layer (170) may include one or more light-emitting structures (or light-emitting elements or elements) stacked in the order of a hole transport layer and an electron transport layer or in reverse order. For example, the hole transport layer may include a hole transport layer, a hole injection layer, an electron blocking layer, or a P-type charge generation layer, but the embodiments of the present specification are not limited thereto, and the electron transport layer may include an electron transport layer, an electron injection layer, a hole blocking layer, or an N-type charge generation layer, but the embodiments of the present specification are not limited thereto. The organic layer (170) may be an organic light-emitting layer.

[0109] A cathode electrode (180) may be disposed on an organic layer (170). The cathode electrode (180) may be a reflective electrode that reflects light, but the embodiments of this specification are not limited thereto. The cathode electrode (180) may include a stacked structure of aluminum (Al) and titanium (Ti) (Ti / Al / Ti), a stacked structure of aluminum (Al) and ITO (ITO / Al / ITO), a highly reflective metallic material such as an APC alloy, and may be composed of a single layer or multiple layers, but the embodiments of this specification are not limited thereto.

[0110] Figure 7 is a cross-sectional view taken along the BB' line of Figure 5.

[0111] Referring to FIG. 7, a buffer layer (120) may be disposed on a substrate (110), and a thin-film transistor (130) may be disposed between the buffer layer (120) and a second insulating layer (150). The thin-film transistor (130) may be a driving transistor (see DRT in FIG. 3) and may include a source electrode (131), a gate electrode (132), a semiconductor layer (133), and a drain electrode (134).

[0112] The source electrode (131), the semiconductor layer (133), and the drain electrode (134) may be disposed between the buffer layer (120) and the first insulating layer (140), and each may be disposed in the first non-luminous region (NEA1) of the first pixel (PX1).

[0113] The semiconductor layer (133) may include a silicon-based semiconductor material such as a metal oxide semiconductor such as IGZO (Indium-Gallium-Zinc Oxide), amorphous silicon, or polycrystalline silicon, but the embodiments of the present specification are not limited thereto.

[0114] Since the polycrystalline semiconductor layer has higher mobility than the amorphous semiconductor layer and oxide semiconductor layer, it can have low power consumption and excellent reliability. Accordingly, the semiconductor layer (133) can be composed of a polycrystalline semiconductor layer.

[0115] A source electrode (131) may be disposed on one side of the second direction of the semiconductor layer (133), and a drain electrode (134) may be disposed on the other side. The source electrode (131) and the drain electrode (134) may be formed of a metallic material. For example, the source electrode (131) and the drain electrode (134) may be composed of a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof, but the embodiments of this specification are not limited thereto.

[0116] A first insulating layer (140) is disposed on the source electrode (131), the semiconductor layer (133), and the drain electrode (134), thereby preventing a short circuit between each component (131, 133, 134) and the gate electrode (132).

[0117] The second conductive layer may be disposed between the first insulating layer (140) and the second insulating layer (150). The second conductive layer may include a gate electrode (132) and a scan line (SL).

[0118] The gate electrode (132) may be positioned to overlap with the semiconductor layer (133). The gate electrode (132) may be composed of a single layer or multiple layers comprising molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), or compounds thereof, but the embodiments of this specification are not limited thereto.

[0119] The scan line (SL) may be spaced apart from the gate electrode (132). The scan line (SL) and the gate electrode (132) may be placed in the first non-luminous region (NEA1) of the first pixel (PX).

[0120] The second insulating layer (150) is positioned between the second conductive layer and the third conductive layer to prevent a short circuit between the gate electrode (132) and the second high voltage line (DVL_2).

[0121] The third conductive layer may be disposed between the second insulating layer (150) and the third insulating layer (160) and may include a second high voltage line (DVL_2). The second high voltage line (DVL_2) may be disposed in the first non-luminous region (NEA1) of the first pixel (PX1). The second high voltage line (DVL_2) may be electrically connected to the drain electrode (134) through a contact hole (CT). The contact hole (CT) may be formed by penetrating the second insulating layer (150) and the first insulating layer (140) in a third direction (DR3), and the interior of the contact hole (CT) may be filled with the same material as the second high voltage line (DVL_2), but the embodiments of the present specification are not limited thereto, and may be filled with, for example, the same material as the drain electrode (134).

[0122] Although the second high voltage line (DVL_2) is shown as being placed in the third conductive layer, it may also be placed in the first conductive layer. In this case, the contact hole (CT) may be formed through the buffer layer (120) and, likewise, may be electrically connected to the drain electrode (134) through the contact hole (CT).

[0123] A third insulating layer (160) may be disposed on the third conductive layer, and a color filter (CF1) may be disposed on the third insulating layer (160). In one embodiment, a plurality of color filters (CF1) disposed along a pixel row may be color filters (CF1) that allow the same color to pass through. Accordingly, a color filter (CF1) disposed on the second high voltage line (DVL_2) and a color filter (CF1) disposed on the scan line (SL) may be color filters (CF1) that allow the same color to pass through. However, the present specification is not limited thereto, and may be color filters (CF1) that allow different colors to pass through. A plurality of color filters (CF1) disposed along a pixel row may overlap in the thickness direction (e.g., the third direction (DR)) in the first non-emissive region (NEA1) of the first pixel (PX1). However, the embodiments of the present specification are not limited thereto, and may be spaced apart.

[0124] A flattening layer (OC) may be disposed on the color filter (CF1), and a first anode electrode (AND1) may be disposed between the flattening layer (OC) and the organic layer (170). The first anode electrode (AND1) may be disposed across the first light-emitting region (EA1) and the first non-light-emitting region (NEA1) of the first pixel (PX1). That is, the first anode electrode (AND1) may be disposed in the first light-emitting region (EA1) and extended in the second direction (DR2), and one side of the extended first anode electrode (AND1) may be extended to the first non-light-emitting region (NEA1). At this time, the area of ​​the first anode electrode (AND1) disposed in the first light-emitting region (EA1) may be larger than the area of ​​the first anode electrode (AND1) disposed in the first non-light-emitting region (NEA1).

[0125] The first anode electrode (AND1) can be electrically connected to the source electrode (131) through a contact hole (CT). At this time, the contact hole (CT) can be formed by penetrating the flattening layer (OC), the color filter (CF1), the third insulating layer (160), the second insulating layer (150), and the first insulating layer (140). The interior of the contact hole (CT) may be filled with the same material as the first anode electrode (AND1), but the embodiments of this specification are not limited thereto, and may be filled with, for example, the same material as the source electrode (131).

[0126] An organic layer (170) may be disposed on the first anode electrode (AND1) and the planarization layer (OC) where the first anode electrode (AND1) is not disposed, and a cathode electrode (180) may be disposed on the organic layer (170). Other descriptions are as described in detail in FIG. 6, so further detailed descriptions will be omitted.

[0127] FIG. 8 is a cross-sectional view taken along the BB' line of a display panel according to another embodiment.

[0128] Referring to FIG. 8, the second high voltage line (DVL_2) can be placed in the second conductive layer. That is, the second high voltage line (DVL_2) can be placed between the first insulating layer (140) and the second insulating layer (150). Accordingly, the contact hole (CT) connecting the second high voltage line (DVL_2) and the drain electrode (134) can be formed by penetrating only the first insulating layer (140).

[0129] The scan line (SL) can be placed in the third conductive layer. That is, the scan line (SL) can be placed between the second insulating layer (150) and the third insulating layer (160).

[0130] The second high voltage line (DVL_2) and the scan line (SL) can be placed in the first non-emissive region (NEA1) of the first pixel (PX1). Other explanations are described in detail in FIG. 6, so further detailed explanations will be omitted.

[0131] FIG. 9 is a plan view showing a display panel according to another embodiment.

[0132] Referring to FIG. 9, the pixels (PX) of the display panel (100_2) may each include subpixels (PX1, PX2, PX3, PX4, PX5, PX6). For example, the first subpixel (PX1), the second subpixel (PX2), and the third subpixel (PX3) may form one pixel (PX), and the fourth subpixel (PX4), the fifth subpixel (PX5), and the sixth subpixel (PX6) may form one pixel (PX).

[0133] At this time, a first scan line (SL1), a second high voltage line (DVL_2_1), and a second scan line (SL2) may be arranged between adjacent subpixels (PX1, PX2, PX3, PX4, PX5, PX6) along the second direction (DR2). That is, a first scan line (SL1), a second high voltage line (DVL_2_1), and a second scan line (SL2) may be arranged between the first subpixel (PX1) and the fourth subpixel (PX4), between the second subpixel (PX2) and the fifth subpixel (PX5), and between the third subpixel (PX3) and the sixth subpixel (PX6).

[0134] A first scan line (SL1) may be positioned between a first anode electrode (AND1), a second anode electrode (AND2), and a third anode electrode (AND3) spaced apart along a first direction (DR1) and a second high voltage line (DVL_2_1), and a second high voltage line (DVL_2_1) may be positioned between a first scan line (SL1) and a second scan line (SL2), and a second scan line (SL2) may be positioned between a fourth anode electrode (AND4), a fifth anode electrode (AND5), and a sixth anode electrode (AND6) spaced apart along a first direction (DR1) and a second high voltage line (DVL_2_1).

[0135] A first scan line (SL1) may be placed in adjacent non-luminous regions (NEA1, NEA2, NEA3) arranged along a first direction (DR1), a second scan line (SL2) may be placed in adjacent non-luminous regions (NEA4, NEA5, NEA6) arranged along a first direction (DR1), and a second high voltage line (DVL_2_1) may be placed across adjacent non-luminous regions (NEA1, NEA2, NEA3, NEA4, NEA5, NEA6) arranged along a first direction (DR1) and a second direction (DR2). A detailed description will be provided later in FIG. 10.

[0136] Other explanations are described in detail in Fig. 5, so further detailed explanations will be omitted.

[0137] Figure 10 is a cross-sectional view taken along the CC' line of Figure 9.

[0138] Referring to FIG. 10, a thin-film transistor (130) may be disposed between the buffer layer (120) and the first insulating layer (140). A plurality of thin-film transistors (130) may be provided and may be disposed in the non-luminescent regions (NEA1, NEA4) of each pixel (PX1, PX4).

[0139] The source electrode (131) of the thin-film transistor (130) placed in the first non-luminous region (NEA1) can be electrically connected to the first anode electrode (AND1), and the source electrode (131) of the thin-film transistor (130) placed in the fourth non-luminous region (NEA4) can be electrically connected to the fourth anode electrode (AND4).

[0140] The second high voltage line (DVL_2_1) may be positioned between the first insulating layer (140) and the second insulating layer (150). The second high voltage line (DVL_2_1) may be positioned across the boundary between the first non-display area (NEA1) of the first pixel (PX1) and the fourth non-display area (NEA4) of the fourth pixel (PX4). Thus, the first pixel (PX1) and the fourth pixel (PX4) may be positioned to share the second high voltage line (DVL_2_1).

[0141] The second high voltage line (DVL_2_1) can be electrically connected to the drain electrode (134) of the thin-film transistor (130) placed in the first non-display area (NEA1), and can also be electrically connected to the drain electrode (134) of the thin-film transistor (130) placed in the fourth non-display area (NEA4). That is, the drain electrode (134) of the thin-film transistor (130) placed in the first non-display area (NEA1) and the drain electrode (134) of the thin-film transistor (130) placed in the fourth non-display area (NEA4) can be electrically connected to each other through the second high voltage line (DVL_2_1).

[0142] The first scan line (SL1) and the second scan line (SL2) may be positioned between the second insulating layer (150) and the third insulating layer (160), and each scan line (SL1, SL2) may be positioned in the non-luminous region (NEA1, NEA4) of each pixel (PX1, PX4). The scan lines (SL1, SL2) and the second high voltage line (DVL_2_1) may be positioned so as not to overlap each other in the third direction (DR3). That is, the first scan line (SL1) can be positioned between the gate electrode (132) placed in the first non-luminous region (NEA1) and the second high voltage line (DVL_2_1) based on the second direction (DR2), and the second scan line (SL2) can be positioned between the gate electrode (132) placed in the fourth non-luminous region (NEA4) and the second high voltage line (DVL_2_1) based on the second direction (DR2). Signal interference between each line can be prevented by ensuring that the scan lines (SL1, SL2) do not overlap with the second high voltage line (DVL_2_1) and the third direction (DR3).

[0143] Other explanations are described in detail in FIGS. 6 and FIGS. 7, so further detailed explanations will be omitted below.

[0144] FIG. 11 is a cross-sectional view taken along the CC' line of a display panel according to another embodiment.

[0145] Referring to FIG. 11, scan lines (SL1, SL2) can be placed between the first insulating layer (140) and the second insulating layer (150), and the second high voltage line (DVL_2_1) can be placed between the second insulating layer (150) and the third insulating layer (160).

[0146] In order to prevent signal interference between the scan lines (SL1, SL2) and the second high voltage line (DVL_2_1), the lines must not overlap with respect to the third direction (DR3). Therefore, with respect to the second direction (DR2), the first scan line (SL1) can be placed between the gate electrode (132) placed in the first non-luminous region (NEA1) and the second high voltage line (DVL_2_1), and the second scan line (SL2) can be placed between the gate electrode (132) placed in the fourth non-luminous region (NEA4) and the second high voltage line (DVL_2_1).

[0147] Other explanations are described in detail in FIGS. 8 and FIGS. 10, so further detailed explanations will be omitted.

[0148] A display device according to various embodiments of the present specification may be described as follows.

[0149] A display device according to various embodiments of the present specification comprises: a substrate including a display area comprising a plurality of pixels and a non-display area surrounding the display area; a first high-voltage line surrounding the display area in the non-display area on the substrate; and a second high-voltage line having one end and the other end connected to the first high-voltage line and connected to a first pixel row comprising the pixels arranged along a first direction, wherein one end and the other end of the second high-voltage line are each connected to the first high-voltage line in the non-display area.

[0150] According to various embodiments of the present specification, a display device further comprises a scan line connected to the first pixel row and a data line connected to the first pixel column, the scan line and the data line including pixels arranged along a second direction intersecting the first direction, and the second high voltage line, the scan line and the data line may each be arranged on different layers.

[0151] According to various embodiments of the present specification, a display device may further include a first conductive layer on the substrate, a second conductive layer on the first conductive layer, and a third conductive layer on the second conductive layer.

[0152] According to a display device according to various embodiments of the present specification, the data line may be disposed in the first conductive layer, the second high voltage line may be disposed in the third conductive layer, and the scan line may be disposed in the second conductive layer.

[0153] According to a display device according to various embodiments of the present specification, the data line may be disposed in the first conductive layer, the second high voltage line may be disposed in the second conductive layer, and the scan line may be disposed in the third conductive layer.

[0154] According to various embodiments of the present specification, a display device may further include a color filter on the third conductive layer and a flattening layer on the color filter.

[0155] According to a display device according to various embodiments of the present specification, the pixel includes a plurality of subpixels, and each color filter disposed on the adjacent subpixels can overlap at the boundary of the adjacent subpixels.

[0156] According to various embodiments of the present specification, a display device further comprises an anode electrode, and said anode electrode may be disposed on the third conductive layer.

[0157] According to a display device according to various embodiments of the present specification, the pixel includes a light-emitting region and a non-light-emitting region surrounding the light-emitting region, and the anode electrode overlaps the entirety of the light-emitting region and a portion of the anode electrode may overlap the non-light-emitting region.

[0158] According to a display device according to various embodiments of the present specification, the anode electrode and the second high voltage line can be electrically connected.

[0159] According to a display device according to various embodiments of the present specification, the anode electrode and the second high voltage line can be electrically connected in the non-luminous region.

[0160] According to various embodiments of the present specification, a display device further comprises a second pixel row adjacent to the first pixel row and arranged parallel to the second direction, and the second high voltage line may be arranged between the first pixel row and the second pixel row.

[0161] According to a display device according to various embodiments of the present specification, the first pixel row and the second pixel row may be electrically connected to a second high-voltage line disposed between the first pixel row and the second pixel row.

[0162] According to various embodiments of the present specification, a display device further comprises a plurality of pixel rows parallel to the first pixel row and a plurality of second high-voltage lines, and the arrangement of the pixel rows and the second high-voltage lines may be repeated along a second direction.

[0163] According to various embodiments of the present specification, a display device comprises: a substrate including a first pixel row comprising a plurality of pixels arranged along a first direction, and a non-display area surrounding the display area; a first conductive layer; a buffer layer on the first conductive layer; a semiconductor layer on the buffer layer; a first insulating layer on the semiconductor layer; a second conductive layer on the first insulating layer; a second insulating layer on the second conductive layer; and a third conductive layer on the second insulating layer, and further comprises a high-voltage line connected to the first pixel row and extending along the first direction, wherein the high-voltage line is disposed on the first conductive layer, the second conductive layer, or the third conductive layer, and the high-voltage line extends to the non-display area.

[0164] According to various embodiments of the present specification, a display device further comprises a scan line connected to the first pixel row and a data line connected to the first pixel column, the data line including pixels arranged along a second direction intersecting the first direction, wherein the high voltage line is disposed in the third conductive layer, the scan line is disposed in the second conductive layer, and the data line is disposed in the first conductive layer.

[0165] According to various embodiments of the present specification, a display device further comprises a scan line connected to the first pixel row and a data line connected to the first pixel column, the data line including pixels arranged along a second direction intersecting the first direction, wherein the high voltage line is disposed in the second conductive layer, the scan line is disposed in the third conductive layer, and the data line is disposed in the first conductive layer.

[0166] According to various embodiments of the present specification, a display device further comprises a color filter on the third conductive layer and a flattening layer on the color filter, and each color filter disposed on the plurality of pixels can overlap at the boundary of the adjacent pixels.

[0167] According to various embodiments of the present specification, a display device further comprises an anode electrode, wherein the anode electrode is disposed on the third conductive layer, and the display area comprises a light-emitting area and a non-light-emitting area surrounding the light-emitting area, and the anode electrode and the high voltage line may be electrically connected in the non-light-emitting area.

[0168] According to various embodiments of the present specification, a display device further comprises a second pixel row adjacent to the first pixel row and parallel to the second direction, and a high voltage line is disposed between the first pixel row and the second pixel row, and the first pixel row and the second pixel row may be electrically connected to the high voltage line.

[0169] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the technical configuration of the present invention described above may be implemented in other specific forms without altering the technical concept or essential features of the present invention. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Furthermore, the scope of the present invention is defined by the claims set forth below rather than by the detailed description above. Additionally, all modifications or variations derived from the meaning and scope of the claims and equivalent concepts should be interpreted as being included within the scope of the present invention. Explanation of the symbols

[0170] 1: Display device 10: Display panel 110: Substrate 120: Buffer layer 130: Thin-film transistor 140: First insulating layer 150: Second insulating layer 160: Third insulating layer CF: Color filter OC: Leveling layer AND : Anode electrode 170: Organic layer 180: Cathode electrode CT: Contact hole DL: Data line SL: Scan line DVL_1: 1st high-voltage line DVL_2: Second high-voltage line SB: Shortening bar RVL: Reference Voltage Line

Claims

Claim 1 A substrate comprising a display area including a plurality of pixels and a non-display area surrounding the display area; a first high-voltage line surrounding the display area in the non-display area on the substrate; and a second high-voltage line having one end and the other end respectively connected to the first high-voltage line and connected to a first pixel row including the pixels arranged along a first direction, wherein one end and the other end of the second high-voltage line are respectively connected to the first high-voltage line in the non-display area and the first high-voltage line. Claim 2 A display device according to claim 1, further comprising a scan line connected to the first pixel row and a data line connected to a first pixel column including pixels arranged along a second direction intersecting the first direction, wherein the second high voltage line, the scan line, and the data line are each arranged on different layers. Claim 3 A display device according to claim 2, further comprising a first conductive layer on the substrate, a second conductive layer on the first conductive layer, and a third conductive layer on the second conductive layer. Claim 4 A display device according to claim 3, wherein the data line is disposed in the first conductive layer, the second high voltage line is disposed in the third conductive layer, and the scan line is disposed in the second conductive layer. Claim 5 A display device according to claim 3, wherein the data line is disposed in the first conductive layer, the second high voltage line is disposed in the second conductive layer, and the scan line is disposed in the third conductive layer. Claim 6 A display device according to claim 3, further comprising a color filter on the third conductive layer and a planarization layer on the color filter. Claim 7 In claim 6, the pixel comprises a plurality of subpixels, and each color filter disposed on the adjacent subpixels overlaps at the boundary of the adjacent subpixels. Claim 8 A display device according to claim 3, further comprising an anode electrode, wherein the anode electrode is disposed on the third conductive layer. Claim 9 A display device according to claim 8, wherein the pixel comprises a light-emitting region and a non-light-emitting region surrounding the light-emitting region, and the anode electrode overlaps the entirety of the light-emitting region and a portion of the anode electrode overlaps the non-light-emitting region. Claim 10 In claim 9, the anode electrode and the second high-voltage line are electrically connected to a display device. Claim 11 In claim 10, the anode electrode and the second high-voltage line are electrically connected in the non-luminous region of the display device. Claim 12 A display device according to claim 2, further comprising a second pixel row adjacent to the first pixel row and arranged parallel to the second direction, wherein the second high-voltage line is arranged between the first pixel row and the second pixel row. Claim 13 In claim 12, the first pixel row and the second pixel row are electrically connected to a second high-voltage line disposed between the first pixel row and the second pixel row. Claim 14 A display device according to claim 12, further comprising a plurality of pixel rows parallel to the first pixel row and a plurality of second high-voltage lines, wherein the arrangement of the pixel rows and the second high-voltage lines is repeated along a second direction. Claim 15 A display device comprising: a substrate including a first pixel row comprising a plurality of pixels arranged along a first direction, and a non-display area surrounding the display area; a first conductive layer; a buffer layer on the first conductive layer; a semiconductor layer on the buffer layer; a first insulating layer on the semiconductor layer; a second conductive layer on the first insulating layer; a second insulating layer on the second conductive layer; and a third conductive layer on the second insulating layer, and further comprising a high-voltage line connected to the first pixel row and extending along the first direction, wherein the high-voltage line is disposed on the first conductive layer, the second conductive layer, or the third conductive layer, and the high-voltage line extends to the non-display area. Claim 16 In Article 15, A display device further comprising a scan line connected to the first pixel row and a data line connected to a first pixel column including pixels arranged along a second direction intersecting the first direction, wherein the high voltage line is disposed in the third conductive layer, the scan line is disposed in the second conductive layer, and the data line is disposed in the first conductive layer. Claim 17 In Article 15, A display device further comprising a scan line connected to the first pixel row and a data line connected to a first pixel column including pixels arranged along a second direction intersecting the first direction, wherein the high voltage line is disposed in the second conductive layer, the scan line is disposed in the third conductive layer, and the data line is disposed in the first conductive layer. Claim 18 In Article 15, A display device further comprising a color filter on the third conductive layer and a flattening layer on the color filter, wherein each color filter disposed on the plurality of pixels overlaps at the boundary of the adjacent pixels. Claim 19 In Article 15, A display device further comprising an anode electrode, wherein the anode electrode is disposed on the third conductive layer, and the display area includes a light-emitting area and a non-light-emitting area surrounding the light-emitting area, and the anode electrode and the high voltage line are electrically connected in the non-light-emitting area. Claim 20 A display device according to claim 15, further comprising a second pixel row adjacent to the first pixel row and a second direction intersecting the first direction, wherein the high voltage line is disposed between the first pixel row and the second pixel row, and the first pixel row and the second pixel row are electrically connected to the high voltage line.

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