Memory device and operating method of memory device

Abstract

In a memory device according to an exemplary embodiment of the present disclosure, a controller that generates a control signal based on the type of memory cell to perform a read operation of the memory device; a cell array including a normal memory region including a normal memory cell capable of multiple programmable times, an OTP memory region including an OTP (one-time programmable) memory cell capable of one-time programmable times, a normal reference region including a normal reference cell corresponding to the normal memory cell, and an OTP reference region including an OTP reference cell corresponding to the OTP memory cell; and a detection amplifier that detects a difference between an input signal applied from the memory cell and a reference signal applied from the reference cell and generates a comparison signal, wherein the normal reference cell and the OTP reference cell may be configured to share a target reference bit line.

Description

Technology Field

[0001] The technical concept of the present disclosure relates to a memory device and a method of operating a memory device, and more specifically, to a memory device and a method of operating the same that share a reference bit line between a normal reference cell and an OTP (One Time Programmable) reference cell. Background Technology

[0002] A resistive memory device can store data in a memory cell that includes a variable resistance element. The variable resistance element may include a magnetic tunnel junction (MTJ) element. For example, the MTJ element may include two magnetic materials and an insulating film interposed between them. The resistance value of the MTJ element may vary depending on the magnetization directions of the two magnetic materials. For example, when the magnetization directions of the two magnetic materials are antiparallel, the MTJ element may have a large resistance value, and when the magnetization directions of the two magnetic materials are parallel, the MTJ element may have a small resistance value. Data can be programmed and read using this difference in resistance values.

[0003] A resistive memory device includes a normal memory cell and an OTP memory cell, and each of the normal memory cell and the OTP memory cell may include a variable resistor element. The normal memory cell can store data or read stored data using the variable resistor element. The OTP memory cell can be programmed only once, and once programmed, the contents cannot be changed and can be retained even after the power is removed.

[0004] OTP memory cells can be used for security-sensitive data, such as configuration values ​​for memory devices. Since OTP memory cells can store security-sensitive data, errors must be minimized when reading data from them. Accordingly, there has recently been increasing interest in technology that combines normal memory cells and OTP memory cells into a single IP (or a single memory chip). However, when combining normal memory cells and OTP memory cells into a single IP, the OTP reference cell may require a separate reference bit line because it generates a reference signal in a manner different from that of the normal reference cell. Therefore, when combining normal memory cells and OTP memory cells into a single IP, technology is required to share the reference bit line between the normal reference cell and the OTP reference cell. The problem to be solved

[0005] The problem that the technical concept of the present invention aims to solve is to provide a memory device and a method of operation thereof for preventing an increase in the core area for a separate reference bit line and improving the read margin of the normal memory cell and the OTP memory cell by sharing the reference bit line between the normal reference cell and the OTP reference cell when designing the normal memory cell and the OTP memory cell as a single IP (or a single memory chip). means of solving the problem

[0006] As a technical means for achieving the technical problem described above, the memory device according to the present disclosure comprises: a controller that generates a control signal based on the type of memory cell to perform a read operation of the memory device; a cell array comprising a normal memory region including a normal memory cell capable of multiple programmable times, an OTP memory region including an OTP (one-time programmable) memory cell capable of one-time programmable time, a normal reference region including a normal reference cell corresponding to the normal memory cell, and an OTP reference region including an OTP reference cell corresponding to the OTP memory cell; and a detection amplifier that detects the difference between an input signal applied from the memory cell and a reference signal applied from the reference cell and generates a comparison signal, wherein the normal reference cell and the OTP reference cell may be configured to share a target reference bit line.

[0007] As a technical means for achieving the aforementioned technical problem, a method of operation of a memory device according to the present disclosure comprising a normal memory cell capable of multiple programmable operations, a one-time programmable (OTP) memory cell capable of one-time programmable operations, a normal reference cell, an OTP reference cell, and a reference switching circuit, comprising: an operation of identifying whether a read operation of the normal memory cell or a read operation of the OTP memory cell is based on a control signal received from a memory controller; an operation of turning off a switch transistor of the reference switching circuit to generate a first reference resistance value based on a resistor element of the reference switching circuit when the identification result is a read operation of the normal memory cell; and an operation of turning on a switch transistor of the reference switching circuit to bypass the resistor element of the reference switching circuit and generating a second reference resistance value by combining a plurality of OTP reference cells when the identification result is a read operation of the OTP memory cell. The OTP reference cell shares a target reference bit line and can be connected to the reference switching circuit through the target reference bit line.

[0008] As a technical means for achieving the technical problem described above, a memory system according to the present disclosure comprises: a memory controller; a cell array including a normal memory cell capable of multiple programmables, an OTP memory cell capable of one programmable, a normal reference cell, and an OTP reference cell; and a reference switching circuit connected to the cell array through a target reference bit line, wherein the normal reference cell and the OTP reference cell share the target reference bit line, and the memory device, when a read operation of the normal memory cell is performed, generates a first reference signal based on a resistor element of the reference switching circuit using the target reference bit line, and when a read operation of the OTP memory cell is performed, generates a second reference signal based on a switch transistor of the reference switching circuit and a variable resistor element of the OTP reference cell using the target reference bit line. Effects of the invention

[0009] According to the technical concept of the present disclosure, a memory device and a method of operating a memory device can improve the read margin of a memory cell by preventing an increase in the core (or memory chip) area for a separate reference bit line and preventing deterioration of word line offset characteristics when designing a normal memory cell and an OTP memory cell as a single IP and sharing a reference bit line between a normal reference cell and an OTP reference cell.

[0010] In addition, the memory device and the method of operating the memory device according to the technical concept of the present disclosure can maximize the read margin of each memory cell based on low design complexity by sharing the reference bit line between the normal reference cell and the OTP reference cell.

[0011] The effects obtainable from the exemplary embodiments of the present disclosure are not limited to those mentioned above, and other unmentioned effects can be clearly derived and understood by those skilled in the art to which the exemplary embodiments of the present disclosure belong from the following description. That is, unintended effects resulting from the implementation of the exemplary embodiments of the present disclosure can also be derived by those skilled in the art from the exemplary embodiments of the present disclosure. Brief explanation of the drawing

[0012] FIG. 1 is a block diagram showing a memory device according to an exemplary embodiment of the present invention. FIG. 2a is a drawing showing an example of a memory cell according to an exemplary embodiment of the present disclosure. FIG. 2b is a drawing showing an example of a reference cell according to an exemplary embodiment of the present disclosure. FIG. 3 is a diagram showing the dispersion of resistance values ​​of a memory cell and a reference cell according to an exemplary embodiment of the present disclosure. FIG. 4a is a drawing for illustrating a cell array according to an exemplary embodiment of the present disclosure. FIG. 4b is a drawing for illustrating a cell array according to an exemplary embodiment of the present disclosure. FIG. 5 is a diagram showing the structure of a memory device during a read operation according to an exemplary embodiment of the present disclosure. FIG. 6 is a diagram showing a wiring structure associated with a reference cell and a reference bit line of a memory device according to an exemplary embodiment of the present disclosure. FIG. 7 is a diagram showing a wiring structure associated with a reference cell and a reference bit line of a memory device according to an exemplary embodiment of the present disclosure. FIG. 8 is a diagram showing a wiring structure associated with a reference cell and a reference bit line of a memory device according to an exemplary embodiment of the present disclosure. FIG. 9 is a diagram showing a wiring structure associated with a reference cell and a reference bit line of a memory device according to an exemplary embodiment of the present disclosure. FIG. 10 is a flowchart illustrating a method of operation of a memory device according to an exemplary embodiment of the present disclosure. FIG. 11 is a block diagram showing a memory system including a memory device according to an exemplary embodiment of the present disclosure. FIG. 12 is a block diagram showing a system-on-chip including a memory device according to an exemplary embodiment of the present disclosure. Specific details for implementing the invention

[0013] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. Identical components in the drawings are denoted by the same reference numerals, and redundant descriptions thereof are omitted.

[0014] FIG. 1 is a block diagram showing a memory device according to an exemplary embodiment of the present invention.

[0015] Referring to FIG. 1, the memory device (10) may include a cell array (110), a row decoder (120), a column decoder (130), a read circuit (140), an address decoder (150), a data buffer (160), and a controller (170).

[0016] A memory device (10) can receive a command (CMD) and an address (ADDR), and can receive or output data (DATA). For example, the memory device (10) can receive a command (CMD), such as a write command or a read command, and an address (ADDR) corresponding to the command (CMD) from a memory controller. Additionally, the memory device (10) can receive data (DATA) (i.e., write data) from the memory controller or provide data (DATA) (i.e., read data) to the memory controller. In some embodiments, at least two of the command (CMD), address (ADDR), and data (DATA) may be received or output through the same channel.

[0017] A cell array (110) may include a plurality of memory cells (NMC, OMC). The cell array (110) includes a plurality of memory cells (NMC, OMC) arranged in rows and columns. A plurality of memory cells (NMC, OMC) may be connected to a plurality of word lines (WLs). Memory cells connected to a single word line may be referred to as pages, and data may be read out or written on a page-by-page basis.

[0018] In some embodiments, the memory cell may include a variable resistor element (e.g., the MTJ of FIG. 2a), and the variable resistor element (MTJ) may have a resistance value corresponding to a value (or bit) stored in the memory cell. Hereinafter, the normal memory cell (NMC) and the OTP memory cell (OMC) may be referred to as memory cells, and the normal reference cell (NRC) and the OTP reference cell (ORC) may be referred to as reference cells. When the memory cell includes a variable resistor element (MTJ), the memory device (10) may be referred to as a resistive memory device. For example, the memory device (10) may include a cell array (110) of an MRAM (Magnetic Random Access Memory) structure, such as STT-MRAM (Spin-Transfer Torque Magnetic Random Access Memory), Spin-RAM (Spin Torque Transfer Magnetization Switching RAM), and SMT-RAM (Spin Momentum Transfer), as a non-limiting example, and may also include a cell array (110) of a structure such as PRAM (Phase Change Random Access Memory), FRAM (Ferroelectric Random Access Memory), etc. In the following, exemplary embodiments of the present disclosure will be described with reference mainly to MRAM, but it should be noted that the exemplary embodiments of the present disclosure are not limited thereto.

[0019] In the memory device (10), each of the memory cells (NMC, OMC) may include a cell transistor (e.g., the cell transistor (CT) of FIG. 2a) and a variable resistor element (MTJ). The cell array (110) may include a plurality of word lines (WLs), a plurality of bit lines (BLs), and a plurality of source lines (e.g., the source line (SLj) of FIG. 2a) connected to the memory cells (NMC, OMC). Each of the word lines (WLs) may be connected to the gate of the cell transistor of the memory cells (NMC, OMC) located in one of the rows of the cell array (110), and each of the bit lines (BLs) and source lines may be connected to the source of the cell transistor and the variable resistor element of the memory cells (NMC, OMC) located in one of the columns of the cell array (110).

[0020] The memory cell array (110) may include a normal memory cell (NMC) and an OTP (One Time Programmable) memory cell (OMC). The normal memory cell (NMC) refers to a memory cell that operates to store data in a general manner and can be programmed multiple times. The OTP memory cell (OMC) may refer to a memory cell that operates for an OTP function. The OTP memory cell (OMC) can be programmed once. In an embodiment, the normal memory cell (NMC) and the OTP memory cell (OMC) may be implemented as a single memory chip, and the memory device (10) may use the normal memory cell (NMC) and the OTP memory cell (OMC) simultaneously through a single memory chip.

[0021] The cell array (110) may include normal memory cells (NMC) and OTP memory cells (OMC) connected to different word lines (WL). For example, normal memory cells (NMC) may be connected to word line (WL1), and OTP memory cells (OMC) may be connected to word line (WLn). Although the cell array (110) of FIG. 1 is illustrated with one row containing normal memory cells (NMC) and one row containing OTP memory cells (OMC), it is not necessarily limited thereto, and the cell array (110) may include at least one row containing normal memory cells (NMC) and at least one row containing OTP memory cells (OMC). Additionally, Figure 1 illustrates that the normal memory cell (NMC) and the OTP memory cell (OMC) are connected to different word lines (WL) and share a bit line (BL), but this is not necessarily limited to the normal memory cell (NMC) and the OTP memory cell (OMC) may be configured to share the same word line (WL).

[0022] Each of the normal memory cell (NMC) and the OTP memory cell (OMC) may include a variable resistor element and a cell transistor. Hereinafter, the variable resistor element and the cell transistor included in the normal memory cell (NMC) are referred to as the first variable resistor element (e.g., the first variable resistor element (MTJ1) of FIG. 3a) and the first cell transistor (e.g., the first cell transistor (CT1) of FIG. 3a), respectively, and the variable resistor element and the cell transistor included in the OTP memory cell (OMC) are referred to as the second variable resistor element (e.g., the second variable resistor element (MTJ2) of FIG. 3a) and the second cell transistor (e.g., the second cell transistor (CT2) of FIG. 3a), respectively. Rows of normal memory cells (NMCs) may be connected to a corresponding word line (WL1), and rows of OTP memory cells (OMCs) may be connected to a corresponding word line (WLn).

[0023] The OTP memory cell (OMC) is one-time programmable, and once programmed, the contents cannot be changed and are retained even after the power is removed. The OTP memory cell (OMC) can store security-sensitive data. For example, the OTP memory cell (OMC) can store digital security tokens, smart cards, keys, passwords, boot codes, production settings, manufacturing settings, setting values ​​of the memory device (10), trim values, etc. The second variable resistor element of the OTP memory cell (OMC) can have an irreversible resistance state (i.e., a breakdown state) by applying a breakdown voltage (BV) through a one-time programming operation to dielectricly break down the tunnel barrier layer (e.g., the barrier layer (TBL) of FIG. 2a).

[0024] Since the OTP memory cell (OMC) stores security-sensitive data such as the setting value of the memory device (10), it needs to be implemented as a single chip with the normal memory cell (NMC) as an essential element of the memory device (10). As described below with reference to the drawings, the memory device (10) according to the present disclosure can improve the read margin of the memory device (10) by preventing the occurrence of word line offsets caused by the use of separate reference bit lines, by sharing a reference bit line between the normal reference cell (NRC) and the OTP reference cell (ORC) (i.e., the normal reference cell (NRC) and the OTP reference cell (ORC) are connected to the same reference bit line). Accordingly, errors can be reduced and data reliability improved when reading data stored in the normal memory cell (NMC) and the OTP memory cell (OMC). In addition, since the cell array (110) and peripheral circuits can be utilized as they are, the memory device (10) can have a simple structure and low cost. Also, since a separate reference bit line, cell array (110), and peripheral circuits for storing security-sensitive data can be omitted, the system including the memory device (10) can have a simple structure and low cost.

[0025] In the embodiment, the structure of the OTP memory cell (OMC) may be identical to the structure of the normal memory cell (NMC). For example, the normal memory cell (NMC) may include one first cell transistor and one first variable resistor element. The OTP memory cell (OMC) may include one second cell transistor and one second variable resistor element. However, it is not necessarily limited thereto. The structure of the OTP memory cell (OMC) may differ from the structure of the normal memory cell (NMC). For example, the normal memory cell (NMC) may include one first cell transistor and one first variable resistor element. The OTP memory cell (OMC) may include three second cell transistors and one second variable resistor element, or six second cell transistors and one second variable resistor element.

[0026] The cell array (110) may include a plurality of reference cells (NRC, ORC). The cell array (110) may include normal reference cells (NRC) and OTP reference cells (ORC). The normal reference cell (NRC) may refer to a reference cell corresponding to a normal memory cell (NMC). The normal reference cell (NRC) may be connected to a word line (WL) corresponding to the normal memory cell (NMC). For example, the normal memory cell (NMC) and the normal reference cell (NRC) may share a word line (WL1). The normal reference cell (NRC) may be used to determine a value stored in the normal memory cell (NMC). When one of a plurality of word lines is activated by a row decoder (120) and the activated word line (WL) corresponds to a normal memory cell (NMC), not only the normal memory cell (NMC) connected to the activated word line (WL1) but also the normal reference cell (NRC) connected to the activated word line (WL1) can be selected. For example, the normal memory cell (NMC) and the normal reference cell (NRC) can be selected by the activated word line (WL1).

[0027] When determining the value stored in the normal memory cell (NMC), a normal reference cell (NRC) corresponding to the normal memory cell (NMC) may be used. For example, a normal reference cell (NRC) selected by the same word line as the normal memory cell (NMC) may be used to read out the data stored in the normal memory cell (NMC). The normal reference cell (NRC) may have a first reference resistance value. In an embodiment, the normal reference cell (NRC) may include a resistor element such as a variable resistor element, and the fact that the normal reference cell (NRC) has a first reference resistance value may mean that the resistance value of the resistor element included in the normal reference cell (NRC) corresponds to the first reference resistance value. However, it is not necessarily limited thereto, and in an embodiment, the normal reference cell (NRC) may be a shorted cell in which a resistor element such as a variable resistor element is omitted. If the normal reference cell (NRC) is a short-circuited cell, it may include a resistor circuit connected to the normal reference cell (NRC) outside the cell array (110) (e.g., a resistor element (RM) of the reference switching circuit (RSC) of FIG. 4a). The fact that the normal reference cell (NRC) has a first reference resistor value may mean that the resistor value of the resistor circuit connected to the normal reference cell (NRC) (e.g., a resistor element (RM) of the reference switching circuit (RSC) of FIG. 4a) corresponds to the first reference resistor value.

[0028] Data stored in a normal memory cell (NMC) can be read out based on a first reference resistance value. For example, to determine the data stored in the normal memory cell (NMC), the resistance value of a first variable resistance element of the normal memory cell (NMC) can be compared with the first reference resistance value of a normal reference cell (NRC).

[0029] An OTP reference cell (ORC) may refer to a reference cell corresponding to an OTP memory cell (OMC). An OTP reference cell (ORC) may be connected to a word line (WLm) corresponding to an OTP memory cell (OMC). For example, an OTP memory cell (OMC) and an OTP reference cell (ORC) may share a word line (WLn). An OTP reference cell (ORC) may be used to determine a value stored in an OTP memory cell (OMC). When one of a plurality of word lines is activated by a row decoder (120) and the activated word line (WL) corresponds to an OTP memory cell (OMC), not only the OTP memory cell (OMC) connected to the activated word line (WL) but also the OTP reference cell (ORC) connected to the activated word line (WL) may be selected. For example, the OTP memory cell (OMC) and OTP reference cell (ORC) can be selected by the activated word line (WLn).

[0030] When determining the value stored in the OTP memory cell (OMC), an OTP reference cell (ORC) corresponding to the OTP memory cell (OMC) may be used. For example, an OTP reference cell (ORC) selected by the same word line as the OTP memory cell (OMC) may be used to read out the data stored in the OTP memory cell (OMC). The OTP reference cell (ORC) may have a second reference resistance value. In an embodiment, the OTP reference cell (ORC) may include a resistor element such as a variable resistor element, and the fact that the OTP reference cell (ORC) has a second reference resistance value may mean that the resistance value of the resistor element included in the OTP reference cell (ORC) corresponds to the second reference resistance value. The second reference resistance value of the OTP reference cell (ORC) can be generated based on the connection / combination between multiple OTP reference cells (ORCs) (e.g., variable resistance elements of the OTP reference cells (ORCs). However, this is not necessarily limited thereto, and in the embodiment, the OTP reference cell (ORC) may be a shorted cell in which a resistance element, such as a variable resistance element, is omitted.

[0031] Data stored in the OTP memory cell (OMC) can be read out based on the second reference resistance value. For example, to determine the data stored in the OTP memory cell (OMC), the resistance value of the second variable resistor element of the OTP memory cell (OMC) can be compared with the second reference resistance value of the OTP reference cell (ORC).

[0032] In one embodiment, the first reference resistance value of the normal reference cell (NRC) may be different from the second reference resistance value of the OTP reference cell (ORC). The first reference resistance value may be a resistance value for distinguishing between the parallel state (e.g., the parallel state (R_S2)(P) of FIG. 3) and the anti-parallel state (e.g., the anti-parallel state (R_S1)(AP) of FIG. 3) of the normal memory cell (NMC). The second reference resistance value may be a resistance value for distinguishing between the breakdown state (e.g., the breakdown state (R_S3)(BD) of FIG. 3) and the non-breakdown state (e.g., the non-breakdown state is a state that is not a breakdown state and may include the parallel state (R_S2)(P) and the anti-parallel state (R_S1)(AP) of FIG. 3). That is, the first reference resistance value may be a resistance value that distinguishes between the parallel state (P) and the antiparallel state (AP) of the variable resistor element of the memory cell, and the second reference resistance value may be a resistance value that distinguishes between the breakdown state (BD) and the non-breakdown state of the variable resistor element. For example, the first reference resistance value may be an intermediate value between the resistance value of the parallel state (P) and the resistance value of the antiparallel state (AP) of the variable resistor element, and the second reference resistance value may be an intermediate value between the resistance value of the breakdown state (BD) and the resistance value of the parallel state (P) of the variable resistor element. However, it is not necessarily limited thereto.

[0033] The row decoder (120) can activate at least one of a plurality of word lines (WLs) based on a row address (ROW) provided from the address decoder (150), and memory cells and reference cells connected to the activated word line can be selected. For example, the row decoder (120) may activate one of the word lines (WLs) connected to a normal memory cell (NMC) in response to the row address (ROW), and may activate one of the word lines (WLs) connected to an OTP memory cell (OMC).

[0034] The column decoder (130) can be connected to the cell array (110) via a plurality of bit lines (BLs). The column decoder (130) can select a memory cell based on a column address (COL) provided by the address decoder (150). In an embodiment, the column decoder (130) can select a memory cell based on the column address (COL) and select a reference cell corresponding to the selected memory cell. For example, the column decoder (130) can select a normal memory cell (NMC) based on the column address (COL) and select a normal reference cell (NRC) corresponding to the normal memory cell (NMC). The column decoder (130) can select an OTP memory cell (OMC) based on the column address (COL) and select an OTP reference cell (ORC) corresponding to the OTP memory cell (OMC).

[0035] The readout circuit (140) can be connected to the column decoder (130) through output bit lines (BLOs). For example, the output bit lines (BLOs) include a first output bit line and a second output bit line, and the readout circuit (140) can determine a value stored in a memory cell based on a signal received through the first output bit line and the second output bit line, and can generate a data signal (D_OUT) containing the determined value. For example, the first output bit line can be connected to a memory cell and the second output bit line can be connected to a reference cell, but is not necessarily limited thereto.

[0036] The readout circuit (140) can provide a preset electrical signal to each of the memory cell and the reference cell, and can determine the value stored in the memory cell by detecting signals passing through the memory cell and the reference cell. During the readout operation of the normal memory cell (NMC), the readout circuit (140) can provide a preset electrical signal to each of the normal memory cell (NMC) and the normal reference cell (NRC), and can determine the value stored in the normal memory cell (NMC) by detecting signals passing through the normal memory cell (NMC) and the normal reference cell (NRC) through output bit lines (BLOs). During the readout operation of the normal memory cell (NMC), the readout circuit (140) can read out the data stored in the normal memory cell (NMC) based on the first reference resistance value. The readout circuit (140) can determine the value stored in the normal memory cell (NMC) using a signal generated based on the first reference resistance value through the normal reference cell (NRC) and the output bit line connected to the normal reference cell (NRC).

[0037] When the OTP memory cell (OMC) is read out, the read circuit (140) can provide a preset electrical signal to each of the OTP memory cell (OMC) and the OTP reference cell (ORC), and can determine the value stored in the OTP memory cell (OMC) by detecting signals passing through the OTP memory cell (OMC) and the OTP reference cell (ORC) through output bit lines (BLOs). When the OTP memory cell (OMC) is read out, the read circuit (140) can read out the data stored in the OTP memory cell (OMC) based on the second reference resistance value. The read circuit (140) can determine the value stored in the OTP memory cell (OMC) using a signal generated based on the second reference resistance value through the OTP reference cell (ORC) and the output bit line connected to the OTP reference cell (ORC).

[0038] In one embodiment, the read circuit (140) can read data stored in the OTP memory cell (OMC) based on a second reference resistance value after writing the OTP memory cell (OMC) to a semi-parallel state during the read operation of the OTP memory cell (OMC). For example, the second reference resistance value may be a resistance value for distinguishing between the breakdown state and the semi-parallel state of the OTP memory cell (OMC). During the read operation of the OTP memory cell (OMC), it is necessary to distinguish between the breakdown state and the non-breakdown state, and the non-breakdown state may include a parallel state and a semi-parallel state. The resistance value corresponding to the breakdown state may be lower than the resistance value of the parallel state, and the resistance value of the parallel state may be lower than the resistance value of the semi-parallel state.

[0039] The readout circuit (140) may include a readout driver (141) and a sensing amplifier (142). However, although not shown in FIG. 1, the readout circuit (140) may include other components other than the readout driver (141) and the sensing amplifier (142) as needed. The readout circuit (140) can provide an electrical signal of a preset size to the memory cell and the reference cell, and can determine the value stored in the memory cell by sensing the currents passing through the memory cell and the reference cell. Specifically, the readout driver (141) can provide an electrical signal of a preset size to the memory cell and the reference cell. The sensing amplifier (142) can sense the currents passing through the memory cell and the reference cell.

[0040] In one embodiment, the readout circuit (140) may provide a current of a preset size to the memory cell and the reference cell, respectively. The electrical signal may include a current, and the readout driver (141) may provide a current of a preset size to the memory cell and the reference cell. In an embodiment, the readout driver (141) may include a current generator that provides current to the memory cell and the reference cell. The sensing amplifier (142) may be a voltage sensing amplifier. The sensing amplifier (142) may determine the value stored in the memory cell by sensing the voltages applied to the memory cell and the reference cell.

[0041] In one embodiment, the read circuit (140) may provide a voltage of a preset size to the memory cell and the reference cell, respectively. The electrical signal may include a voltage, and the read driver (141) may provide a voltage of a preset size to the memory cell and the reference cell. In an embodiment, the read driver (141) may include a voltage generator that provides a voltage to the memory cell and the reference cell. The sensing amplifier (142) may be a current sensing amplifier. The sensing amplifier (142) may determine a value stored in the memory cell by sensing currents passing through the memory cell and the reference cell. Although not shown in FIG. 1, the memory device (10) may further include a write circuit for writing data to the memory cells.

[0042] Although not illustrated in FIG. 1, the memory device (10) may include a reference switching circuit (RSC) connected to a normal reference cell (NRC) and an OTP reference cell (ORC) through a target reference bit line. The reference switching circuit (RSC) may include a resistor element and a switch transistor. The reference switching circuit (RSC) may turn on or turn off a select stanzistor according to a control signal of the controller (170). For example, in the case of a read operation of a normal memory cell (NMC), the reference switching circuit (RSC) turns off the select stanzistor according to a first control signal of the controller (170), and the first reference signal may be generated based on the resistor element of the reference switching circuit (RSC). In the case of a read operation of the OTP reference cell (ORC), the reference switching circuit (RSC) turns on the select stanzistor according to the second control signal of the controller (170) (at this time, bypasses the resistor element of the reference switching circuit (RSC)), and the first reference signal can be generated based on the variable resistor element of the OTP reference cell (ORC).

[0043] The detection amplifier (142) can determine the value stored in the normal memory cell (NMC) by detecting the difference between the first readout voltage value applied from the normal memory cell (NMC) and the first reference signal applied from the normal reference cell (NRC) based on the first electrical signal during the readout operation of the normal memory cell (NMC). The detection amplifier (142) can determine the value stored in the OTP memory cell (OMC) by detecting the difference between the second readout voltage value applied from the OTP memory cell (OMC) and the second reference signal applied from the OTP reference cell (ORC) based on the second electrical signal during the readout operation of the OTP memory cell (OMC).

[0044] The address decoder (150) can generate a row address (ROW) and a column address (COL) based on an address (ADDR). The data buffer (160) can receive a data signal (D_OUT) from the readout circuit (140) and can store data corresponding to the data signal (D_OUT). The data buffer (160) can provide the stored data to the input / output circuit.

[0045] Although not illustrated in FIG. 1, the memory device (10) may further include an input / output circuit. The input / output circuit may provide a memory interface. For example, the input / output circuit may receive a command (CMD) and an address (ADDR) from the outside, and may receive data (DATA) from the outside or output it to the outside. The input / output circuit may provide the address (ADDR) to an address decoder (150) and may provide the command (CMD) and the address (ADDR) to a controller (170). The input / output circuit may provide the received data (DATA) to a data buffer (160) and may output a data signal (D_OUT) provided from the data buffer (160) to the outside as data (DATA).

[0046] The controller (170) can control the memory device (10) overall. The controller (170) can control the components of the memory device (10) based on a command (CMD). For example, the controller (170) can identify instructions for a write operation or a read operation based on a command (CMD) and can control the components so that the write operation or the read operation is performed.

[0047] In one embodiment, the controller (170) can control the components based on an address (ADDR). Since the normal memory cell (NMC) and the OTP memory cell (OMC) can be connected to different word lines, the read operation of the normal memory cell (NMC) and the read operation of the OTP memory cell (OMC) can be distinguished based on the address (ADDR). For example, the controller (170) can distinguish the read operation of the OTP memory cell (OMC) based on a row address (Row) and a command, and can control the components so that the read operation of the OTP memory cell (OMC) is performed. However, it is not necessarily limited thereto, and the read operation of the OTP memory cell (OMC) may also be distinguished based on a column address (COL).

[0048] To prevent I / O offset, the controller (170) has a plurality of first bit line connection cells (1 of FIG. 8) prior to the read operation. st You can control the BCCs to be all preset to a parallel state or all preset to an anti-parallel state.

[0049] To prevent word line offset, the controller (170) applies a high bias of a predetermined magnitude prior to the read operation to the second bit line connection cell (2 in FIG. 9). nd By applying to BCC), the second bit line connection cell can be controlled to be preset to a breakdown state.

[0050] FIG. 2a is a drawing showing an example of a memory cell according to an exemplary embodiment of the present disclosure. The structure of the normal memory cell (NMC), OTP memory cell (OMC), and OTP reference cell (ORC) of FIG. 2a can be applied to the normal memory cell (NMC), OTP memory cell (OMC), and OTP reference cell (ORC) of FIG. 1. Content that overlaps with the above description is omitted.

[0051] Referring to FIG. 2a, a normal memory cell (NMC), an OTP memory cell (OMC), and an OTP reference cell (ORC) may include a variable resistor element (MTJ) and a cell transistor (CT) connected in series between a bit line (BLj) and a source line (SLj). In the case of a normal memory cell (NMC), the variable resistor element (MTJ) may be a first variable resistor element and the cell transistor (CT) may be a first cell transistor. In the case of an OTP memory cell (OMC), the variable resistor element (MTJ) may be a second variable resistor element and the cell transistor (CT) may be a second cell transistor. In the case of an OTP reference cell (ORC), the variable resistor element (MTJ) may be a third variable resistor element and the cell transistor (CT) may be a third cell transistor. In FIG. 2a, it is shown that one variable resistor element (MTJ) and one cell transistor (CT) are included in the normal memory cell (NMC), the OTP memory cell (OMC), and the OTP reference cell (ORC), but this is merely an example, and the number of variable resistor elements (MTJ) and cell transistors (CT) included in the normal memory cell (NMC), the OTP memory cell (OMC), and the OTP reference cell (ORC) may vary.

[0052] In some embodiments, as shown in FIG. 2a, the bit line (BLj) and source line (SLj) may be connected in the order of a variable resistor element (MTJ) and a cell transistor (CT), and in some embodiments, unlike that shown in FIG. 2a, the bit line (BLj) and source line (SLj) may be connected in the order of a cell transistor (CT) and a variable resistor element (MTJ).

[0053] A variable resistor element (MTJ) may include a free layer (FL) and a pinned layer (PL), and may include a barrier layer (TBL) between the free layer (FL) and the pinned layer (PL). As indicated by the arrows in FIG. 2a, the magnetization direction of the pinned layer (PL) may be fixed, while the free layer (FL) may have a magnetization direction that is the same as or opposite to the magnetization direction of the pinned layer (PL). When the fixed layer (PL) and the free layer (FL) have magnetization directions in the same direction, the variable resistor element (MTJ) may be referred to as being in a parallel state (e.g., the parallel state (R_S2)(P) of FIG. 3), whereas when the fixed layer (PL) and the free layer (FL) have magnetization directions in opposite directions, the variable resistor element (MTJ) may be referred to as being in an anti-parallel state (e.g., the anti-parallel state (R_S1)(AP) of FIG. 3). In some embodiments, the variable resistor element (MTJ) may further include an anti-ferromagnetic layer so that the fixed layer (PL) has a fixed magnetization direction. In FIG. 2a, for convenience of explanation, the magnetization direction of the free layer (FL) and the fixed layer (PL) is shown as being horizontal, but is not limited thereto, and in the variable resistor element (MTJ) according to the embodiment of the present disclosure, the magnetization direction of the free layer (FL) and the fixed layer (PL) may be vertical.

[0054] In the case of a normal memory cell (NMC), the variable resistor element (MTJ) may have a relatively low resistance value (e.g., R_S2 in FIG. 3) in the parallel state (P), while having a relatively high resistance value (e.g., R_S1 in FIG. 3) in the antiparallel state (AP). In this specification, in the case of a normal memory cell (NMC), it is assumed that when the variable resistor element (MTJ) in the parallel state (P) has a low resistance value (R_S2), the memory cell (MC) stores "0", and when the variable resistor element (MTJ) in the antiparallel state (AP) has a high resistance value (R_S1), the memory cell (MC) stores "1".

[0055] The cell transistor (CT) may have a gate connected to the word line (WLi), a source line (SLj), and a source and drain connected to the variable resistor element (MTJ). The cell transistor (CT) may electrically connect or disconnect the variable resistor element (MTJ) and the source line (SLj) depending on a signal applied to the word line (WLi). For example, in a write operation, to write "0" to the normal memory cell (NMC), the cell transistor (CTj) may be turned on, and current flowing from the bit line (BLj) to the source line (SLj) may pass through the variable resistor element (MTJ) and the cell transistor (CTj). Also, to write "1" to the normal memory cell (NMC), the cell transistor (CTj) may be turned on, and current flowing from the source line (SLj) to the bit line (BLj) may pass through the cell transistor (CTj) and the variable resistor element (MTJ). In a read operation, the cell transistor (CTj) can be turned on, and the current flowing from the bit line (BLj) to the source line (SLj), or the current flowing from the source line (SLj) to the bit line (BLj), i.e., the read current, can pass through the cell transistor (CT) and the variable resistor element (MTJ).

[0056] In the case of an OTP memory cell (OMC), the variable resistor element (MTJ) may have a relatively low resistance value (e.g., R_S2 in FIG. 3) in the parallel state (P) and a relatively high resistance value (e.g., R_S1 in FIG. 3) in the antiparallel state (AP), while having a relatively lower resistance value (e.g., R_S3 in FIG. 3) in the breakdown state (e.g., breakdown state (BD) in FIG. 3). The cell transistor (CTj) may apply a breakdown current to the OTP memory cell (OMC) that is higher than the normal write current applied to the variable resistor element (MTJ). The breakdown current may damage or destroy the barrier layer (TBL) of the variable resistor element (MTJ). The lower resistance value (R_S3) in the breakdown state (BD) is lower than the low resistance value (R_S2) in the parallel state (P) and the high resistance value (R_S1) in the antiparallel state (AP). When the variable resistor element (MTJ) reaches the breakdown state (BD), it cannot be changed to another state.

[0057] In the following, it is assumed that in an OTP memory cell (OMC), when the variable resistor element (MTJ) in the breakdown state (BD) has a lower resistance value (R_S3), the memory cell (MC) stores "0", and when the variable resistor element (MTJ) in the parallel state (P) has a lower resistance value (R_S2) and when the variable resistor element (MTJ) in the antiparallel state (AP) has a higher resistance value (R_S1), the memory cell (MC) stores "1". In this case, the parallel state (P) and the antiparallel state (AP) may be referred to as non-breakdown states.

[0058] In the OTP memory cell (OMC), for example, to write "0" to the memory cell (MC), the cell transistor (CTj) can be turned on, and the breakdown current from the bit line (BLj) to the source line (SLj) can pass through the variable resistor element (MTJ) and the cell transistor (CTj).

[0059] FIG. 2b is a drawing showing an example of a reference cell according to an exemplary embodiment of the present disclosure.

[0060] The structure of the normal reference cell (NRC) of FIG. 2b can be applied to the normal reference cell (NRC) of FIG. 1. Content that overlaps with the above description is omitted. Compared to the cell structure of FIG. 2a, the variable resistor element (MTJ) in the normal reference cell (NRC) may be omitted, and the normal reference cell (NRC) may be referred to as a shorted cell. FIG. 2a will be referenced below.

[0061] A normal reference cell (NRC) may include a reference cell transistor (RT). The reference cell transistor (RT) may have a gate connected to a word line (WLi), and a source and drain connected to a source line (SLk) and a bit line (BLk). The reference cell transistor (RT) may electrically connect or disconnect the source line (SLk) and the bit line (BLj) depending on a signal applied to the word line (WLi).

[0062] A memory device (e.g., memory device (10) of FIG. 1) may include a resistor circuit (e.g., resistor element (RM) of the reference switching circuit (RSCa, RSCb) of FIG. 4a and 4b) outside of a cell array (e.g., cell array (110) of FIG. 1), and to determine a value stored in a normal memory cell (NMC), the resistance value of a variable resistor element (MTJ) may be compared with the resistance value of the resistor circuit (e.g., resistor value (RM) of FIG. 4a and 4b) due to a normal reference cell (NRC) which is a short-circuited cell. Hereinafter, the normal reference cell (NRC) is assumed to be a short-circuited cell such as the normal reference cell (NRC) of FIG. 2b, but is not necessarily limited thereto, and it will be understood that a reference cell including a variable resistor element (MTJ) is also possible.

[0063] FIG. 3 is a diagram showing the dispersion of resistance values ​​of a memory cell and a reference cell according to an exemplary embodiment of the present disclosure.

[0064] FIG. 3 shows the dispersion of resistance values ​​of a normal memory cell (NMC), an OTP memory cell (OMC), a normal reference cell (NRC), and an OTP memory cell (OMC) according to an embodiment of the present disclosure. In FIG. 3, the horizontal axis represents the resistance value (R) of a variable resistor element included in each cell, and the vertical axis represents the number (count) of variable resistor elements having the corresponding resistance value.

[0065] Referring to FIG. 3, a normal memory cell (NMC) may have resistance values ​​corresponding to a first state (R_S1) and a second state (R_S2). The first state (R_S1) may correspond to a state having a relatively high resistance value, such as the anti-parallel (AP) state of the normal memory cell (NMC) or the amorphous state of the phase change memory cell. The second state (R_S2) may correspond to a state having a relatively low resistance value, such as the parallel (P) state of the normal memory cell (NMC) or the chrystalline state of the phase change memory cell. The variable resistor element (MTJ) of the normal memory cell (NMC) can store data by being programmed to have one of the first state (R_S1) and the second state (R_S2). During a read operation, the normal memory cell (NMC) can provide a voltage or current corresponding to the resistance of the corresponding state among the first state (R_S1) and the second state (R_S2).

[0066] A normal reference cell (NRC) may have a reference state (R_NRC). The reference state (R_NRC) may have a resistance value between the resistance value of the first state (R_S1) and the resistance value of the second state (R_S2). The reference state (R_NRC) may provide a voltage or current that enables identification of the first state (R_S1) and the second state (R_S2) during a read operation.

[0067] The OTP memory cell (OMC) may have a resistance value corresponding to a third state (R_S3). For example, the third state (R_S3) can be achieved by breaking down (BD) a variable resistor element (MTJ). For example, the OTP memory cell (OMC) may include one effective variable resistor element (MTJ). Since one variable resistor element (MTJ) is connected to three OTP word lines, the variable resistor element (MTJ) can be easily broken down (BD) to have the third state (R_S3) using a lower voltage.

[0068] The OTP reference cell (ORC) may have a reference state (R_ORC). The reference state (R_ORC) may have a resistance value between the resistance value of the third state (R_S3) and the resistance value of the second state (R_S2). The reference state (R_ORC) may provide a voltage or current that enables identification of the third state (R_S3) and the second state (R_S2) during a read operation.

[0069] For example, each of the three valid variable resistor elements (MTJ) of the OTP reference cell (ORC) can be programmed to a second state (R_S2). Since the three valid variable resistor elements (MTJ) of the OTP reference cell (ORC) are connected in parallel between the reference source line (RSL) and the reference bit line (RBL), the total resistance value of the OTP reference cell (ORC) can correspond to one-third of the resistance value of the second state (R_S2). By programming each of the valid variable resistor elements (MTJ) of the OTP reference cell (ORC) to the second state (R_S2), the OTP reference cell (ORC) can be easily achieved.

[0070] For example, the OTP reference cell (ORC) can be modified to have two valid variable resistor elements (MTJ). In this case, if the valid variable resistor elements (MTJ) of the OTP reference cell (ORC) are programmed to a second state (R_S2), the total resistance value of the OTP reference cell (ORC) may be half of that of the second state (R_S2).

[0071] FIG. 4a is a drawing for illustrating a cell array according to an exemplary embodiment of the present disclosure.

[0072] Referring to FIG. 4a, the cell array (110a) may include a normal memory cell (NMC), an OTP memory cell (OMC), a normal reference cell (NRC), an OTP reference cell (ORC), and a switching circuit (RSCa). In this case, the normal cell region (NCA) may include a normal memory region containing a plurality of normal memory cells (NMC) and a normal reference region containing a plurality of normal reference cells (NRC). The OTP cell region (OCA) may include an OTP memory region containing a plurality of OTP memory cells (OMC) and an OTP reference region containing a plurality of OTP reference cells (ORC). The cell array (110a) of FIG. 4a may correspond to the cell array (110) of FIG. 1. The reference switching circuit (RSCa) of FIG. 4a can be used in cases where either the normal reference cell (NRC) or the OTP reference cell (ORC) generates a reference signal based on a fixed resistor element, and the other generates a reference signal based on a combination of multiple cells. The method of generating the reference signal can be determined according to the read margin. For example, when the read margin is relatively large (e.g., in the case of a read operation of a normal memory cell (NMC)), a reference signal can be generated based on a fixed resistor element, and when the read margin is relatively small (e.g., in the case of a read operation of an OTP memory cell (OMC)), a reference signal can be generated based on a combination of multiple cells. However, the embodiments of the present disclosure are not limited thereto. Content that overlaps with the above description is omitted.

[0073] A normal memory cell (NMC) may include a first variable resistor element (MTJ1) and a first cell transistor (CT1). The gate of the first cell transistor (CT1) is connected to a word line (WL), the drain is connected to one end of the first variable resistor element (MTJ1), and the source is connected to a source line (SL). The other end of the first variable resistor element (MTJ1) is connected to a bit line (BL).

[0074] The OTP memory cell (OMC) may have a structure different from that of the normal memory cell (NMC). In one embodiment, the number of second cell transistors (CT2) included in the OTP memory cell (OMC) may be greater than the number of first cell transistors (CT1) included in the normal memory cell (NMC). The normal memory cell (NMC) may include one first variable resistor element (MTJ1) and two first cell transistors (CT1). A 2T-1R structure in which one normal memory cell (NMC) is connected to two first cell transistors (CT1) may constitute one unit normal memory cell (NMC) in the cell array (110a).

[0075] The OTP memory cell (OMC) may include a second variable resistor element (MTJ2) and a second cell transistor (CT2). The gate of the second cell transistor (CT2) is connected to the word line (WL), the drain is connected to one end of the second variable resistor element (MTJ2), and the source is connected to the source line (SL). The other end of the second variable resistor element (MTJ2) is connected to the bit line (BL).

[0076] An OTP memory cell (OMC) may include one second variable resistor element (MTJ2) and six second cell transistors (CT2). The second cell transistors (CT2) may be connected in parallel to the second variable resistor element (MTJ2). The second cell transistors (CT2) may apply a higher breakdown current to the OTP memory cell (OMC). A 6T-1R structure in which one OTP memory cell (OMC) is connected to six second cell transistors (CT2) may constitute a single unit OTP memory cell (OMC) in the cell array (110a). The 6T-1R structure may facilitate changing the second variable resistor element (MTJ2) to a breakdown state by applying a higher voltage value to the second variable resistor element (MTJ2) relative to the cell transistors (CT2). However, this is merely an example and is not necessarily limited thereto.

[0077] In some embodiments, the OTP memory cell (OMC) may have the same structure as the normal memory cell (NMC). For example, a 1T-1R structure in which one normal memory cell (NMC) is connected to one first cell transistor (CT1) may form one unit normal memory cell (NMC) in the cell array (110a), and a 1T-1R structure in which one OTP memory cell (OMC) is connected to one second cell transistor (CT2) may form one unit OTP memory cell (OMC) in the cell array (110a). However, this is not necessarily limited thereto, and the normal memory cell (NMC) and the OTP memory cell (OMC) may be various, such as a 2T-2R structure in which two adjacent memory cells (NMC, OMC) are commonly connected to two cell transistors (CT).

[0078] The cell array (110b) may include dummy cells (DC), and the dummy cells (DC) may not be connected to the corresponding second cell transistor (CT2) and word lines, and may not be connected to the corresponding bit line (BL) and source line (SL).

[0079] The normal reference cell (NRC) may include a third cell transistor (CT3) with the variable resistor element (MTJ) omitted, as shown in FIG. 2b. The gate of the third cell transistor (CT3) is connected to the word line (WL), the drain is connected to the reference bit line (RBL), and the source is connected to the reference source line (RSL).

[0080] The OTP reference cell (ORC) may include a third variable resistor element (MTJ3) and a fourth cell transistor (CT4). The gate of the fourth cell transistor (CT4) is connected to the word line (WL), the drain is connected to one end of the third variable resistor element (MTJ3), and the source is connected to the reference source line (RSL). The other end of the fourth variable resistor element (MTJ2) is connected to the reference bit line (RBL).

[0081] The reference switching circuit (RSCa) may include a resistor element (RM) and a switch transistor (ST). The resistor element (RM) and the switch transistor (ST) are connected in parallel and connected to the reference bit line (RBL). The switch transistor (ST) is turned on or turned off according to a control signal from the controller (170). The controller (170) may generate different control signals depending on whether it is a read operation of a normal memory cell (NMC) or a read operation of an OTP memory cell (OMC). That is, the controller (170) may generate different control signals depending on the type of memory cell. When a read operation of a normal memory cell (NMC) occurs, the switch transistor (ST) may be turned off according to a first control signal from the controller (170). At this time, the resistance value of the resistor element (RM) (for example, the resistance value (NRR) of the resistor element (RM) in FIG. 5) may correspond to the resistance value of the normal reference cell (NRC). When the OTP reference cell (ORC) is read out, the switch transistor (ST) can be turned on according to the second control signal of the controller (170). At this time, the resistor element (RM) is bypassed, and a resistor value generated by connecting / combining multiple OTP reference cells (ORCs) (e.g., variable resistor elements of multiple OTP reference cells (ORCs)) (see FIG. 3) (e.g., the resistor value (ORR) of the resistor element (RO) in FIG. 5) can correspond to the resistor value of the OTP reference cell (ORC).

[0082] FIG. 4b is a drawing for illustrating a cell array according to an exemplary embodiment of the present disclosure.

[0083] Referring to FIG. 4b, the cell array (110b) may include a normal reference cell (NRC), an OTP reference cell (ORC), and a switching circuit (RSCb). Compared to FIG. 4a, the structure of the switching circuit (RSCb) and the structure of the OTP reference cell (ORC) may differ as the method of generating the OTP reference resistance value in FIG. 4b is changed. The cell array (110b) of FIG. 4b may correspond to the cell array (110) of FIG. 1. The reference switching circuit (RSCb) of FIG. 4b may be used when both the normal reference cell (NRC) and the OTP reference cell (ORC) generate a reference signal based on a fixed resistance element. Details that overlap with the above description are omitted.

[0084] Compared to FIG. 4a, the method of generating the OTP reference resistance value in FIG. 4b may differ. The method of generating the OTP reference resistance value in FIG. 4a is a method of generating a reference resistance value by connecting / combining multiple OTP reference cells (ORCs) (e.g., variable resistance elements of multiple OTP reference cells (ORCs)). On the other hand, the method of generating the OTP reference resistance value in FIG. 4b is a method of generating a reference resistance value based on a fixed resistance value of a resistance element (RO) (e.g., resistance value (ORR)). The method of generating the normal reference resistance value is a method of generating a reference resistance value based on a fixed resistance value of a resistance element (RM) (e.g., resistance value (NRR)), and is the same in FIG. 4a and FIG. 4b.

[0085] As the method of generating the OTP reference resistance value differs, the structure of the OTP reference cell (ORC) in FIG. 4a and the structure of the OTP reference cell (ORC) in FIG. 4b may differ. For example, the structure of the OTP reference cell (ORC) in FIG. 4a may have the structure illustrated in FIG. 2a, and the structure of the OTP reference cell (ORC) in FIG. 4b may have the structure illustrated in FIG. 2b. The descriptions of the normal memory cell (NMC), OTP memory cell (OMC), and normal reference cell (NRC) are omitted as they overlap with the description of FIG. 4a.

[0086] The normal reference cell (NRC) may include a third cell transistor (CT3) with the variable resistor element (MTJ) omitted, as shown in FIG. 2b. The gate of the third cell transistor (CT3) is connected to the word line (WL), the drain is connected to the reference bit line (RBL), and the source is connected to the reference source line (RSL).

[0087] As shown in FIG. 2b, the OTP reference cell (ORC) may omit the variable resistor element (MTJ) and include a fourth cell transistor (CT4). The gate of the fourth cell transistor (CT4) is connected to the word line (WL), the drain is connected to the reference bit line (RBL), and the source is connected to the reference source line (RSL).

[0088] As the method of generating the OTP reference resistance value is different, the switching circuit (RSCb) of FIG. 4b may have a different structure from the switching circuit (RSCa) of FIG. 4a. Unlike the switching circuit (RSCa) of FIG. 4a, the switching circuit (RSCb) may include a resistor element (RM), a resistor element (RO), and a switch (SW). The switch element (SW) may be connected to either the resistor element (RM) or the resistor element (RO) according to a control signal from the controller (170). The controller (170) may generate different control signals depending on whether it recognizes a read operation of a normal memory cell (NMC) or a read operation of an OTP memory cell (OMC). That is, the controller (170) may generate different control signals depending on the type of memory cell. When a read operation of a normal memory cell (NMC) occurs, the switch element (SW) may be connected to the resistor element (RM) according to a first control signal from the controller (170). At this time, the resistance value of the resistor element (RM) (e.g., the resistance value (NRR) of the resistor element (RM) in FIG. 5) may correspond to the resistance value of the normal reference cell (NRC). When the OTP reference cell (ORC) is read out, the switch element (SW) may be connected to the resistor element (RO) according to the second control signal of the controller (170). At this time, the resistance value of the resistor element (RO) (e.g., the resistance value (ORR) of the resistor element (RO) in FIG. 5) may correspond to the resistance value of the OTP reference cell (ORC).

[0089] Referring to FIGS. 4a and 4b, a normal reference cell (NRC) and an OTP reference cell (ORC) according to an embodiment of the present disclosure may share a reference bit line (RBL) based on reference switching circuits (RSCa, RSCb). In the present disclosure, the reference bit line (RBL) shared by the normal reference cell (NRC) and the OTP reference cell (ORC) may be referred to as a target reference bit line.

[0090] According to an embodiment of the present disclosure, the normal reference cell (NRC) and the OTP reference cell (ORC) share a reference bit line (RBL), thereby preventing an increase in the core area of ​​the memory device (10) by not adding a separate bit line for the OTP reference cell (ORC). In addition, the read margin of the memory device (10) can be improved by preventing the deterioration of word line offset characteristics that occurs when a reference bit line for the OTP reference cell (ORC) is separately arranged.

[0091] FIG. 5 is a diagram showing the structure of a memory device during a read operation according to an exemplary embodiment of the present disclosure.

[0092] Specifically, FIG. 5 is an equivalent circuit diagram schematically showing the structure of a memory device (10a) during a read operation of a normal memory cell (NMC) and an OTP memory cell (OMC), and the memory device (10a) of FIG. 5 may correspond to the memory device (10) of FIG. 1. Content that overlaps with the above description is omitted.

[0093] Referring to FIG. 5, the memory device (10a) may include a sensing amplifier (142a), a normal memory cell (NMC), an OTP memory cell (OMC), a normal reference cell (NRC), a normal memory cell (NMC), and a reference switching circuit (RSC). The sensing amplifier (142a) may be included in the readout circuit (140) of FIG. 1. FIG. 5 is described assuming that the sensing amplifier (142a) is a voltage sensing amplifier. Additionally, FIG. 5 is described assuming that the normal reference cell (NRC) is a short-circuited cell, but is not limited thereto.

[0094] The memory device (10a) may include a reference switching circuit (RSC) connected to a normal reference cell (NRC) and an OTP reference cell (ORC) outside the cell array. The reference switching circuit (RSC) may include a resistor element (RM) and a switch transistor (ST). The normal reference cell (NRC) and the OTP reference cell (ORC) may be connected to the reference switching circuit (RSC) through a shared reference bit line (i.e., a target reference bit line (TRBL)). The reference switching circuit (RSC) may connect the normal reference cell (NRC) and the resistor element (RM) by turning off the switch transistor (ST) according to a control signal from the controller (170). The reference switching circuit (RSC) can turn on the switch transistor (ST) according to a control signal to bypass the resistor element (RM) and connect the OTP reference cell (ORC) and the switch transistor (ST). The normal reference cell (NRC) and the OTP reference cell (ORC) can transmit the generated reference signal to the sensing amplifier (142a) through a reference bit line (i.e., target reference bit line (TRBL)) that shares the reference signal. If the sensing amplifier (142a) is a voltage sensing amplifier, the reference signal can represent a reference voltage value corresponding to the reference resistor value of each of the normal reference cell (NRC) and the OTP reference cell (ORC).

[0095] The normal reference cell (NRC) and the normal memory cell (NMC) may be included in the normal cell region (NCA) of the cell array of the memory device (10a) and may be connected to the same word line (WL1). FIG. 5 describes the normal reference cell (NRC) and the normal memory cell (NMC) as being connected to the word line (WL1). The normal memory cell (NMC) may include a first cell transistor (CT1) and a first variable resistor element (MTJ1). The normal reference cell (NRC) may be a short-circuited cell and may include a third cell transistor (i.e., a reference cell transistor) (CT3).

[0096] The memory device (10a) may include a reference switching circuit (RSC) connected to a normal reference cell (NRC) outside the cell array. The normal reference cell (NRC) may have a first reference resistance value (NRR). That the normal reference cell (NRC) has a first reference resistance value (NRR) may mean that the reference switching circuit (RSC) connected to the normal reference cell (NRC) (in other words, the resistor element (RM) of the reference switching circuit (RSC)) has a first reference resistance value (NRR). For example, the first reference resistance value (NRR) may be a resistance value for distinguishing between the parallel state and the antiparallel state of the normal memory cell (NMC). Data stored in the normal memory cell (NMC) may be read out based on the first reference resistance value (NRR).

[0097] When a normal memory cell (NMC) is read out, the read-out circuit (140) of FIG. 1 can provide a preset electrical signal to each of the normal memory cell (NMC) and the normal reference cell (NRC) using a current generator. The current generator can provide a first current (IR1) to the normal memory cell (NMC) and a first reference current (IREF1) to the normal reference cell (NRC). At this time, the first current (IREF1) provided to the normal reference cell (NRC) can flow from a positive supply voltage (VDD) through the resistor element (RM) of the normal reference cell (NRC) and the reference switching circuit (RSC) to a negative supply voltage (VSS), and the first current (IR1) provided to the normal memory cell (NMC) can flow from a positive supply voltage (VDD) through the normal memory cell (NMC) to a negative supply voltage (VSS).

[0098] The sensing amplifier (142a) can determine the value stored in the normal memory cell (NMC) by detecting the difference between a first input signal (e.g., a readout voltage value applied from the normal memory cell (NMC)) applied from the normal memory cell (NMC) based on a first current during a readout operation of the normal memory cell (NMC) and a first reference signal (e.g., a reference voltage value applied from the normal reference cell (NRC)) applied from the normal reference cell (NRC). The sensing amplifier (142a) can detect the difference between a first input signal, which is the voltage of the normal memory cell (NMC) based on the first current (IR1), and a first reference signal, which is the voltage of the normal reference cell based on the first reference current (IREF1). The sensing amplifier (142a) can receive a first reference signal, which is the voltage of a normal reference cell, through a reference bit line (RBL) (i.e., a target reference bit line (TRBL)).

[0099] The sensing amplifier (142a) can generate a comparison signal (i.e., the difference between the readout voltage value applied from the normal memory cell (NMC) and the reference voltage value applied from the normal reference cell (NRC)) by comparing a first reference signal by the resistor element (RM) of the normal reference cell (NRC) and the first input signal by the normal memory cell (NMC). The comparison signal can represent a value stored in the normal memory cell (NMC). The memory device (10a) can generate a data signal (V_OUT) representing a value stored in the normal memory cell (NMC) based on the comparison signal.

[0100] The OTP memory cell (OMC) and the OTP reference cell (ORC) may be included in the OTP cell region (OCA) of the cell array of the memory device (10a) and may be connected to the same word line (WLn). The sensing amplifier (142a) may be connected to the OTP memory cell (OMC) and the OTP reference cell (ORC). FIG. 5 describes the OTP reference cell (ORC) and the OTP memory cell (OMC) assuming they are connected to the word line (WLn). The OTP memory cell (OMC) may include a second cell transistor (CT2) and a second variable resistor element (MTJ2). The OTP reference cell (ORC) may include a variable resistor element (RO) and a fourth cell transistor (CT4). Here, the variable resistor element (RO) may be a resistor element created by combining / connecting the variable resistor elements (MTJ) of a plurality of OTP reference cells (ORC). The OTP reference cell (ORC) may have a second reference resistance value (ORR). That the OTP reference cell (ORC) has a second reference resistance value (ORR) may mean that the variable resistor element (RO) of the OTP reference cell (ORC) has the second reference resistance value (ORR). For example, since the three valid variable resistor elements (MTJ) of the OTP reference cell (ORC) are combined / connected in parallel between the reference source line (RSL) and the reference bit line (RBL), the resistance value of the variable resistor element (RO) may correspond to 1 / 3 of the resistance value of the parallel state (P) (here, it is assumed that each of the three valid variable resistor elements (MTJ) is programmed to the parallel state (P)). At this time, the second reference resistance value (ORR) of the OTP reference cell (ORC) may be 1 / 3 of the resistance value of the parallel state (P) corresponding to the resistance value of the variable resistance element (RO).

[0101] For example, the second reference resistance value (ORR) may be a resistance value for distinguishing between the breakdown state and the parallel state (P) of the OTP memory cell (OMC). However, it is not limited thereto, and the second reference resistance value (ORR) may be a resistance value for distinguishing between the breakdown state and the antiparallel state (AP) of the OTP memory cell (OMC). Data stored in the OTP memory cell (OMC) can be read out based on the second reference resistance value (ORR).

[0102] When the OTP memory cell (OMC) is read out, the read-out circuit (140) of FIG. 1 can use a current generator to provide a second current (IR2) to the OTP memory cell (OMC) and a second reference current (IREF2) to the OTP reference cell (ORC). As shown in FIG. 5, the second current (IREF2) provided to the OTP reference cell (ORC) can flow from a positive supply voltage (VDD) through the switch transistor (ST) of the OTP reference cell (ORC) and the reference switching circuit (RSC) (i.e., the resistor element (RM) of the reference switching circuit (RSC) is bypassed) to a negative supply voltage (VSS). Additionally, the second current (IR2) can flow from a positive supply voltage (VDD) through the OTP memory cell (OMC) to a negative supply voltage (VSS).

[0103] The detection amplifier (142a) can determine the value stored in the OTP memory cell (OMC) by detecting the difference between the second input signal applied from the OTP memory cell (OMC) based on the second current (IR2) during the read operation of the OTP memory cell (OMC) (e.g., the read voltage value applied from the OTP memory cell (OMC)) and the second reference signal applied from the OTP reference cell (ORC) based on the second reference current (IREF2) (e.g., the reference voltage value applied from the OTP reference cell (ORC)). The detection amplifier (142a) can generate a comparison signal (i.e., the difference between the readout voltage value applied from the OTP memory cell (OMC) and the reference voltage value applied from the OTP reference cell (ORC)) by comparing a second reference signal, which is a voltage from the OTP reference cell (ORC), and a second input signal, which is a voltage from the OTP memory cell (OMC). The comparison signal can represent a value stored in the OTP memory cell (OMC). The memory device (10a) can generate a data signal (V_OUT) representing a value stored in the OTP memory cell (OMC) based on the comparison signal.

[0104] FIGS. 6 to 9 described below illustrate a wiring structure for a normal reference cell (NRC) and an OTP reference cell (ORC) to share a target reference bit line (TRBL) based on a reference switching circuit (RSC) according to an embodiment of the present disclosure.

[0105] FIG. 6 is a diagram showing a wiring structure associated with a reference cell and a reference bit line of a memory device according to an exemplary embodiment of the present disclosure.

[0106] In FIG. 6, it is assumed that the reference resistance value of the normal reference cell (NRC) is generated based on a fixed resistance value, and the reference resistance value of the OTP reference cell (ORC) is generated based on the connection / combination of multiple OTP reference cells (ORCs) (e.g., variable resistance elements of multiple OTP reference cells (ORCs). Content that overlaps with the above is omitted.

[0107] Referring to FIG. 6, the bit line and source line of the memory device can be extended in a second direction. The reference bit line (D3) can be extended in a second direction by being connected to a reference switching circuit (RSC). At this time, the reference bit line (D3) can correspond to the target reference bit line (TRBL) as it is shared by the normal reference cell (NRC) and the OTP reference cell (ORC). The bit line (D2) and source line (M1) can be extended in a second direction. However, this is not limited thereto, and depending on the embodiment, the bit line (D2) may be omitted.

[0108] In the normal cell region (NCA), vias (e.g., S1, S2, MD, V2, V1, V0 in FIG. 6) can connect bit lines to bit lines (e.g., D2, D3 in FIG. 6), connect bit lines / source lines (e.g., M1 in FIG. 6) to metal (e.g., D1, M2, M3 in FIG. 6), or connect metal to metal. In particular, as a plurality of cell vias (S1) are formed below the reference bit line (D3) in the normal cell region (NCA) (e.g., a plurality of cell vias (S1) are formed in the cell via region (CVA) of FIG. 6), the first reference current (IREF1) can generate a first reference signal without passing through the normal reference cell (NRC). That is, the first reference signal can be generated based on the fixed resistance value (NRR) of the resistor element (RM) using the cell via (S1). For example, the reference bit line (D3) and the bit line (D2) can be connected by the via (S2), the bit line (D2) and the metal (D1) can be connected by the cell via (S1), the metal (D1) and the metal (M3) can be connected by the via (MD), and the source line (M1) and the contact (CA) can be connected by the via (V0).

[0109] In the OTP cell area (OCA), vias (e.g., S1, S2, MD, V2, V1, V0 in FIG. 6) can connect bit lines to bit lines (e.g., D2, D3 in FIG. 6), connect a bit line / source line (e.g., M1 in FIG. 6) to metal, or connect metal to metal (e.g., D1, M2, M3 in FIG. 6). Content that overlaps with the above description is omitted. In the OTP cell area (OCA), the OTP reference cell (ORC) and metal can be connected by a contact (BEC).

[0110] When the normal memory cell (NMC) is read out (as the switch transistor (ST) is turned off by a control signal), the first current (IREF1) provided by the readout circuit (140) of FIG. 1 can pass through the normal reference cell (NRC) and the resistor element (RM) to generate a first reference signal. Here, the resistance value (NRR) of the resistor element (RM) can correspond to the reference resistance value of the normal reference cell (NRC). The sensing amplifier (142) can determine the value stored in the normal memory cell (NMC) by detecting the difference between the first input signal applied from the normal memory cell (NMC) and the first reference signal applied from the normal reference cell (NRC). The sensing amplifier (142) can generate a comparison signal by comparing the first reference signal from the normal reference cell (NRC) and the resistor element (RM) with the first input signal from the normal memory cell (NMC). The comparison signal can represent a value stored in a normal memory cell (NMC). The memory device (10) can generate a data signal representing a value stored in a normal memory cell (NMC) from the comparison signal.

[0111] When the OTP reference cell (ORC) is read out, the second current (IREF2) provided by the read-out circuit (140) bypasses the resistor element (RM) and passes through the OTP reference cell (ORC) to generate a second reference signal. At this time, the resistance value of the variable resistor element of the OTP reference cell (ORC) may be a resistance value generated by connecting / combining multiple OTP reference cells (ORCs) (e.g., variable resistor elements of multiple OTP reference cells (ORCs)) (see FIG. 3). The detection amplifier (142) can determine the value stored in the OTP memory cell (OMC) by detecting the difference between the second input signal applied from the OTP memory cell (OMC) and the second reference signal applied from the OTP reference cell (ORC). The detection amplifier (142) can generate a comparison signal by comparing a second reference signal obtained by the connection / combination of a plurality of OTP reference cells (ORCs) and a second input signal obtained by an OTP memory cell (OMC). The comparison signal can represent a value stored in the OTP memory cell (OMC). The memory device (10) can generate a data signal representing a value stored in the OTP memory cell (OMC) from the comparison signal.

[0112] In the wiring structure of the normal cell region (NCA) according to an embodiment of the present disclosure, as a plurality of cell vias (S1) are formed below the target reference bit line (TRBL) (i.e., reference bit line (D3)), the first reference current (IREF1) can generate a first reference signal by passing through a resistor element (RM) without passing through the normal reference cell (NRC). That is, the normal reference cell (NRC) can generate a first reference signal based on a fixed resistor element (e.g., resistor element (RM)) through the plurality of cell vias (S1). To this end, the variable resistor element (MTJ) of the normal reference cell (NRC) is omitted, and the normal reference cell (NRC) can be implemented as a shorted cell (see FIG. 2b). As OTP reference cells (ORCs) are positioned below the target reference bit line (TRBL) (i.e., reference bit line (D3)) in the wiring structure of the OTP cell area (OCA), the second reference current (IREF1) can pass through the switch transistor (ST) (bypassing the resistor element (RM)) and the OTP reference cell to generate a second reference signal. That is, the memory device can generate a reference signal in different ways depending on whether it is a read operation of a normal memory cell (NMC) or a read operation of an OTP memory cell (OMC).

[0113] A memory device according to an embodiment of the present disclosure can design a normal memory cell (NMC) and an OTP memory cell (OMC) as a single IP (or a single memory chip) by sharing a target reference bit line (TRBL) between a normal reference cell (NRC) and an OTP reference cell (ORC). Additionally, the memory device can maximize the read margin of each memory cell by varying the method of generating a reference signal (e.g., a method based on a fixed resistance value / a hybrid method based on the connection / combination of multiple reference cells) according to the type of memory cell (e.g., normal memory cell (NMC) / OTP memory cell (OMC)) through cell vias (S1) connected to the target reference bit line (TRBL).

[0114] FIG. 7 is a diagram showing a wiring structure associated with a reference cell and a reference bit line of a memory device according to an exemplary embodiment of the present disclosure.

[0115] In FIG. 7, it is assumed that the reference resistance value of the normal reference cell (NRC) is generated based on a fixed resistance value, and the reference resistance value of the OTP reference cell (ORC) is generated based on the connection / combination of multiple OTP reference cells (ORCs) (e.g., variable resistance elements of multiple OTP reference cells (ORCs). Content that overlaps with the above is omitted.

[0116] Referring to FIG. 7, the bit line and source line of the memory device can be extended in a second direction. The reference bit line (D3_ref) can be connected to the reference switching circuit (RSC) and extended in a second direction to the connection area (CA). At this time, the reference bit line (D3_ref) can constitute a part of the target reference bit line (TRBL) shared by the normal reference cell (NRC) and the OTP reference cell (ORC) (e.g., the first reference bit line of the target reference bit line (TRBL).

[0117] In the normal cell region (NCA), vias (e.g., S2, MD, V2, V1, V0 in FIG. 7) can connect bit lines to bit lines (e.g., D2, D3 in FIG. 7), connect bit line / source line (e.g., M1 in FIG. 7) to metal (e.g., D1, M2, M3 in FIG. 7), or connect metal to metal. For example, a reference bit line (D1) and metal (M3) can be connected by a via (MD), and a source line (M1) and a contact (CA) can be connected by a via (V0).

[0118] In the OTP cell area (OCA), vias (e.g., S2, MD, V2, V1, V0 in FIG. 7) can connect bit lines to bit lines (e.g., D2, D3_ref in FIG. 7), connect bit line / source lines (e.g., M1 in FIG. 7) to metal, or connect metal to metal (e.g., D1, M2, M3 in FIG. 7). Content that overlaps with the above description is omitted. In the OTP cell area (OCA), the OTP reference cell (ORC) and metal can be connected by a contact (BEC).

[0119] The connection area (CA) may represent the area between the normal reference cell and the OTP reference cell (i.e., the area between the normal reference area (NRA) and the OTP reference area (ORA). As a cell via (S1) is formed below the bit line (D2) in the connection area (CA), the reference bit line (D3_ref) and the reference bit line (D1) can be connected through the cell via (S1). At this time, the reference bit line (D3_ref) and the reference bit line (D1) may be placed in different layers. The reference bit line (D1) may constitute a part of the target reference bit line (TRBL) shared by the normal reference cell (NRC) and the OTP reference cell (ORC) (e.g., the second reference bit line of the target reference bit line (TRBL). A reference bit line (D3_ref) and a reference bit line (D1) can be connected through a cell via (S1) to form a target reference bit line (TRBL). A first reference current (IREF1) can generate a first reference signal without passing through a normal reference cell (NRC) based on the target reference bit line (TRBL) configured based on the cell via (S1). That is, the first reference signal can be generated based on a fixed resistance value (NRR) of a resistor element (RM) using the cell via (S1). Although a single cell via (S1) is shown in FIG. 7 for convenience of explanation, it is not limited thereto, and the cell via (S1) according to an embodiment of the present disclosure can be formed in various numbers depending on the embodiment.

[0120] When the normal memory cell (NMC) is read out (as the switch transistor (ST) is turned off by a control signal), the first current (IREF1) provided by the readout circuit (140) of FIG. 1 can pass through the normal reference cell (NRC) and the resistor element (RM) to generate a first reference signal. Here, the resistance value (NRR) of the resistor element (RM) can correspond to the reference resistance value of the normal reference cell (NRC). The sensing amplifier (142) can determine the value stored in the normal memory cell (NMC) by detecting the difference between the first input signal applied from the normal memory cell (NMC) and the first reference signal applied from the normal reference cell (NRC). The sensing amplifier (142) can generate a comparison signal by comparing the first reference signal from the normal reference cell (NRC) and the resistor element (RM) with the first input signal from the normal memory cell (NMC). The comparison signal can represent a value stored in a normal memory cell (NMC). The memory device (10) can generate a data signal representing a value stored in a normal memory cell (NMC) from the comparison signal.

[0121] When the OTP reference cell (ORC) is read out, the second current (IREF2) provided by the read-out circuit (140) bypasses the resistor element (RM) and passes through the OTP reference cell (ORC) to generate a second reference signal. At this time, the resistance value of the variable resistor element of the OTP reference cell (ORC) may be a resistance value generated by connecting / combining multiple OTP reference cells (ORCs) (e.g., variable resistor elements of multiple OTP reference cells (ORCs)) (see FIG. 3). The detection amplifier (142) can determine the value stored in the OTP memory cell (OMC) by detecting the difference between the second input signal applied from the OTP memory cell (OMC) and the second reference signal applied from the OTP reference cell (ORC). The detection amplifier (142) can generate a comparison signal by comparing a second reference signal obtained by the connection / combination of a plurality of OTP reference cells (ORCs) and a second input signal obtained by an OTP memory cell (OMC). The comparison signal can represent a value stored in the OTP memory cell (OMC). The memory device (10) can generate a data signal representing a value stored in the OTP memory cell (OMC) from the comparison signal.

[0122] In the wiring structure of the connection area (CA) according to an embodiment of the present disclosure, a cell via (S1) is formed below the bit line (D2), so that the reference bit line (D3_ref) and the reference bit line (D1) are connected through the cell via (S1) to form a target reference bit line (TRBL). The first reference current (IREF1) can generate a first reference signal by passing through the resistor element (RM) without passing through the normal reference cell (NRC) using the cell via (S1). In the wiring structure of the OTP cell area (OCA), OTP reference cells (ORC) are arranged below the reference bit line (D3_ref), so that the second reference current (IREF1) can generate a second reference signal by passing through the switch transistor (ST) (bypassing the resistor element (RM)) and passing through the OTP reference cell. That is, the memory device can generate a reference signal in different ways depending on whether it is a read operation of a normal memory cell (NMC) or an OTP memory cell (OMC).

[0123] A memory device according to an embodiment of the present disclosure can configure a target reference bit line (TRBL) through a cell via (S1) in a connection area and share the target reference bit line (TRBL) between a normal reference cell (NRC) and an OTP reference cell (ORC), thereby enabling the normal memory cell (NMC) and the OTP memory cell (OMC) to be designed as a single IP (or a single memory chip). Additionally, the memory device can maximize the read margin of each memory cell by varying the method of generating a reference signal (e.g., a method based on a fixed resistance value / a hybrid method based on the connection / combination of multiple reference cells) according to the type of memory cell (e.g., normal memory cell (NMC) / OTP memory cell (OMC)) through the cell via (S1) connected to the target reference bit line (TRBL).

[0124] FIG. 8 is a diagram showing a wiring structure associated with a reference cell and a reference bit line of a memory device according to an exemplary embodiment of the present disclosure.

[0125] In FIG. 8, it is assumed that the reference resistance value of the normal reference cell (NRC) is generated based on a fixed resistance value, and the reference resistance value of the OTP reference cell (ORC) is generated based on the connection / combination of multiple OTP reference cells (ORCs) (e.g., variable resistance elements of multiple OTP reference cells (ORCs). Content that overlaps with the above is omitted.

[0126] Referring to FIG. 8, the bit line and source line of the memory device can be extended in a second direction. The reference bit line (D3_ref) can be connected to a reference switching circuit (RSC) and extended in a second direction to a connection area (CA). At this time, the reference bit line (D3_ref) can constitute a part of the target reference bit line (TRBL) shared by the normal reference cell (NRC) and the OTP reference cell (ORC) (e.g., the first reference bit line of the target reference bit line (TRBL).

[0127] In the normal cell region (NCA), vias (e.g., S2, MD, V2, V1, V0 in FIG. 8) can connect bit lines to bit lines (e.g., D2, D3 in FIG. 8), connect bit lines / source lines (e.g., M1 in FIG. 8) to metal (e.g., D1, M2, M3 in FIG. 8), or connect metal to metal. For example, a reference bit line (D1) and metal (M3) can be connected by a via (MD), and a source line (M1) and a contact (CA) can be connected by a via (V0).

[0128] In the OTP cell area (OCA), vias (e.g., S2, MD, V2, V1, V0 in FIG. 8) can connect bit lines to bit lines (e.g., D2, D3_ref in FIG. 8), connect bit line / source lines (e.g., M1 in FIG. 8) to metal, or connect metal to metal (e.g., D1, M2, M3 in FIG. 8). Content that overlaps with the above description is omitted. In the OTP cell area (OCA), the OTP reference cell (ORC) and metal can be connected by a contact (BEC).

[0129] The connection area (CA) may represent the area between the normal reference cell and the OTP reference cell (i.e., the area between the normal reference area (NRA) and the OTP reference area (ORA)). In the connection area (CA), a plurality of first bit line connection cells (1 st As BCCs) are formed, the reference bit line (D3_ref) and the reference bit line (D1) are a plurality of first bit line connection cells (1 st It can be connected via BCCs). Multiple first bit line connection cells (1 st BCCs) may include a variable resistor element (MTJ). A plurality of first bit line connection cells (1 st Each of the BCCs and the reference bit line (D1) can be connected via a contact (BEC). For example, a plurality of first bit line connection cells (1 st As the BCCs) are connected in parallel to the bit line (D2) and the reference bit line (D1), a plurality of first bit line connection cells (1 st The resistance value of the variable resistor element included in each of the BCCs can be made relatively small. A plurality of first bit line connection cells (1 stBCCs) have a relatively small resistance value so as to correspond to a plurality of cell vias (S1) of FIG. 6. To prevent I / O offset, the controller (170) has a plurality of first bit line connected cells (1 st All BCCs) are pre-set to a parallel state, or multiple first bit line connection cells (1 st All BCCs can be pre-set to an anti-parallel state.

[0130] The reference bit line (D1) may constitute a part of the target reference bit line (TRBL) shared by the normal reference cell (NRC) and the OTP reference cell (ORC) (e.g., a second reference bit line of the target reference bit line (TRBL). In this case, the reference bit line (D3_ref) and the reference bit line (D1) may be placed in different layers. The reference bit line (D3_ref) and the reference bit line (D1) are a plurality of first bit line connection cells (1 st A target reference bit line (TRBL) can be configured by being connected via BCCs). The first reference current (IREF1) is a plurality of first bit line connection cells (1) connected in parallel. st A first reference signal can be generated without passing through a normal reference cell (NRC) through a target reference bit line (TRBL) configured based on BCCs). That is, the first reference signal is formed by a plurality of first bit line connection cells (1 st It can be generated based on the fixed resistance value (NRR) of the resistor element (RM) using BCCs). In FIG. 7, for convenience of explanation, three first bit line connection cells (1 st Although BCCs) are shown as being connected in parallel, they are not limited thereto, and a plurality of first bit line connection cells (1 stBCCs) can be arranged in various numbers and forms depending on the embodiment.

[0131] When the normal memory cell (NMC) is read out (as the switch transistor (ST) is turned off by a control signal), the first current (IREF1) provided by the readout circuit (140) of FIG. 1 can pass through the normal reference cell (NRC) and the resistor element (RM) to generate a first reference signal. Here, the resistance value (NRR) of the resistor element (RM) can correspond to the reference resistance value of the normal reference cell (NRC). The sensing amplifier (142) can determine the value stored in the normal memory cell (NMC) by detecting the difference between the first input signal applied from the normal memory cell (NMC) and the first reference signal applied from the normal reference cell (NRC). The sensing amplifier (142) can generate a comparison signal by comparing the first reference signal from the normal reference cell (NRC) and the resistor element (RM) with the first input signal from the normal memory cell (NMC). The comparison signal can represent a value stored in a normal memory cell (NMC). The memory device (10) can generate a data signal representing a value stored in a normal memory cell (NMC) from the comparison signal.

[0132] When the OTP reference cell (ORC) is read out, the second current (IREF2) provided by the read-out circuit (140) bypasses the resistor element (RM) and passes through the OTP reference cell (ORC) to generate a second reference signal. At this time, the resistance value of the variable resistor element of the OTP reference cell (ORC) may be a resistance value generated by connecting / combining multiple OTP reference cells (ORCs) (e.g., variable resistor elements of multiple OTP reference cells (ORCs)) (see FIG. 3). The detection amplifier (142) can determine the value stored in the OTP memory cell (OMC) by detecting the difference between the second input signal applied from the OTP memory cell (OMC) and the second reference signal applied from the OTP reference cell (ORC). The detection amplifier (142) can generate a comparison signal by comparing a second reference signal obtained by the connection / combination of a plurality of OTP reference cells (ORCs) and a second input signal obtained by an OTP memory cell (OMC). The comparison signal can represent a value stored in the OTP memory cell (OMC). The memory device (10) can generate a data signal representing a value stored in the OTP memory cell (OMC) from the comparison signal.

[0133] In the wiring structure of the connection area (CA) according to an embodiment of the present disclosure, a plurality of first bit line connection cells (1) are located below the bit line (D2) st As BCCs) are formed, the reference bit line (D3_ref) and the reference bit line (D1) are connected to a plurality of first bit line connection cells (1 st A target reference bit line (TRBL) can be configured by being connected via BCCs). The first reference current (IREF1) is connected to a plurality of first bit line connection cells (1 stBy utilizing BCCs, a first reference signal can be generated by passing through a resistor element (RM) without passing through a normal reference cell (NRC). As OTP reference cells (ORCs) are arranged below the reference bit line (D3_ref) in the wiring structure of the OTP cell region (OCA), the second reference current (IREF1) can generate a second reference signal by passing through the switch transistor (ST) (bypassing the resistor element (RM)) and the OTP reference cell. That is, the memory device can generate reference signals in different ways depending on whether it is a read operation of a normal memory cell (NMC) or a read operation of an OTP memory cell (OMC).

[0134] A memory device according to an embodiment of the present disclosure comprises a plurality of first bit line connection cells (1) in a connection area st By configuring the target reference bit line (TRBL) through BCCs and sharing the target reference bit line (TRBL) between the normal reference cell (NRC) and the OTP reference cell (ORC), the normal memory cell (NMC) and the OTP memory cell (OMC) can be designed as a single IP (or a single memory chip). Additionally, the memory device comprises a plurality of first bit line connection cells (1 st By using BCCs, the method of generating the reference signal (e.g., a method based on a fixed resistance value, a hybrid method based on the connection or combination of multiple reference cells) can be varied according to the type of memory cell (e.g., normal memory cell (NMC) / OTP memory cell (OMC)), thereby maximizing the read margin of each memory cell.

[0135] FIG. 9 is a diagram showing a wiring structure associated with a reference cell and a reference bit line of a memory device according to an exemplary embodiment of the present disclosure.

[0136] In FIG. 9, it is assumed that the reference resistance value of the normal reference cell (NRC) is generated based on a fixed resistance value, and the reference resistance value of the OTP reference cell (ORC) is generated based on the connection / combination of multiple OTP reference cells (ORCs) (e.g., variable resistance elements of multiple OTP reference cells (ORCs). Content that overlaps with the above is omitted.

[0137] Referring to FIG. 9, the bit line and source line of the memory device can be extended in a second direction. The reference bit line (D3_ref) can be connected to a reference switching circuit (RSC) and extended in a second direction to a connection area (CA). At this time, the reference bit line (D3_ref) can constitute a part of the target reference bit line (TRBL) shared by the normal reference cell (NRC) and the OTP reference cell (ORC) (e.g., the first reference bit line of the target reference bit line (TRBL).

[0138] In the normal cell region (NCA), vias (e.g., S2, MD, V2, V1, V0 in FIG. 9) can connect bit lines to bit lines (e.g., D2, D3 in FIG. 9), connect bit line / source line (e.g., M1 in FIG. 9) to metal (e.g., D1, M2, M3 in FIG. 9), or connect metal to metal. For example, a reference bit line (D1) and metal (M3) can be connected by a via (MD), and a source line (M1) and a contact (CA) can be connected by a via (V0).

[0139] In the OTP cell area (OCA), vias (e.g., S2, MD, V2, V1, V0 in FIG. 9) can connect bit lines to bit lines (e.g., D2, D3_ref in FIG. 9), connect bit line / source lines (e.g., M1 in FIG. 9) to metal, or connect metal to metal (e.g., D1, M2, M3 in FIG. 9). Content that overlaps with the above description is omitted. In the OTP cell area (OCA), the OTP reference cell (ORC) and metal can be connected by a contact (BEC).

[0140] The connection area (CA) may represent the area between the normal reference cell and the OTP reference cell (i.e., the area between the normal reference area (NRA) and the OTP reference area (ORA)). In the connection area (CA), a second bit line connection cell (2 nd As BCC) is formed, the reference bit line (D3_ref) and the reference bit line (D1) are connected to the second bit line connection cell (2 nd It can be connected via BCC). The second bit line connection cell (2 nd BCC) may include a variable resistor element (MTJ). The second bit line connection cell (2 nd BCC) and the reference bit line (D1) can be connected through a contact (BEC). For example, a second bit line connection cell (2 nd BCC) is preset to breakdown state (i.e., the second bit line connected cell (2 nd BCC) is shorted, according to the second bit line connection cell (2 nd The resistance value of the variable resistor element included in the BCC can be relatively small. The second bit line connection cell (2 nd BCC) has a relatively small resistance value, so it can correspond to the cell via (S1) of FIG. 7. The controller (170) applies a high bias of a predetermined size to the second bit line connected cell (2nd By applying to BCC), the second bit line connected cell (2 nd BCC) is in a breakdown state (i.e., the second bit line connected cell (2 nd BCC can be pre-set to a shorted state.

[0141] The reference bit line (D1) can constitute a part of the target reference bit line (TRBL) shared by the normal reference cell (NRC) and the OTP reference cell (ORC) (e.g., the second reference bit line of the target reference bit line (TRBL). In this case, the reference bit line (D3_ref) and the reference bit line (D1) may be placed in different layers. The reference bit line (D3_ref) and the reference bit line (D1) are connected to the second bit line connection cell (2 nd It can be connected via BCC to configure the target reference bit line (TRBL). The first reference current (IREF1) is connected to the second bit line connection cell (2 nd Based on a target reference bit line (TRBL) configured based on BCC), a first reference signal can be generated without passing through a normal reference cell (NRC). That is, the first reference signal is a second bit line connection cell (2 nd It can be generated based on the fixed resistance value (NRR) of the resistor element (RM) using BCC). In FIG. 7, for convenience of explanation, one second bit line connection cell (2 nd Although illustrated as BCC), it is not limited thereto, and a second bit line connection cell (2 nd BCC) can be arranged in various numbers depending on the embodiment.

[0142] When the normal memory cell (NMC) is read out (as the switch transistor (ST) is turned off by a control signal), the first current (IREF1) provided by the readout circuit (140) of FIG. 1 can pass through the normal reference cell (NRC) and the resistor element (RM) to generate a first reference signal. Here, the resistance value (NRR) of the resistor element (RM) can correspond to the reference resistance value of the normal reference cell (NRC). The sensing amplifier (142) can determine the value stored in the normal memory cell (NMC) by detecting the difference between the first input signal applied from the normal memory cell (NMC) and the first reference signal applied from the normal reference cell (NRC). The sensing amplifier (142) can generate a comparison signal by comparing the first reference signal from the normal reference cell (NRC) and the resistor element (RM) with the first input signal from the normal memory cell (NMC). The comparison signal can represent a value stored in a normal memory cell (NMC). The memory device (10) can generate a data signal representing a value stored in a normal memory cell (NMC) from the comparison signal.

[0143] When the OTP reference cell (ORC) is read out, the second current (IREF2) provided by the read-out circuit (140) bypasses the resistor element (RM) and passes through the OTP reference cell (ORC) to generate a second reference signal. At this time, the resistance value of the variable resistor element of the OTP reference cell (ORC) may be a resistance value generated by connecting / combining multiple OTP reference cells (ORCs) (e.g., variable resistor elements of multiple OTP reference cells (ORCs)) (see FIG. 3). The detection amplifier (142) can determine the value stored in the OTP memory cell (OMC) by detecting the difference between the second input signal applied from the OTP memory cell (OMC) and the second reference signal applied from the OTP reference cell (ORC). The detection amplifier (142) can generate a comparison signal by comparing a second reference signal obtained by the connection / combination of a plurality of OTP reference cells (ORCs) and a second input signal obtained by an OTP memory cell (OMC). The comparison signal can represent a value stored in the OTP memory cell (OMC). The memory device (10) can generate a data signal representing a value stored in the OTP memory cell (OMC) from the comparison signal.

[0144] In the wiring structure of the connection area (CA) according to an embodiment of the present disclosure, a second bit line connection cell (2) is located below the bit line (D2). nd As BCC) is formed, the reference bit line (D3_ref) and the reference bit line (D1) are connected to the second bit line connection cell (2 nd It can be connected via BCC to configure the target reference bit line (TRBL). The first reference current (IREF1) is connected to the second bit line connection cell (2 ndBy utilizing BCC, a first reference signal can be generated by passing through a resistor element (RM) without passing through a normal reference cell (NRC). As OTP reference cells (ORCs) are arranged below the reference bit line (D3_ref) in the wiring structure of the OTP cell region (OCA), the second reference current (IREF1) can generate a second reference signal by passing through the switch transistor (ST) (bypassing the resistor element (RM)) and the OTP reference cell. That is, the memory device can generate reference signals in different ways depending on whether it is a read operation of a normal memory cell (NMC) or a read operation of an OTP memory cell (OMC).

[0145] A memory device according to an embodiment of the present disclosure comprises a second bit line connection cell (2) of a connection area. nd By configuring the target reference bit line (TRBL) through the BCC and sharing the target reference bit line (TRBL) between the normal reference cell (NRC) and the OTP reference cell (ORC), the normal memory cell (NMC) and the OTP memory cell (OMC) can be designed as a single IP (or a single memory chip). Additionally, the memory device includes a second bit line connection cell (2) connected to the target reference bit line (TRBL). nd By using BCC, the method of generating the reference signal (e.g., a method based on a fixed resistance value, a hybrid method based on the connection or combination of multiple reference cells) can be varied according to the type of memory cell (e.g., normal memory cell (NMC) / OTP memory cell (OMC)), thereby maximizing the read margin of each memory cell.

[0146] FIG. 10 is a flowchart illustrating a method of operation of a memory device according to an exemplary embodiment of the present disclosure.

[0147] Referring to FIG. 10, when a normal reference cell and an OTP reference cell share a reference bit line, the operation method of a memory device (10) for reading data stored in a memory cell may include operations S110 to S150. In FIG. 10, the target reference bit line may represent a reference bit line shared by the normal reference cell and the OTP reference cell. Hereinafter, FIG. 1 and FIG. 9 are referred to together. Content that overlaps with the above description is omitted.

[0148] In operation S110, the memory device (10) can identify whether it is a normal memory cell read operation or an OTP memory cell read operation based on a control signal from the controller (170). The memory device (10) can perform operation S120 if it is a normal memory cell read operation, and perform operation S125 if it is an OTP memory cell read operation.

[0149] In operation S120, the memory device (10) can turn off the switch transistor of the reference switching circuit to generate a first reference resistance value based on a resistance element.

[0150] In operation S125, the memory device (10) can turn on the switch transistor of the reference switching circuit to bypass the resistor element and connect / combine the resistors of at least two OTP reference cells (e.g., variable resistor elements (MTJs)) to generate a second reference resistor value.

[0151] In operation S130, the memory device (10) can generate a reference signal based on a reference resistance value. In operation S140, the memory device (10) can generate a comparison signal by detecting the difference between an input signal applied from a memory cell and a reference signal applied from a reference cell. In operation S150, the memory device (10) can output a data signal of the memory cell based on the comparison signal.

[0152] If the identification result is a read operation of a normal memory cell, the memory device (10) transmits a first reference signal of a normal reference cell corresponding to a first reference resistance value to a detection amplifier through a target reference bit line, and can generate a first comparison signal by detecting the difference between a first input signal applied from a normal memory cell and a first reference signal applied from a normal reference cell. The memory device (10) can output a data signal of a normal memory cell based on the first comparison signal.

[0153] If the identification result is a read operation of the OTP memory cell, the memory device (10) transmits a second reference signal of the OTP reference cell corresponding to the second reference resistance value to a detection amplifier through a target reference bit line, and can generate a second comparison signal by detecting the difference between the second input signal applied from the OTP memory cell and the second reference signal applied from the OTP reference cell. The memory device (10) can output a data signal of the OTP memory cell based on the second comparison signal.

[0154] In one embodiment, the OTP reference cell of the memory device (10) is connected to the target reference bit line, and the normal reference cell can be connected to the target reference bit line based on a plurality of cell vias. Here, the plurality of cell vias can be formed below the target reference bit line in the normal reference region.

[0155] In one embodiment, a normal reference cell of a memory device (10) may be connected to a first reference bit line located below the normal reference cell, and an OTP reference cell may be connected to a second reference bit line located above the OTP reference cell. Here, the first reference bit line and the second reference bit line may be connected through at least one cell via formed in a connection area to form a target reference bit line. The connection area may represent the area between the normal reference cell and the OTP reference cell in FIG. 7 (i.e., the area between the normal reference area (NRA) and the OTP reference area (ORA)).

[0156] In one embodiment, a normal reference cell of a memory device (10) may be connected to a first reference bit line positioned below the normal reference cell, and an OTP reference cell may be connected to a second reference bit line positioned above the OTP reference cell. Here, the first reference bit line and the second reference bit line are a plurality of first bit line connection cells (1) connected in parallel in a connection area. st A target reference bit line can be configured by being connected via BCCs). The connection area may represent the area between the normal reference cell and the OTP reference cell in FIG. 8 (i.e., the area between the normal reference area (NRA) and the OTP reference area (ORA)). The method of operation of the memory device (10) of the present disclosure is to prevent I / O offset by connecting a plurality of first bit line connection cells (1 st It may further include an operation to pre-set all BCCs to a parallel state or pre-set all of them to an anti-parallel state.

[0157] In one embodiment, a normal reference cell of a memory device (10) may be connected to a first reference bit line located below the normal reference cell, and an OTP reference cell may be connected to a second reference bit line located above the OTP reference cell. Here, the first reference bit line and the second reference bit line may be connected through a second bit line connection cell in a connection area to form a target reference bit line. The connection area may represent the area between the normal reference cell and the OTP reference cell in FIG. 9 (i.e., the area between the normal reference area (NRA) and the OTP reference area (ORA)). The method of operation of the memory device (10) of the present disclosure may further include an operation of applying a high bias of a predetermined size to the second bit line connection cell prior to operation S120 to prevent word line offset, thereby pre-setting the second bit line connection cell to a breakdown state.

[0158] The memory device (10) according to the embodiment of the present disclosure has the technical effect of preventing core area waste and deterioration of word line offset characteristics due to the addition of a separate reference bit line for the OTP reference cell by having the normal reference cell and the OTP reference cell share a reference bit line, and improving the read margin of the memory device (10).

[0159] FIG. 11 is a block diagram showing a memory system including a memory device according to an exemplary embodiment of the present disclosure.

[0160] Referring to FIG. 11, the memory system (1200) can communicate with a host (1100) and may include a memory controller (1210) and a memory device (1220). The memory device (1220) may be applied to the memory device (10) described in FIG. 1 through 10.

[0161] The interface (1300) through which the memory system (1200) and the host (1100) communicate may use electrical signals and / or optical signals via wired or wireless means, and, as a non-limiting example, may be implemented as a SATA (serial advanced technology attachment) interface, SATAe (SATA express) interface, SAS (serial attached small computer system interface; serial attached SCSI), PCIe (peripheral component interconnect express) interface, NVMe (non-volatile memory Express) interface, AHCI (advanced host controller interface), or a combination thereof.

[0162] In some embodiments, the memory system (1200) may communicate with the host (1100) by being removablely coupled to the host (1100). As a resistive memory, the memory device (1220) may be a non-volatile memory, and the memory system (1200) may be referred to as a storage system. For example, the memory system (1200) may be implemented as a solid-state drive (SSD), an embedded SSD (eSSD), a multimedia card (MMC), an embedded multimedia card (eMMC), etc., as a non-limiting example.

[0163] The memory controller (1210) can control the memory device (1220) in response to a request received from the host (1100) through the interface (1300). For example, the memory controller (1210) may write data received accompanying the write request to the memory device (1220) in response to a write request, or provide data stored in the memory device (1220) to the host (1100) in response to a read request.

[0164] The memory system (1200) may include at least one memory device (1220). The memory device (1220) may be implemented as the memory device (10) described in FIGS. 1 to 10.

[0165] In one embodiment, the memory system (1200) includes a memory controller (1210); a cell array including a normal memory cell capable of multiple programmable operations, an OTP memory cell capable of one programmable operation, a normal reference cell, and an OTP reference cell, and a reference switching circuit connected to the cell array through a target reference bit line, wherein the normal reference cell and the OTP reference cell share the target reference bit line, and the memory device (1220) can generate a first reference signal based on a resistor element of the reference switching circuit using the target reference bit line when the normal memory cell is in a read operation, and generate a second reference signal based on a switch transistor of the reference switching circuit and a variable resistor element of the OTP reference cell using the target reference bit line when the OTP memory cell is in a read operation.

[0166] A memory system (1200) according to an embodiment of the present disclosure can configure a target reference bit line (TRBL) based on various methods described in FIGS. 6 to 9, and by sharing the target reference bit line (TRBL) between a normal reference cell (NRC) and an OTP reference cell (ORC), a normal memory cell (NMC) and an OTP memory cell (OMC) can be designed as a single IP (or a single memory chip).

[0167] In addition, the memory system (1200) according to the embodiment of the present disclosure can maximize the read margin of each memory cell by varying the method of generating a reference signal (e.g., a method based on a fixed resistance value / a hybrid method based on the connection / combination of multiple reference cells) according to the type of memory cell (e.g., a normal memory cell (NMC) / an OTP memory cell (OMC)) based on a reference switching circuit (RSC).

[0168] FIG. 12 is a block diagram showing a system-on-chip including a memory device according to an exemplary embodiment of the present disclosure.

[0169] Referring to FIG. 12, a System on Chip (SoC) (2000) may include a core (2100), a Digital Signal Processor (DSP; 2200), a Graphic Processing Unit (GPU; 2300), an embedded memory (2400), a communication interface (2500), and a memory interface (2600). The components of the System on Chip (2000) may communicate with each other through a bus (2700).

[0170] A system-on-chip (2000) may refer to an integrated circuit that integrates components of a computing system or other electronic system. For example, as one of the system-on-chip (2000), an application processor (AP) may include components for a processor and other functions.

[0171] The core (2100) can process instructions and control the operation of components included in the system-on-chip (2000). For example, the core (2100) can run an operating system and execute applications on the operating system by processing a series of instructions. The DSP (2200) can generate useful data by processing digital signals, such as digital signals provided from the communication interface (2500). The GPU (2300) can generate data for an image to be output through a display device from image data provided from the built-in memory (2400) or the memory interface (2600), and can also encode image data. The communication interface (2500) can provide an interface for a communication network or one-to-one communication. The memory interface (2600) can provide an interface to external memory of the system-on-chip (2000), such as Dynamic Random Access Memory (DRAM), flash memory, etc.

[0172] The built-in memory (2400) can store data necessary for the operation of the core (2100), DSP (2200), and GPU (2300). The built-in memory (2400) may include the memory device (10) described in FIGS. 1 through 10.

[0173] As described above, exemplary embodiments have been disclosed in the drawings and specification. Although specific terms have been used to describe the embodiments in this specification, they are used only for the purpose of explaining the technical concept of this disclosure and are not intended to limit the meaning or the scope of this disclosure as defined in the claims. Therefore, those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of this disclosure should be determined by the technical concept of the appended claims.

Claims

Claim 1 A memory device comprising: a controller that generates a control signal based on the type of memory cell to perform a read operation of the memory device; a cell array comprising a normal memory region including a normal memory cell capable of multiple programmable cycles, an OTP memory region including an OTP (one-time programmable) memory cell capable of one-time programmable cycles, a normal reference region including a normal reference cell corresponding to the normal memory cell, and an OTP reference region including an OTP reference cell corresponding to the OTP memory cell; and a detection amplifier that detects a difference between an input signal applied from the memory cell and a reference signal applied from the reference cell and generates a comparison signal, wherein the normal reference cell and the OTP reference cell are configured to share a target reference bit line. Claim 2 A memory device according to claim 1, wherein when the normal memory cell is read, the reference switching circuit generates a first reference resistance value based on a resistor element by turning off the switch transistor according to the control signal, and when the OTP memory cell is read, the reference switching circuit generates a second reference resistance value by combining a plurality of OTP reference cells by turning on the switch transistor according to the control signal. Claim 3 A memory device according to claim 1, wherein the OTP reference cell is connected to the target reference bit line, the normal reference cell is connected to the target reference bit line based on a plurality of cell vias in the normal reference region, and the plurality of cell vias are formed below the target reference bit line in the normal reference region. Claim 4 A memory device according to claim 1, wherein the normal reference cell is connected to a first reference bit line disposed below the normal reference cell, and the OTP reference cell is connected to a second reference bit line disposed above the OTP reference cell, and the first reference bit line and the second reference bit line are connected through at least one cell via formed in a connection area to form the target reference bit line, and the connection area is an area between the normal reference area and the OTP reference area in the cell array. Claim 5 A memory device according to claim 1, wherein the normal reference cell is connected to a first reference bit line disposed below the normal reference cell, and the OTP reference cell is connected to a second reference bit line disposed above the OTP reference cell, and the first reference bit line and the second reference bit line are connected through a plurality of first bit line connection cells connected in parallel in a connection area to form the target reference bit line, and the connection area is an area between the normal reference area and the OTP reference area in the cell array. Claim 6 A memory device according to claim 5, wherein the plurality of first bit line connection cells are all pre-set to a parallel state or all pre-set to an anti-parallel state prior to reading the memory cell. Claim 7 A memory device according to claim 1, wherein the normal reference cell is connected to a first reference bit line disposed below the normal reference cell, the OTP reference cell is connected to a second reference bit line disposed above the OTP reference cell, the first reference bit line and the second reference bit line are connected through a second bit line connection cell of a connection area to form the target reference bit line, and the connection area is an area between the normal reference area and the OTP reference area in the cell array. Claim 8 A memory device according to claim 7, wherein the second bit line connection cell is preset to a breakdown state by applying a high bias to the second bit line connection cell. Claim 9 A method of operation of a memory device comprising a normal memory cell capable of multiple programmable operations, a one-time programmable (OTP) memory cell capable of one-time programmable operations, a normal reference cell, an OTP reference cell, and a reference switching circuit, comprising: an operation of identifying whether a read operation of the normal memory cell or a read operation of the OTP memory cell is performed based on a control signal received from a memory controller; an operation of, if the identification result is a read operation of the normal memory cell, turning off a switch transistor of the reference switching circuit to generate a first reference resistance value based on a resistor element of the reference switching circuit; and, if the identification result is a read operation of the OTP memory cell, turning on a switch transistor of the reference switching circuit to bypass the resistor element of the reference switching circuit and combining a plurality of OTP reference cells to generate a second reference resistance value, wherein the normal reference cell and the OTP reference cell share a target reference bit line, and the A method characterized by being connected to the reference switching circuit through a target reference bit line. Claim 10 A memory system comprising: a memory controller; a cell array comprising a normal memory cell capable of multiple programming operations, an OTP memory cell capable of one programming operation, a normal reference cell, and an OTP reference cell, and a reference switching circuit connected to the cell array through a target reference bit line, wherein the normal reference cell and the OTP reference cell share the target reference bit line, and wherein, when a read operation of the normal memory cell occurs, the memory device generates a first reference signal based on a resistor element of the reference switching circuit using the target reference bit line, and when a read operation of the OTP memory cell occurs, generates a second reference signal based on a switch transistor of the reference switching circuit and a variable resistor element of the OTP reference cell using the target reference bit line.

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