Semiconductor structure and method of formation

Abstract

The present disclosure relates to an integrated chip in some embodiments. The integrated chip comprises a lower interconnect layer disposed within a lower inter-level dielectric (ILD) layer on a substrate, and an upper interconnect layer disposed within an upper ILD layer on the substrate. One or more intermediate ILD layers are disposed vertically between the lower ILD layer and the upper ILD layer. One or more intermediate interconnect layers are disposed within one or more intermediate ILD layers. A via extends vertically between the lower interconnect layer and the upper interconnect layer. The via contacts laterally with one or more sidewalls of one or more intermediate interconnect layers.

Description

Technology Field

[0001] This application claims the benefit of U.S. provisional application No. 63 / 769,855 filed March 11, 2025, the entire contents of which are incorporated herein by reference. Background Technology

[0002] Modern integrated chips include millions or billions of semiconductor devices formed on a semiconductor substrate (e.g., a silicon substrate). The semiconductor devices are electrically coupled to each other by interconnects. The interconnects include interconnect wires and interconnect vias disposed within a dielectric structure on the semiconductor substrate. By using interconnects to electrically couple the semiconductor devices, the semiconductor devices can perform logical functions that enable the operation of the integrated chip. Brief explanation of the drawing

[0003] The aspects of the present disclosure are best understood from the following detailed description when read together with the accompanying drawings. The drawings are illustrated to clearly illustrate relevant aspects of the embodiments. The drawings may illustrate the relationships between various structures and / or elements within the embodiments. It should be noted that the drawings are not necessarily drawn to actual scale. In some cases, the dimensions of various features may be increased or decreased at will for clarity of discussion. FIG. 1 illustrates a cross-sectional view of some embodiment of an integrated chip structure having vias extending across a plurality of interconnection layers. FIG. 2 illustrates a cross-sectional view of some additional embodiment of an integrated chip structure having vias extending across a plurality of interconnection layers. FIGS. 3a to 3c illustrate top views of various embodiments of an integrated chip structure having vias extending across a plurality of interconnection layers. FIG. 4 illustrates a cross-sectional view of some additional embodiment of an integrated chip structure having vias extending across a plurality of interconnection layers. FIGS. 5a and 5b illustrate some additional embodiments of an integrated chip structure having vias extended across a plurality of interconnect layers. FIG. 6 illustrates a cross-sectional view of some additional embodiment of an integrated chip structure having vias extending across a plurality of interconnection layers. FIG. 7 illustrates a cross-sectional view of some additional embodiment of an integrated chip structure having vias extending across a plurality of interconnection layers. FIG. 8 illustrates a cross-sectional view of some additional embodiment of an integrated chip structure having vias extending across a plurality of interconnection layers. FIG. 9 illustrates a cross-sectional view of some additional embodiment of an integrated chip structure having vias extending across a plurality of interconnection layers. FIGS. 10a through 10f illustrate cross-sectional views of some additional embodiments of an integrated chip structure having vias extending across a plurality of interconnection layers. FIGS. 11 to 19 illustrate cross-sectional views of some embodiments of a method for forming an integrated chip structure having vias extending across a plurality of interconnection layers. FIGS. 20 through 29 illustrate cross-sectional views of some additional embodiments of a method for forming an integrated chip structure having vias extending across a plurality of interconnection layers. FIG. 30 illustrates a flowchart of some embodiment of a method for forming an integrated chip structure having vias extending across a plurality of interconnection layers. Specific details for implementing the invention

[0004] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. To simplify the disclosure, specific examples of components and arrangements are described below. These are, of course, examples only and are not intended to be limiting. For example, in the following description, forming a first feature on or above a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature are not in direct contact. Additionally, the disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the sake of simplicity and clarity and does not affect the relationship between the various embodiments and / or configurations discussed in itself.

[0005] Additionally, spatially relative terms such as “bottom,” “below,” “lower,” “top,” and “upper” may be used herein for convenience of explanation to describe the relationship between one element or feature and another element(s) or feature(s), as illustrated in the drawings. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations illustrated in the drawings. The device may be oriented differently (rotated 90 degrees or oriented in a different way), and spatially relative terms used herein may likewise be interpreted accordingly. In some embodiments, the terms “approximately” and / or “about” may be interpreted to mean + / - 10% or + / - 5%, while in other embodiments, the terms “approximately” and / or “about” may be interpreted to mean within the normal manufacturing tolerance of a given fab manufacturing flow.

[0006] An integrated chip structure comprises a conductive interconnect disposed on a substrate. The conductive interconnect comprises alternating layers of conductive vias and conductive wires, the size of which increases as the distance across the substrate increases. The conductive wires are configured to provide lateral routing, while the conductive vias are configured to provide vertical routing between adjacent conductive wires. For example, a first conductive via may provide vertical routing between a conductive wire placed underneath and a conductive wire placed above. The conductive interconnect is often formed using a damascene process (e.g., a single damascene process or a double damascene process). The damascene process is performed by forming an ILD layer on the substrate, etching the ILD layer to form holes and / or trenches, and filling the holes and / or trenches with a conductive material.

[0007] The damascene process for forming conductive interconnects requires a different mask for each interconnect wire and interconnect via layer. Additionally, in a single damascene process, a planarization process (e.g., CMP process) is used during the formation of each interconnect wire and interconnect via layer. The lithography and CMP processes used to form interconnect layers are costly and time-consuming. An interconnect stack having multiple interconnect layers in a back-end-of-line (BEOL) manner may require multiple masks and / or CMP processes, which can limit throughput (e.g., limit wafers per hour) and lead to high integrated chip production costs.

[0008] The present disclosure relates to a method for forming an integrated chip structure comprising vias extending vertically through intermediate interconnects to electrically couple a lower interconnect placed below to an upper interconnect placed above. In some embodiments, the method comprises forming a lower interconnect within a lower ILD layer formed on a substrate. One or more intermediate interconnects are subsequently formed within one or more intermediate ILD layers formed above the lower ILD layer. One or more intermediate ILD layers are patterned to form an opening extending through one or more intermediate ILD layers. An etchant is introduced into the opening to laterally etch one or more intermediate ILD layers and form a via opening, which exposes the upper surface of the lower interconnect and the sidewalls of one or more intermediate interconnects. A via is formed within the via opening, and an upper interconnect is formed over the via. By forming vias that extend between the lower interconnect and the upper interconnect, a single manufacturing process can be used to connect multiple interconnect layers, thereby reducing costs (e.g., using fewer lithography and CMP processes) and increasing the throughput of integrated chip manufacturing.

[0009] FIG. 1 illustrates a cross-sectional view of some embodiment of an integrated chip structure (100) having vias extending across a plurality of interconnection layers.

[0010] An integrated chip structure (100) includes an inter-level dielectric (ILD) structure (110) disposed on a substrate (102). The ILD structure (110) includes a plurality of different ILD layers stacked on top of each other. A lower interconnect layer (104) (e.g., a lower tier metal) and an upper interconnect layer (108) (e.g., an upper tier metal) are disposed within the ILD structure (110). The lower interconnect layer (104) includes one or more lower interconnect portions (e.g., a lower tier metal pattern), and the upper interconnect layer (108) includes one or more upper interconnect portions (e.g., an upper tier metal pattern). One or more intermediate interconnect layers (106) (e.g., an intermediate tier metal) are disposed vertically within the ILD metal layer (110) between the lower interconnect layer (104) and the upper interconnect layer (108). Each of one or more intermediate interconnect layers (106) includes one or more intermediate interconnect portions (e.g., intermediate tier metal patterns). In some embodiments, the lower interconnect layer (104), one or more intermediate interconnect layers (106), and the upper interconnect layer (108) include interconnect wires configured to extend laterally across the substrate (102).

[0011] In some embodiments, one or more intermediate interconnect layers (106) include a first intermediate interconnect layer (106a) and a second intermediate interconnect layer (106b) on a first intermediate interconnect layer (106a). In some embodiments, each of the one or more intermediate interconnect layers (106) may include intermediate interconnect segments that are laterally separated from each other in a cross-sectional view. For example, the first intermediate interconnect layer (106a) may include a first intermediate interconnect segment (106a1) and a second intermediate interconnect segment (106a2).

[0012] In this specification, a via (112), also known as a deep via or protracted via, is disposed within an ILD structure (110). The via (112) extends vertically between a lower interconnection layer (104) and an upper interconnection layer (108). The via (112) contacts laterally with one or more sidewalls of one or more intermediate interconnection layers (106). For example, the via (112) contacts a first outer sidewall (112) of one or more intermediate interconnection layers (106). S1 It may include ). In some embodiments, the via (112) extends laterally between the sidewalls of one or more intermediate interconnect segments (106a1 and 106a2) facing each other. In some embodiments, the first outer sidewall (112) of the via (112) S1 ) can laterally contact the first sidewall of the first intermediate interconnect segment (106a1) and the second outer sidewall (112) of the via (112) S2 ) can make lateral contact with the second intermediate interconnect segment (106a2).

[0013] By causing the via (112) to come into contact with a lower interconnect layer (104) located below one or more intermediate interconnect layers (106) and an upper interconnect layer (108) located above one or more intermediate interconnect layers (106), the via (112) can electrically couple at least three different interconnect layers (e.g., interconnect wire layers). By causing the via (112) to electrically couple at least three different interconnect layers, the via (112) can reduce the cost associated with forming an interconnect stack (e.g., back-end-of-line interconnect stack). This is because a single lithography process and a single CMP process can be used to form the via (112) rather than using multiple lithography and CMP processes to form multiple vias. Since lithography and CMP processes can be time-consuming, this also improves the throughput of the manufacturing process.

[0014] FIG. 2 illustrates a cross-sectional view of some additional embodiment of an integrated chip structure (200) having vias extending across a plurality of interconnection layers.

[0015] The integrated chip structure (200) includes an inter-level dielectric (ILD) structure (110) disposed on a substrate (102). The ILD structure (110) includes a plurality of different ILD layers stacked on top of each other. In some embodiments, the plurality of different ILD layers may include one or more of silicon dioxide, carbon-doped silicon oxide (SiCOH), PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), BSG (borosilicate glass), FSG (fluorosilicate glass), USG (undoped silicate glass), etc.

[0016] A lower interconnect layer (104) is disposed within an ILD structure (110). The lower interconnect layer comprises one or more lower interconnect portions, each comprising a lower barrier (104b) and a lower conductive core (104c). The lower barrier (104b) extends along the sidewall and lower surface of the lower conductive core (104c). In some embodiments, the lower conductive core (104c) may comprise tungsten, copper, aluminum, etc. In some embodiments, the lower barrier (104b) may comprise titanium nitride, tantalum nitride, tungsten titanium, etc.

[0017] One or more intermediate interconnect layers (106) are disposed within the ILD structure (110) above the lower interconnect layer (104). In some embodiments, one or more intermediate interconnect layers (106) may include a first intermediate interconnect layer (106a), a second intermediate interconnect layer (106b) above the first intermediate interconnect layer (106a), and a third intermediate interconnect layer (106c) above the second intermediate interconnect layer (106b). One or more intermediate interconnect layers (106) each include one or more intermediate interconnect portions comprising an intermediate barrier (107b) and an intermediate conductive core (107c). The intermediate barrier (107b) extends along the sidewall and lower surface of the intermediate conductive core (107c). In some embodiments, the intermediate conductive core (107c) may include tungsten, copper, aluminum, etc. In some embodiments, the intermediate barrier (107b) may include titanium nitride, tantalum nitride, tungsten titanium, etc. In some embodiments, one or more of the one or more intermediate interconnect layers (106) may include intermediate interconnect segments that are laterally separated from each other in a cross-sectional view.

[0018] An upper interconnect layer (108) is disposed within an ILD structure (110) on one or more intermediate interconnect layers (106). The upper interconnect layer (108) comprises one or more upper interconnect portions, each comprising an upper barrier (108b) and an upper conductive core (108c). The upper barrier (108b) extends along the sidewall and lower surface of the upper conductive core (108c). In some embodiments, the upper conductive core (108c) may comprise tungsten, copper, aluminum, etc. In some embodiments, the upper barrier (108b) may comprise titanium nitride, tantalum nitride, tungsten-titanium, etc.

[0019] A via (112) is disposed within an ILD structure (110). The via (112) extends vertically between a lower interconnect layer (104) and an upper interconnect layer (108). The via (112) includes a via barrier (112b) and a via conductive core (112c). The via barrier (112b) extends along the sidewall and lower surface of the via conductive core (112c). In some embodiments, the via conductive core (112c) may include tungsten, copper, aluminum, etc. In some embodiments, the via barrier (112b) may include titanium nitride, tantalum nitride, tungsten-titanium, etc. In some embodiments, the via (112) may have an inclined outermost sidewall that causes the via (112) to have a tapered width, increasing from a first width (202) along the bottom surface to a second width (204) along the top surface. In some embodiments, the second width (204) may be substantially the same as the width of the interconnection portion (measured along the minimum lateral distance of the interconnection portion) on the lower interconnection layer (104), the width of one or more intermediate interconnection layers (106), and / or the width of the upper interconnection layer (108).

[0020] The via (112) contacts the lower interconnect layer (104) and the upper interconnect layer (108) vertically. The via (112) also contacts one or more side walls of one or more intermediate interconnect layers (106) laterally. In some embodiments, the via barrier (112b) contacts the intermediate barrier (107b) along the interface. In some embodiments, the first distance (206) may differ from (e.g., be smaller than) the second distance (208). In some embodiments, the via (112) contacts one or more intermediate interconnect layers (106) both laterally and vertically. In some embodiments, the via (112) surrounds the upper and lower surfaces of one or more intermediate interconnect layers (106). For example, the via (112) may extend along the lower surface of the first intermediate interconnect layer (106a) in the first direction and may extend along the upper surface of the first intermediate interconnect part (106a) in the second direction (208).

[0021] In some embodiments, the via (112) may have recesses (210) arranged along both sides of the via (112). One or more intermediate interconnect layers (106) may be partially embedded within the recesses (210). One or more intermediate interconnect layers (106) protrude laterally from within the recesses (210) outwardly. In some embodiments, the via (112) includes a protrusion extending laterally outwardly from the sidewall of the via (112) to just between the first intermediate interconnect layer (106a) and the second intermediate interconnect layer (106b).

[0022] FIGS. 3a to 3c illustrate top views of various embodiments of an integrated chip structure having vias extending across a plurality of interconnection layers.

[0023] FIG. 3a illustrates a top view (300) of some embodiments of an intermediate interconnect layer and vias.

[0024] The top view (300) illustrates a first intermediate interconnection layer comprising a first intermediate interconnection segment (106a1) and a second intermediate interconnection segment (106a2). The first intermediate interconnection segment (106a1) and the second intermediate interconnection segment (106a2) include interconnection portions disposed on both sides of a via (112). The first intermediate interconnection segment (106a1) and the second intermediate interconnection segment (106a2) have outermost sidewalls (302a and 302b) which face each other and are separated by a via (112) along a first direction (304). In some embodiments, the first intermediate interconnection segment (106a1) contacts a first sidewall of the via (112), and the second intermediate interconnection segment (106a2) contacts a second sidewall of the via (112) on the opposite side. The via (112) extends laterally in the second direction (306) through the opposing edges of the outermost sidewalls (302a and 302b). The second direction (306) is perpendicular to the first direction (304).

[0025] FIG. 3b illustrates a top view (308) of some additional embodiments of an intermediate interconnect layer and vias.

[0026] The top view (308) illustrates a first intermediate interconnection layer comprising a first intermediate interconnection section having a first intermediate interconnection segment (106a1), a second intermediate interconnection segment (106a2), and a third intermediate interconnection segment (106a3). The first intermediate interconnection segment (106a1) and the third intermediate interconnection segment (106a3) are arranged on both sides of the second intermediate interconnection segment (106a2). The first intermediate interconnection segment (106a1) and the third intermediate interconnection segment (106a3) have a narrower width than the second intermediate interconnection segment (106a2). The second intermediate interconnection segment (106a2) forms an elliptical opening (310) (e.g., an elliptical or circular opening) and has an inner side wall that extends through the first intermediate interconnection section. The via (112) extends through the elliptical opening (310), and the first intermediate interconnection wraps around part of the via (112) in a closed loop and a complete loop.

[0027] FIG. 3c illustrates a top view (312) of some alternative embodiments of an intermediate interconnection layer and vias.

[0028] The top view (312) illustrates a first intermediate interconnection layer comprising a first intermediate interconnection section having a first intermediate interconnection segment (106a1), a second intermediate interconnection segment (106a2), and a third intermediate interconnection segment (106a3). The third intermediate interconnection segment (106a3) has an inner side wall that forms a rectangular opening (314) and extends through the first intermediate interconnection section. A via (112) extends through the rectangular opening (314), so that the first intermediate interconnection section encloses a portion of the via (112) in a closed loop and a complete loop.

[0029] FIG. 4 illustrates a cross-sectional view of some additional embodiment of an integrated chip structure (400) having vias extending across a plurality of interconnection layers.

[0030] An integrated chip structure (400) comprises an ILD structure (110) disposed on a substrate (102). The ILD structure (110) comprises a plurality of different ILD layers (110a-110f) stacked on top of each other. In some embodiments, the plurality of different ILD layers (110a-110f) comprises one or more lower ILD layers (110a-110b), one or more intermediate ILD layers (110c-110e) on the lower ILD layer (110b), and an upper ILD layer (110f) on the one or more intermediate ILD layers (110c-110e). In some embodiments, the plurality of different ILD layers (110a-110e) are vertically separated from each other by a plurality of etch stop layers (ESL) (402a-402e). A plurality of ESLs (402a-402e) may include a lower ESL (402a), one or more intermediate ESLs (402b-402d), and an upper ESL (402e). A lower interconnect layer (104) is disposed within a lower ILD layer (110b), one or more intermediate interconnect layers (106) are disposed within one or more intermediate ILD layers (110c-110e), and an upper interconnect layer (108) is disposed within an upper ILD layer (110f).

[0031] A via (112) is disposed within an ILD structure (110). The via (112) extends vertically through one or more intermediate ILD layers (110c-110e) and one or more intermediate ESLs (402a-402d) to electrically couple a lower interconnect layer (104) and an upper interconnect layer (108). In some embodiments, the lower via (404) may be disposed below the lower interconnect layer (104). In some embodiments, the via (112) has a wider width than the lower via (404). In other embodiments (not shown), the via (112) has substantially the same width as the lower via (404).

[0032] In some embodiments, the integrated chip structure (400) may further include one or more additional vias (406) arranged within the ILD structure (110) and laterally isolated from the via (112) by the ILD structure. The via (112) may extend vertically through one or more of the one or more additional vias (406).

[0033] FIG. 5a illustrates a cross-sectional view of some additional embodiment of an integrated chip structure (500) having vias extending across a plurality of interconnection layers.

[0034] An integrated chip structure (500) includes an ILD structure (110) disposed on a substrate (102). The ILD structure includes a plurality of ILD layers interleaved between adjacent ESLs. A lower interconnect layer (104) and an upper interconnect layer (108) are disposed within the ILD structure (110). One or more intermediate interconnect layers (106a-106c) are disposed vertically within the ILD structure (110) between the lower interconnect layer (104) and the upper interconnect layer (108). One or more intermediate interconnect layers (106a-106c) include a first intermediate interconnect layer (106a) comprising a first intermediate interconnect segment (106a1) and a second intermediate interconnect segment (106a2).

[0035] A via (112) is disposed within an ILD structure (110). The via (112) extends vertically between a lower interconnection layer (104) and an upper interconnection layer (108). The via (112) overlaps laterally with a first intermediate interconnection segment (106a1) by a first non-zero distance (502) and overlaps laterally with a second intermediate interconnection segment (106a2) by a second non-zero distance (504). The via (112) is laterally off-centered from the first intermediate interconnection segment (106a1) such that the first non-zero distance (502) is greater than the second non-zero distance (504). Since the via (112) laterally overlaps the first intermediate interconnect segment (106a1) and the second intermediate interconnect segment (106a2), the via (112) can make good electrical contact with the first intermediate interconnect segment (106a1) and the second intermediate interconnect segment (106a2) even though the via (112) is laterally off-center.

[0036] FIG. 5b illustrates a top view (506) of some additional embodiment of an integrated chip structure having vias extending across a plurality of interconnection layers.

[0037] The top view (506) illustrates a first intermediate interconnection layer (106a) having a first intermediate interconnection segment (106a1) and a second intermediate interconnection segment (106a2) disposed on both sides of a via (112). The first intermediate interconnection segment (106a1) and the second intermediate interconnection segment (106a2) have outermost side walls that are opposite each other and separated from each other by the via (112). The first intermediate interconnection segment (106a1) contacts the first side wall of the via (112), and the second intermediate interconnection segment (106a2) contacts the second side wall of the via (112) on the opposite side.

[0038] FIG. 6 illustrates a cross-sectional view of some additional embodiment of an integrated chip structure (600) having vias extending across a plurality of interconnection layers.

[0039] The integrated chip structure (600) includes a semiconductor device (602) disposed within a substrate (102). In some embodiments, the semiconductor device (602) may include a transistor device (e.g., planar FET, Fin-FET, gate all around FET, complementary FET (C-FET), etc.). In some embodiments, the transistor device may include a gate structure (604) disposed over a channel region arranged between source / drain regions (606).

[0040] A semiconductor device (602) is coupled to a lower interconnect layer (104) by a lower via (608) disposed within an ILD structure (110) placed on a substrate (102). In some embodiments, the lower via (608) may include a conductive contact that physically contacts one of the source / drain regions (606) of the transistor device. The lower via (608) has a first width. A via (112) is arranged on the lower interconnect layer (104). The via (112) extends vertically through one or more intermediate interconnect layers (106) to contact an upper interconnect layer (108) located immediately above the lower interconnect layer (104). The via (112) has a second width greater than the first width. The greater width of the via (112) allows the via (112) to provide a relatively low resistive contact between the lower interconnect layer (104) and the upper interconnect layer (108).

[0041] The upper interconnect layer (108) is also coupled to the bonding structure (610). In some embodiments, the bonding structure (610) may have an under bump metallization (UBM) structure (612) and a conductive bump structure (614) placed on top. In some embodiments, the conductive bump structure (614) may include a solder bump. In other embodiments, the bonding structure (610) may alternatively and / or additionally include a rewiring structure, a bonding pad, etc.

[0042] FIG. 7 illustrates a cross-sectional view of some additional embodiment of an integrated chip structure (700) having vias extending across a plurality of interconnection layers.

[0043] The integrated chip structure (700) includes a semiconductor device (602) arranged along a first side (102a) of the substrate (102). In some embodiments, the semiconductor device (602) includes a transistor device.

[0044] A front-side ILD structure (702) is arranged along a first side (102a) (e.g., the front side) of a substrate (102). The front-side ILD structure (702) may include a plurality of ILD layers stacked on top of each other. A plurality of front-side interconnect layers (704) are disposed within the front-side ILD structure (702). In some embodiments, the plurality of front-side interconnect layers (704) may include front-side interconnect portions including conductive contacts, interconnect wires, interconnect vias, etc. In some embodiments, the front-side ILD structure (702) may also surround a lower interconnect layer within a lower ILD layer within the front-side ILD structure (702). In some embodiments, the front-side ILD structure (702) may include an etching stop layer (402) between adjacent ILD layers.

[0045] The ILD structure (110) is arranged along the second side (102b) (e.g., the rear side) of the substrate (102) opposite the first side (102a) of the substrate (102). The ILD structure (110) surrounds a plurality of interconnect layers (106-108), including one or more intermediate interconnect layers (106) and upper interconnect layers (108). The ILD structure (110) also surrounds vias (112), which extend between the lower interconnect layer (104) and the upper interconnect layer (108). The vias (112) extend vertically from inside the ILD structure (110) through the substrate (102) into the front side ILD structure (702). In some embodiments, the ILD structure (110) may include an etching stop layer (402) between adjacent ILD layers. In another embodiment, the ILD structure (110) may omit the etching stop layer so that adjacent ILD layers come into contact with each other.

[0046] In some embodiments, a plurality of interconnect layers (106-108) are configured to transfer power from the package to the semiconductor device (602). For example, the upper interconnect layer (108) may include a power rail configured to transfer power (e.g., VDD, VSS, etc.) and / or a ground signal. Transferring power to the semiconductor device (602) using a plurality of interconnect layers (106-108) on the second side (102b) of the substrate (102) frees up space on the first side of the substrate (102) for electrical routing between the semiconductor devices. Additionally, this can enable power transfer to the semiconductor device (602) through wider and less resistive metal lines without requiring electrons to travel through a complex BEOL stack. This may be advantageous for IR drop, improved power transfer performance, and reduced routing congestion in BEOL.

[0047] FIG. 8 illustrates a cross-sectional view of some additional embodiment of an integrated chip structure (800) having vias extending across a plurality of interconnection layers.

[0048] An integrated chip structure (800) comprises a plurality of chiplets (802-804) laterally surrounded by a molding compound (806). In various embodiments, the molding compound (806) may comprise a polymer, a thermosetting plastic, a resin, etc. The molding compound (806) may laterally separate the plurality of chiplets (802-804) from each other and from one or more conductive fillers (808) extending through the molding compound (806). The plurality of chiplets (802-804) are electrically coupled to a redistribution structure (810) placed on the molding compound (806) by a back-end-of-line (BEOL) surrounded by the molding compound (806). In some embodiments, the plurality of chiplets (802-804) and the molding compound (806) may be placed on a carrier substrate or an interposer substrate (not shown) underneath. In some embodiments, one or more conductive fillers (808) may be coupled to an underlying carrier substrate or interposer substrate by one or more conductive bumps (811) (e.g., microbumps).

[0049] The rewiring structure (810) comprises a plurality of conductive rewiring interconnects, which electrically couple a plurality of chiplets (802-804) to each other, to a conductive filler (808), to one or more additional chiplets (812), and / or to a bonding structure (610). In some embodiments, the conductive rewiring interconnects comprise a lower interconnect layer (104), one or more intermediate interconnect layers (106), and an upper interconnect layer (108). The conductive rewiring interconnects may also include vias (112) extending across a plurality of the conductive rewiring interconnects. The vias (112) allow the rewiring structure (810) to be formed at a lower cost and with a higher throughput.

[0050] FIG. 9 illustrates a cross-sectional view of some additional embodiment of an integrated chip structure (900) having vias extending across a plurality of interconnection layers.

[0051] An integrated chip structure (900) comprises a substrate (102) having a logic region (902) and a memory region (904). An ILD structure (110) is placed on the substrate (102) within the logic region (902) and the memory region (904). Within the logic region (902), the ILD structure (110) surrounds a plurality of interconnection layers, including a lower interconnection layer (104), one or more intermediate interconnection layers (106), and an upper interconnection layer (108). Within the memory region (904), the ILD structure (110) also surrounds a plurality of memory devices (906).

[0052] A plurality of memory devices (906) include a plurality of transistor devices (908) individually coupled to a data storage element (910) configured to store a first data state. In some embodiments, the data storage element (910) may include a capacitor. In other embodiments, the data storage element (910) may include a resistive random access memory device (RRAM), a ferroelectric random access memory (FeRAM) device, a magneto-resistive random access memory (MRAM) device, a phase change random access memory (PCRAM) device, etc.

[0053] The via (112) extends through one or more intermediate interconnect layers (106) within the logic region (902). In some embodiments, the via (112) extends vertically through the top and bottom surfaces of the data storage element (910). In some embodiments, the via (112) extends vertically through a plurality of transistor devices (908) and the data storage element (910).

[0054] FIG. 10a illustrates a cross-sectional view of some additional embodiment of an integrated chip structure (1000) having vias extending across a plurality of interconnection layers.

[0055] An integrated chip structure (1000) comprises a substrate (102) having a logic region (902) and a memory region (904). An ILD structure (110) is placed on the substrate (102) within the logic region (902) and the memory region (904). Within the logic region (902), the ILD structure (110) surrounds a plurality of interconnection layers, including a lower interconnection layer (104), one or more intermediate interconnection layers (106), and an upper interconnection layer (108). Within the memory region (904), the ILD structure (110) also surrounds a plurality of memory devices.

[0056] A plurality of memory devices include transistor devices (908) coupled to a data storage element (910). Each transistor device (908) includes a channel layer (1004) disposed on a gate structure (1002) within a lower interconnect layer (104). In some embodiments, the channel layer (1004) may include an oxide semiconductor, a high-k dielectric layer, etc. In some embodiments, the gate structure (1002) may extend continuously through a plurality of channel layers and function as a word line. In some embodiments, a gate dielectric (not shown) may isolate the gate structure (1002) from the channel layer (1004). Alternating source contacts (1006) and drain contacts (1008) are disposed on the channel layer (1004). A bit line via (1010) extends from a drain contact (1008) to a bit line (1012) that extends laterally through a plurality of memory device vias (1014) that extend from a source contact (1006) to a data storage element (910). During operation, one or more memory control circuits (not shown) may access a plurality of memory devices by applying a voltage to select a word line and / or a bit line.

[0057] In some embodiments, one of the memory device vias (1014) couples a source contact (1006) to a first intermediate interconnect on a first intermediate interconnect layer (106a). The first intermediate interconnect extends laterally from within the memory region (904) into the local region (902) (e.g., to one or more memory control circuits implemented in the logic region (902)). In some embodiments, a data storage element (910) extends from a plurality of memory device vias (1014) to a second intermediate interconnect on a second intermediate interconnect layer (106b). The second intermediate interconnect extends laterally from within the memory region (904) into the local region (902) (e.g., to one or more memory control circuits implemented in the logic region (902)). A via (112) extends through one or more intermediate interconnect layers (106) within the logic region (902). The via (112) extends vertically through a plurality of transistor devices (908) and data storage elements (910).

[0058] FIG. 10b illustrates a three-dimensional drawing (1016) of the integrated chip structure of FIG. 10a.

[0059] As illustrated in the three-dimensional drawing (1016), the memory device is arranged in a memory array that extends along a first direction (1018) and along a second direction (1020) perpendicular to the first direction (1018). A row of the memory array (extending along the first direction (1018)) is coupled to one of the intermediate interconnects on a first intermediate interconnect layer (106a) that extends into a logical area (902).

[0060] FIG. 10c illustrates a top view (1022) showing a partial embodiment of a first intermediate interconnection layer taken along the cross-sectional line A-A' of FIG. 10a.

[0061] As illustrated in the top view (1022), the first intermediate interconnect layer comprises a plurality of first intermediate interconnect segments (106a1-106a3). The first intermediate interconnect segment (106a1) and the third intermediate interconnect segment (106a3) have the same first shape, while the second intermediate interconnect segment (106a2) has a second shape. The first shape is a rectangular shape having substantially a constant width. The second shape includes a transition region (1023) comprising an opening (310a) through which a via extends.

[0062] FIG. 10d illustrates a top view (1024) showing a partial alternative embodiment of the first intermediate interconnection layer taken along the cross-sectional line A-A' of FIG. 10a.

[0063] As illustrated in the top view (1024), the first intermediate interconnect layer comprises a plurality of first intermediate interconnect segments (106a1-106a3). The plurality of first intermediate interconnect segments have a first intermediate interconnect segment (106a1), a second intermediate interconnect segment (106a2), and a third intermediate interconnect segment (106a3) having the same shape (e.g., a rectangular shape having substantially a constant width). An opening (310a) extends through the second intermediate interconnect segment (106a2). Since the via (112) may have a width greater than that of the second intermediate interconnect segment (106a2), the opening (310a) may extend between both sides of the second intermediate interconnect segment (106a2).

[0064] FIG. 10e illustrates a top view (1026) showing a partial embodiment of a second intermediate interconnection layer taken along the cross-sectional line B-B' of FIG. 10a.

[0065] As illustrated in the plan view (1026), the second intermediate interconnect layer includes a first portion (1026a) within the memory region and a second intermediate interconnect segment (106b1) having a first width within a third portion (1027c) surrounding an opening (310b) through which a via extends. The second intermediate interconnect segment (106b1) has a second width narrower than the first width within a second portion (1027b) located between the first portion (1027a) and the third portion (1027c).

[0066] FIG. 10f illustrates a top view (1028) showing a partial embodiment of a second intermediate interconnect layer taken along the cross-sectional line B-B' of FIG. 10a.

[0067] As illustrated in the top view (1028), the second intermediate interconnection layer includes a second intermediate interconnection segment (106b1) having a substantially constant width.

[0068] FIGS. 11 through 19 illustrate cross-sectional views (1100-1900) corresponding to some embodiments of a method for forming an integrated chip structure having vias extending across a plurality of interconnect layers. Although the structure illustrated in the cross-sectional views (1100-1900) of FIGS. 11 through 19 is described with reference to the method, it will be understood that the structure illustrated in the cross-sectional views of FIGS. 11 through 19 may exist independently of the method rather than being limited to the manufacturing method.

[0069] As illustrated in the cross-sectional view (1100) of FIG. 11, a substrate (102) is provided. In various embodiments, the substrate (102) may be any type of substrate such as a semiconductor wafer (e.g., silicon, SiGE, SOI, etc.) and any type of semiconductor and / or epitaxial layer associated therewith.

[0070] As illustrated in the cross-sectional view (1200) of FIG. 12, a lower etching stop layer (ESL) (402a) is formed on the substrate (102), and a lower inter-level dielectric (ILD) layer (110b) is formed on the lower ESL (402a). In some embodiments, the lower ESL (402a) and the lower ILD layer (110b) may be formed by one or more deposition processes (e.g., a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, a plasma enhanced CVD (PECVD) process, etc.). In some embodiments, the lower ESL (402a) may include nitrides, carbides, etc. In some embodiments, the lower ILD layer (110b) may comprise silicon dioxide, carbon-doped silicon oxide (SiCOH), PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), BSG (borosilicate glass), FSG (fluorosilicate glass), USG (undoped silicate glass), etc. In some embodiments (not shown), one or more additional ILD layers (110a) may be disposed between the lower ESL (402a) and the substrate (102).

[0071] A lower interconnect layer (104) is formed within the lower ILD layer (110b). In some embodiments, the lower interconnect layer (104) may include a lower interconnect formed using a damascene process. The damascene process includes performing a patterning process on the lower ILD layer (110b) to form a lower interconnect opening (1202) formed by the sidewalls of the lower ILD layer (110b). In some embodiments, the patterning process may include a lithography process following an etching process that selectively exposes the lower ILD layer (110b) to an etchant (e.g., a dry etchant having fluorine chemistry, chlorine chemistry, etc.). A lower barrier (104b) is formed within the lower interconnect opening (1202). A lower conductive core (104c) is formed on the lower barrier (104b) and within the lower interconnect opening (1202). A planarization process (e.g., a chemical mechanical planarization (CMP) process) is performed to remove a portion of the lower barrier (104b) and the lower conductive core (104c) on the lower ILD layer (110b) and to form a lower interconnect layer (104).

[0072] After the formation of the lower interconnect layer (104), one or more intermediate interconnect layers are formed. FIGS. 12 to 14 illustrate the formation of three intermediate interconnect layers. FIGS. 12 to 14 illustrate the formation of three interconnect layers, and it will be understood that in various embodiments, more or fewer than three interconnect layers may be formed on the lower interconnect layer.

[0073] As illustrated in the cross-sectional view (1300) of FIG. 13, the thickness of the lower ILD layer is increased to form the lower interconnect layer (104). Subsequently, a first intermediate ESL (402b) is formed on the lower ILD layer (110b), and a first intermediate ILD layer (110c) is formed on the first intermediate ESL (402b). The first intermediate interconnect layer (106a) is formed within the first intermediate ILD layer (110c). The first intermediate interconnect layer (106a) may include a plurality of intermediate interconnect segments (106a1-106a2). In various embodiments, the plurality of intermediate interconnect segments (106a1-106a2) may include separate interconnect sections or be part of a single interconnect section. In some embodiments, the first intermediate ESL (402b) and the first intermediate ILD layer (110c) may be formed individually by one or more deposition processes (e.g., PVD process, CVD process, PE-CVD process, etc.). In some embodiments, the first intermediate interconnect layer (106a) may be formed by a damascene process that forms an intermediate barrier (107b) and an intermediate conductive core (107c) within the intermediate interconnect opening.

[0074] As illustrated in the cross-sectional view (1400) of FIG. 14, the thickness of the first intermediate ILD layer (110c) can be increased to cover the first intermediate interconnect layer (106a). Subsequently, a second intermediate ESL (402c) is formed over the first intermediate ILD layer (110c), and a second intermediate ILD layer (110d) is formed over the second intermediate ESL (402c). The second intermediate interconnect layer (106b) is formed within the second intermediate ILD layer (110d). In some embodiments, the second intermediate ESL (402c) and the second intermediate ILD layer (110d) may be formed individually by one or more deposition processes (e.g., PVD process, CVD process, PE-CVD process, etc.). In some embodiments, the second intermediate interconnect layer (106b) may be formed by a damascene process.

[0075] As illustrated in the cross-sectional view (1500) of FIG. 15, the thickness of the second intermediate ILD layer (110d) can be increased to cover the second intermediate interconnect layer (106b). Subsequently, a third intermediate ESL (402d) is formed over the second intermediate ILD layer (110d), and a third intermediate ILD layer (110e) is formed over the third intermediate ESL (402d). The third intermediate interconnect layer (106c) is formed within the third intermediate ILD layer (110e). In some embodiments, the second intermediate ESL (402d) and the second intermediate ILD layer (110e) may be formed individually by one or more deposition processes (e.g., PVD process, CVD process, PE-CVD process, etc.). In some embodiments, the third intermediate interconnect layer (106e) may be formed by a damascene process.

[0076] FIGS. 16a and FIGS. 17a illustrate some embodiments illustrating the formation of via openings.

[0077] As illustrated in the cross-sectional view (1600a) of FIG. 16a, the thickness of the third intermediate ILD layer (110e) is increased to cover the third intermediate interconnect layer (106c). A patterning process is subsequently performed on the intermediate ILD layers (110c-110e). The patterning process removes a portion of the intermediate ILD layers (110c-110e) to form an opening (1602) between the sidewalls of the intermediate interconnect layers (106a-106c) facing each other. In some embodiments, the opening (1602) may have a first width (1604). In some embodiments, the patterning process may include an etching process (e.g., an anisotropic etching process) that selectively exposes the intermediate ILD layer (110c-110e) to the etchant (1608) according to a mask (1606) formed on the intermediate ILD layer (110c-110e). In some embodiments, the etchant (1608) may include a dry etchant or be a dry etchant (e.g., having fluorine or chlorine-based etching chemistry).

[0078] As illustrated in the cross-sectional view (1700a) of FIG. 17a, a lateral etching process is performed on the intermediate ILD layers (110c-110e) to increase the width of the opening (e.g., 1602) and to form a via opening (1702) having a second width (1704) greater than the first width of the opening (e.g., 1604 of FIG. 16). The via opening (1702) exposes the upper and lower surfaces of one or more intermediate interconnect layers (106a-106c). In some embodiments, the lateral etching process may include an etching process that selectively exposes the intermediate ILD layers (110c-110e) to a wet etchant (1706). In some embodiments, the wet etchant (1706) may be potassium hydroxide (KOH), hydrofluoric acid (HF), piranha solution, or may contain the same.

[0079] FIGS. 16b and FIGS. 17b illustrate some alternative embodiments illustrating the formation of via openings.

[0080] As illustrated in the cross-sectional view (1600b) of FIG. 16b, a patterning process is performed to remove a portion of the intermediate ILD layer (110c-110e) to form an opening (1602) that is off-center from the intermediate interconnect layer (106a-106c). For example, the center of the opening (illustrated along line (1610)) may be a first distance (1612) from the first intermediate interconnect segment (106a1) and a second distance (1614) different from the first distance (1612) from the second intermediate interconnect segment (106a2). In some embodiments (not illustrated), the opening (1602) may expose the sidewall of the first intermediate interconnect segment (106a1) while being isolated from the sidewall of the second intermediate interconnect segment (106a2) by the ILD layer.

[0081] As illustrated in the cross-sectional view (1700b) of FIG. 17b, a lateral etching process may be performed on the intermediate ILD layers (110c-110e) to increase the width of the opening and form via openings (1702). The via openings (1702) expose the upper and lower surfaces of one or more intermediate interconnect layers (106a-106c).

[0082] As shown in the cross-sectional view (1800) of FIG. 18, a via barrier (112b) is formed within a via opening (1702). A via conductive core (112c) is formed within the via barrier (112b) and the via opening (1702). A planarization process (e.g., chemical mechanical planarization (CMP) process) is performed to remove a portion of the via barrier (112b) and the via conductive core (112c) on the intermediate ILD layer (110c-110e) and to form a via (112).

[0083] As illustrated in the cross-sectional view (1900) of FIG. 19, an upper ESL (402e) is formed on the third intermediate ILD layer (110e), and an upper ILD layer (110f) is formed on the upper ESL (402e). An upper interconnect layer (108) is formed within the upper ILD layer (110f). In some embodiments, the upper ESL (402e) and the lower ILD layer (110f) may be formed individually by one or more deposition processes (e.g., PVD process, CVD process, PE-CVD process, etc.). In some embodiments, the upper interconnect layer (108) may be formed by a damascene process that forms an upper barrier (108b) and an upper conductive core (108c) within the upper interconnect opening.

[0084] FIGS. 20 through 29 illustrate cross-sectional views (2000-2900) corresponding to some additional embodiments of a method for forming an integrated chip structure having vias extending across a plurality of interconnect layers. Although the structure illustrated in the cross-sectional views (2000-2900) of FIGS. 20 through 29 is described with reference to the method, it will be understood that the structure illustrated in the cross-sectional views (2000-2900) of FIGS. 20 through 29 may exist independently of the method rather than being limited to the manufacturing method.

[0085] As illustrated in the cross-sectional view (2000) of FIG. 20, a substrate (102) is provided. In various embodiments, the substrate (102) may be any type of substrate such as a semiconductor wafer (e.g., silicon, SiGE, SOI, etc.) and any type of semiconductor and / or epitaxial layer associated therewith. The substrate includes a logic region (902) and a memory region (904).

[0086] As illustrated in the cross-sectional view (2100) of FIG. 21, a lower etching stop layer (ESL) (402a) is formed on the substrate (102), and a lower inter-level dielectric (ILD) layer (110b) is formed on the lower ESL (402a). In some embodiments, the lower ESL (402a) and the lower ILD layer (110b) may be formed by one or more deposition processes (e.g., PVD process, CVD process, PE-CVD process, etc.). A lower interconnect layer (104) is formed within the lower ILD layer (110b). In some embodiments, the lower interconnect layer (104) may be formed using a damascene process.

[0087] After the lower interconnect layer (104) is formed, one or more transistor devices (908) are formed within the device ILD structure (905). One or more transistor devices (908) may be formed to include a channel layer (1004) formed on a gate dielectric (not shown) on a gate structure within the lower interconnect layer (104). Alternating source contacts (1006) and drain contacts (1008) may be formed on the channel layer (1004). A bit-line via (1010) is formed on the drain contact (1008), and a bit line (1012) is formed on the bit-line via (1010). A plurality of memory device vias (1014) are subsequently formed on the source contact (1006).

[0088] As illustrated in the cross-sectional view (2200) of FIG. 22, the first intermediate interconnect layer (106a) is formed within the first intermediate ILD layer (110c) formed on the device ILD structure (905). In some embodiments, the first intermediate interconnect layer (106a) may be formed using a damascene process.

[0089] As shown in the cross-sectional view (2300) of FIG. 23, one or more data storage elements (910) are formed within the first intermediate ILD layer (110c), and a second intermediate ILD layer (110d) is formed on the first intermediate ILD layer (110c).

[0090] As illustrated in the cross-sectional view (2400) of FIG. 24, the thickness of the second intermediate ILD layer (110d) is increased to cover one or more data storage elements (910). A second intermediate interconnect layer (106b) is subsequently formed within the second intermediate ILD layer (110d) and on one or more data storage elements (910).

[0091] As illustrated in the cross-sectional view (2500) of FIG. 25, a third intermediate ILD layer (110e) is formed on the second intermediate ILD layer (110d). Subsequently, a masking structure (2502) is formed on the third intermediate ILD layer (110e). In some embodiments, the masking structure (2502) may include a hard mask layer (2502a) and a photoresist layer (2502b) disposed on the hard mask layer (2502a). In some embodiments, the hard mask layer (2502a) may include a metal (e.g., titanium, titanium nitride, tantalum, etc.) and an oxide (e.g., silicon oxynitride), etc.

[0092] As illustrated in the cross-sectional view (2600) of FIG. 26, a patterning process is subsequently performed on the ILD layers (110c-110e). The patterning process removes a portion of the intermediate ILD layers (110c-110e) to form an opening (1602) between the sidewalls of the intermediate interconnect layers (106a-106c) facing each other. In some embodiments, the opening (1602) may have a first width (1604). In some embodiments, the patterning process may include an etching process (e.g., an anisotropic etching process) that selectively exposes the intermediate ILD layers (110c-110e) to an etchant (1608) according to a masking structure.

[0093] As illustrated in the cross-sectional view (2700) of FIG. 27, an anisotropic etching process is performed on the intermediate ILD layers (110c-110e) to increase the width of the opening (e.g., 1602) and form via openings (1702). The via openings (1702) expose the upper and lower surfaces of one or more intermediate interconnect layers (106a-106c). In some embodiments, the lateral etching process may include an etching process that selectively exposes the intermediate ILD layers (110c-110e) to a wet etchant (1706).

[0094] As shown in the cross-sectional view (2800) of FIG. 28, a via barrier (112b) is formed within a via opening (1702). A via conductive core (112c) is formed within the via barrier (112b) and the via opening (1702). A planarization process (e.g., chemical mechanical planarization (CMP) process) is performed to remove a portion of the via barrier (112b) and the via conductive core (112c) on the intermediate ILD layer (110c-110e) and to form a via (112).

[0095] As illustrated in the cross-sectional view (2900) of FIG. 29, an upper ESL (402e) is formed on the third intermediate ILD layer (110e), and an upper ILD layer (110f) is formed on the upper ESL (402e). An upper interconnect layer (108) is formed within the upper ILD layer (110f). In some embodiments, the upper ESL (402e) and the lower ILD layer (110f) may be formed individually by one or more deposition processes (e.g., PVD process, CVD process, PE-CVD process, etc.). In some embodiments, the lower interconnect layer (108) may be formed by a damascene process.

[0096] FIG. 30 illustrates a flowchart of some embodiment of a method (3000) for forming an integrated chip memory structure having an access transistor having an asymmetric source / drain design.

[0097] Although the method (3000) is illustrated and described herein as a series of actions or events, it will be understood that the illustrated order of such actions or events should not be interpreted as limiting. For example, some actions may occur in a different order and / or in parallel with actions or events distinct from those illustrated and / or described herein. Furthermore, not all illustrated actions may be required to implement one or more aspects or embodiments of the detailed description herein. Additionally, one or more actions described herein may be performed in one or more distinct actions and / or phases.

[0098] In step (3002), a lower interconnect layer including a lower interconnect portion is manufactured within a lower ILD layer on a substrate. FIG. 12 illustrates a cross-sectional view (1300) of some embodiment corresponding to operation (3002). FIG. 21 illustrates a cross-sectional view (2100) of some additional embodiment corresponding to operation (3002).

[0099] In some embodiments, in operation (3004), the transistor device may be formed within the device ILD layer formed on the lower ILD layer. FIG. 22 illustrates a cross-sectional view (2200) of some embodiments corresponding to operation (3004).

[0100] In step (3006), one or more intermediate interconnect layers are formed within one or more intermediate ILD layers above the lower ILD layer. FIGS. 13 through 15 illustrate cross-sectional views (1300-1500) of some embodiments corresponding to operation (3006). FIGS. 22 and 24 illustrate cross-sectional views (2200 and 2400) of some additional embodiments corresponding to operation (3006).

[0101] In some embodiments, in operation (3008), the data storage element is formed within one or more intermediate ILD layers and may be coupled to a transistor device. FIGS. 21 and FIGS. 23 illustrate cross-sectional views (2100 and 2300) of some additional embodiments corresponding to operation (3008).

[0102] In operation (3010), one or more intermediate ILD layers are etched to form an opening that extends through one or more intermediate ILD layers. FIG. 15a illustrates a cross-sectional view (1500a) of some embodiment corresponding to operation (3010). FIG. 15b illustrates a cross-sectional view (1500b) of some additional embodiment corresponding to operation (3010). FIG. 26 illustrates a cross-sectional view (2600) of some additional embodiment corresponding to operation (3010).

[0103] In operation (3012), an etchant is introduced into the opening to laterally etch one or more intermediate ILD layers and form a via opening that exposes the sidewalls and top and / or bottom surfaces of one or more intermediate interconnect layers. FIG. 16a illustrates a cross-sectional view (1600a) of some embodiment corresponding to operation (3012). FIG. 16b illustrates a cross-sectional view (1600b) of some additional embodiment corresponding to operation (3012). FIG. 27 illustrates a cross-sectional view (2700) of some additional embodiment corresponding to operation (3012).

[0104] In operation (3014), a via is manufactured within a via opening. FIG. 18 illustrates a cross-sectional view (1800) of some embodiment corresponding to operation (3014). FIG. 28 illustrates a cross-sectional view (2800) of some additional embodiment corresponding to operation (3014).

[0105] In operation (3016), an upper interconnection layer having an upper interconnection portion within an upper ILD formed on one or more interconnection ILD layers is formed. FIG. 19 illustrates a cross-sectional view (1900) of some embodiment corresponding to operation (3016). FIG. 29 illustrates a cross-sectional view (2900) of some additional embodiment corresponding to operation (3016).

[0106] Accordingly, in some embodiments, the present disclosure relates to a method for forming an integrated chip structure comprising vias that extend vertically through an intermediate interconnect layer to electrically couple a lower interconnection portion placed below to an upper interconnection portion placed above.

[0107] In some embodiments, the present disclosure relates to an integrated chip. The integrated chip comprises: a lower interconnect layer disposed within a lower inter-level dielectric (ILD) layer on a substrate; an upper interconnect layer disposed within an upper ILD layer on a substrate; one or more intermediate ILD layers disposed between the lower ILD layer and the upper ILD layer; one or more intermediate interconnect layers disposed within one or more intermediate ILD layers; and vias extending between the lower interconnect layer and the upper interconnect layer, wherein the vias are in lateral contact with one or more sidewalls of the one or more intermediate interconnect layers. In some embodiments, the one or more intermediate interconnect layers comprise, when viewed in a cross-sectional view, a first intermediate interconnect segment in contact with a first sidewall of the via, and a second intermediate interconnect segment in contact with a second sidewall of the via on the opposite side. In some embodiments, the via is laterally overlapped with a first intermediate interconnect segment by a first non-zero distance and laterally overlapped with a second intermediate interconnect segment by a second non-zero distance different from the first non-zero distance. In some embodiments, the first non-zero distance is greater than the second non-zero distance. In some embodiments, one or more intermediate interconnect layers include a first intermediate interconnect layer and a second intermediate interconnect layer immediately above the first intermediate interconnect layer;

[0108] The via includes a projection extending laterally outward from the sidewall of the via to just between the first intermediate interconnect layer and the second intermediate interconnect layer. In some embodiments, the via extends just above the upper surface of one or more intermediate interconnect layers. In some embodiments, the integrated chip further includes a lower via disposed below the lower interconnect layer, and the via has a wider width than the lower via. In some embodiments, the via contacts one or more intermediate interconnect layers in both the lateral and vertical directions. In some embodiments, the transistor device disposed along the front side of the substrate; further include a plurality of front interconnect layers disposed within a front ILD structure arranged on the front side of the substrate—the lower interconnect layers being disposed between the plurality of front interconnect layers and the front side of the substrate—and one or more intermediate interconnect layers and upper interconnect layers are disposed on the rear side of the substrate opposite the front side, and the via extends through the substrate. In some embodiments, the transistor device disposed on a device ILD layer arranged between one or more intermediate ILD layers; further comprising a data storage element disposed within one or more intermediate ILD layers and electrically coupled to the transistor device—the transistor device being between the data storage element and the lower ILD layer—and vias extend vertically through the top surface and bottom surface of the data storage element.

[0109] In another embodiment, the present disclosure relates to a method for forming an integrated chip. The method comprises: forming a lower interconnection within a lower ILD layer formed on a substrate; forming one or more intermediate interconnections within one or more intermediate ILD layers formed on a substrate; etching one or more intermediate ILD layers to form an opening extending through one or more intermediate ILD layers; introducing an etchant into the opening to etch one or more intermediate ILD layers to form a via opening, wherein the via opening exposes the upper surface of the lower interconnection and the sidewalls of one or more intermediate interconnections; and forming a via comprising a conductive material within the via opening. In some embodiments, the method further comprises the step of forming an upper interconnection within an upper ILD isolated from the substrate by one or more intermediate ILD layers, wherein the upper interconnection contacts the upper surface of the via. In some embodiments, the via encloses the upper and lower surfaces of one or more intermediate interconnections. In some embodiments, one or more intermediate interconnects include a first intermediate interconnect having an intermediate conductive core laterally surrounded by an intermediate barrier, and a via includes a via conductive core laterally surrounded by a via barrier, and the via barrier contacts the intermediate barrier along the interface. In some embodiments, one or more intermediate interconnects protrude outwardly laterally from within a recess on the side of the via.

[0110] In another embodiment, the present disclosure relates to a method for forming an integrated chip. The method comprises the step of manufacturing a lower interconnect layer within a lower ILD layer formed on a substrate;

[0111] The method comprises the steps of: manufacturing a first intermediate interconnect segment and a second intermediate interconnect segment within an intermediate ILD layer formed on a lower ILD layer; etching the intermediate ILD layer to form an opening extending through the intermediate ILD layer between the first intermediate interconnect segment and the second intermediate interconnect segment; increasing the width of the opening to form a via opening—the via opening exposes the upper surface of the lower interconnect layer and the sidewalls of the first intermediate interconnect segment and the second intermediate interconnect segment—; and depositing a conductive material within the via opening. In some embodiments, the via opening exposes the upper and lower surfaces of the first intermediate interconnect segment and the second intermediate interconnect segment. In some embodiments, the first intermediate interconnect segment and the second intermediate interconnect segment are part of an intermediate interconnection that encloses the via opening in a closed loop and an intact loop. In some embodiments, the first intermediate interconnect segment is the first intermediate interconnect part, and the second intermediate interconnect segment is the second intermediate interconnect part, and the first intermediate interconnect part and the second interconnect part have outermost sidewalls facing each other and isolated from each other by the via opening. In some embodiments, the first intermediate interconnect segment includes an intermediate conductive core laterally surrounded by an intermediate barrier, and the via includes a via conductive core laterally surrounded by a via barrier, and the via barrier contacts the intermediate barrier along the interface.

[0112] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the various aspects of the present disclosure. Those skilled in the art will understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to perform the same purpose and / or achieve the same gain as the embodiments introduced herein. Those skilled in the art should also recognize that various modifications, substitutions, and alterations may be made to these equivalents in the present disclosure without departing from the nature and scope of the present disclosure.

[0113] [Example 1]

[0114] In integrated chips,

[0115] A lower interconnect layer disposed within an inter-level dielectric (ILD) layer on a substrate;

[0116] An upper interconnect layer disposed within the upper ILD layer on the substrate;

[0117] One or more intermediate ILD layers disposed between the lower ILD layer and the upper ILD layer;

[0118] One or more intermediate interconnect layers disposed within the above one or more intermediate ILD layers; and

[0119] A via extending between the lower interconnection layer and the upper interconnection layer

[0120] Includes,

[0121] An integrated chip in which the vias are in lateral contact with one or more sidewalls of one or more intermediate interconnect layers.

[0122] [Example 2]

[0123] An integrated chip according to claim 1, wherein the one or more intermediate interconnect layers comprise, when viewed in a cross-sectional view, a first intermediate interconnect segment in contact with a first sidewall of the via, and a second intermediate interconnect segment in contact with a second sidewall of the via on the opposite side.

[0124] [Example 3]

[0125] An integrated chip according to paragraph 2, wherein the via is laterally overlapped with the first intermediate interconnect segment by a first non-zero distance and laterally overlapped with the second intermediate interconnect segment by a second non-zero distance different from the first non-zero distance.

[0126] [Example 4]

[0127] In paragraph 1,

[0128] A first etching stop layer arranged between the one or more intermediate ILD layers and the upper ILD layer; and

[0129] A second etching stop layer arranged between the one or more intermediate ILD layers and the lower ILD layer.

[0130] An integrated chip further comprising, wherein the vias extend through the first etching stop layer and the second etching stop layer.

[0131] [Example 5]

[0132] In paragraph 1,

[0133] The above one or more intermediate interconnect layers include a first intermediate interconnect layer and a second intermediate interconnect layer located immediately above the first intermediate interconnect layer;

[0134] An integrated chip in which the via comprises a projection extending laterally outward from the sidewall of the via to the space between the first intermediate interconnect layer and the second intermediate interconnect layer.

[0135] [Example 6]

[0136] An integrated chip according to claim 1, wherein the via extends just above the upper surface of the one or more intermediate interconnect layers.

[0137] [Example 7]

[0138] In paragraph 1,

[0139] An integrated chip further comprising a lower via disposed below the lower interconnection layer, wherein the via has a wider width than the lower via.

[0140] [Example 8]

[0141] An integrated chip according to claim 1, wherein the vias are in contact with one or more intermediate interconnect layers in both lateral and vertical directions.

[0142] [Example 9]

[0143] In paragraph 1,

[0144] A transistor device disposed along the front side of the above substrate;

[0145] A plurality of front interconnect layers disposed within a front ILD structure arranged on the front side of the substrate - the lower interconnect layer is arranged between the plurality of front interconnect layers and the front side of the substrate -

[0146] Includes more,

[0147] An integrated chip in which one or more intermediate interconnect layers and the upper interconnect layer are disposed on the rear side of the substrate opposite the front side, and the vias extend through the substrate.

[0148] [Example 10]

[0149] In paragraph 1,

[0150] A transistor device disposed within a device ILD layer arranged between one or more intermediate ILD layers;

[0151] A data storage element disposed within one or more intermediate ILD layers and electrically coupled to the transistor device—the transistor device is located between the data storage element and the lower ILD layer—

[0152] Includes more,

[0153] A method in which the above via extends vertically through the top and bottom surfaces of the data storage element.

[0154] [Example 11]

[0155] In a method for forming an integrated chip;

[0156] A step of forming a lower interconnection portion within a lower ILD layer formed on a substrate;

[0157] A step of forming one or more intermediate interconnects within one or more intermediate ILD layers formed on the substrate;

[0158] A step of etching one or more intermediate ILD layers to form an opening extending through one or more intermediate ILD layers;

[0159] A step of introducing an etchant into the opening to etch one or more intermediate ILD layers to form a via opening—the via opening exposes the upper surface of the lower interconnect and the sidewall of the one or more intermediate interconnects—; and

[0160] Step of forming a via containing a conductive material within the above-mentioned via opening

[0161] A method including

[0162] [Example 12]

[0163] In Paragraph 11,

[0164] A method further comprising the step of forming an upper interconnect portion within an upper ILD isolated from the substrate by one or more intermediate ILD layers, wherein the upper interconnect portion contacts the upper surface of the via.

[0165] [Example 13]

[0166] A method according to claim 11, wherein the vias surround the upper and lower surfaces of one or more intermediate interconnects.

[0167] [Example 14]

[0168] In Paragraph 11,

[0169] The above one or more intermediate interconnects include a first intermediate interconnect having an intermediate conductive core laterally surrounded by an intermediate barrier, and

[0170] A method in which the via comprises a via conductive core laterally surrounded by a via barrier, and the via barrier contacts the intermediate barrier along the interface.

[0171] [Example 15]

[0172] A method according to claim 11, wherein one or more intermediate interconnects protrude outwardly from within a recess on the side of the via toward the via.

[0173] [Example 16]

[0174] In a method for forming an integrated chip;

[0175] A step of manufacturing a lower interconnection layer within a lower ILD layer formed on a substrate;

[0176] A step of manufacturing a first intermediate interconnection segment and a second intermediate interconnection segment within an intermediate ILD layer formed on the lower ILD layer;

[0177] A step of etching the intermediate ILD layer and forming an opening extending through the intermediate ILD layer between the first intermediate interconnect segment and the second intermediate interconnect segment;

[0178] A step of increasing the width of the opening to form a via opening - the via opening exposes the upper surface of the lower interconnection layer and the sidewalls of the first intermediate interconnection segment and the second intermediate interconnection segment - ; and

[0179] Step of depositing a conductive material within the above via opening

[0180] A method including

[0181] [Example 17]

[0182] A method according to claim 16, wherein the via opening exposes the upper and lower surfaces of the first intermediate interconnect segment and the second intermediate interconnect segment.

[0183] [Example 18]

[0184] A method according to claim 16, wherein the first intermediate interconnect segment and the second intermediate interconnect segment are part of an intermediate interconnect portion that encloses the via opening in a closed loop and a complete loop.

[0185] [Example 19]

[0186] A method according to claim 16, wherein the first intermediate interconnect segment is a first intermediate interconnect part and the second intermediate interconnect segment is a second intermediate interconnect part, and the first intermediate interconnect part and the second interconnect part have outermost side walls facing each other and separated from each other by the via opening.

[0187] [Example 20]

[0188] In Paragraph 16,

[0189] The first intermediate interconnect segment includes an intermediate conductive core laterally surrounded by an intermediate barrier, and

[0190] A method in which the via comprises a via conductive core laterally surrounded by a via barrier, and the via barrier contacts the intermediate barrier along the interface.

Claims

Claim 1 An integrated chip comprising: a lower interconnect layer disposed within a lower inter-level dielectric (ILD) layer on a substrate; an upper interconnect layer disposed within an upper ILD layer on the substrate; one or more intermediate ILD layers disposed between the lower ILD layer and the upper ILD layer; one or more intermediate interconnect layers disposed within the one or more intermediate ILD layers; and vias extending between the lower interconnect layer and the upper interconnect layer, wherein the vias are in lateral contact with one or more sidewalls of the one or more intermediate interconnect layers. Claim 2 An integrated chip according to claim 1, wherein the one or more intermediate interconnect layers comprise, when viewed in a cross-sectional view, a first intermediate interconnect segment in contact with a first sidewall of the via, and a second intermediate interconnect segment in contact with a second sidewall of the via on the opposite side. Claim 3 An integrated chip according to claim 1, further comprising: a first etching stop layer arranged between one or more intermediate ILD layers and the upper ILD layer; and a second etching stop layer arranged between one or more intermediate ILD layers and the lower ILD layer, wherein the vias extend through the first etching stop layer and the second etching stop layer. Claim 4 An integrated chip according to claim 1, wherein the one or more intermediate interconnect layers comprise a first intermediate interconnect layer and a second intermediate interconnect layer immediately above the first intermediate interconnect layer; and the via comprises a projection extending laterally outward from the sidewall of the via to immediately between the first intermediate interconnect layer and the second intermediate interconnect layer. Claim 5 An integrated chip according to claim 1, further comprising a lower via disposed below the lower interconnection layer, wherein the via has a wider width than the lower via. Claim 6 An integrated chip according to claim 1, wherein the vias are in contact with one or more intermediate interconnect layers in both lateral and vertical directions. Claim 7 An integrated chip according to claim 1, further comprising: a transistor device disposed along the front side of the substrate; a plurality of front interconnect layers disposed within a front ILD structure arranged on the front side of the substrate—the lower interconnect layers being disposed between the plurality of front interconnect layers and the front side of the substrate—wherein one or more intermediate interconnect layers and the upper interconnect layers are disposed on the rear side of the substrate opposite the front side, and the vias extending through the substrate. Claim 8 The method of claim 1 further comprises: a transistor device disposed within a device ILD layer arranged between one or more intermediate ILD layers; a data storage element disposed within one or more intermediate ILD layers and electrically coupled to the transistor device, wherein the transistor device is located between the data storage element and the lower ILD layer, and the via extends vertically through the upper surface and the lower surface of the data storage element. Claim 9 A method for forming an integrated chip comprising: forming a lower interconnect portion within a lower ILD layer formed on a substrate; forming one or more intermediate interconnect portions within one or more intermediate ILD layers formed on the substrate; etching the one or more intermediate ILD layers to form an opening extending through the one or more intermediate ILD layers; introducing an etchant into the opening to etch the one or more intermediate ILD layers to form a via opening, wherein the via opening exposes the upper surface of the lower interconnect portion and the sidewall of the one or more intermediate interconnect portions; and forming a via comprising a conductive material within the via opening. Claim 10 A method for forming an integrated chip comprising: a step of forming a lower interconnect layer within a lower ILD layer formed on a substrate; a step of forming a first intermediate interconnect segment and a second intermediate interconnect segment within an intermediate ILD layer formed on the lower ILD layer; a step of etching the intermediate ILD layer to form an opening extending between the first intermediate interconnect segment and the second intermediate interconnect segment and through the intermediate ILD layer; a step of increasing the width of the opening to form a via opening, wherein the via opening exposes the upper surface of the lower interconnect layer and the sidewalls of the first intermediate interconnect segment and the second intermediate interconnect segment; and a step of depositing a conductive material within the via opening.

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