Function debug permission control circuit, integrated circuit and integrated circuit debug system

Abstract

The present disclosure provides a function debug authority control circuit, an integrated circuit, and an integrated circuit debug system. The circuit comprises a debug authority control module, a latch module, and at least one function module. The debug authority control module is used to transmit at least one debug acknowledgment signal to the latch module in response to conditions that meet for performing a current function debug operation. The latch module is used to generate at least one debug enable signal based on the at least one debug acknowledgment signal, transmit at least one debug enable signal to a corresponding function module through at least one signal latch output terminal, and control each signal latch output terminal to be in a signal latch state, thereby causing each function module to be in a debug state during the corresponding debug enable signal latch period. By implementing that the latch state is not affected by the state of each module within the integrated circuit, the loss of debug authority caused by operations such as restarts within the integrated circuit can be avoided, and the convenience and efficiency of debugging can be improved.

Description

Technology Field

[0001] The present disclosure relates to integrated circuit technology and chip security technology, and in particular to a function debug privilege control circuit, an integrated circuit, and an integrated circuit debug system. Background Technology

[0002] For some current integrated circuits (e.g., automotive-grade chips), debug permissions are generally disabled during the commercial phase. Debugging permissions for integrated circuits can be enabled through a method that authenticates debug certificates, and these certificates must include an invalidation mechanism to ensure that debug permissions are not abused. However, during the debugging period for current integrated circuits, debug permissions are typically invalidated after a restart (including on-chip and off-chip restarts). Consequently, if re-debugging is required, a new debug certificate must be generated and downloaded to the integrated circuit, which reduces the convenience of debugging. The problem to be solved

[0003] To solve the aforementioned technical problem, the present disclosure provides a function debug privilege control circuit, an integrated circuit, and an integrated circuit debug system, thereby solving the problem of low convenience in controlling the debug privileges of a function module when debugging an integrated circuit. means of solving the problem

[0004] According to a first aspect of an embodiment of the present disclosure, a function debug authority control circuit is provided, comprising a debug authority control module, a latch module, and at least one function module, wherein the latch module comprises at least one signal latch output terminal, the signal output terminal of the debug authority control module is connected to a signal input terminal of the latch module, the at least one signal latch output terminal corresponds one-to-one with at least one function module, and the at least one signal latch output terminal is connected to a debug enable control terminal of each corresponding function module, wherein the debug authority control module is used to transmit at least one debug acknowledgment signal to the latch module in response to a condition for performing a current function debug operation, the at least one debug acknowledgment signal corresponds one-to-one with at least one function module, and the latch module is used to generate at least one debug enable signal based on the at least one debug acknowledgment signal, transmit at least one debug enable signal to each corresponding function module through the at least one signal latch output terminal, and control the at least one signal latch output terminal to be in a signal latch state, so as to control at least one function Each module is made to enter a debug state during its corresponding debug enable signal latch period.

[0005] According to a second aspect of an embodiment of the present disclosure, an integrated circuit is provided, comprising a debug communication interface and the above-described function debug privilege control circuit, wherein the debug communication interface is connected to a debug privilege control module included in the function debug privilege control circuit and is used to establish a communication connection between the integrated circuit and a test device when performing function debugging on the integrated circuit.

[0006] According to a third aspect of an embodiment of the present disclosure, an integrated circuit debug system is provided, comprising a test device and the integrated circuit described above, wherein the test device is connected to a debug communication interface included in the integrated circuit. Effects of the invention

[0007] Based on the function debug authority control circuit, integrated circuit, and integrated circuit debug system provided by an embodiment of the present disclosure, a debug authority control module, a latch module, and at least one function module are configured. The debug authority control module transmits at least one debug acknowledgment signal to the latch module in response to conditions that meet for performing a current function debug operation. The at least one debug acknowledgment signal corresponds one-to-one with at least one function module. The latch module generates at least one debug enable signal based on the at least one debug acknowledgment signal. The at least one debug enable signal is transmitted to the corresponding function module through a signal latch output terminal. The at least one signal latch output terminal is controlled to be in a signal latch state, thereby causing at least one function module to be in a debug state during the corresponding debug enable signal latch period. During the integrated circuit debugging period, the debug enable signal of each functional module is implemented to maintain a latch state. Since the latch state is not affected by the state of each module within the integrated circuit, the loss of debug privileges caused by operations such as restarts within the integrated circuit can be avoided, and the convenience and efficiency of debugging can be improved. Brief explanation of the drawing

[0008] FIG. 1 is a configuration diagram of a function debug privilege control circuit provided by an exemplary embodiment of the present disclosure. FIG. 2 is a configuration diagram of a debug privilege control circuit provided by another exemplary embodiment of the present disclosure. FIG. 3 is a configuration diagram of a signal input unit provided by an exemplary embodiment of the present disclosure. FIG. 4 is a configuration diagram of a gate control sub-unit provided by an exemplary embodiment of the present disclosure. FIG. 5 is an exemplary configuration diagram of a gate control sub-unit and a latch unit provided by an exemplary embodiment of the present disclosure. FIG. 6 is a configuration diagram of a debug privilege control circuit provided by another exemplary embodiment of the present disclosure. FIG. 7 is a diagram of an integrated circuit provided by an exemplary embodiment of the present disclosure. FIG. 8 is a configuration diagram of an integrated circuit debug system provided by an exemplary embodiment of the present disclosure. Specific details for implementing the invention

[0009] To explain the present disclosure, exemplary embodiments of the present disclosure are described in detail with reference to the drawings below; however, it should be understood that the embodiments clearly described are only a part of the present disclosure and not the whole of the embodiments, and that the present disclosure is not limited to exemplary embodiments.

[0010] It should be noted that, unless otherwise specifically described, the relative arrangement of parts and steps, numerical expressions, and numbers described in these embodiments do not limit the scope of the present disclosure.

[0011] Application Overview

[0012] During the design process of integrated circuits, such as automotive-grade chips, various debugging capabilities are typically retained, such as the debug or trace capabilities of ARM CPUs, or some debugging measures designed in-house by the chip manufacturer. Access rights to these chip resources must all be effectively controlled to prevent information leakage or to avoid intruders gaining privileges to attack the chip and affect its normal operation. In the early stages of integrated circuit development, debugging rights are open to ensure the convenience of software code development. In the application stage of the integrated circuit, debugging rights are restricted to the user by default. For example, if a user encounters a problem and needs to identify a fault, they must contact the chip manufacturer to have a debug certificate produced and provided; debugging rights can only be opened after downloading this certificate to the chip and passing signature verification.

[0013] Generally, on-chip restart behavior may be involved during the debugging process. That is, if an on-chip restart occurs in a situation where the internal power to the chip is not turned off or the chip's reset pin is not triggered, the debug certificate may be invalidated, debugging privileges may be lost, or the certificate may need to be recreated, thereby reducing the efficiency of the debugging process.

[0014] To solve the above-mentioned problem, the function debug authority control circuit provided by the embodiment of the present disclosure maintains the debug enable signal of each function module in a latch state during the integrated circuit debugging period, and the latch state is not affected by the state of each module inside the integrated circuit, thereby avoiding the loss of debug authority caused by operations such as restarts inside the integrated circuit and improving the convenience and efficiency of debugging.

[0015] Exemplary circuit structure

[0016] FIG. 1 is an exemplary configuration diagram of a function debug authority control circuit (100) provided by an exemplary embodiment of the present disclosure. The function debug authority control circuit (100) of the embodiment of the present disclosure can be used to perform function debugging on an integrated circuit such as a vehicle-grade chip.

[0017] As illustrated in FIG. 1, the function debug privilege control circuit includes a debug privilege control module (101), a latch module (102), and at least one function module (103).

[0018] The latch module (102) includes at least one signal latch output terminal, and the signal output terminal of the debug authority control module (101) is connected to the signal input terminal of the latch module (102), and the at least one signal latch output terminal corresponds one-to-one with at least one function module (103), and the at least one signal latch output terminal is connected to the debug enable control terminal of each corresponding function module.

[0019] The debug permission control module (101) may be used to transmit at least one debug acknowledgment signal to the latch module (102) in response to conditions that meet the requirements for performing a current function debug operation. The at least one debug acknowledgment signal corresponds one-to-one with at least one function module (103).

[0020] In this embodiment, the debug privilege control module (101) may be a module used to monitor the security of the integrated circuit within the integrated circuit. For example, a Hardware Security Module (HSM) within the integrated circuit may serve as the debug privilege control module (101). The HSM is a dedicated security subsystem embedded within the chip and is used to provide hardware-level security guarantees, primarily handling core functions such as key management, cryptographic operations, safe startup, and tamper protection. When conditions for performing a current function debug operation are met, the debug privilege control module (101) may transmit a debug acknowledgment signal to each signal input terminal of the latch module (102).

[0021] Optionally, the latch module (102) may be composed of at least one latch, and the input terminal of each latch may receive an input debug acknowledgment signal and output one debug enable signal.

[0022] The conditions for the aforementioned function debug operation may be preset preconditions that allow the integrated circuit to be debugged. For example, after the debug permission control module (101) passes the verification of a debug request entered by a user, it determines that the conditions for the function debug operation are met.

[0023] The latch module (102) generates at least one debug enable signal based on at least one debug acknowledgment signal, transmits at least one debug enable signal to each corresponding function module through at least one signal latch output terminal, and is used to control at least one signal latch output terminal to be in a signal latch state so that at least one function module (103) is in a debug state during each corresponding debug enable signal latch period.

[0024] The latch module (102) can be implemented by a latch circuit and can also be implemented by a device capable of performing logical processing capabilities (e.g., an MCU, a DSP, etc.). The latch module (102) receives an input debug acknowledgment signal (e.g., a high-level signal indicating the number "1") and outputs a corresponding debug enable signal (e.g., a high-level signal likewise). At the same time, the output debug enable signal is latched, and during the debug period, any other operation on any integrated circuit (e.g., an on-chip reset operation) other than the operation of the latch module (102) forcibly resetting the output signal does not affect the state of the debug enable signal. Therefore, during the latch period of the debug enable signal, each function module maintains a debug state under the action of the input debug enable signal.

[0025] The above-described at least one function module (103) may include various types of function modules, and as illustrated in FIG. 1, the at least one function module (103) includes, but is not limited to, at least one CPU (Central Processing Unit), DSP (Digital Signal Processor), GPU (Graphics Processing Unit), DFT (Design For Test), Coresight (Debug and Trace System Architecture on Chip). Each function module is always in a debug state unless a specific reset operation (e.g., off-chip reset) is triggered during debugging. For example, because there is a need to reset a shift operation and a register alone under DFT mode, the debug state of the DFT can be latched, and the debug state can be avoided due to said operation.

[0026] In one application scenario, after the chip having the circuit provided by the present embodiment starts up, it first enters the BootROM (starting read-only memory) execution phase. If an on-chip reset occurs during the debugging process, the program is executed again in the BootROM. Since the debugging privilege is opened and the debug enable signal is latched, the debugging privilege does not disappear, and the debugging privilege in the BootROM always exists. Since there is no need to place the debug certificate in the BootROM and execute the privilege authentication code, debugging efficiency is improved.

[0027] A function debug authority control circuit provided by an embodiment of the present disclosure is configured by setting a debug authority control module (101), a latch module (102), and at least one function module (103). In response to the condition that the debug authority control module (101) performs a current function debug operation, at least one debug acknowledgment signal is transmitted to the latch module (102), and the at least one debug acknowledgment signal corresponds one-to-one with the at least one function module (103). The latch module (102) generates at least one debug enable signal based on the at least one debug acknowledgment signal and transmits at least one debug enable signal to each corresponding function module through a signal latch output terminal, and controls at least one signal latch output terminal to be in a signal latch state so that at least one function module (103) is in a debug state during the corresponding debug enable signal latch period. During the integrated circuit debugging period, the debug enable signal of each functional module is implemented to maintain a latch state. Since the latch state is not affected by the state of each module within the integrated circuit, the loss of debug privileges caused by operations such as restarts within the integrated circuit can be avoided, and the convenience and efficiency of debugging can be improved.

[0028] In some optional implementations, the debug authorization control module (101) is further used to perform debug authorization verification based on a pre-downloaded debug certificate in response to a received debug request, and if the verification is passed, to determine that it meets the conditions for performing the current function debug operation.

[0029] Specifically, the debug authority of the integrated circuit supported by the present embodiment is implemented through a method of authorizing a certificate. For example, when debugging an automotive-grade chip, it is first necessary to send a debug request to the on-chip HSM using a debug host. The HSM generates a random number based on a pre-stored chip ID and returns it to the debug host. The debug host generates a debug certificate based on the chip ID and the random number, and downloads the certificate to the chip. The HSM verifies the debug certificate using the random number, and if it passes, determines that it meets the conditions for performing a functional debug operation and allows the debug host to perform a functional debug operation on the chip.

[0030] In this embodiment, after performing debug authorization verification using a debug certificate, if the conditions for functional debug operation are met, the debug enable signal of each functional module is latched to enhance the safety of the debug.

[0031] In some optional implementations, as illustrated in FIG. 2, the latch module (102) includes at least one signal input unit (1021) and at least one latch unit (1022), the at least one latch unit (1022) corresponds one-to-one with the at least one signal input unit (1021), and the at least one latch unit (1022) is connected to each corresponding signal input unit.

[0032] Any of the signal input units among at least one signal input unit (1021) is used to receive a corresponding debug acknowledgment signal from the debug authorization control module (101), generate a corresponding debug enable signal based on the received debug acknowledgment signal, and transmit the generated debug enable signal to a corresponding latch unit.

[0033] Any latch unit among at least one latch unit (1022) is used to transmit a received debug enable signal to a corresponding function module and to latch the received debug enable signal.

[0034] The above-described signal input unit can convert an input debug acknowledgment signal into a debug enable signal. The signal input unit can be a single buffer unit and directly transmits the debug acknowledgment signal as a debug enable signal to the latch unit. The signal input unit can also perform other functions (e.g., synchronizing with other signals) based on the debug acknowledgment signal to output a debug enable signal.

[0035] The latch unit described above is used to latch an input signal, and the latch unit can be implemented based on the associated latch. For example, the latch can be configured through a gate circuit and a trigger. As an example, as shown in FIG. 5, the latch unit may include one OR gate circuit (OR) and one trigger (FF). One input terminal of the OR gate circuit receives a debug enable signal, and the other input terminal receives an electrical level fed back by the trigger output terminal. When the debug enable signal is at a high level (the number "1"), the OR gate outputs a high level. The clock signal input terminal (CP terminal) included in the trigger may be at a preset electrical level (e.g., a high level) at this time, so that the output signal of the trigger matches the input signal, i.e., the trigger also outputs a high level. After the output high level is fed back to the input terminal of the OR gate, the output debug enable signal is always at a high level regardless of how the input debug enable signal changes, thereby implementing the latch function.

[0036] This embodiment configures a latch module (102) by setting a signal input unit and a latch unit, and implements effective control and switching for an input debug acknowledgment signal, thereby helping to improve the stability of the circuit performing the latch function.

[0037] In some optional implementations, as shown in FIG. 3, any of the signal input units (1021) of at least one signal input unit includes a debug acceptance signal input terminal, a debug reference signal input terminal, and a gate control sub-unit (10211), and the debug acceptance signal input terminal is connected to the debug permission control module (101) and the gate control sub-unit (10211), respectively, and the debug reference signal input terminal is connected to the debug permission control module (101) and the gate control sub-unit (10211), respectively.

[0038] The structure shown in Fig. 3 is that of a single signal input unit, and other signal input units are the same as the structure shown in Fig. 3.

[0039] The gate control sub-unit (10211) receives a debug acknowledgment signal and a debug reference signal from the debug acknowledgment signal input terminal and the debug reference signal input terminal, respectively, and is used to transmit a debug enable signal to the corresponding latch unit when the received debug acknowledgment signal and the debug reference signal meet the debug acknowledgment conditions.

[0040] The aforementioned debug reference signal interacts with the debug enable signal and is used to output the debug enable signal. As shown in FIG. 5, the debug reference signal input by the debug reference signal input terminal is the efuse_autoload_done signal, and the signal indicates that the efuse memory data has been loaded, at which time the debug state of each function module can be enabled.

[0041] Optionally, as illustrated in FIG. 5, the latch module (102) may further include a multi-signal selector MUX, the two inputs of which receive debug_en (i.e., a debug acknowledgment signal output by the HSM) and the number "1" (i.e., a high-level signal), respectively. hsm_disable is used to select debug_en or to set a fixed high-level signal as the debug acknowledgment signal. hsm_disable allows the user to bypass the debug_en signal output by the HSM in some scenarios and switch directly to the number "1", i.e., to force the debug acknowledgment signal to "1".

[0042] The gate control sub-unit (10211) can be implemented by selecting a suitable gate circuit according to actual demand. For example, the gate control sub-unit (10211) may include an AND gate, that is, when both the debug reference signal and the debug acknowledgment signal are "1", it transmits a debug enable signal "1" to the latch unit.

[0043] In this embodiment, a gate control sub-unit (10211) is configured in the signal input unit, and by using the gate control sub-unit (10211) to receive a debug acknowledgment signal and a debug reference signal, each latch unit can more effectively control the received signal, which helps to improve the convenience and debug efficiency of integrated circuit debugging.

[0044] In some optional implementations, as shown in FIG. 4, the gate control sub-unit (10211) includes a signal synchronization circuit (102111) and a gate control circuit (102112), the input terminal of the gate control circuit (102112) is connected to the output terminal of the signal synchronization circuit (102111), and the output terminal of the gate control circuit (102112) is connected to a corresponding latch unit.

[0045] The signal synchronization circuit (102111) performs synchronization of transmission times for the debug acknowledgment signal and the debug reference signal, and is used to input the debug acknowledgment signal and the debug reference signal after synchronization to the gate control circuit (102112).

[0046] The signal synchronization circuit (102111) can output a debug reference signal and a debug acknowledgment signal in synchronization according to the clock signal. For example, it can be implemented using two D triggers, that is, the debug reference signal and the debug acknowledgment signal are simultaneously input to corresponding D triggers, and the two D triggers output the synchronously input debug reference signal and the debug acknowledgment signal under the control of the clock signal.

[0047] As shown in FIG. 5, efuse_autoload_done is a debug reference signal, and the debug reference signal and the debug accept signal output from the MUX are input to a signal synchronization circuit (102111), and the debug reference signal and the debug accept signal after synchronization are input to a gate control circuit (102112) (Fig. 5 uses an AND gate circuit) to output a debug enable signal. When the debug reference signal and the debug accept signal are the same "1", the debug enable signal is "1".

[0048] This embodiment enables accurate control of the timing of the input latch unit's signal by setting the gate control circuit (102112) and the signal synchronization circuit (102111), thereby avoiding errors caused by the debug enable signal not being synchronized with other signals during latch and improving the accuracy of the test.

[0049] In some optional implementations, as illustrated in FIG. 6, the latch module (102) further includes a debug permission termination signal input. The debug permission termination signal input is connected to each latch unit included in the latch module (102) and is used to reset the debug enable signal output by each latch unit.

[0050] The latch module (102) is further used to terminate the latch state of at least one signal latch output in response to receiving a debug permission termination signal from a debug permission termination signal input, and to transmit a debug disable signal to at least one function module (103), thereby causing at least one function module (103) to exit the debug state.

[0051] The above-described debug permission termination signal is input to the reset control terminal of each latch unit in the above-described embodiment, so that the electrical level of the output terminal of each latch unit is reset (for example, reset to the number "0"). For example, the debug permission termination signal can be input to the clock signal input terminal (CP) of the trigger shown in FIG. 5, and when the clock signal input terminal receives a signal of a corresponding electrical level, the debug enable signal output by the trigger is reset.

[0052] The debug permission termination signal input terminal can be connected to a corresponding port according to actual demand, and through said port, a reset for the debug enable signal after latch is implemented, and furthermore, each functional module in this circuit can be exited from the debug state.

[0053] This embodiment can improve the convenience of integrated circuit debugging by accurately controlling the timing of exiting the debug state through transmitting a debug authority termination signal to the latch module (102).

[0054] In some optional implementations, the debug permission termination signal input terminal is connected to an off-chip reset trigger terminal outside the function debug permission control circuit (100), and the debug permission termination signal is an off-chip reset signal transmitted when the off-chip reset trigger terminal triggers an off-chip reset operation.

[0055] The off-chip reset trigger terminal is an external reset pin of the function debug authority control circuit (100), and generally, as shown in FIG. 6, the reset pin may be connected to a reset button (Hard rst) or to a control port capable of adjusting the electrical level of the reset pin, and when it is detected that the electrical level of the off-chip reset trigger terminal is a preset electrical level (e.g., a low level, i.e., a button press), the debug authority termination signal is valid (the number "0" is valid), and the latch module (102) outputs a debug disable signal (e.g., a low level signal) to each function module.

[0056] This embodiment improves debugging convenience in the debug state by connecting the debug authority termination signal input terminal to the off-chip reset trigger terminal, thereby latching the electrical level of the debug enable terminal of each function module so that when an on-chip reset occurs in the circuit, it does not exit the debug state, and each function module exits the debug state only when an off-chip reset occurs.

[0057] In some optional implementations, the latch module (102) includes at least one latch unit (1022) and at least one signal input unit (1021), the at least one latch unit (1022) corresponds one-to-one with the at least one signal input unit (1021), and the at least one latch unit (1022) is connected to each corresponding signal input unit.

[0058] The at least one latch unit (1022) and at least one signal input unit (1021) of the present embodiment are the same as the at least one latch unit (1022) and at least one signal input unit (1021) shown in FIG. 2 described above.

[0059] For any latch unit among at least one latch unit (1022), the reset signal input terminal included in the latch unit is connected to the debug authority termination signal input terminal.

[0060] The aforementioned debug permission termination signal can be input to the reset control terminal of each latch unit, so that the electrical level of the output terminal of each latch unit is reset (for example, reset to the number "0"). For example, the debug permission termination signal can be input to the clock signal input terminal of the trigger shown in FIG. 5, the clock signal input terminal is, that is, the reset signal input terminal, and when the clock signal input terminal receives a signal of a corresponding electrical level, the debug enable signal output by the trigger is reset.

[0061] This embodiment enables the control of the reset of each latch unit using the same debug authority termination signal by connecting the reset signal input terminal to the reset signal input terminal of each latch unit, which helps improve the convenience of integrated circuit debugging.

[0062] In some optional implementations, the function debug privilege control circuit (100) may further include a self-check exemption area, and the latch module (102) is set in said self-check exemption area, and said self-check exemption area is an area in which the function debug privilege control circuit (100) does not perform a self-check operation upon startup.

[0063] By setting the latch module (102) in a self-check exemption area, the state of the latch module (102) can be prevented from being disrupted when the function debug privilege control circuit (100) performs a self-check, thereby improving test stability. For example, the self-check exemption area described above may be an AON (Always-On Domain) within the function debug privilege control circuit (100), and the AON area is a special area that independently and continuously supplies power to one of the low-power chips and maintains the core functions of the chip. Since the AON area is responsible for starting the refuge island and does not perform a self-check operation at the same time, the latch module (102) is set in the area to prevent the state of the latch module (102) from being disrupted when performing a self-check.

[0064] Exemplary integrated circuit

[0065] FIG. 7 is a diagram of an integrated circuit (700) provided by an exemplary embodiment of the present disclosure. The integrated circuit may be any type of integrated circuit, for example, an SOC chip.

[0066] The integrated circuit includes a debug communication interface and a function debug privilege control circuit (100) provided by any of the embodiments described above. The debug communication interface is connected to a debug privilege control module included in the function debug privilege control circuit and is used to establish a communication connection between the integrated circuit and a test device when performing function debugging on the integrated circuit.

[0067] In an exemplary embodiment of the integrated circuit, by applying the function debug privilege control circuit described above, the debug enable signal of each function module is implemented to maintain a latch state during the integrated circuit debugging period. Since the latch state is not affected by the state of each module within the integrated circuit, the loss of debug privileges caused by operations such as restarts within the integrated circuit can be avoided, and the convenience and efficiency of debugging can be improved.

[0068] The function debug privilege control circuit (100) in an exemplary embodiment of the integrated circuit can be implemented by using any exemplary embodiment of the function debug privilege control circuit described above, and is not described further herein. For beneficial technical effects corresponding to the exemplary embodiment of the integrated circuit, refer to the corresponding beneficial technical effects of the exemplary embodiment of the function debug privilege control circuit described above, and are not described further herein.

[0069] Exemplary integrated circuit debug system

[0070] FIG. 8 is a configuration diagram of an integrated circuit debug system (800) provided by an exemplary embodiment of the present disclosure. The integrated circuit debug system includes a test device (801) and an integrated circuit (700) illustrated in FIG. 7 above, and the test device is connected to a debug communication interface included in the integrated circuit.

[0071] The test device can be various types of electronic devices, such as personal computers, smartphones, and servers. The test device can transmit information such as debug requests, debug certificates, and test use cases to the integrated circuit, and can test each functional module when each functional module of the integrated circuit enters a debug state.

[0072] In an exemplary embodiment of the integrated circuit debug system, the debug enable signal of each functional module is implemented to maintain a latch state during the integrated circuit debugging period. Since the latch state is not affected by the state of each module within the integrated circuit, the loss of debug authority caused by operations such as restarts within the integrated circuit can be avoided, and the convenience and efficiency of debugging can be improved.

[0073] The integrated circuit in the exemplary embodiment of the integrated circuit debug system may be implemented using any exemplary embodiment of the integrated circuit described above, and is not described further herein. For beneficial technical effects corresponding to the exemplary embodiment of the integrated circuit debug system, refer to the exemplary embodiment of the function debug privilege control circuit described above or the corresponding beneficial technical effects of the exemplary embodiment of the integrated circuit debug system, and are not described further herein.

[0074] Although the basic principles of the present disclosure have been described in combination with the specific embodiments above, the advantages, advantages, effects, etc. mentioned in the present disclosure are merely examples and not limitations, and should not be considered as something that each embodiment of the present disclosure must necessarily possess. Furthermore, the specific details described above are intended only for illustrative purposes and to facilitate understanding, and are not limitations; the details described above do not restrict the present disclosure from being implemented using the specific details described above.

[0075] Those skilled in the art may make various modifications and variations to the present disclosure without departing from the spirit and scope of the application. Accordingly, the present disclosure also includes such modifications and variations if they fall within the scope of the claims of the present disclosure and the equivalent technology.

Claims

Claim 1 In a function debug authorization control circuit, the circuit comprises a debug authorization control module, a latch module, and at least one function module, wherein the latch module comprises at least one signal latch output terminal, the signal output terminal of the debug authorization control module is connected to the signal input terminal of the latch module, the at least one signal latch output terminal corresponds one-to-one with the at least one function module, and the at least one signal latch output terminal is connected to a debug enable control terminal of the corresponding function module, wherein the debug authorization control module is used to transmit at least one debug authorization signal to the latch module in response to a condition for performing a current function debug operation, the at least one debug authorization signal corresponds one-to-one with the at least one function module, and the latch module generates at least one debug enable signal based on the at least one debug authorization signal, transmits the at least one debug enable signal to the corresponding function module through the at least one signal latch output terminal, and the at least one signal latch A function debug authority control circuit used to control the output terminal to enter a signal latch state, so that at least one function module enters a debug state during a corresponding debug enable signal latch period. Claim 2 In claim 1, the debug permission control module is further used to perform debug permission verification based on a pre-downloaded debug certificate in response to the receipt of a debug request, and, if the verification is passed, to determine that it meets the conditions for performing the current function debug operation. Claim 3 In claim 1, the latch module comprises at least one latch unit and at least one signal input unit, the at least one latch unit corresponds one-to-one with the at least one signal input unit, the at least one latch unit is connected to each corresponding signal input unit, any of the at least one signal input units is used to receive a corresponding debug acknowledgment signal from the debug authorization control module, generate a corresponding debug enable signal based on the received debug acknowledgment signal, and transmit the generated debug enable signal to the corresponding latch unit, and any of the at least one latch unit is used to transmit the received debug enable signal to the corresponding function module and to latch the received debug enable signal, a function debug authorization control circuit. Claim 4 In paragraph 3, any signal input unit among the at least one signal input unit comprises a debug approval signal input terminal, a debug reference signal input terminal, and a gate control sub-unit, wherein the debug approval signal input terminal is connected to the debug authority control module and the gate control sub-unit, respectively, and the debug reference signal input terminal is connected to the debug authority control module and the gate control sub-unit, respectively, and the gate control sub-unit receives a debug approval signal and a debug reference signal from the debug approval signal input terminal and the debug reference signal input terminal, respectively, and when the received debug approval signal and the debug reference signal meet the debug approval condition, the function debug authority control circuit is used to transmit a debug enable signal to a corresponding latch unit. Claim 5 In paragraph 4, the gate control sub-unit comprises a gate control circuit and a signal synchronization circuit, the input terminal of the gate control circuit is connected to the output terminal of the signal synchronization circuit, the output terminal of the gate control circuit is connected to a corresponding latch unit, and the signal synchronization circuit performs synchronization of transmission time for the debug acknowledgment signal and the debug reference signal, and is used to input the debug acknowledgment signal and the debug reference signal after synchronization to the gate control circuit, a functional debug authorization control circuit. Claim 6 A function debug authority control circuit according to claim 1, wherein the latch module further includes a debug authority termination signal input terminal, and the latch module is further used to terminate the latch state of the at least one signal latch output terminal in response to the receipt of a debug authority termination signal from the debug authority termination signal input terminal, and to transmit a debug disable signal to each of the at least one function module, thereby causing the at least one function module to exit the debug state. Claim 7 In claim 6, the debug authority termination signal input terminal is connected to an off-chip reset trigger terminal outside the function debug authority control circuit, and the debug authority termination signal is an off-chip reset signal transmitted when the off-chip reset trigger terminal triggers an off-chip reset operation, function debug authority control circuit. Claim 8 In claim 6, the latch module comprises at least one latch unit and at least one signal input unit, the at least one latch unit corresponds one-to-one with the at least one signal input unit, the at least one latch unit is connected to the corresponding signal input unit, and for any latch unit among the at least one latch unit, a reset signal input terminal included in the latch unit is connected to the debug authority termination signal input terminal, a functional debug authority control circuit. Claim 9 A function debug authority control circuit according to any one of claims 1 to 8, wherein the function debug authority control circuit further includes a self-check exemption area, the latch module is set in the self-check exemption area, and the self-check exemption area is an area in the function debug authority control circuit that does not perform a self-check operation during startup. Claim 10 An integrated circuit comprising a debug communication interface and a function debug authority control circuit of any one of claims 1 to 8, wherein the debug communication interface is connected to a debug authority control module included in the function debug authority control circuit and is used to establish a communication connection between the integrated circuit and a test device when performing function debugging on the integrated circuit. Claim 11 An integrated circuit debug system comprising a test device and the integrated circuit of claim 10, wherein the test device is connected to a debug communication interface included in the integrated circuit.

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