Smart IC substrate, smart IC module and IC card including the same

Abstract

A smart IC substrate according to an embodiment comprises: a substrate including a first surface and a second surface opposite to the first surface; and a circuit pattern disposed on at least one of the first surface and the second surface, wherein the circuit pattern comprises a first metal layer and a second metal layer on the first metal layer, and the second metal layer has an L* value of 83 to 87, an a* value of 12.0 to 13.5, and a b* value of 15 to 20 in the CIE L*a*b* color space.

Description

Technology Field

[0001] The embodiments relate to a smart IC substrate, a smart IC module, and an IC card including the same. Background Technology

[0002] An IC card can be formed by combining a smart IC module and a card module.

[0003] A smart IC module is a circuit board equipped with an IC that stores personal security information required for electronic ID cards, credit cards, SIM cards, etc., and it can transmit this information to a reader in the form of an electrical signal.

[0004] The above smart IC module can be classified into single type and dual type depending on the structure of the substrate, and can be classified into contact, contactless, hybrid, and combi cards depending on the form of the card used.

[0005] Specifically, contact-type smart IC modules transmit and receive information through physical contact, contactless smart IC modules transmit and receive information without physical contact using NFC (transportation card, etc.) functions, and combi-smart IC modules and hybrid smart IC modules include both physical contact functions and NFC functions without physical contact.

[0006] Accordingly, the smart IC module may include a contact surface and a bonding surface, a chip is placed on the bonding surface, and the contact surface may be in direct or indirect contact with another device from the outside.

[0007] Recently, research is being conducted on varying the colors of circuit patterns on the contact surface to improve the design freedom of IC cards.

[0008] However, when attempting to implement the above color, there is a problem in that the reliability of the circuit pattern is reduced due to changes in the physical characteristics of the top layer.

[0009] In addition, there is a problem in that the process of manufacturing the above-mentioned smart IC module is unnecessarily increased.

[0010] Therefore, a smart IC substrate with a new structure capable of solving the above-mentioned problems, a smart IC module, and an IC card including the same are required. The problem to be solved

[0011] The embodiment aims to provide a smart IC substrate, a smart IC module, and an IC card including the same, which can improve user visibility and design freedom by implementing the contact surface with a color having color coordinates within a set range. means of solving the problem

[0012] A smart IC substrate according to an embodiment comprises: a substrate including a first surface and a second surface opposite to the first surface; and a circuit pattern disposed on the first surface of the substrate, wherein the circuit pattern comprises a first metal layer disposed on the first surface; and a second metal layer disposed on the first metal layer, wherein the second metal layer comprises a copper-gold (Cu-Au) alloy, and the copper-gold (Cu-Au) alloy comprises 40% to 60% by weight of copper based on the total weight of the second metal layer.

[0013] In addition, the second metal layer has an L* value of 83 to 87, an a* value of 12.0 to 13.5, and a b* value of 15 to 20 in the CIE L*a*b* color space.

[0014] In addition, the first metal layer contains copper (Cu).

[0015] In addition, the smart IC substrate further includes an intermediate layer disposed between the first metal layer and the second metal layer.

[0016] In addition, the above intermediate layer contains nickel (Ni).

[0017] In addition, the intermediate layer is disposed on the upper and side surfaces of the first metal layer, and the second metal layer is disposed surrounding the intermediate layer.

[0018] In addition, the thickness of the second metal layer is 0.3% to 15% of the thickness of the intermediate layer.

[0019] In addition, the thickness of the intermediate layer is 1 μm to 5 μm, and the thickness of the second metal layer is 0.03 μm to 0.1 μm.

[0020] In addition, the first surface is a contact surface of the smart IC substrate.

[0021] Additionally, the smart IC substrate further comprises a second circuit pattern disposed under the second surface of the substrate, wherein the circuit pattern is a first circuit pattern, and the second circuit pattern comprises a third metal layer disposed under the second surface; and a fourth metal layer disposed under the third metal layer.

[0022] In addition, the first metal layer and the third metal layer contain the same metal material, and the second metal layer and the fourth metal layer contain different metal materials.

[0023] In addition, the second metal layer and the fourth metal layer have different colors from each other.

[0024] In addition, the fourth metal layer contains gold (Au) or palladium (Pd).

[0025] Additionally, the smart IC substrate further comprises a first intermediate layer disposed between the first metal layer and the second metal layer; and a second intermediate layer disposed between the third metal layer and the fourth metal layer, wherein the first intermediate layer comprises nickel (Ni), and the second intermediate layer comprises a nickel-gold (Ni-Au) alloy or a nickel-palladium (Ni-Pd) alloy.

[0026] In addition, the third metal layer and the fourth metal layer are in direct contact with each other. Effects of the invention

[0027] The smart IC substrate and smart IC substrate module according to the embodiment can form various colors for the contact surface and the bonding surface.

[0028] The smart IC substrate and smart IC substrate module according to the embodiment can implement the color of the contact surface as a color having color coordinates of a set range.

[0029] Specifically, a metal layer disposed on the outermost side of a circuit pattern is formed from a copper-gold alloy in a set weight percentage, thereby enabling a rose gold color to be realized at the contact surface of a smart IC substrate and a smart IC substrate module.

[0030] Accordingly, the aesthetic appeal of the color can be enhanced while preventing corrosion of the circuit pattern at the contact surface visible to the user from the outside.

[0031] In addition, the smart IC substrate and smart IC substrate module according to the embodiment may have different colors for the contact surface and the bonding surface.

[0032] In other words, the color of the circuit pattern on the contact surface visible to the user from the outside and the bonding surface where the chip is placed can be different.

[0033] In other words, the color of the contact surface visible to the user from the outside can be implemented as a color that enhances the user's aesthetic sense through a metal layer having color coordinates within a set range. Additionally, the bonding surface, which is not visible to the user from the outside, can be formed as a single layer or multiple layers to protect the circuit pattern, and can be formed regardless of the color of the circuit pattern.

[0034] Accordingly, by forming the circuit patterns of the contact surface and the bonding surface with different materials, the metal layer can be formed using a process method suitable for the purpose of each surface, thereby improving process efficiency. Brief explanation of the drawing

[0035] FIG. 1 is a top view of the first surface of a smart IC substrate according to an embodiment. FIGS. 2 and FIGS. 3 are top view drawings of a second surface of a smart IC substrate according to an embodiment. FIGS. 4 and 5 are top view drawings of the bonding surface of a smart IC module in which a chip is placed on the second surface of a smart IC substrate. Figure 6 is a cross-sectional view of the AA' region of Figure 4. Figures 7 and 8 are cross-sectional views of the AA' region of Figure 5. FIG. 9 is a diagram illustrating the color coordinates of a circuit pattern of a smart IC substrate according to an embodiment. FIG. 10 is a top view of an IC card according to an embodiment. Specific details for implementing the invention

[0036] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. However, the technical concept of the present invention is not limited to some of the described embodiments but can be implemented in various different forms, and within the scope of the technical concept of the present invention, one or more of the components among the embodiments may be selectively combined or substituted.

[0037] In addition, terms used in the embodiments of the present invention (including technical and scientific terms) may be interpreted in a sense that is generally understood by those skilled in the art to which the present invention belongs, unless explicitly and specifically defined otherwise. Terms that are commonly used, such as terms defined in advance, may be interpreted in consideration of their meaning in the context of the relevant technology.

[0038] Furthermore, the terms used in the embodiments of the present invention are for describing the embodiments and are not intended to limit the present invention. In this specification, the singular form may include the plural form unless specifically stated otherwise in the text, and when described as “A and at least one of B and C (or more than one),” it may include one or more of all combinations that can be formed from A, B, and C.

[0039] In addition, terms such as first, second, A, B, (a), (b), etc., may be used when describing the components of the embodiments of the present invention. These terms are used merely to distinguish the components from other components and are not intended to limit the essence, order, or sequence of the components.

[0040] And, where it is stated that a component is 'connected', 'combined', or 'joined' to another component, this may include not only cases where the component is directly connected, combined, or joined to the other component, but also cases where it is 'connected', 'combined', or 'joined' due to another component located between the component and the other component.

[0041] Additionally, where described as being formed or placed on the "top or bottom" of each component, the top or bottom includes not only cases where two components are in direct contact with each other, but also cases where one or more other components are formed or placed between the two components.

[0042] In addition, when expressed as “up” or “down,” it can include the meaning of a downward direction as well as an upward direction relative to a single component.

[0044] Hereinafter, a smart IC substrate, a smart IC module, and an IC card including the same according to an embodiment will be described with reference to the drawings.

[0046] FIGS. 1 to 8 are drawings illustrating a top view of one side and the other side of a smart IC substrate and a cross-sectional view of a smart IC module according to an embodiment.

[0047] Referring to FIGS. 1 to 3, the smart IC substrate (1000) may include one side and another side opposite to the one side. A chip may be mounted on the smart IC substrate (1000) to form a smart IC module. The one side may be the contact side of the smart IC substrate (1000). Additionally, the other side may be the bonding side of the smart IC substrate (1200).

[0048] That is, the above-mentioned one side may be a surface capable of recognizing information of a smart IC module through direct or indirect contact with the IC card, and the other side may be a surface on which a chip is mounted and which is bonded to the main body of the IC card.

[0049] The smart IC substrate (1000) may include a substrate (100) and a plurality of circuit patterns.

[0050] The above substrate (100) may include a resin material. The above substrate (100) may include a first surface (1S) and a second surface (2S) opposite to the first surface (1S). The first surface (1S) may be defined as a surface corresponding to the contact surface of the smart IC substrate (1000) described above, i.e., the contact surface of the smart IC substrate (1000), and the second surface (2S) may be defined as a surface corresponding to the bonding surface of the smart IC substrate (1000) described above.

[0051] The above material (100) may include a prepreg containing glass fibers. Specifically, the above material (100) may include an epoxy resin and a material in which glass fibers and a silicone-based filler (Si filler) are dispersed in the epoxy resin.

[0052] Additionally, the above substrate (100) may be rigid or flexible. For example, the above substrate (100) may include glass or plastic. Specifically, the above substrate (100) may include chemically strengthened / semi-strengthened glass such as soda lime glass or aluminosilicate glass, or strengthened or flexible plastic such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG) polycarbonate (PC), or sapphire.

[0053] Additionally, the above substrate (100) may include a photoisotropic film. For example, the above substrate (100) may include COC (Cyclic Olefin Copolymer), COP (Cyclic Olefin Polymer), photoisotropic polycarbonate (PC), or photoisotropic polymethyl methacrylate (PMMA), etc.

[0054] Additionally, the above-mentioned substrate (100) may be bent while having a partially curved surface. That is, the substrate (100) may be bent while having a partially flat surface and a partially curved surface. Specifically, the end of the above-mentioned substrate (100) may be bent while having a curved surface or may be bent or curved while having a surface that includes random curvature.

[0055] Additionally, the above substrate (100) may be a flexible substrate having flexible properties. Additionally, the above substrate (100) may be a curved or bent substrate.

[0056] An adhesive layer (200) may be disposed on at least one of the first surface (1S) and the second surface (2S) of the above substrate (100). The adhesive layer (200) may be disposed on the front surface of the first surface (1S) and the second surface (2S) of the above substrate (100). Specifically, the adhesive layer (200) may be disposed on the front surface of the first surface (1S) and the second surface (2S) of the above substrate (100), excluding the area where a via is formed.

[0057] The adhesive layer (200) may include a resin material. For example, the adhesive layer (200) may include at least one of epoxy resin, acrylic resin, and polyimide resin. Additionally, the adhesive layer (20) may further include additives such as natural rubber, plasticizers, curing agents, and flame retardants such as phosphorus-based agents to impart flexibility to the adhesive layer (200).

[0058] The adhesive layer (200) may have a thickness within a set range. For example, the thickness of the adhesive layer (200) may be 15㎛ to 30㎛. If the thickness of the adhesive layer (200) is less than 15㎛, the adhesive strength may decrease, causing the circuit pattern on the adhesive layer to peel off. Additionally, if the thickness of the adhesive layer (200) exceeds 30㎛, the overall thickness of the smart IC substrate may be increased by the adhesive layer.

[0060] A circuit pattern (300) may be disposed on the above substrate (100). Specifically, a circuit pattern (300) may be disposed on at least one of the first surface (1S) and the second surface (2S) of the above substrate (100).

[0061] For example, with reference to FIGS. 1, 2, 4 and 6, a circuit pattern may be disposed on only one of the first surface (1S) and the second surface (2S) of the substrate (100). Specifically, a circuit pattern (300) disposed on the adhesive layer (200) may be disposed on the first surface (1S) of the substrate (100), and the adhesive layer (200) and the circuit pattern (300) may not be disposed on the second surface (2S) of the substrate (100).

[0062] Alternatively, referring to FIGS. 1, FIGS. 3, FIGS. 5 and FIGS. 7, a circuit pattern may be disposed on the first surface (1S) and the second surface (2S) of the substrate (100), respectively. Specifically, a first circuit pattern (310) disposed on the adhesive layer (200) may be disposed on the first surface (1S) of the substrate (100), and a second circuit pattern (320) disposed on the adhesive layer (200) may be disposed on the second surface (2S) of the substrate (100).

[0063] The above circuit pattern (300, 310) may include a plurality of circuit patterns. That is, the circuit pattern (300, 310) disposed on the first surface (1S) of the above substrate (100) may include a plurality of circuit patterns.

[0064] Specifically, the circuit pattern (300, 310) may include a first-1 circuit pattern (351), a first-2 circuit pattern (352), a first-3 circuit pattern (353), a first-4 circuit pattern (354), a first-5 circuit pattern (355), and a first-6 circuit pattern (356).

[0065] In FIG. 1, the first-1 circuit pattern (351), the first-2 circuit pattern (352), the first-3 circuit pattern (353), the first-4 circuit pattern (354), the first-5 circuit pattern (355) and the first-6 circuit pattern (356) are illustrated, but the embodiments are not limited thereto, and the circuit patterns (300, 310) may include fewer than 6 or more than 6 circuit patterns.

[0066] The above 1-1 circuit pattern (351), the above 1-2 circuit pattern (352), the above 1-3 circuit pattern (353), the above 1-4 circuit pattern (354), the above 1-5 circuit pattern (355) and the above 1-6 circuit pattern (356) may be spaced apart from each other.

[0067] Specifically, space areas (SA) in which no circuit patterns are placed are formed between the first-1 circuit pattern (351), the first-2 circuit pattern (352), the first-3 circuit pattern (353), the first-4 circuit pattern (354), the first-5 circuit pattern (355) and the first-6 circuit pattern (356), and the first-1 circuit pattern (351), the first-2 circuit pattern (352), the first-3 circuit pattern (353), the first-4 circuit pattern (354), the first-5 circuit pattern (355) and the first-6 circuit pattern (356) can be spaced apart from each other by the space areas (SA). That is, the spacer area (SA) may be the interval between the first-1 circuit pattern (351), the first-2 circuit pattern (352), the first-3 circuit pattern (353), the first-4 circuit pattern (354), the first-5 circuit pattern (355), and the first-6 circuit pattern (356).

[0068] The above spacer region (SA) may have a set size. For example, the above spacer region (SA) may be 100 μm to 250 μm.

[0069] Accordingly, the first-1 circuit pattern (351), the first-2 circuit pattern (352), the first-3 circuit pattern (353), the first-4 circuit pattern (354), the first-5 circuit pattern (355) and the first-6 circuit pattern (356) may be arranged so as not to be electrically connected on the first surface (1S) of the substrate (100).

[0070] The above substrate (100) may include a plurality of vias (V). Referring to FIGS. 2 and FIGS. 3, a plurality of vias (V) may be formed in the above substrate (100). The plurality of vias (V) may each be positioned in a location that overlaps with the thickness direction of the above substrate (100) with the above circuit pattern (351), the above circuit pattern (352), the above circuit pattern (353), the above circuit pattern (354), the above circuit pattern (355), and the above circuit pattern (356).

[0071] Through the above via (V), the chip (C) placed on the second surface (2S) and the circuit pattern (300, 310) placed on the first surface (1S) can be electrically connected.

[0072] Accordingly, a smart IC module (2000) can be formed as shown in FIGS. 4 and FIGS. 5.

[0074] The above circuit pattern (300, 310, 320) may include a first metal layer (301) and a second metal layer (302). Specifically, the above circuit pattern (300, 310, 320) may include a first metal layer (301) on the adhesive layer (200) and a second metal layer (302) on the first metal layer (301).

[0075] The first metal layer (301) may include a metal material. Specifically, the first metal layer (301) may include a metal material with high electrical conductivity. For example, the first metal layer (301) may include at least one material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). Preferably, the first metal layer (301) may include copper (Cu).

[0076] The first metal layer (301) may have a thickness within a set range. Specifically, the thickness of the first metal layer (301) may be 35 μm to 70 μm. If the thickness of the first metal layer (301) is less than 35 μm, the conductivity of the first metal layer (301) may decrease, and electrical characteristics may be degraded. Additionally, if the thickness of the first metal layer (301) is greater than 70 μm, the overall thickness of the smart IC substrate may increase due to the increase in the thickness of the first metal layer (301).

[0077] The second metal layer (302) may be disposed on the first metal layer (301). The second metal layer (302) may be disposed surrounding the first metal layer (301). That is, the second metal layer (302) may be disposed on the front surface of the first metal layer (301).

[0078] The second metal layer (302) can be placed on the first metal layer (301) to protect the first metal layer (301). That is, the second metal layer (302) can be placed on the first metal layer (301) to prevent corrosion of the first metal layer (301). That is, the second metal layer (302) can serve as a protective layer for the circuit pattern (300, 310, 320).

[0079] Additionally, the second metal layer (302) is disposed on the first metal layer (301) to enable various colors to be implemented in the circuit pattern (300, 310, 320). That is, the circuit pattern (300, 310, 320) can have the color formed by the second metal layer (302) implemented by the second metal layer (302) disposed on the outermost side of the circuit pattern (300, 310, 320).

[0081] Referring to FIGS. 1, FIGS. 2, FIGS. 4 and FIGS. 6, the circuit pattern (300) may further include an intermediate layer (305).

[0082] The intermediate layer (305) may be disposed between the first metal layer (301) and the second metal layer (302). The intermediate layer (305) may be disposed surrounding the first metal layer (301). That is, the intermediate layer (305) may be disposed on the upper surface and side surface of the first metal layer (301). That is, the intermediate layer (305) may be disposed surrounding the first metal layer (301), and the second metal layer (302) may be disposed surrounding the intermediate layer (305).

[0083] The intermediate layer (302) is disposed between the first metal layer (301) and the second metal layer (302) to improve the adhesion between the first metal layer (301) and the second metal layer (302). That is, the intermediate layer (305) may be an adhesion-enhancing layer.

[0084] The intermediate layer (305) may have a different color from the first metal layer (301) and the second metal layer (302). Additionally, the intermediate layer (305) may contain a material different from the first metal layer (301) and the second metal layer (302).

[0085] For example, the intermediate layer (305) may include a metal. For example, the intermediate layer (305) may include nickel (Ni). Additionally, the second layer (L2) may include a binary alloy material.

[0086] The circuit pattern (300) may include a copper alloy. Specifically, the second metal layer (302) may include a copper alloy. Specifically, the second metal layer (302) may include a copper-gold (Cu-Au) alloy.

[0087] The second metal layer (302) may include a copper-gold (Cu-Au) alloy having color coordinates of a set range. Referring to FIG. 9, the second metal layer (302) may include a copper-gold (Cu-Au) alloy having an L* value of 83 to 87, an a* value of 12.0 to 13.5, and a b* value of 15 to 20 in the CIE L*a*b* color space.

[0088] That is, the second metal layer (302) can realize the color of area A in FIG. 9. Specifically, the second metal layer (302) can realize a rose gold color that combines rose and gold colors by having a similar redness (a* value) and a similar or increased yellowness (b* value) when compared to pure copper.

[0089] The second metal layer (302) may include a copper-gold (Cu-Au) alloy containing 30 weight% or more of copper when the total weight% of the second metal layer (302) is 100 weight%. Specifically, the second metal layer (302) may include a copper-gold (Cu-Au) alloy containing 35 weight% or more of copper. Even more specifically, the second metal layer (302) may include a copper-gold (Cu-Au) alloy containing 40 weight% or more of copper. Even more specifically, the second metal layer (302) may include a copper-gold (Cu-Au) alloy containing 50 weight% or more of copper. For example, the second metal layer (302) may include a copper-gold (Cu-Au) alloy containing 30 weight% to 90 weight% of copper. In detail, the second metal layer (302) may comprise a copper-gold (Cu-Au) alloy containing 30% to 80% by weight of copper. More specifically, the second metal layer (302) may comprise a copper-gold (Cu-Au) alloy containing 35% to 70% by weight of copper. More specifically, the second metal layer (302) may comprise a copper-gold (Cu-Au) alloy containing 35% to 60% by weight of copper.

[0090] Meanwhile, the second metal layer (302) may have a small amount of impurities such as silver, nickel, aluminum, or chromium added in addition to copper and gold.

[0091] If the copper in the second metal layer (302) is less than 30 weight%, the redness (a* value) of the copper-gold (Cu-Au) alloy decreases, making it impossible to achieve the desired color coordinate range. Additionally, if the copper in the second metal layer (302) is more than 90 weight%, the yellowness (b* value) of the copper-gold (Cu-Au) alloy decreases, making it impossible to achieve the desired color coordinate range, and due to changes in the physical properties of the second metal layer (302), the first metal layer cannot be effectively protected through the second metal layer.

[0092] In addition, if the copper of the second metal layer (302) exceeds 60 weight% under some environmental conditions, the color of the color coordinate range described above can be achieved, but red discoloration may occur under the reliability test conditions of the adverse conditions below, or a change in physical properties such as a resistance value exceeding 0.5Ω may occur, so it is preferable that the copper of the second metal layer (302) be 60 weight% or less.

[0093] 2 Gas Test Conditions: Hydrogen sulfide (H2S) 100 ppb, Sulfur dioxide (SO2) 500 ppb, 5℃, 75% RH 240Hr

[0095] The second metal layer (302) and the intermediate layer (305) may be arranged with different thicknesses. Specifically, the thickness (T1) of the intermediate layer (305) may be greater than the thickness (T2) of the second metal layer (302). For example, the thickness of the second metal layer (302) may be 0.3% to 15% of the thickness of the intermediate layer (305).

[0096] For example, the thickness of the intermediate layer (305) may be 0.5 μm or more. Specifically, the thickness of the intermediate layer (305) may be 1 μm to 7 μm. More specifically, the thickness of the intermediate layer (305) may be 1 μm to 5 μm.

[0097] Additionally, the thickness of the second metal layer (302) may be 0.01 μm or more. Specifically, the thickness of the second metal layer (302) may be 0.01 μm to 0.3 μm. Even more specifically, the thickness of the second metal layer (302) may be 0.03 μm to 0.1 μm.

[0098] If the thickness of the second metal layer (302) is formed to be less than 0.3% of the thickness of the intermediate layer (305), the thickness of the second metal layer (302) may be formed as too thin, making it difficult to implement the process, and the color of the second metal layer (302) may not be sufficiently visible.

[0099] Additionally, if the thickness of the second metal layer (302) is formed to be more than 15% of the thickness of the intermediate layer (305), the thickness of the second metal layer (302) becomes too thick, and the thickness of the circuit pattern may be increased. Accordingly, the thickness of the IC card to which the smart IC substrate is applied may be increased.

[0101] Referring to FIGS. 1, FIGS. 3, FIGS. 5, FIGS. 7 and FIGS. 8, the smart IC substrate may include the first circuit pattern (310) and the second circuit pattern (320).

[0102] The first circuit pattern (310) may include a first metal layer (301) and a second metal layer (302) on the first metal layer (301). Additionally, a first intermediate layer (305a) may be disposed between the first metal layer (301) and the second metal layer (302).

[0103] The second circuit pattern (320) may include a third metal layer (303) and a fourth metal layer (304) under the third metal layer (303). Additionally, a second intermediate layer (305b) may be disposed between the third metal layer (303) and the fourth metal layer (304).

[0104] The first metal layer (301) and the third metal layer (30) may contain the same or similar material. Alternatively, the first metal layer (301) and the third metal layer (303) may contain different materials.

[0105] Additionally, the first metal layer (301) and the third metal layer (30) may be formed with the same or similar thickness. Alternatively, the first metal layer (301) and the third metal layer (303) may be formed with different thicknesses.

[0106] The first intermediate layer (305a) and the second intermediate layer (305b) may contain the same or similar material. For example, the first intermediate layer (305a) and the second intermediate layer (305b) may contain nickel (Ni).

[0107] Additionally, the second metal layer (302) and the fourth metal layer (304) may contain the same or different materials.

[0108] For example, the second metal layer (302) and the fourth metal layer (304) may contain the same material.

[0109] In detail, the second metal layer (302) and the fourth metal layer (304) may comprise an alloy having the color coordinate range described above. In detail, the second metal layer (302) and the fourth metal layer (304) may comprise a copper-gold (Cu-Au) alloy having an L* value of 83 to 87, an a* value of 12.0 to 13.5, and a b* value of 15 to 20 in the CIE L*a*b* color space.

[0110] That is, the second metal layer (302) and the fourth metal layer (304) may both include a copper-gold (Cu-Au) alloy. Additionally, the second metal layer (302) and the fourth metal layer (304) may include a copper-gold (Cu-Au) alloy having the color coordinate range.

[0112] Alternatively, the second metal layer (302) and the fourth metal layer (304) may contain other materials.

[0113] In detail, the second metal layer (302) may comprise an alloy having the color coordinate range described above. In detail, the second metal layer (302) may comprise a copper-gold (Cu-Au) alloy having an L* value of 83 to 87, an a* value of 12.0 to 13.5, and a b* value of 15 to 20 in the CIE L*a*b* color space.

[0114] Additionally, the fourth metal layer (304) may include gold (Au) or palladium (Pd). That is, after forming a second intermediate layer (305b) under the third metal layer (303), a gold (Au) layer may be placed under the second intermediate layer (305b), or after forming a second intermediate layer (305b) under the third metal layer (301), a palladium layer may be placed under the second intermediate layer (305b). In this case, if the second intermediate layer (305b) includes nickel, a nickel-gold alloy layer may be formed between the second intermediate layer (305b) and the gold layer, and a nickel-palladium alloy layer may be formed between the second intermediate layer (305b) and the palladium layer.

[0115] Accordingly, the first circuit pattern (310) and the second circuit pattern (320) can be formed in different colors. That is, the first circuit pattern (310) and the second circuit pattern (320) can be formed in colors having different coordinates in the CIE L*a*b* color space.

[0116] The fourth metal layer (304) is a layer placed on the bonding surface of the smart IC substrate and is not visible to the user from the outside. Accordingly, the fourth metal layer (304) is not formed from a separate alloy material, but is formed mainly from a material for protecting the third metal layer (303), thereby reducing process costs and improving process efficiency.

[0117] That is, an alloy layer having a set color coordinate range is formed only on the second metal layer (302) of the contact surface where color is implemented for the user, and a layer having a single material is formed on the fourth metal layer (304) of the bonding surface, so that the second metal layer and the fourth metal layer can be formed according to the use of each surface of the smart IC substrate. Accordingly, improved process efficiency can be achieved during manufacturing.

[0119] Referring to FIG. 8, the first circuit pattern (310) and the second circuit pattern (320) may include different layers.

[0120] The first circuit pattern (310) may include a first metal layer (301) and a second metal layer (302). Additionally, an intermediate layer (305) may be disposed between the first metal layer (301) and the second metal layer (302).

[0121] The second circuit pattern (320) may include a third metal layer (303) and a fourth metal layer (304). The fourth metal layer (304) may be placed directly under the third metal layer (303). Specifically, the fourth metal layer (304) may be placed in contact with the third metal layer (303). That is, the fourth metal layer (304) may be placed surrounding the third metal layer (303). That is, the fourth metal layer (304) may be placed on the lower surface and side surface of the third metal layer (303).

[0122] The third metal layer (303) and the fourth metal layer (304) may contain different materials. Additionally, the third metal layer (303) and the fourth metal layer (304) may have different thicknesses.

[0123] That is, the second circuit pattern (320) may not include a separate intermediate layer, unlike the first circuit pattern (310).

[0124] The second metal layer (302) may include a material different from at least one of the third metal layer (303) and the fourth metal layer (304).

[0125] For example, the second metal layer (302) may include an alloy having the color coordinate range described above. Specifically, the second metal layer (302) may include a copper-gold (Cu-Au) alloy having an L* value of 83 to 87, an a* value of 12.0 to 13.5, and a b* value of 15 to 20 in the CIE L*a*b* color space.

[0126] The fourth metal layer (304) may include a binary alloy. Specifically, the fourth metal layer (304) may include a nickel-gold (Ni-Au) alloy or a nickel-palladium (Ni-Pd) alloy.

[0127] Accordingly, the first circuit pattern (310) and the second circuit pattern (320) can be formed in different colors.

[0128] The fourth metal layer (304) is a layer placed on the bonding surface of the smart IC substrate and is not visible to the user from the outside. Accordingly, the fourth metal layer (304) can be formed in a single process using a material for protecting the first metal layer (301), thereby reducing process costs and improving process efficiency.

[0129] That is, the second metal layer (302) of the contact surface where color is implemented for the user is formed as a multilayer including an alloy layer having a color coordinate range set only on the second metal layer (302), and the fourth metal layer (304) of the bonding surface is formed as a single layer having an alloy material, so that the second metal layer can be formed according to the use of each surface of the smart IC substrate. Accordingly, improved process efficiency can be achieved during manufacturing.

[0131] The smart IC substrate and smart IC substrate module according to the embodiment can form various colors for the contact surface and the bonding surface.

[0132] The smart IC substrate and smart IC substrate module according to the embodiment can implement the color of the contact surface as a color having color coordinates of a set range.

[0133] Specifically, a metal layer disposed on the outermost side of a circuit pattern is formed from a copper-gold alloy in a set weight percentage, thereby enabling a rose gold color to be realized at the contact surface of a smart IC substrate and a smart IC substrate module.

[0134] Accordingly, the aesthetic appeal of the color can be enhanced while preventing corrosion of the circuit pattern at the contact surface visible to the user from the outside.

[0135] In addition, the smart IC substrate and smart IC substrate module according to the embodiment may have different colors for the contact surface and the bonding surface.

[0136] In other words, the color of the circuit pattern on the contact surface visible to the user from the outside and the bonding surface where the chip is placed can be different.

[0137] In other words, the color of the contact surface visible to the user from the outside can be implemented as a color that enhances the user's aesthetic sense through a metal layer having color coordinates within a set range. Additionally, the bonding surface, which is not visible to the user from the outside, can be formed as a single layer or multiple layers to protect the circuit pattern, and can be formed regardless of the color of the circuit pattern.

[0138] Accordingly, by forming the circuit patterns of the contact surface and the bonding surface with different materials, the metal layer can be formed using a process method suitable for the purpose of each surface, thereby improving process efficiency.

[0140] FIG. 10 is a top view of an IC card to which a smart IC substrate according to an embodiment is applied.

[0141] Referring to FIG. 10, the IC card (3000) may include a card body (3100), a smart IC board module (2000) accommodated in the card body (3100), a chip (3300), a microcontroller unit (MCU, 3400), a connection circuit pattern (3350) electrically connecting the chip (3300) and the microcontroller unit (3400), a fingerprint sensor (3500), an antenna (3600), and a battery (3700).

[0142] The smart IC substrate module (2000) can be accommodated in the card body (3100). Specifically, an opening (OA) for accommodating the smart IC substrate module (2000) is formed in the card body (3100), and the smart IC substrate module (2000) can be inserted and bonded into the opening (OA).

[0143] Accordingly, either one of the sides of the smart IC substrate module (2000) and the other side may be exposed to the outside of the IC card.

[0144] The IC card may include a fingerprint sensor (3500). The fingerprint sensor (3500) can recognize the user's fingerprint and match it with fingerprint information stored in the chip (3300).

[0145] That is, one or more fingerprint information of a predetermined user is stored in the chip (3300), and the fingerprint recognized through the fingerprint sensor (3500) can be matched with the fingerprint information stored in the chip (3300).

[0146] For example, when a user's finger comes into contact with the fingerprint sensor (3500), power is supplied from the battery (3700) to the micro control unit (3400), and the fingerprint sensor (3500), which is powered by the micro control unit (3400), can be driven.

[0147] Next, the micro control unit (3300) receives fingerprint information recognized through the fingerprint sensor (3500), and the authentication process of the recognized fingerprint information can be carried out.

[0148] Next, when the recognized fingerprint information and the fingerprint information stored in the chip (3300) match, the smart IC board module (2000) connected to the chip (3300) and acting as a contact pad is activated, and the function of the IC card can also be activated.

[0149] On the other hand, if the recognized fingerprint information and the fingerprint information stored in the chip (3300) do not match, the smart IC substrate (2000) connected to the chip (1300) is deactivated, and the function of the IC card may also be deactivated.

[0150] However, the embodiments are not limited thereto, and the IC card does not include a fingerprint sensor (3500), and the IC card's functions can be activated without separate fingerprint authentication.

[0151] Additionally, the IC card may include an antenna (3600). Accordingly, the IC card can operate as a contactless card. That is, through the antenna of the IC card, information can be transmitted and received wirelessly with a server even in a contactless state with the card reader.

[0152] However, the embodiments are not limited thereto, and the IC card may not include an antenna (3600), and the IC card may operate as a contact card. That is, the IC card may be inserted into a reader and transmit and receive information to and from a server through contact with a circuit board.

[0154] The features, structures, effects, etc. described in the above-described embodiments are included in at least one embodiment of the present invention and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment may be combined or modified and implemented in other embodiments by a person skilled in the art to which the embodiments belong. Therefore, details regarding such combinations and modifications should be interpreted as being included within the scope of the present invention.

[0155] Furthermore, although the invention has been described above with reference to embodiments, this is merely illustrative and does not limit the invention. Those skilled in the art will understand that various modifications and applications not exemplified above are possible within the scope of the essential characteristics of the embodiments. For example, each component specifically shown in the embodiments may be modified and implemented. Differences related to such modifications and applications should be interpreted as being included within the scope of the invention as defined in the appended claims.

Claims

Claim 1 A smart IC substrate comprising: a substrate including a first surface and a second surface opposite to the first surface; and a circuit pattern disposed on the first surface of the substrate, wherein the circuit pattern comprises: a first metal layer disposed on the first surface; and a second metal layer disposed on the first metal layer, wherein the second metal layer comprises a copper-gold (Cu-Au) alloy, and the copper-gold (Cu-Au) alloy comprises 40% to 60% by weight of copper based on the total weight of the second metal layer. Claim 2 In claim 1, the second metal layer is a smart IC substrate having an L* value of 83 to 87, an a* value of 12.0 to 13.5, and a b* value of 15 to 20 in the CIE L*a*b* color space. Claim 3 In claim 1, the first metal layer comprises a smart IC substrate containing copper (Cu). Claim 4 A smart IC substrate according to claim 1, further comprising an intermediate layer disposed between the first metal layer and the second metal layer. Claim 5 In paragraph 4, the intermediate layer is a smart IC substrate containing nickel (Ni). Claim 6 A smart IC substrate according to claim 4, wherein the intermediate layer is disposed on the upper and side surfaces of the first metal layer, and the second metal layer is disposed surrounding the intermediate layer. Claim 7 A smart IC substrate according to claim 4, wherein the thickness of the second metal layer is 0.3% to 15% of the thickness of the intermediate layer. Claim 8 A smart IC substrate according to claim 4, wherein the thickness of the intermediate layer is 1 μm to 5 μm and the thickness of the second metal layer is 0.03 μm to 0.1 μm. Claim 9 In claim 1, the first surface is a smart IC substrate that is a contact surface of the smart IC substrate. Claim 10 A smart IC substrate according to claim 1, further comprising a second circuit pattern disposed under the second surface of the above-described circuit, wherein the circuit pattern is a first circuit pattern, and the second circuit pattern comprises a third metal layer disposed under the second surface; and a fourth metal layer disposed under the third metal layer. Claim 11 A smart IC substrate according to claim 10, wherein the first metal layer and the third metal layer comprise the same metal material, and the second metal layer and the fourth metal layer comprise different metal materials. Claim 12 In claim 10, the smart IC substrate having the second metal layer and the fourth metal layer have different colors. Claim 13 In claim 10, the above-mentioned fourth metal layer comprises gold (Au) or palladium (Pd) and is a smart IC substrate. Claim 14 A smart IC substrate according to claim 10, further comprising: a first intermediate layer disposed between the first metal layer and the second metal layer; and a second intermediate layer disposed between the third metal layer and the fourth metal layer, wherein the first intermediate layer comprises nickel (Ni), and the second intermediate layer comprises a nickel-gold (Ni-Au) alloy or a nickel-palladium (Ni-Pd) alloy. Claim 15 In claim 10, the smart IC substrate in which the third metal layer and the fourth metal layer are in direct contact with each other. Claim 16 A smart IC module comprising a smart IC substrate according to claim 1; and a chip disposed on the second surface of the substrate.

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