3D Architecture for Large-Scale Quantum Processors

Abstract

The present specification describes a superconducting quantum processor package comprising: a package substrate having an external connector port; an interposer having a first surface and a second surface facing each other, wherein the first surface of the interposer faces the package substrate and the interposer mounts a first quantum reader coupled to the external connector port; a first qubit substrate having an upper surface and a lower surface facing each other, wherein the lower surface of the first qubit substrate faces the second surface of the interposer and the first qubit substrate mounts a first qubit circuit having interleaved qubits and couplers, wherein the first qubit circuit is coupled to the first quantum reader and the first qubit circuit, the first quantum reader, and the external connector port form a first read communication path; and a first amplifier coupled between the first quantum reader and the external connector port on the first read communication path to amplify a read signal from the first quantum reader.

Description

Technology Field

[0001] The present invention generally relates to a three-dimensional architecture for a superconducting quantum processor. This application claims the benefit of priority to U.S. Provisional Application No. 63 / 621,143 filed January 16, 2024, the entire contents of which are incorporated herein by reference. Background Technology

[0002] Superconducting qubit technology is a leading platform for developing large-scale quantum processors. Superconducting quantum processors are electronic devices fabricated using advanced nanofabrication processes on special substrates such as high-resistance silicon or sapphire. These fabrication processes include lithography, deposition, and etching steps widely used in the semiconductor industry.

[0003] Currently, the most advanced quantum processors typically feature tens to hundreds of superconducting qubits fabricated using academic or prototype nanofabrication facilities with low reproducibility and relatively low yields. Furthermore, until recently, quantum chips for superconducting qubits have primarily been fabricated in planar structures where the qubits and other components on the chip are placed on a single substrate. As the number of qubits increases, more surface area is required, and the limits of 2D architecture have already been reached. To accommodate more qubits, it is necessary to scale to an integrated 3D architecture. It should be noted that useful quantum processors require the fabrication of tens of thousands to millions of qubits with high yield and reliability.

[0004] Therefore, improvement is needed. means of solving the problem

[0005] The present specification describes an advanced nanofabrication and three-dimensional packaging architecture for a large-scale superconducting quantum processor. As used in the present specification, the term “large-scale” is understood to mean a quantum processor comprising 100 or more qubits, including but not limited to 500 qubits, 1,000 qubits, 10,000 qubits, 100,000 qubits, etc.

[0006] Generally, in some embodiments, the subject of the present disclosure comprises: a package substrate having an external connector port; an interposer having a first surface and a second surface facing each other, wherein the first surface of the interposer faces the package substrate, and the interposer mounts a first quantum reader coupled to the external connector port; a first qubit substrate having an upper surface and a lower surface facing each other, wherein the lower surface of the first qubit substrate faces the second surface of the interposer, and the first qubit substrate mounts a first qubit circuit having interleaved qubits and couplers, wherein the first qubit circuit is coupled to the first quantum reader, and the first qubit circuit, the first quantum reader, and the external connector port form a first read communication path; It can be implemented as a superconducting quantum processor package comprising: a first amplifier coupled between the first quantum reading device and the external connector port on the first reading communication path to amplify a reading signal from the first quantum reading device.

[0007] An embodiment of the above superconducting quantum processor package may include one or more of the following features described herein or other features. For example, in some embodiments, the first amplifier is mounted on the interposer.

[0008] In some embodiments, the package further comprises a first amplifier substrate having an upper surface and a lower surface facing each other, the lower surface of the first amplifier substrate facing a second surface of the interposer, the first amplifier device is mounted on the first amplifier substrate, and the first amplifier substrate is separated from the first qubit substrate and adjacent to the first qubit substrate.

[0009] In some embodiments, the first amplification device includes at least one amplifier and at least one circulator coupled thereto.

[0010] In some embodiments, the circulator is coupled between the external connector port, the first quantum reader, and the amplifier.

[0011] In some embodiments, the first amplifier includes a Josephson Parametric Amplifier (JPA).

[0012] In some embodiments, the interposer is bonded to the package substrate via a ball grid array (BGA).

[0013] In some embodiments, the first qubit substrate is bonded to the interposer through a first grid of superconducting microspheres.

[0014] In some embodiments, the first quantum readout device includes a plurality of resonators coupled to a transmission line.

[0015] In some embodiments, the resonators are arranged in a curved pattern and are aligned with the qubits in the first qubit circuit arranged in the curved pattern.

[0016] In some embodiments, the first quantum readout device includes at least one filter.

[0017] In some embodiments, the external connector port is bidirectional and performs reading and input.

[0018] In some embodiments, the external connector port is configured for a plurality of output lines, and the first amplifier includes a plurality of amplifiers corresponding to each of the plurality of output lines.

[0019] In some embodiments, the package comprises: a second quantum readout device mounted on the interposer; a second qubit substrate separated from the first qubit substrate and having an upper surface and a lower surface facing each other, wherein the lower surface of the second qubit substrate faces the second surface of the interposer, and the second qubit substrate mounts a second qubit circuit having interleaved qubits and couplers, and the second qubit circuit is coupled to the second quantum readout device; and a coupling substrate overlapping facing the upper surfaces of the first qubit substrate and the second qubit substrate, and comprising at least one coupler configured to selectively couple at least one qubit of the first qubit circuit with at least one qubit of the second qubit circuit.

[0020] In some embodiments, the package further includes a second amplifier coupled between the second quantum reader and the external connector port to amplify a read signal from the second qubit circuit.

[0021] In some embodiments, the package further includes a second amplifier coupled between the second quantum readout device and a second external connector port on the package substrate to amplify a read signal from the second qubit circuit.

[0022] In some embodiments, the package further comprises: third and fourth quantum readout devices mounted on the interposer; and third and fourth qubit substrates separated from the first and second qubit substrates, each mounted with a third and fourth qubit circuit, and each coupled to the third and fourth quantum readout devices. The coupling substrate overlaps with the first, second, third, and fourth qubit substrates, and the at least one coupler is configured to selectively couple at least one qubit from any one of the first, second, third, and fourth qubit circuits with at least one qubit from any other of the first, second, third, and fourth qubit circuits.

[0023] In some embodiments, the package further includes third and fourth amplification devices coupled to each of the third and fourth quantum readout devices.

[0024] In some embodiments, the second, third, and fourth amplification devices are mounted on the interposer.

[0025] In some embodiments, the second, third, and fourth amplifier devices are each mounted on the second, third, and fourth amplifier substrates, and the second, third, and fourth amplifier substrates are separated from the first, second, third, and fourth qubit substrates and seated on the interposer.

[0026] Details of one or more embodiments are described in the attached drawings and the following description. Other features will become apparent from the foregoing description, drawings, and claims. Brief explanation of the drawing

[0027] FIG. 1 is an exemplary embodiment of a flip-chip architecture for a superconducting quantum processor package; FIG. 2 is an exemplary embodiment of a flip-chip architecture having superconducting vias for a superconducting quantum processor package; FIG. 3 is an exemplary embodiment of a through silicon via having a scallop; FIG. 4 is an exemplary embodiment of qubit substrates coupled through a coupler in an interposer; FIG. 5 is an exemplary embodiment of qubit substrates coupled through a coupler in a coupling substrate; FIG. 6 is an exemplary embodiment of the qubit substrate connection architecture of FIG. 5, in which an interposer is wire-bonded to a package substrate; FIG. 7 is an exemplary embodiment of the qubit substrate connection architecture of FIG. 4, in which an interposer is wire-bonded to a package substrate; FIG. 8 is a planar schematic diagram of an exemplary quantum reader; FIG. 9 is a planar schematic diagram of an exemplary qubit circuit superimposed with the quantum reader of FIG. 8; FIG. 10 is a side schematic diagram of an exemplary embodiment for a superconducting quantum processor package having an amplification device within an interposer; FIG. 11 is a side schematic diagram of an exemplary embodiment for a superconducting quantum processor package having an amplification device within an amplifier substrate; FIGS. 12a and FIGS. 12b are exemplary embodiments of an amplification device; FIGS. 13a and 13b are side schematic diagrams of exemplary embodiments for a superconducting quantum processor package having a bidirectional external connector port; FIG. 14 is another exemplary embodiment of an amplification device; and FIGS. 15a to 15c are top views of exemplary layouts for a superconducting quantum processor package having a plurality of qubit substrates and one or more amplifier substrates. Specific details for implementing the invention

[0028] The present invention relates to advanced nanofabrication and three-dimensional packaging processes for large-scale superconducting quantum processors. This includes fabrication processes and architectures for superconducting multichip modules to reduce the impact of defects on yield. Furthermore, to address the need to increase the number of qubits within a limited area available on a substrate, it includes utilizing various vertical strategies such as through-silicon vias, flip-chips, the use of multiple interposers, and combinations of various vertical stacking. These processes are combined with the use of superconducting materials such as aluminum, indium, titanium nitride, and niobium in a series of subtractive patterning, etching, lithography, and deposition processes to yield ultra-low loss superconducting devices.

[0029] The present invention refers to a qubit circuit comprising interleaved qubits and couplers. In some embodiments, the qubit circuit used in some or all of the three-dimensional architectures described herein corresponds to the superconducting qubit circuit described in U.S. Patent No. 10,622,998, the entire contents of which are incorporated herein by reference. The qubits are superconducting qubits, including but not limited to charge qubits, flux qubits, phase qubits, fluxonium, transmons, differential transmons, etc. In other embodiments, the qubits are spin qubits or any quantum object having a plurality of discrete levels, of which at least two levels can be selectively addressed. The qubits may be fixed-frequency qubits or tunable-frequency qubits. The qubits may be configured to simultaneously represent information of one or more states and to operate on them. In some embodiments, the qubits are formed as quantum circuit elements including circuit elements such as a superconducting co-planar waveguide, a quantum LC oscillator, a superconducting quantum interference device (SQUID) (e.g., RF-SQUID or DC-SQUID). The quantum circuit elements may include circuit elements formed partially of a superconducting material (e.g., aluminum, titanium nitride, or niobium).

[0030] The above qubits are interleaved with couplers, and the couplers may also be implemented as qubits. In some embodiments, the couplers have the same architecture as the qubits. However, the qubits and couplers do not necessarily have to have the same architecture or type. The couplers may be frequency-variable and may be tuned by applying a frequency change signal to a transmission line coupled to each coupler.

[0031] The above qubits are mounted on a qubit substrate and may be formed on and / or within the substrate. The qubit substrate may be formed of a low-loss dielectric material suitable for quantum circuit elements, such as a silicon or sapphire wafer. Other materials may be used in addition to or instead of the above for the qubit substrate.

[0032] Referring to FIG. 1, a first exemplary embodiment of a superconducting quantum processor package (100) is illustrated. In this architecture, a qubit substrate (102) is attached to an interposer (104). The interposer (104) may be composed of one or more layers of a material, such as a low-loss dielectric material suitable for quantum circuits, such as single-crystal silicon or sapphire. The interposer (104) may include quantum circuit elements and / or classical circuit elements. The qubit substrate (102) may be bonded to the interposer (104) through an array of interconnects (108). In some embodiments, the interconnects (108) are bump bonds arranged to couple data between qubits on the qubit chip (102) and circuit elements on the interposer (104). The bump bonds may include a superconducting material to prevent energy loss and decoherence of the qubits located on the qubit substrate (102). For example, superconducting materials suitable for use as bump bonds include, but are not limited to, indium, lead, rhenium, palladium, or niobium having a thin gold layer. The bump bonds may be formed on interconnect pads on both sides of the qubit substrate (102) and the interposer (104). In some embodiments, the interconnects (108) are microspheres, for example, indium microspheres. Indium bump bonds are typically grown via electroplating or deposition and then face-to-face compression bonded using a flip-chip bonder, but the microspheres may be manually placed on the surface of the interposer (104) or the qubit substrate (102) and then the two are compressed together using a transfer stage. This eliminates the need to pattern and grow indium microbumps. Other materials and types of interconnects may also be used.

[0033] The interposer (104) is seated on a package substrate (106) within a cutout. In some embodiments, the package substrate (106) is a printed circuit board (PCB). The interposer (104) is connected to the PCB through wire bonding (110) to pads around the interposer (104).

[0034] Referring to FIG. 2, another embodiment of a superconducting quantum processor package (202) is illustrated. In this embodiment, the interposer (204) is connected to the package substrate (206) from the bottom surface rather than the side surface. To transition to the bottom surface connection between the interposer (204) and the package substrate (206), an interconnect (212), such as a ball grid array (BGA) or another type of interconnect, is used. Through-silicon vias (210) are also added to the interposer (204) from the bottom surface to the top surface to replace wire bonding and allow connection between the package substrate (206) and the qubit substrate (202). A superconducting material must be added inside the vias (210).

[0035] In some embodiments, the interconnect (208) is a superconducting bump bond of about 5 microns and is fabricated using a deposition system. In some embodiments, the interconnect (212) is about 100 microns and cannot be deposited. Electroplating can be used to fabricate the BGA.

[0036] Deep silicon etching, known as the Bosch process, can be used to form the vias. However, this technique can produce scallops (304) as shown in FIG. 3, which makes it more difficult to deposit the superconducting material (306) inside the vias (302). If measures are not taken to flatten the inner walls of the vias, the superconducting material (306) may break off during the deposition process or fail to reach the bottom of the vias (302). The wafers used may vary in dimensions. If the aspect ratio of the vias (302) is low, shadow evaporation may be used to flatten the vias (302). In some embodiments, the wafer has a diameter of 8 inches and a thickness of about 750 μm. The vias (302) may have a diameter of about 10 to 50 μm. Therefore, the aspect ratio between the diameter and depth of the vias is very large. When the aspect ratio of the via is large, and in some embodiments, a liner is placed inside the via to flatten sharp scallop edges on the inner wall. In some embodiments, silicon oxide is grown on the inner wall of the via to flatten sharp scallops. In some embodiments, cryogenic etching is used to completely prevent scallops. A constant aspect ratio must be maintained throughout the entire depth of the via.

[0037] Qubits are typically fabricated on a single wafer. As the number of qubits increases, the size of the wafer also increases. If any material falls onto the wafer, all qubits may be lost. To increase the yield of qubits, a large qubit wafer may be divided into multiple chiplets, each having approximately 20 to 50 qubits. More or fewer qubits may be used per chiplet. With the chiplet method, development time and costs may be reduced. As used herein, a chiplet is referred to as a qubit substrate within the superconducting quantum processor package, and multiple qubit substrates may be provided in the same package. In some embodiments, qubits within different qubit substrates may be coupled to each other through the interposer, as illustrated in the exemplary embodiment of FIG. 4. For example, a first qubit substrate (402A) carries a first qubit circuit (404A) having multiple interleaved qubits and a coupler. The second qubit substrate (402B) is equipped with a second qubit circuit (404B) having a plurality of interleaved qubits and a coupler. A coupler (406) is placed on an interposer (412) and is configured to selectively couple at least one qubit in the first qubit circuit (404A) of the first qubit substrate (402A) with at least one qubit in the second qubit circuit (404B) of the second qubit substrate (402B) (according to the interleaved architecture of the qubit and coupler). The coupler (406) is coupled to the qubit circuits (404A, 404B) through a superconducting interconnect (408).

[0038] In this manner, it should be noted that the interposer (412) includes both the via (410) and the coupler (406) (along with other components). The equipment used to manufacture the via (410) may be found on the semiconducting side of a facility where gold is also present. The coupler, which includes a Josephson junction, is a superconducting structure that cannot be exposed to gold. There is a strict rule that components exposed to gold cannot be brought into a gold-free quantum facility. This means that the coupler (406) must be manufactured first, followed by the via (410), and the coupler (406) must be protected from potential gold contamination.

[0039] In some embodiments, a resist layer is added on the coupler (on the interposer) before fabricating the via, and the layer is removed via lift-off at the final stage of the process. However, there is always a risk that residue from the resist will remain on the coupler.

[0040] In some embodiments, as illustrated in the exemplary embodiment of FIG. 5, a coupling substrate is equipped with a coupler that couples qubits from different qubit circuits of different qubit substrates. The coupling substrate (506) is positioned on top of and overlaps with qubit substrates (502A, 502B) each equipped with qubit circuits (504A, 504B). An interconnect (510) is used to connect the coupling substrate (506) to the qubit substrates (502A, 502B). The interconnect (510) may be the same as or different from the interconnect (512) used to connect the qubit substrates (502A, 502B) to the interposer (514), as long as an electrical connection can be made between the coupler (508) and the qubit circuits (504A, 504B). In this way, the coupling substrate (506) is equipped with the coupler (508), which allows the interposer (514) to be manufactured separately from the coupling substrate (506) and prevents the difficulty of having to manufacture the via (516) and the coupler (508) on the same component. However, this method makes the qubit substrates (502A, 504A) double-sided, and complexity increases as a double-sided wafer process is required.

[0041] In some embodiments, as illustrated in the exemplary embodiment of FIG. 6, the qubit substrates (602A, 602B) and the coupling substrate (604) are used without vias within the interposer (606). In this case, the interposer (606) is provided within a cutout on the package substrate (608), and wire bonding (610) electrically connects the interposer (606) to the package substrate (608).

[0042] In some embodiments, as illustrated in the exemplary embodiment of FIG. 7, the qubits of the first qubit circuit (704A) and the second qubit circuit (704B) from the first and second qubit substrates (702A, 702B) are connected through a coupler (706) mounted on an interposer (708). The interposer (708) is provided within a cutout on a package substrate (710), and wire bonding (712) electrically connects the interposer (708) to the package substrate (710).

[0043] Although the examples in this specification illustrate two qubit substrates and one coupling substrate, it will be understood that more qubit substrates may be provided within the same package, and that each pair of qubit substrates may be coupled to each other with a coupling substrate. In some embodiments, the coupling substrate spans four qubit substrates and may selectively couple a qubit from any one of the four qubit substrates to another qubit from any one of the other qubit substrates.

[0044] Reading of qubits within a qubit circuit may be performed using a quantum reading device that can be mounted on the interposer. The quantum reading device comprises at least one resonator and at least one transmission line. In some embodiments, the quantum reading device comprises a plurality of reading resonators, each reading resonator being associated with a respective qubit. In some embodiments, each reading transmission line has an input port for transmitting an input signal and an output port for receiving an output signal. Note that a single port of the transmission line may be used for both input and output. In such cases, an input signal is applied to one port of the transmission line, and a reflected wave of the input signal is measured as an output signal at the same port. As used herein, the expression “performing a reading” encompasses steps of applying one or more input signals to one port of the transmission line and subsequently measuring one or more output signals at the same port or another port of the transmission line. Further processing steps of the measured raw data may also be included in performing the reading, and thus additional components may be provided to the quantum reading device. In some embodiments, a plurality of reading resonators are connected to a single transmission line. In contrast, each readout resonator may be connected to a separate transmission line.

[0045] Referring to FIG. 8, an embodiment of a quantum reading device (800) according to a specific and non-limiting example is illustrated. A plurality of resonators (802A, 802B, 802C, 802D, 802E) are coupled to a transmission line (804) having an input port (806A) and an output port (806B). In some embodiments, a filter (808) is coupled to the resonator (802A) to filter the reading signal. The filter (808) may be a frequency filter (e.g., a bandpass filter, a highpass filter, a lowpass filter, a step impedance filter, etc.) for blocking propagating photons emitted from the qubit at the qubit frequency to prevent energy leakage of the qubit through an unwanted decay channel. In some embodiments, the filter (808) is a Purcell filter. Although only one filter (808) is shown, a filter may be provided for each resonator of the quantum reading device (800).

[0046] The quantum readout device (800) may be capacitively or inductively coupled to a qubit circuit. In some embodiments, the quantum readout device of the interposer and the qubit circuit of the qubit substrate are aligned for coupling. FIG. 9 is a top view of the quantum readout device and the superimposed qubit circuit. For ease of understanding, the interposer and the qubit substrate are omitted from the illustration. The qubit circuit consists of couplers (904A, 904B, 904C, 904D) and interleaved qubits (902A, 902B, 902C, 902D, 902E). The qubits (902A, 902B, 902C, 902D, 902E) are each superimposed with the resonators (906A, 906B, 906C, 906D, 906E) to allow for capacitive or inductive coupling between them. In this example, the qubits (902A, 902B, 902C, 902D, 902E) and the resonators (906A, 906B, 906C, 906D, 906E) are arranged in a curved pattern around a transmission line (908) shaped accordingly. Other arrangements may also be used. Although five qubits and resonators are shown in the above example, more or fewer than five may be used.

[0047] The superconducting quantum processor package is maintained at a cryogenic temperature for operation, for example, within a dilution refrigerator. A dilution refrigerator is a cryogenic system that provides continuous cooling from ambient temperature to millikelvin temperature. The dilution refrigerator consists of a cryostat, and the superconducting quantum processor package is placed inside the cryostat. Control and reading of qubits within the quantum processor package are performed by classical control electronics, which are placed outside the cryostat but communicate with the quantum processor housed within the core of the cryostat. Some of the components of the classical control electronics involved in the control and reading of qubits may be partially or wholly integrated inside the cryostat depending on the actual application. Signals may be transmitted between the quantum processor and the classical control electronics via an interconnect, which may be, for example, a plurality of coaxial lines entering and exiting the cryostat. Other types of cables, such as optical fibers or optical fiber-based RF signals (RF over fiber), may also be used to transmit control signals to and from the cryostat, and / or to and from the quantum processor inside the cryostat.

[0048] The superconducting quantum processor package may be coupled to the cable (for microwave, optical, or similar applications) through various types of connectors. The connector may be a coaxial connector, such as an RF connector, such as an SMA connector, an SMP connector, or an SMMP connector. In some embodiments, the connector is a High Density (HD) connector in which multiple lines are provided within a single connector housing. Accordingly, the superconducting quantum processor package includes one or more external connector ports mounted on the package substrate for connection to one or more cables.

[0049] When performing a qubit read, a probe tone may be generated to sample the frequency of the quantum reader and measure a phase shift dependent on the state / frequency of the qubit. However, the signal obtained from the quantum reader may experience significant attenuation while passing through the output line, which degrades the signal-to-noise ratio and makes measurement more difficult. To mitigate the attenuation of the read signal from the quantum reader, an amplifier may be used. According to the embodiments described herein, the amplifier may be integrated inside the superconducting quantum processor package.

[0050] Referring to FIG. 10, an exemplary embodiment of a superconducting quantum processor package having an amplification device is illustrated. A qubit substrate (1002) carries a qubit circuit (1008) aligned with a quantum reader (1010) mounted on an interposer (1004). The interposer (1004) is mounted on top of a package substrate (1006) which carries at least one external connector port, in this case, an external connector port (1012, 1014). In this example, a signal is introduced through the external connector port (1014) and passes through the package substrate (1006) and the interposer (1004) to reach a transmission line within the quantum reader (1010). Various conductive paths, such as one or more conductive vias, one or more conductive lines, microspheres, bump bonds, ball grid arrays, or combinations thereof, are provided so that the signal can travel through the package (1000). The conductive path may be disposed on various layers of the substrate (1002, 1004, 1006). An amplification device (1016) is provided in a read communication path between the quantum reader (1010) and the external connector port (1012) to amplify a read signal from the quantum reader (1010).

[0051] As illustrated in FIG. 10, the amplification device (1016) may be mounted on the interposer (1004) and coupled to the quantum reader (1010) via a conductive path. In some embodiments, the amplification device is positioned on the opposite surface of the interposer (1004) from the quantum reader (1010) to minimize interaction with the qubits in the qubit circuit (1008) within the qubit substrate (1002).

[0052] In some embodiments, the amplifier is placed on a separate substrate from the substrate on which the qubit circuit is mounted and the substrate on which the quantum reader is mounted. An exemplary embodiment of such an embodiment is shown in FIG. 11. A superconducting quantum processor package (1100) includes a package substrate (1106) and an external connector port (1112). The qubit substrate (1102) mounts a qubit circuit (1108) aligned with a quantum reader (1110) mounted on an interposer (1104). The amplifier substrate (1120) mounts an amplifier (1116) coupled between the quantum reader (1110) and the external connector port (1112). Thus, as in the example shown in FIG. 10, the amplifier (1116) is still provided to the read communication path and can still amplify the read signal from the quantum reader (1110).

[0053] Referring to FIGS. 12A and 12B, two exemplary embodiments of an amplification device are illustrated. In FIG. 12A, the amplification device (1202) is illustrated as comprising at least one amplifier (1204) and at least one circulator (1206). In some embodiments, the amplifier (1204) is a parametric amplifier, such as a Josephson Parametric Amplifier (JPA). The JPA may be a high-gain, broadband cryogenic amplifier designed to amplify low-power microwave signals. In this way, the JPA introduces very low noise into the signal such that its noise temperature approaches the quantum limit. The JPA operates at the lowest temperature of a dilution refrigerator, i.e., 50 millikelvin or lower. Although not illustrated, a DC current and an RF signal pump signal are provided to the JPA. In some embodiments, the amplifier (1204) is a traveling wave parametric amplifier (TWPA). The TWPA may be a Josephson junction TWPA, a kinetic inductance TWPA, etc. More than one amplifier (1204) may be used to further increase the signal-to-noise ratio. The circulator (1206) may be used to block reflected signals from the amplifier (1204). In the embodiment of FIG. 12B, another circulator (1212) within the amplification device (1222) is also provided at the output of the amplifier (1204) to protect the amplifier (1204) from noise passing through the output line in the reverse direction. The embodiments of FIG. 12A and FIG. 12B may be used with a superconducting quantum processor package (1000, 1100).The reading signal coming from the quantum reading device (1010, 1110) enters the amplification device (1202, 1222) through the input (1208), exits through the output (1210), and continues its path toward the external connector port (1012, 1112).

[0054] In some embodiments, and as illustrated in FIG. 13A and FIG. 13B, a bidirectional external connector port (1312) may be used for both input and output transmission of a signal. The signal enters through the bidirectional external connector port (1312), passes through the package substrate (1306) and the interposer (1304), and reaches the transmission line within the quantum readout device (1310). The readout signal measured from the qubit circuit (1308) mounted on the qubit substrate (1302) returns through the same path from the quantum readout device (1310) to the external connector port (1312), passing through the amplifier device (1316). In FIG. 13A, the amplifier device (1316) is mounted on the interposer. In FIG. 13B, the amplifier device (1316) is mounted on the amplifier substrate (1318).

[0055] In an embodiment using a bidirectional external connector port (1312), the amplifier device (1316) may be configured as illustrated in the example of FIG. 14. An incoming signal is received at the port (1410) and flows toward the port (1408) via a circulator (1406) so as not to pass through the amplifier (1404). The port (1408) is connected to the quantum reader. The signal received from the quantum reader at the port (1408) flows toward the amplifier (1404) via the circulator (1406). The amplified signal is reflected back to the circulator (1406) and moves out of the amplifier device (1402) through the port (1410) connected to the external coupler port, for example, the bidirectional external connector port (1312). Other embodiments for the amplifier device (1316) may also be used.

[0056] In some embodiments, the superconducting quantum processor package comprises a plurality of qubit substrates and one or more amplifier substrates, each equipped with one or more amplification devices. Exemplary embodiments are illustrated in FIGS. 15A through 15C. FIG. 15A illustrates a top view of a first exemplary embodiment. The package (1500) comprises a package substrate (1502) and an interposer (1504). A pair of qubit substrates (1506A, 1506B) are disposed on the interposer (1504), and a coupling substrate (1508) overlaps the qubit substrates (1506A, 1506B) to selectively couple at least one qubit from a qubit circuit in the qubit substrate (1506A) with at least one qubit from a qubit circuit in the qubit substrate (1506B). An amplifier substrate (1510) is positioned along the outer edges of the first and second qubit substrates (1506A, 1506B). Amplification devices (1512A, 1512B) are mounted on the amplifier substrate (1510) and are each coupled to a quantum readout device (not shown) within the interposer (1504). Various other embodiments may be used for the superconducting quantum processor package having a plurality of qubit substrates and amplifier substrates. For example, as illustrated in the example of FIG. 15B, there may be four qubit substrates (1506A, 1506B, 1506C, 1506D) and one coupling substrate (1508).Amplifier substrates (1510A, 1510B) may be provided on each outer edge of the pairs of qubit substrates such that an amplifier device (1512A) is coupled to a quantum reader coupled to a qubit circuit mounted on a qubit substrate (1506A), an amplifier device (1512B) is coupled to a quantum reader coupled to a qubit circuit mounted on a qubit substrate (1506B), an amplifier device (1512C) is coupled to a quantum reader coupled to a qubit circuit mounted on a qubit substrate (1506C), and an amplifier device (1512D) is coupled to a quantum reader coupled to a qubit circuit mounted on a qubit substrate (1506D). Alternatively, each pair of qubit substrates may be coupled with a coupling substrate, and an embodiment having 4 qubit substrates may have 2 coupling substrates, an embodiment having 6 qubit substrates may have 3 coupling substrates, an embodiment having 8 qubit substrates may have 4 coupling substrates, etc.

[0057] The amplifier substrates may be arranged in various configurations along the periphery of the qubit substrates. In some embodiments, as illustrated in the example of FIG. 15C, each amplifier substrate carries one amplifier device. In this example, amplifier substrates (1522A, 1522B, 1522C, 1522D) are provided at the corners of the interposer (1504) and each carries an amplifier device (1512A, 1512B, 1512C, 1512D). A combination of the features illustrated in the superconducting quantum processor package (1500, 1520, 1530) may be used. For example, the amplifier substrates do not need to be arranged symmetrically on the interposer. Additionally, there may be package configurations in which one amplifier substrate carries multiple amplifier devices and another amplifier substrate carries one amplifier device. Additionally, although the embodiments of this specification are illustrated such that each qubit substrate carries one qubit circuit, multiple qubit circuits may be provided per qubit substrate. Qubit circuits mounted on the same qubit substrate may be electrically independent of each other and may be coupled with different quantum readout devices within the interposer. Thus, various layouts may be used for the placement of the amplifier substrate and / or the amplifier device (within the interposer or within the amplifier substrate) in order to optimize space within the package and to facilitate appropriate connections through various conductive paths provided in various layers of the package.

[0058] The fabrication process of a superconducting quantum processor includes steps of lithography, etching, characterization, deposition, and packaging. In addition, in addition to the equipment typically required to fabricate a superconducting quantum processor, additional equipment required for the various architectures described herein may include one or more of: indium deposition equipment; indium native oxide etching equipment (e.g., atmospheric pressure plasma etching); CVD or ALD equipment for coating a superconducting material on the sidewalls of the vias; and a polisher for thinning the wafer to expose the vias.

[0059] The embodiments and examples described above are exemplary and not limiting. Actual implementation of the features described herein may include a combination of some or all of the embodiments described herein, and the features described herein should not be construed as representing future or current product plans. The applicant engages in both basic and applied research, and in some cases, the described features were developed on an exploratory basis.

[0060] The terms “connected” or “coupled to” may include both direct coupling (where two elements coupled to each other come into contact) and indirect coupling (where at least one additional element is located between the two elements).

[0061] Although the above embodiments have been described in detail, it should be understood that various changes, substitutions, and modifications may be made without departing from the scope of the present disclosure. Furthermore, the scope of this application is not intended to be limited to specific embodiments of the processes, machines, manufactured products, compositions of materials, means, methods, and steps described in the specification.

[0062] A person skilled in the art will readily understand from this disclosure that existing or subsequently developed processes, machines, manufactured products, compositions of materials, means, methods, or steps that perform substantially the same function or achieve substantially the same results as the corresponding embodiments described herein may be utilized. Accordingly, the appended claims are intended to include such processes, machines, manufactured products, compositions of materials, means, methods, or steps within their scope.

[0063] As can be understood, the examples described and illustrated above are intended for illustrative purposes only.

Claims

Claim 1 A superconducting quantum processor package comprising: a package substrate having an external connector port; an interposer having a first surface and a second surface facing each other, wherein the first surface of the interposer faces the package substrate and the interposer mounts a first quantum reader coupled to the external connector port; a first qubit substrate having an upper surface and a lower surface facing each other, wherein the lower surface of the first qubit substrate faces the second surface of the interposer and the first qubit substrate mounts a first qubit circuit having interleaved qubits and couplers, wherein the first qubit circuit is coupled to the first quantum reader and the first qubit circuit, the first quantum reader, and the external connector port form a first read communication path; and a first amplifier coupled between the first quantum reader and the external connector port on the first read communication path to amplify a read signal from the first quantum reader. Claim 2 In claim 1, the first amplification device is a superconducting quantum processor package mounted on the interposer. Claim 3 A superconducting quantum processor package according to claim 1, further comprising a first amplifier substrate having upper and lower surfaces facing each other, wherein the lower surface of the first amplifier substrate faces a second surface of the interposer, the first amplifier device is mounted on the first amplifier substrate, and the first amplifier substrate is separated from the first qubit substrate and adjacent to the first qubit substrate. Claim 4 A superconducting quantum processor package according to any one of claims 1 to 3, wherein the first amplification device comprises at least one amplifier and at least one circulator coupled thereto. Claim 5 In paragraph 4, the circulator is a superconducting quantum processor package coupled between the external connector port, the first quantum reader, and the amplifier. Claim 6 A superconducting quantum processor package according to any one of claims 1 to 5, wherein the first amplification device comprises a Josephson Parametric Amplifier (JPA). Claim 7 A superconducting quantum processor package according to any one of claims 1 to 6, wherein the interposer is bonded to the package substrate through a ball grid array (BGA). Claim 8 A superconducting quantum processor package according to any one of claims 1 to 7, wherein the first qubit substrate is bonded to the interposer through a first grid of superconducting microspheres. Claim 9 A superconducting quantum processor package according to any one of claims 1 to 8, wherein the first quantum reading device comprises a plurality of resonators coupled to a transmission line. Claim 10 A superconducting quantum processor package according to claim 9, wherein the resonators are arranged in a curved pattern and aligned with the qubits in the first qubit circuit arranged in the curved pattern. Claim 11 A superconducting quantum processor package according to any one of claims 1 to 10, wherein the first quantum reading device comprises at least one filter. Claim 12 A superconducting quantum processor package according to any one of claims 1 to 11, wherein the external connector port is bidirectional and performs reading and input. Claim 13 A superconducting quantum processor package according to claim 1, wherein the external connector port includes a plurality of output lines, and the first amplifier device includes a plurality of amplifiers corresponding to each of the plurality of output lines. Claim 14 A superconducting quantum processor package further comprising, in any one of claims 1 to 13, a second quantum readout device mounted on the interposer; a second qubit substrate separated from the first qubit substrate and having an upper surface and a lower surface facing each other, wherein the lower surface of the second qubit substrate faces the second surface of the interposer, and the second qubit substrate mounts a second qubit circuit having interleaved qubits and couplers, and the second qubit circuit is coupled to the second quantum readout device; and a coupling substrate superimposed facing the upper surfaces of the first qubit substrate and the second qubit substrate, wherein the coupling substrate mounts at least one coupler configured to selectively couple at least one qubit of the first qubit circuit with at least one qubit of the second qubit circuit. Claim 15 A superconducting quantum processor package according to claim 14, further comprising a second amplifier coupled between the second quantum reading device and the external connector port to amplify a reading signal from the second qubit circuit. Claim 16 A superconducting quantum processor package according to claim 14, further comprising a second amplifier coupled between the second quantum reading device and the second external connector port on the package substrate to amplify a reading signal from the second qubit circuit. Claim 17 A superconducting quantum processor package according to any one of claims 14 to 16, further comprising: third and fourth quantum readout devices mounted on the interposer; and third and fourth qubit substrates separated from the first and second qubit substrates, each mounted with a third and fourth qubit circuit, and each coupled to the third and fourth quantum readout devices, wherein the coupling substrate overlaps with the first, second, third, and fourth qubit substrates, and the at least one coupler is configured to selectively couple at least one qubit from any one of the first, second, third, and fourth qubit circuits with at least one qubit from any other of the first, second, third, and fourth qubit circuits. Claim 18 A superconducting quantum processor package according to claim 17, further comprising third and fourth amplification devices coupled to the third and fourth quantum reading devices, respectively. Claim 19 In paragraph 18, the second, third, and fourth amplification devices are a superconducting quantum processor package mounted on the interposer. Claim 20 A superconducting quantum processor package according to claim 18, wherein the second, third, and fourth amplifier devices are each mounted on the second, third, and fourth amplifier substrates, and the second, third, and fourth amplifier substrates are separated from the first, second, third, and fourth qubit substrates and seated on the interposer.

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