Low resistivity tungsten interconnect structure

Abstract

An ion beam deposition process using an auxiliary ion beam or etching forms an insert layer and a tungsten interconnect that may have a gradient composition in contact with the underlying layer. The interconnect has a microstructure comprising a preferred alpha phase of the tungsten layer and highly oriented (110) crystal grains, in which at least 95%, or at least 99%, or 99.9%, or even 100% of the stacked tungsten thin film has a (110) crystal orientation plane with respect to the upper surface of the thin film.

Description

Technology Field

[0001] (Cross-reference)

[0002] This application claims priority to U.S. Provisional Application No. 63 / 621,212 filed on January 16, 2024, the entire contents of which are incorporated herein by reference for all purposes.

[0003] (Technology field)

[0004] The present disclosure relates to a method for forming a low resistivity tungsten thin film and a tungsten interconnect produced by such method. Background Technology

[0005] Modern electronic integrated circuits for memory applications such as Dynamic Random Access Memory (DRAM), Flash Memory, and Phase Change Random Access Memory (PCRAM), as well as microprocessors such as Central Processing Units (CPUs) and Graphics Processing Units (GPUs), contain multiple electrically conductive interconnect layers arranged at high density and fine pitch. As electronic devices become further miniaturized into the nanometer era, a key technological means of implementation is to form smaller and finer interconnect structures that possess high electrical conductivity, i.e., low electrical resistivity. For example, in the case of DRAM devices, advanced technology nodes require that the dimensions of the interconnect structure be reduced as the device is miniaturized while maintaining low electrical resistivity. However, current technology cannot provide the desired structures, and this limitation acts as a technological bottleneck by adversely affecting memory performance and hindering the miniaturization of DRAM.

[0006] Interconnection structures are made of metallic elements or alloys. Major technical barriers affecting interconnection performance include the phenomenon where metal resistivity increases as physical dimensions, such as wiring length, width, and height, approach or become smaller than the average free path of electrons, and the fact that many metal interconnection structures require critical template layers, adhesion layers, or barrier layers that are difficult to miniaturize and reduce. The dimension-dependent increase in resistivity is primarily attributed to increased electron scattering at metal surfaces and layer boundaries, and is further exacerbated by increased scattering at grain boundaries in the polycrystalline structure of metals—which generally becomes finer with miniaturization—as well as surface roughness. This increase in resistivity is a major challenge that must be addressed for the continuous miniaturization of the most critical and smallest interconnection sections in integrated circuits. The reason a template layer, adhesive layer, or barrier layer (hereinafter collectively referred to as a template layer) is required stems from the limitation that many conventional deposition technologies, such as Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), and Atomic Layer Deposition (ALD), including magnetron sputtering PVD and RF sputtering PVD, cannot control the nucleation, growth, phase, crystal structure, texture, and microstructure of a metal film when a suitable template layer with a specific thickness does not exist. This creates difficulties in continuously shrinking the most critical and smallest interconnects in integrated circuits, as the template layer cannot be further reduced without degrading the resistivity of the metal interconnect layer.

[0007] Metals commonly used in interconnection structures include aluminum (Al), copper (Cu), tungsten (W), ruthenium (Ru), molybdenum (Mo), and cobalt (Co).

[0008] Refractory metals such as tungsten (W) are receiving significant interest as materials for specific interconnect structures in DRAM memory, other memory, and advanced logic devices due to their relatively short average free path of electrons, excellent resistivity scaling characteristics with dimensional reduction, high electron migration resistance, and high oxidation resistance. Additionally, tungsten exhibits dimension-dependent anisotropic electrical resistivity, and while resistivity is typically isotropic, it depends on the crystal structure, which is essentially related to the grain texture, orientation, and epitaxy of the polycrystalline film. According to modeling and experimental results in the literature, for body-centered cubic (BCC) alpha tungsten, the (110) orientation conducting along the (110) plane—that is, the (110) plane oriented parallel to the film surface—is most advantageous for low resistivity. In general, it is well known in the literature that the resistivity of metal thin films is closely related to the microstructure due to its influence on electron scattering mechanisms. The microstructure can be described through parameters such as grain shape, grain size, grain size distribution characteristics of grain volume, grain boundaries with varying spacing and frequency, grain boundary characteristics such as low-angle and high-angle grain boundaries, and grain orientation such as the orientation of dominant poles and planes of the grains. Therefore, for tungsten thin films used in interconnect structures, the lowest resistivity can be achieved by depositing and growing tungsten by various methods to form an alpha BCC tungsten thin film with (110) plane orientation having the largest grain size, the most uniform grain size distribution, and low-angle grain boundaries.

[0009] However, optimizing the microstructure of metal thin films to achieve the lowest resistivity can be very difficult. As is well known in the literature, the nucleation, growth, and microstructure of metal thin films depend significantly on the structure and thickness of the template layer, because the template layer influences the sticking coefficient of sputtered or reacted metal atoms, the mobility of metal adatoms, surface energy and kinetics, growth modes such as islanding, layer-by-layer, or mixed modes, as well as crystal strain, stress, and reconstruction. Therefore, as is well known in the literature, thin film growth and the resulting film properties are complex functions heavily influenced by the deposited metal, the composition of the template layer, the thickness of the template layer, the deposition temperature, and the surface chemistry. For many common interconnect structures, it is desirable to form a structure in which tungsten is deposited on an underlayer composed of a metal such as titanium or tantalum, a semiconductor layer such as silicon, a metal nitride layer such as titanium nitride (TiN), silicon nitride (SiN), or tungsten nitride (WN), or a dielectric layer such as silicon oxide and other metal oxides. However, if tungsten is deposited directly on this desirable underlayer using conventional methods such as PVD, CVD, or ALD, metastable beta-phase tungsten is formed instead of the desired alpha-BCC tungsten, and an undesirable microstructure with high resistivity is formed along with it. Consequently, in the prior art, a relatively thick template layer of amorphous silicides, such as tungsten silicide (WSix) and silicon tungten nitride (WSiNx), with a thickness of up to 50 Å, has been inserted and used between the underlayer and the tungsten.These template layers are generally deposited in separate chambers using the same conventional techniques as PVD, CVD, and ALD; that is, the template layer is first deposited on the underlying layer in one chamber, and then the tungsten layer is deposited on the template layer in another separate chamber. As previously explained, these template layers are a significant obstacle that hinders the miniaturization and technological advancement of integrated circuits.

[0010] The present disclosure relates to a method for forming a low-resistivity tungsten interconnect structure for memory and logic integrated circuits using ion beam deposition (IBD). The interconnect structure comprises a low-resistivity tungsten layer deposited by IBD on a preferred underlying layer that may include a metal layer such as titanium or tantalum, a semiconductor layer such as silicon, and a dielectric layer such as a metal nitride layer comprising titanium nitride (TiN), silicon nitride (SiN), titanium silicon nitride (TiSiN), tungsten nitride (WN), silicon tungsten nitride (WSiN), or tantalum nitride (TaN), each of which may be deposited by PVD, CVD, ALD, and IBD, and in the case of deposition by IBD, may be deposited in the same chamber as the tungsten layer. The method for forming the above interconnect structure includes the step of depositing tungsten on a lower layer by ion beam deposition using auxiliary etching at a deposition temperature of 450 °C or lower in a process chamber equipped with a multi-target turret. The thickness of the tungsten film may be 50 nm or less, and in some embodiments may be 40 nm or less.

[0011] In some embodiments, the interconnect structure comprises a low-resistivity tungsten layer on the lower layer without a separate layer between the lower layer and the tungsten layer, i.e., the tungsten is in direct contact with the lower layer.

[0012] For such interconnect structures, the forming method comprises the steps of first depositing a single sacrificial layer in-situ (i.e., within the same chamber) using an IBD, removing this sacrificial layer by consuming it using an IBD with an auxiliary ion beam or by etching it using an auxiliary etching in a subsequent single or multiple steps, and finally depositing a tungsten film layer using an IBD. This method utilizes an IBD equipped with an auxiliary system having a multi-target turret that includes both a tungsten target and other target materials that meet the composition required for the sacrificial layer.

[0013] In another embodiment, the interconnect structure is formed on or above a sublayer using a plurality of sacrificial layers. For such an interconnect structure, the forming method comprises the step of first depositing a first sacrificial layer in situ (i.e., within the same chamber) using an IBD, then depositing a second sacrificial layer and, if necessary, additional sacrificial layers, and then removing the sacrificial layer by consuming it using an IBD with an auxiliary ion beam or by etching it using an auxiliary etching in a subsequent single or multiple steps. After the sacrificial layer is completely removed or consumed, a tungsten film is deposited on the sublayer using an IBD with an auxiliary ion beam to form an interconnect structure having a low resistivity tungsten layer on the sublayer in a state where there is no layer between the sublayer and the tungsten layer. The sacrificial layer may be the same or different and may be composed of an element or material.

[0014] In another embodiment, a method for creating such an interconnect structure comprises the step of first depositing a tungsten sacrificial layer in situ on a sublayer using an IBD, then removing the sacrificial layer by consuming it with an IBD using an auxiliary ion beam or by etching it using an auxiliary etching in a subsequent single or multiple steps, and finally depositing the remaining thickness of the tungsten film layer using an IBD using an auxiliary ion beam.

[0015] In a method for forming such an interconnect structure, the method utilizes an IBD using an auxiliary ion beam having an ion beam deposition chamber equipped with a multi-target turret including at least a tungsten target.

[0016] In another embodiment, the interconnect structure comprises a low resistivity tungsten layer, a bottom layer, and a thin layer referred to as an inserted layer disposed between the tungsten layer and the bottom layer. In some embodiments, the tungsten layer contacts the inserted layer on one side of the inserted layer, and the bottom layer contacts the inserted layer on the other side of the inserted layer.

[0017] For such interconnect structures, the forming method comprises a single or multiple steps of first depositing an in-situ layer whose thickness can be varied by an IBD or an IBD using an auxiliary ion beam, and then depositing one or more sacrificial layers using an IBD with or without an auxiliary ion beam, a step of using an auxiliary etching to change the thickness of the inserted layer, a step of consuming and etching the sacrificial layer, and a step of depositing a tungsten film layer of the remaining thickness using an IBD. The sacrificial layer(s) are made of a material such as a metal, dielectric, or semiconductor that is the same or different from the inserted layer.

[0018] The above-mentioned insert layer may have a composition based on multiple targets present in a multi-target turret of the process chamber. Alternatively, the above-mentioned insert layer may have a compositional gradient in which the composition of the film, alloy, or compound formed from the multiple targets changes along the thickness direction of the thin film. For example, the composition of the insert layer changes to a form in which the content of one component is high and the content of another component is low at the bottom portion in contact with the lower layer, and changes to a form in which the content of one component is low and the content of another component is high at the top surface in contact with the tungsten layer. Additionally, or alternatively, the composition of the insert layer may be changed in situ to be different from the composition of the target used for deposition. The compositional gradient or variation refers to a change in the composition of the insert layer, examples of which include metal alloys such as W-Ti alloy, nitrides such as titanium nitride or silicon nitride, or dielectrics such as silicides such as tungsten silicide. Consequently, the method for creating the insertion layer can be used to produce an in-situ dielectric layer, such as an in-situ nitride or in-situ silicide, having a graded composition or a changing composition.

[0019] In all embodiments of the present disclosure, the underlying layer is an electrically conductive metal, semiconductor, or dielectric. Examples of the metal layer include titanium and tantalum, and the semiconductor layer is a metal nitride layer such as silicon, titanium nitride (TiN), silicon nitride (SiN), titanium silicon nitride (TiSiN), tungsten nitride (WN), tungsten silicon nitride (WSiN), and tantalum nitride (TaN). The thickness of this underlying layer is 150 Å or less, 50 Å or less in some embodiments, and 40 Å or less in other embodiments.

[0020] The interlayer can be composed of elements such as semiconductors like silicon, metals like titanium, tantalum, and tungsten, oxides like silicon oxide, tungsten oxide, and titanium oxide, nitrides like silicon nitride, titanium nitride, and tungsten nitride, silicides like titanium silicon nitride and tungsten silicon nitride, and silicides like tungsten silicide and titanium silicide. The thickness of the interlayer can be varied, for example, from less than 5 Å up to 35 Å, and generally, the thickness of the interlayer does not exceed 50 Å.

[0021] The sacrificial layer can be an electrical conductor (metal), a semiconductor, or an insulator (dielectric). Examples of materials suitable for the sacrificial layer include semiconductors such as silicon, metals such as titanium, tantalum, and tungsten, dielectrics such as oxides such as silicon oxide, tungsten oxide, and titanium oxide, nitrides such as silicon nitride, titanium nitride, and tungsten nitride, silicides such as titanium silicon nitride, tungsten silicide, and titanium silicide.

[0022] When forming an interconnect structure, the sacrificial layer(s) may be the same as or different from the insertion layer.

[0023] One particular method described herein for forming a low resistivity interconnect structure comprises the step of depositing a sublayer on a substrate using ion beam deposition in a process chamber, wherein the sublayer has a thickness of less than 150 Å and may be a semiconductor, a metal, or a dielectric, and after depositing the sublayer, the step comprises depositing a tungsten film by ion beam deposition in a process chamber at a temperature of 450 °C or lower using a tungsten target maintained in a multi-target turret in the process chamber.

[0024] The thin film tungsten produced by any method described herein may have large (110) highly oriented alpha BCC grains, in which at least 95%, often at least 99%, even at least 99.9% or 100% of the deposited tungsten film has a (110) crystal orientation plane with respect to the top surface of the film. The thickness of the tungsten film may be less than 50 nm (500 Å) or 50 nm (500 Å) or less, and in some embodiments may be less than 40 nm (400 Å) or 40 nm (400 Å) or less, or less than 35 nm (350 Å) or 35 nm (350 Å) or less. The grain size distribution may be such that the average grain size in the as-deposited state without additional annealing is at least 5 times, preferably more than 10 times, the film thickness. In addition, the resulting thin film tungsten interconnect structure may have low resistivity at different thicknesses, for example, less than 7 μΩ-cm when the film thickness is 50 nm or more, less than 8 μΩ-cm when the film thickness is 35 nm or more, less than 9 μΩ-cm when the film thickness is 20 nm or more, less than 11 μΩ-cm when the film thickness is 10 nm or more, or less than 20 μΩ-cm when the film thickness is 2 nm or more.

[0025] The content of this invention is provided to introduce a selection of concepts in a simplified form, which is additionally described below in the detailed description. This summary is not intended to identify the core or essential features of the claimed subject matter, nor is it used to limit the scope of the claimed subject matter. These and other various features and advantages will become apparent from reading the following detailed description. Brief explanation of the drawing

[0026] FIG. 1a is a schematic circuit diagram of a DRAM memory cell; FIG. 1b is a schematic circuit diagram of a logic device wiring method. FIGS. 2a to 2d are schematic side views of a DRAM bit line stack of a DRAM memory cell of FIG. 1a, comprising an interconnect structure having a low resistivity tungsten thin film according to one or more embodiments of the present disclosure; FIG. 2a illustrates an interconnect structure without an insertion layer; FIG. 2b illustrates an interconnect structure having a thin insertion layer; FIG. 2c illustrates an interconnect structure having an insertion layer having a modified composition; and FIG. 2d illustrates an interconnect structure having an insertion layer having a gradient composition from the bottom toward the top. FIGS. 3a to 3d are schematic side views of a logic element interconnect stack, such as the logic element of FIG. 1b, comprising an interconnect structure having a low resistivity tungsten thin film according to one or more embodiments of the present disclosure; FIG. 3a illustrates an interconnect structure without an insertion layer; FIG. 3b illustrates an interconnect structure having a thin insertion layer; FIG. 3c illustrates an interconnect structure having an insertion layer having a modified composition; and FIG. 3d illustrates an interconnect structure having an insertion layer having a gradient composition from the bottom toward the top. FIG. 4 is a flowchart showing step-by-step methods for depositing an interconnect structure having low resistivity tungsten on a lower layer without a layer between the tungsten layer and the lower layer. FIG. 5 is a schematic side view showing, step-by-step, a method for depositing an interconnect structure having low resistivity tungsten on a lower layer without a layer between the tungsten layer and the lower layer. FIG. 6 is a flowchart showing, step-by-step, a method for depositing an interconnect structure having low resistivity tungsten on a lower layer, having a thin insertion layer between the tungsten layer and the lower layer. FIG. 7 is a schematic side view showing, in steps, a method for forming an interconnect structure having low resistivity tungsten on a lower layer, having a thin insertion layer between a tungsten layer and a lower layer. FIG. 8 is a flowchart showing, in steps, a method for forming an interconnection structure having a low resistivity tungsten layer on a lower layer having a thin insertion layer between a tungsten layer and a lower layer, wherein the composition of the insertion layer forms a gradient from the bottom to the top. FIG. 9 is a schematic side view showing, in steps, a method for forming an interconnection structure having a low resistivity tungsten layer on a lower layer having a thin insertion layer between a tungsten layer and a lower layer, wherein the composition of the insertion layer forms a gradient from the bottom to the top. FIG. 10a is a graph showing the scaling relationship between resistivity and thickness for a low-resistivity tungsten interconnect structure; FIG. 10b is a schematic diagram of an interconnect structure having a low-resistivity tungsten layer on a lower layer without an insertion layer between the tungsten layer and the lower layer; FIG. 10c is a schematic diagram of an interconnect structure having a low-resistivity tungsten layer on a lower layer with an insertion layer between the tungsten layer and the lower layer. Specific details for implementing the invention

[0027] As previously mentioned, the present disclosure relates to a method for manufacturing a low-resistivity tungsten interconnect and various structures manufactured thereby.

[0028] In the following description, reference is made to the accompanying drawings, which form part of this specification and illustrate at least one specific implementation. The following description provides additional specific implementations. It should be understood that other implementations are considered and may be made without departing from the scope or spirit of the invention. Therefore, the following detailed description should not be taken in a limiting sense. Although the disclosure is not limited thereto, various aspects of the disclosure will be understood through the description of embodiments including the drawings provided below. In some cases, a reference number may have a related lowercase sub-reference indicating one of several similar components. Where a reference number is referenced without a sub-reference, the reference is intended to refer to all of these similar components.

[0029] Returning to the drawings, FIG. 1a shows a circuit diagram of a DRAM memory cell (100) having a 1-transistor-1-capacitor structure used in most DRAM cells, and metal interconnect lines, such as bit lines and word lines, are used, among other things, to connect the elements constituting the memory cell to one another. Bit lines connect the sources of transistors, and word lines connect the gates of transistors in multiple memory cells of the memory chip. Bit lines and word lines are the main interconnect lines used to transmit power and signals to the memory cells. Generally, DRAM memory uses tungsten metal wires as these interconnect lines.

[0030] FIG. 1b shows a circuit diagram of a logic device wiring structure (150) that connects multiple devices, which may be different devices, with metal interconnect lines. The wiring structure (150) includes a plurality of metal layers, such as a first metal wiring layer (Metal Line Level 1) that connects a contact to devices (device 1, device 2, device 3) and a second metal wiring layer (Metal Line Level 2) that is connected to the first metal wiring layer through a first via layer (Via Level 1).

[0031] Logic chips, such as microprocessors, include multiple such metal interconnect layers, and the number of interconnect layers can reach tens. Generally, interconnects used in memory (e.g., memory cell (100) of FIG. 1a), logic devices (e.g., device (150) of FIG. 1b), and other chips are formed of metal deposited as a thin film on various underlying layers. The underlying layers perform various roles such as diffusion barriers, adhesion liners, and contact enhancers, and are essential components of the devices.

[0032] Generally, logic chips utilize copper metal in the interconnects, particularly in the upper layers. However, copper has several limitations, such as a sharp increase in resistivity as the size of the wiring decreases. Specifically, when deposited on the underlying layer, the metal used for wiring and interconnect structures must have low resistivity.

[0033] Tungsten, molybdenum, ruthenium, and cobalt have been considered as metals that can replace copper. As a refractory metal, tungsten is an attractive choice as a material for metal wiring due to its high melting point, relatively short mean free path of conduction electrons (which leads to favorable scaling of resistivity with dimensional reduction), high resistance to electron migration, oxidation resistance, low resistivity, and excellent processability. However, tungsten exhibits complex behavior during the deposition process and in the resulting thin films. While bulk tungsten has low resistivity due to its body-centered cubic (BCC) structure (sometimes referred to as the alpha phase or alpha structure), in thin films, tungsten can exhibit a metastable, high-resistivity simple cubic (SC) structure (sometimes referred to as the beta phase or beta structure).

[0034] These beta phases of tungsten are prone to forming on common underlying layers such as titanium, particularly on dielectrics such as metal nitrides like titanium nitride, silicon nitride, and tungsten nitride, and oxides like silicon oxide. Avoiding these beta structures requires complex process steps in the manufacturing of interconnects used in memory and logic chips, for example, by using additional insertion layers such as tungsten silicide, tungsten nitride, or silicon tungsten nitride, which typically have a thickness of 2 nm to 5 nm or more. These insertion layers increase the overall thickness of the interconnect and thus the overall dimensions of the interconnect, which runs counter to the trend of miniaturization of integrated circuit devices. Furthermore, as the dimensions of the interconnect decrease, the proportion of the insertion layer in the total size increases, significantly degrading interconnect performance. Reducing the thickness of the insertion layer is difficult because it is not possible to suppress the formation of the tungsten beta phase and / or promote the formation of the desired low-resistivity tungsten alpha phase as the thickness of the insertion layer decreases.

[0035] Additionally, to obtain low resistivity tungsten, a microstructure of crystal grains with a (110) dominant orientation is required, because the (110) orientation exhibits the lowest resistivity due to the dimension-dependent anisotropy of tungsten resistivity. The formation of the (110) microstructure is difficult to achieve on the underlying layer due to the formation of the beta phase.

[0036] Thin film deposition techniques such as magnetron plasma deposition (PVD), high-frequency PVD, chemical vapor deposition (CVD), and atomic layer deposition (ALD) cannot deposit tungsten on a sublayer without placing an interlayer on or between the sublayers. However, ion beam deposition (IBD) is useful for forming layers with higher crystallinity and a controlled microstructure because it can deposit films with maximum energy under reduced pressure conditions and control the deposition shape.

[0037] The IBD system is widely known. The IBD system includes a vacuum chamber equipped with a fixture for fixing a substrate, such as a wafer, and can rotate and heat the wafer, as well as, in some embodiments, tilt the wafer. The chamber contains an ion beam source (deposition ion beam source) used to sputter a target material to be deposited on the substrate. The target can be mounted in a multi-target turret capable of accommodating targets of various materials. The chamber is equipped with a second ion beam source that irradiates an ion beam (auxiliary ion beam) toward the wafer to assist in the deposition of the thin film and to etch the thin film while the thin film is being deposited.

[0038] By using the method described in this specification, a high-quality, low-resistivity interconnect structure for a memory cell, such as the DRAM bit line shown in FIG. 1a, can be manufactured using an IBD. FIGS. 2a to 2d illustrate various interconnect structures in which a low-resistivity tungsten layer is deposited on a preferred underlying layer formed on a contact layer in contact with a transistor.

[0039] In the device (200a) of FIG. 2a, the tungsten layer (201a) is in direct contact with the lower layer (202a) without an insertion layer. The lower layer (202a) is formed on a contact layer (203a) connected to a transistor (204a).

[0040] In FIG. 2b, the device (200b) comprises a tungsten layer (201b) and a lower layer (202b) formed on a contact layer (203b) connected to a transistor (204b). In this structure, an insertion layer (x) exists between the tungsten layer (201b) and the lower layer (202b). The insertion layer (x) is thin (e.g., less than 2 nm, and in some cases, thin to about 1.5 nm, and thin to about 1 nm, 0.5 nm, or even 0.3 nm).

[0041] This interconnect structure (200b) is formed by ion beam deposition, in which an insert layer (x) is deposited on a lower layer (202b) and then a low resistivity tungsten layer (201b) is deposited. The insert layer (x) is formed in-situ using ion beam deposition and an auxiliary ion beam within the same chamber.

[0042] Likewise, in FIG. 2c, the device (200c) comprises a tungsten layer (201c) and a lower layer (202c) formed on a contact layer (203c) connected to a transistor (204c). An insertion layer (x) exists between the tungsten layer (201c) and the lower layer (202c). In this structure (200c), the composition of the insertion layer (x) of the final device (200c) is different from the composition of the sacrificial insertion layer used to form the insertion layer (x).

[0043] As described above, this interconnect structure (200c) is formed using ion beam deposition, which involves depositing an insert layer (x) on a lower layer (202c) and then depositing a low resistivity tungsten layer (201c). The insert layer (x) is formed in situ within the same chamber using ion beam deposition and an auxiliary ion beam, but the target used for the insert layer x is different from the target used for deposition. By utilizing a multi-turret target holder, the configuration of the insert layer (x) can be adjusted in situ as needed without changing the target, the gas, or other materials used for deposition.

[0044] The device (200d) of FIG. 2d includes a tungsten layer (201d) and a lower layer (202d) formed on a contact layer (203d) connected to a transistor (204d). An insertion layer (x) exists between the tungsten layer (201d) and the lower layer (202d). In this structure (200d), the composition of the insertion layer (x) is varied and gradiented from the bottom to the top. Furthermore, the composition is different from the composition of the other layers. This is because the target used for the insertion layer (x) and the target used for deposition are different from each other. The gradient composition is formed in situ without changing the target, the process gas used for deposition, or other materials.

[0045] In a similar manner, an interconnect structure for a logic device, such as the device (150) of FIG. 1b, can be manufactured using an IBD. In FIG. 3a through 3d, a low resistivity tungsten layer is deposited on a preferred underlying layer, such as a contact layer, which is operably in contact with and connected to the device or the first via layer (Via Level 1) as shown in FIG. 1b.

[0046] In the element (300a) of FIG. 3a, the tungsten layer (301a) is in direct contact with the lower layer (302a) without an insertion layer. The lower layer (302a) is in operably contact with the connecting layer (303a).

[0047] In FIG. 3b, the interconnect structure (300b) has the tungsten layer (301b) and the lower layer (302b) separated by an insert layer (x). The lower layer (302b) is operably in contact with the connecting layer (303b). The insert layer (x) is thin (e.g., less than 2 nm, and in some cases, as thin as 1.5 nm, 1 nm, or 0.5 nm, and even as thin as 0.3 nm). The insert layer (x) is formed in situ using ion beam deposition and an auxiliary ion beam within the same chamber as the tungsten layer (301b) and the connecting layer (303b).

[0048] In FIG. 3c, the interconnect structure (300c) includes a thin insert layer (x) between the tungsten layer (301c) and the lower layer (302c), and the composition of the insert layer (x) is changed from the originally deposited composition. The lower layer (302c) is operably in contact with the connecting layer (303c).

[0049] The insertion layer (x) is formed in situ within the same chamber as the layers (301c, 302c) using ion beam deposition and an auxiliary ion beam, but the target used for the insertion layer (x) is different from the target used for the deposition of the other layers. By utilizing a multi-turret target holder, the configuration of the insertion layer (x) can be adjusted in situ as needed without changing the target, the gas, or other materials used for deposition.

[0050] In FIG. 3d, the interconnect structure (300d) includes a thin insert layer (x) between the tungsten layer (301d) and the lower layer (302d), the composition of which is different from the composition of the tungsten layer (301d) and the lower layer (302d). The lower layer (302d) is operablely in contact with the connecting layer (303d). In this structure, the composition of the insert layer (x) varies and forms a gradient from the bottom toward the top. Additionally, the composition is different from the composition of the other layers (301d, 302d). This is because the target used for the insert layer (x) and the target used for deposition are different from each other. The gradient composition is formed in situ without changing the target, the process gas used for deposition, or other materials.

[0051] In all structures of FIGS. 2a to 2d and FIGS. 3a to 3d, the tungsten layer (201, 301) is pure tungsten (at least 99% tungsten, and in some embodiments at least 99.9% tungsten), is in the alpha phase, and has a microstructure of highly oriented grains in which at least 95% of the grains, in some embodiments at least 99% or at least 99.9%, and in other embodiments 100% have an orientation (110). The thickness of the tungsten layer (201, 301) may be 50 nm (500 Å) or less, in some embodiments 40 nm (400 Å) or less, and in other embodiments 35 nm (350 Å) or less.

[0052] The lower layer (202, 302) is a thin film of an electrically conductive material such as a metal such as titanium or tantalum, a semiconductor layer such as silicon, a dielectric such as a metal nitride layer that may include titanium nitride (TiN), silicon nitride (SiN), or tungsten nitride (WN), or other dielectric such as silicon oxide and other metal oxides. The thickness of the lower layer (202, 302) is 150 Å or less, and in some embodiments, 50 Å or less.

[0053] FIG. 4 describes, step-by-step, a method for manufacturing a structure such as the interconnect structure for memory and logic integrated circuits described in FIG. 2a and FIG. 3a, and FIG. 5 schematically illustrates, step-by-step, the configuration of said structure. The resulting structure has a thin insertion layer between a low-resistivity tungsten layer and a lower layer.

[0054] Referring to FIG. 4, a multi-stage method (400) is illustrated. In the first step (402), a target within an IBD system is selected for use in depositing a sacrificial thin film, and this target may be one of a plurality of targets within a multi-target turret. In the step (404), ion beam deposition is performed to deposit a sacrificial thin film on a substrate, which may be performed with or without an auxiliary ion beam. Any additional sacrificial layer or thin film may be deposited in the step (406) in a manner similar to steps (402, 404).

[0055] In step (408), another target is selected for use in depositing another sacrificial thin film, and this target may be one of multiple targets within a multi-target turret. In step (410), ion beam deposition is performed to deposit this sacrificial thin film on the previous sacrificial thin film(s) on the substrate, which may be performed with or without an auxiliary ion beam. Any additional sacrificial layer or thin film may be deposited, and in step (412), all sacrificial layers are deposited by ion deposition with or without an auxiliary ion beam. In step (414), auxiliary ion beam etching is performed to remove part or all of the sacrificial layer(s).

[0056] In step (416), a tungsten target is selected for use in depositing a tungsten thin film by ion beam deposition using an auxiliary ion beam in step (418); and any remaining sacrificial layer can be completely removed. After all sacrificial layers are removed, in step (420), ion beam deposition using an auxiliary ion beam is continued to deposit a low resistivity tungsten film.

[0057] In FIG. 5, the process of forming a structure manufactured by the method (400) of FIG. 4 is illustrated step by step. In FIG. 5, layer (501) represents a tungsten layer, layer (502) represents a preferred lower layer thin film, layer (503) represents another layer that is part of the device structure, such as a contact layer, and, for example, structure (504) represents a device or structure within a DRAM memory cell or another type of memory cell or logic integrated circuit. Layers X and Y are sacrificial layers.

[0058] Referring again to FIG. 4, in step (402), a target material is selected from a multi-target turret of an ion beam deposition chamber, and the target is used to deposit a sacrificial thin film layer X, shown in step A of FIG. 5, on a lower layer (502) through step (404). The thickness of the sacrificial layer X may be thin, for example, 0.5 nm, or thick, for example, 2 nm. A single sacrificial layer X or additional multiple sacrificial layers may be deposited according to step (406). If a single sacrificial layer X is used, the next step is to proceed to the structure of step C. If an additional sacrificial layer is required, another target material is selected from the multi-target according to step (408) in the next step, and then a sacrificial layer Y is deposited using ion beam deposition as shown in step B of FIG. 5 (according to step (410)). The thickness of the sacrificial layer Y may be thin, for example, 0.5 nm, or thick, for example, 2 nm.

[0059] The process used to deposit the sacrificial layer may be ion beam deposition using only the deposition ion beam, or ion beam deposition using both the deposition ion beam and the auxiliary ion beam. Ion beam energy of 50 V or more and 2000 V or less and ion beam current of 50 mA or more and 2000 mA or less may be used.

[0060] After all sacrificial layers are deposited according to step (412), the sacrificial layers are consumed (removed) using an auxiliary ion beam in step (414), and the thin film is etched and atoms of different layers are mixed together as illustrated in step C of FIG. 5. Ion beam energies of 50 V or more and 2000 V or less and ion beam currents of 50 mA or more and 2000 mA or less may be used, but generally, lower range values ​​are used for the consumption of the sacrificial layers. When the auxiliary ion beam is used, sacrificial layers X, Y and any other sacrificial layers are completely consumed by etching and mixing, thereby changing the surface chemistry of the underlying layer (502) without damage. Alternatively, the sacrificial layers are partially consumed by etching and mixing, leaving a sacrificial layer Z that is thin, about 0.1 nm, and 2 nm or less. Step C of FIG. 5 illustrates the partially consumed sacrificial layer Z, and if the sacrificial layer is completely consumed, layer Z does not exist.

[0061] In the case of a partially consumed sacrificial thin film as illustrated in step C of FIG. 5, in the next step D of FIG. 5 corresponding to step (416) of FIG. 4, a tungsten target is selected and used to deposit a tungsten thin film using ion beam deposition with an auxiliary ion beam. By appropriately selecting the conditions of the auxiliary ion beam and the deposition ion beam, the partially consumed sacrificial layer is completely consumed (step (418)), and as a result, no insertion layer exists between the deposited tungsten layer (501) and the lower layer (502). Finally, in steps E and (420) of FIG. 5, the tungsten thin film (501) is deposited to a desired thickness by ion beam deposition using an auxiliary ion beam. If the sacrificial layer is completely consumed in step C (i.e., layer Z does not exist), step D is omitted, and in step E, the tungsten thin film is deposited to a desired thickness by ion beam deposition using an auxiliary ion beam. Ion beam energy of 50 V or more and 2000 V or less and ion beam current of 50 mA or more and 2000 mA or less may be used.

[0062] The sacrificial layer or layers X, Y, Z, etc. may be thin films of metals such as titanium and tungsten, semiconductors such as silicon, dielectrics such as silicon oxide and silicon nitride, silicides such as tungsten silicide, or silicon nitrides such as tungsten silicon nitride.

[0063] In one specific embodiment of the process, a single tungsten sacrificial layer is deposited and consumed, and then low-resistivity tungsten is deposited in a self-sacrificial process to form an interconnect structure in which the tungsten is in direct contact with the underlying layer without an intercalation layer.

[0064] In another specific embodiment of the process, a first silicon sacrificial layer is deposited, followed by a second tungsten sacrificial layer, and then the layers are completely consumed. Then, low-resistivity tungsten is deposited in a self-sacrificial process to form an interconnect structure in which the tungsten is in direct contact with the underlying layer without an insertion layer.

[0065] This process forms an interconnection comprising tungsten and an insertion layer in contact with a sublayer, wherein the tungsten has a preferred alpha phase and at least 95%, often at least 99%, and even 100% of the deposited tungsten thin film has a highly oriented (110) microstructure having a crystal orientation plane (110) with respect to the top surface of the thin film. The grain size distribution can be formed such that the average grain size exceeds at least 5 times, and further exceeds 10 times, and as a result, low resistivity of the tungsten is achieved.

[0066] FIG. 6 describes, step-by-step, a method for manufacturing a structure such as the interconnect structure for memory and logic integrated circuits described in FIG. 2b, FIG. 2c, FIG. 3b, and FIG. 3c, and FIG. 7 schematically illustrates, step-by-step, the configuration of the structure. The structure has a thin insert layer between a low resistivity tungsten layer and a lower layer, wherein the insert layer has the composition as deposited or has a modified composition different from the composition of the deposited insert layer.

[0067] FIG. 6 illustrates a multi-step method (600) for forming an interconnect structure. In the first step (602), a target within an IBD system is selected for use in depositing a sacrificial thin film, and this target may be one of a plurality of targets within a multi-target turret. In the step (604), ion beam deposition is performed to deposit a sacrificial thin film on a substrate, which may be performed with or without an auxiliary ion beam. Any additional sacrificial layer or thin film may be deposited in the step (606) in a manner similar to steps (602, 604).

[0068] In step (608), another target is selected for use in depositing another sacrificial thin film, and this target may be one of a plurality of targets within a multi-target turret. In step (610), ion beam deposition is performed to deposit this sacrificial thin film on the previous sacrificial thin film(s) on the substrate, which may be performed with or without an auxiliary ion beam. Any additional sacrificial layer or thin film may be deposited, and in step (612), all sacrificial layers are deposited by ion deposition with or without an auxiliary ion beam.

[0069] In step (614), a portion of the sacrificial layer(s) is partially removed to a desired thickness, and auxiliary ion beam etching is performed to form a desired composition.

[0070] In step (616), a tungsten target is selected for use in depositing a tungsten thin film by ion beam deposition using an auxiliary ion beam in step (618), and a low resistivity tungsten film is deposited by ion beam deposition using an auxiliary ion beam in step (618).

[0071] In FIG. 7, the process of forming a structure manufactured by the method (600) of FIG. 6 is illustrated step by step. In FIG. 7, layer (701) represents a tungsten layer, layer (702) represents a preferred lower layer thin film, layer (703) represents another layer that is part of the device structure, such as a contact layer, and, for example, structure (704) represents a device or structure within a DRAM memory cell or another type of memory cell or logic integrated circuit. Layers X and Y are sacrificial layers.

[0072] Referring to FIGS. 6 and 7, in the first step (602), a target material is selected from the multi-target turret of the ion beam deposition chamber, and said target material is used to deposit a sacrificial thin film, shown as layer X, on the lower layer (702) in step A of FIG. 7. The thickness of the sacrificial layer may be thin, for example, 0.5 nm, or thick, for example, 2 nm. A single sacrificial layer X or additional multiple sacrificial layers may be deposited according to step (606). In the case of a single sacrificial layer X, the next step is to proceed to the structure of step C of FIG. 7. In the case of additional sacrificial layers, in the next step, another target material is selected from the multi-target turret of the ion beam deposition chamber according to step (608), and then a sacrificial layer Y is deposited (according to step (610)) using ion beam deposition as shown in step B. The thickness of said sacrificial layer may be thin, for example, about 0.5 nm, or thick, about 2 nm.

[0073] The process used to deposit the sacrificial layer may be ion beam deposition using only the deposition ion beam, or ion beam deposition using both the deposition ion beam and the auxiliary ion beam. Ion beam energy of 50 V or more and 2000 V or less and ion beam current of 50 mA or more and 2000 mA or less may be used.

[0074] After the sacrificial layer is deposited according to step (612), the sacrificial layer is partially consumed (removed) using an auxiliary ion beam in step (614), and the thin film is etched and atoms of different layers are mixed together as shown in step C of FIG. 7. Ion beam energy of 50 V or more and 2000 V or less and ion beam current of 50 mA or more and 2000 mA or less may be used, but generally, a lower range value is used for the consumption of the sacrificial layer. The auxiliary ion beam partially consumes the sacrificial layers X and Y through partial etching and mixing, leaving an insertion layer Z that is thin (about 0.1 nm) and thick (about 2 nm) in the process. The thickness of the insertion layer can be controlled by adjusting the amount consumed using the auxiliary ion beam in step (614) and step C of FIG. 7 and the thickness of the sacrificial layers X and Y. If necessary, a thick insertion layer of 3 nm or 4 nm or more can also be formed.

[0075] In some embodiments, a single sacrificial layer is used to form an insert layer. Assisted ion beam etching partially consumes the insert layer and changes its composition to be different from that of the target. For example, in the case of a sacrificial layer X deposited from a metal silicide target such as tungsten silicide, a thin tungsten silicide layer (e.g., at least 0.1 nm and 2 nm or up to 5 nm thick) is deposited and then partially consumed using assisted ion beam etching. By appropriately combining the beam voltage and beam current of the assisted ion beam etching, the thickness of the tungsten silicide layer is reduced by etching, and the content of tungsten and silicon differs from the composition of the target through etching and mutual mixing, so that the composition of the layer is controlled in situ, and the layer is subsequently used to form a thin insert layer.

[0076] In another embodiment, a plurality of sacrificial layers are used to form an insertion layer, and a process of partially consuming them using auxiliary ion beam etching changes the composition to be different from the composition of the plurality of targets used. For example, in the case of a first sacrificial layer X, silicon is deposited from a silicon target, and then tungsten, which is a second sacrificial layer Y, is deposited from a tungsten target. The thickness of each layer may (independently) be at least 0.1 nm, 2 nm, or up to 5 nm. Then, by appropriately combining beam voltage and beam current, auxiliary ion beam etching partially consumes sacrificial layers X and Y by etching and mutual mixing, leaving an insertion layer Z with a thickness of at least 0.1 nm, 2 nm, or up to 5 nm, said new layer Z becomes a compound of tungsten and silicon, such as tungsten silicide, to form a new material having a composition different from the composition of the selected target, thereby forming a new in-situ material composition.

[0077] Different compositions can be deposited by varying the thicknesses of different insert layers and the consumption of auxiliary ion beam etching. For example, if the tungsten layer is made thicker than the silicon layer, tungsten silicide with a high tungsten content is formed. Insert layers with different compositions can be formed by appropriately controlling the sacrificial layer deposition sequence, the material selection of the sacrificial layer, and the thickness of the layer. Additionally, auxiliary ion beam etching can be used to control the thickness of the insert layer. In this way, the insert layer is formed and controlled in situ.

[0078] The insertion layer may be composed of materials such as semiconductors like silicon, metals like titanium, tantalum, tungsten, oxides like silicon oxide, tungsten oxide, and titanium oxide, nitrides like silicon nitride, titanium nitride, and tungsten nitride, silicides like titanium silicon nitride and tungsten silicon nitride, and silicides like tungsten silicide and titanium silicide.

[0079] Returning to FIG. 7, step C illustrates an insert layer Z deposited in situ. In the next step (616), a tungsten target is selected from the multi-target turret of the ion beam chamber and used to deposit a tungsten thin film of the desired thickness by ion beam deposition using an auxiliary ion beam (step (618)), thereby forming the structure of step D. An ion beam energy of 50 V or more and 2000 V or less and an ion beam current of 50 mA or more and 2000 mA or less may be used.

[0080] The process of FIGS. 6 and 7 forms an interconnection comprising tungsten and an insert layer having a modified composition in contact with a sublayer, wherein the tungsten has a preferred alpha phase and at least 95%, often at least 99%, and even 100% of the deposited tungsten thin film has a highly oriented (110) microstructure having a crystal orientation plane (110) with respect to the top surface of the thin film. The grain size distribution can be formed such that the average grain size exceeds at least 5 times, and further exceeds 10 times, and as a result, low resistivity of the tungsten is achieved.

[0081] FIG. 8 describes, step-by-step, the sequence of manufacturing a structure such as the interconnect structure for memory and logic integrated circuits described in FIG. 2d and FIG. 3d, and FIG. 9 schematically illustrates, step-by-step, the configuration of the structure. The structure has a thin insert layer between a low-resistivity tungsten layer and a lower layer, and the insert layer has a gradient composition or a changed composition.

[0082] FIG. 8 illustrates a multi-step method (800) for forming an interconnect structure. In the first step (802), a target within an IBD system is selected for use in depositing a sacrificial thin film, and this target may be one of a plurality of targets within a multi-target turret. In the step (804), ion beam deposition is performed to deposit a sacrificial thin film on a substrate, which may be performed with or without an auxiliary ion beam. In the step (808), another target is selected for use in depositing another sacrificial thin film, and this target may be one of a plurality of targets within a multi-target turret. In the step (810), ion beam etching is performed to partially remove a portion of the sacrificial layer(s) to a desired thickness and to form a desired composition.

[0083] In step (812), steps (802) through (810) can be repeated to deposit a final insertion layer having a desired composition and thickness.

[0084] In step (816), a tungsten target is selected for use in depositing a tungsten thin film by ion beam deposition using an auxiliary ion beam in step (818), and a low resistivity tungsten film is deposited by ion beam deposition using an auxiliary ion beam in step (818).

[0085] FIG. 9 illustrates, in steps, the process of forming a structure manufactured by the method (800) of FIG. 8. In FIG. 9, layer (901) represents a tungsten layer, layer (902) represents a preferred lower layer thin film, layer (903) represents another layer that is part of the device structure, such as a contact layer, and, for example, structure (904) represents a device or structure within a DRAM memory cell or another type of memory cell or logic integrated circuit. Layers X and Y are sacrificial layers.

[0086] Referring to FIGS. 8 and 9, in the first step (802), a target material is selected from the multi-target turret of the ion beam deposition chamber, and said target material is used to deposit a sacrificial thin film layer X1 on the lower layer (902) in step A of FIG. 9. The thickness of this sacrificial layer X1 may be thin, for example, about 0.5 nm, or thick, about 2 nm. A single sacrificial layer or multiple additional sacrificial layers may be deposited. In the case of a single sacrificial layer X1, the next step is to proceed to step C. In the case of additional sacrificial layers on the sacrificial layer X1, in the next step, a target material is selected from the multi-target turret of the ion beam deposition chamber according to step (806), and then a sacrificial layer Y1 is deposited using ion beam deposition as shown in step B. The thickness of the sacrificial layer Y1 may be thin, for example, about 0.5 nm, or thick, about 2 nm.

[0087] As with the prior methods described herein, the process used to deposit the sacrificial layer may be ion beam deposition using only the deposition ion beam, or ion beam deposition using an auxiliary ion beam using both the deposition and the auxiliary ion beam. An ion beam energy of 50 V or more and 2000 V or less and an ion beam current of 50 mA or more and 2000 mA or less may be used.

[0088] After the sacrificial layer is deposited according to step (808), the sacrificial layer is partially consumed (removed) using an auxiliary ion beam in step (810), and the auxiliary ion beam etches the thin film and mixes atoms of different layers. Ion beam energies of 50 V or more and 2000 V or less and ion beam currents of 50 mA or more and 2000 mA or less may be used, but generally, lower values ​​are used for the consumption of the sacrificial layer. The auxiliary ion beam consumes the sacrificial layers X1 and Y1 by partial etching and mixing, leaving an insertion layer Z1 (shown in step C) that is thin with a thickness of about 0.1 nm and thick with a thickness of about 2 nm. The thickness of the insertion layer can be controlled by adjusting the thickness of the sacrificial layer and the amount consumed using the auxiliary ion beam. If necessary, a thicker insertion layer Z1 with a thickness of, for example, 3 nm or 4 nm or more can be formed. This series of steps (step (808), step (810)) is repeated in step (812) to form the sacrificial layers X2 and Y2 of steps D and E, and in step (814) the insertion layer Z2 shown in step F is formed.

[0089] By varying the thicknesses of different layers X1, Y1 and X2, Y2 (etc.) and the amount consumed using auxiliary ion beam etching, insertion layers Z1, Z2, etc., having different compositions can be deposited. Through this process, the composition of layer Z consists of the materials of layers X and Y, and the X:Y composition ratio of layer Z can be controlled by adjusting the thickness of layers X and Y and the auxiliary ion beam etching at each deposition step. By repeating the series of processes described above, an insertion layer composed of multiple partially consumed layers Z can be deposited, and the insertion layer forms a gradient composition layer in which the composition determined by the X:Y components varies across the entire layer.

[0090] For example, a tungsten silicide having a compositional gradient can be formed in situ by this process. First, a silicon sacrificial layer is deposited from a silicon target, followed by the deposition of a tungsten sacrificial layer, and a tungsten silicide insertion layer is formed using assisted ion beam etching. For example, by controlling the layer thickness and assisted ion beam etching, the composition of the first insertion layer can be a composition with a high tungsten content. Next, this series of processes is repeated, but the silicon content of the second insertion layer is increased by controlling the layer thickness and assisted ion beam etching to obtain a composition with a higher silicon content, and this process is continued until a final insertion layer with a high silicon content is deposited. The sum of these insertion layers forms a composite insertion layer, and the composite insertion layer has a compositional gradient of tungsten and silicon that changes from a composition with a high tungsten content to a composition with a high silicon content from the bottom to the top. By appropriately controlling the sacrificial layer deposition sequence, the material selection of the sacrificial layer, and the thickness of the layer, an insert layer having a gradient composition can be formed. Additionally, auxiliary ion beam etching can be used to control the thickness of the insert layer. Accordingly, this specification describes a method for forming an insert layer having a gradient composition in situ.

[0091] The insertion layers X, Y, and Z may be composed of, for example, a semiconductor such as silicon, a metal such as titanium, tantalum, tungsten, etc., an oxide such as silicon oxide, tungsten oxide, and titanium oxide, a nitride such as silicon nitride, titanium nitride, and tungsten nitride, a silicide-nitride such as titanium silicon nitride and tungsten silicon nitride, and a silicide such as tungsten silicide, titanium silicide, etc.

[0092] Referring again to step G of FIGS. 8 and 9, the final low-resistivity tungsten film (901) is deposited by selecting a tungsten target from a multi-target turret of an ion beam chamber (step (816)), and depositing a tungsten thin film of a desired thickness on an insertion layer Z2 by ion beam deposition using an auxiliary ion beam with the tungsten target (step (818)). An ion beam energy of 50 V or more and 2000 V or less and an ion beam current of 50 mA or more and 2000 mA or less may be used.

[0093] The process of FIGS. 8 and 9 forms an interconnection comprising an insertion layer having a gradient composition in contact with a lower layer and tungsten, and also forms a microstructure comprising a preferred alpha phase of the tungsten layer and highly oriented (110) grains having a (110) crystal orientation plane with respect to the upper surface of the thin film, at least 95% to the whole of the deposited tungsten thin film. The grain size distribution can be formed such that the average grain size is at least 5 times, and further exceeds 10 times, and as a result, low resistivity of tungsten is achieved.

[0094] Tungsten interconnection structures produced using any method described above have low resistivity. FIG. 10a illustrates the thickness versus resistivity of a tungsten thin film in a structure in which tungsten is deposited on a lower layer without an insertion layer, manufactured according to the method of the present disclosure. Such a structure is illustrated in FIG. 10b as an interconnection structure (1000), and the tungsten layer (1001) is formed in direct contact with the lower layer (1002).

[0095] However, if there is an insert layer, the resistivity is significantly lowered. By including an insert layer such as that formed by the above methods, a thin tungsten interconnect structure can have low resistivity at different thicknesses. FIG. 10c illustrates an interconnect structure (1050) having a tungsten layer (1051), a lower layer (1052), and an insert layer (1055) located between the layers (1051, 1052) and in contact with them.

[0096] For example, an interconnect structure having an insert layer between a tungsten layer and a sublayer may have a resistivity of less than 7 μΩ-cm when the film thickness is 50 nm or more, less than 8 μΩ-cm when the film thickness is 35 nm or more, less than 9 μΩ-cm when the film thickness is 20 nm or more, less than 11 μΩ-cm when the film thickness is 10 nm or more, or less than 20 μΩ-cm when the film thickness is 2 nm or more. Similar results regarding resistivity can be obtained by using a thin insert layer with a modified composition or a gradient composition.

[0097] From the foregoing, it will be understood that while specific embodiments of the present invention have been described herein for illustrative purposes, various modifications may be made without departing from the scope of the invention. Accordingly, the present invention is limited only by the appended claims.

[0098] Although the present invention has been described in language specific to specific structures and materials, it should be understood that the invention as defined in the appended claims is not necessarily limited to the specific structures and materials described. Rather, specific aspects are described in the form of embodying the claimed invention. Since many embodiments of the invention may be practiced without departing from the spirit and scope of the invention, the invention is limited to the following appended claims.

[0099] The various designs described above include diverse features and details. It should be understood that the features or details of one design may be utilized in or in combination with other designs, as long as they do not violate the process, configuration, or form. Any modification is permissible. For example, processing time, pressure, temperature, etc., may be changed.

[0100] The above specification and examples provide a complete description of the structure and use of exemplary embodiments of the present invention. The above description provides specific implementations. It should be understood that other implementations may be considered and made without departing from the scope or spirit of the present invention. Therefore, the above detailed description should not be taken in a limiting sense. Although the present invention is not limited in this way, an understanding of various aspects of the present invention will be gained through a discussion of the provided examples.

[0101] Unless otherwise indicated, all numbers representing feature size, quantity, and physical properties shall be understood as being modified by the term “approximately,” whether or not the term “approximately” is immediately preceding them. Accordingly, unless otherwise indicated, the described numerical parameters are approximations that may vary depending on the desired properties to be obtained by a person skilled in the art using the teachings disclosed herein.

[0102] As used herein, the singular forms “a,” “an,” and “the” include implementations having multiple referents unless otherwise specified in the content. As used herein and in the appended claims, the term “or” is generally used to include “and / or” unless otherwise specified in the content.

[0103] Spatially related terms used herein, such as “bottom,” “lower,” “top,” “upper,” “beneath,” “below,” “above,” “on top,” and “on,” are used for convenience in describing the spatial relationship between an element and another element. These spatially related terms include other orientations of the device in addition to the specific orientations shown in the drawings and described herein. For example, if a structure shown in the drawings is turned over or flipped over, a part previously described below or beneath another element will be on or above another element.

Claims

Claim 1 A method for forming a low resistivity interconnect structure, wherein the method comprises the step of depositing a tungsten film having a thickness of 50 nm or less on a lower layer film by ion beam deposition in a process chamber at a temperature of 450°C or lower using a tungsten target maintained in a multi-target turret in a process chamber, and wherein the lower layer film is a metal layer, a semiconductor layer, or a metal nitride layer. Claim 2 A method for forming a low resistivity interconnect structure according to claim 1, further comprising, prior to the step of depositing the tungsten film, a step of depositing an insertion layer on a lower layer film, wherein the insertion layer comprises a metal, a semiconductor, or a dielectric and has a thickness of 50 Å or less. Claim 3 A method for forming a low resistivity interconnect structure, wherein, in paragraph 2, the insertion layer has a gradient composition. Claim 4 A method for forming a low resistivity interconnect structure according to claim 1, wherein the lower layer film comprises titanium, tantalum, silicon, titanium nitride (TiN), silicon nitride (SiN), titanium silicon nitride (TiSiN), tungsten nitride (WN), silicon tungsten nitride (WSiN), or tantalum nitride (TaN). Claim 5 A method for forming a low resistivity interconnect structure according to claim 4, wherein the lower layer film is deposited by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or ion beam deposition (IBD). Claim 6 A method for forming a low resistivity interconnect structure according to claim 1, further comprising the step of depositing a semiconductor, dielectric, or metal sacrificial layer on a sublayer film by ion beam deposition in a process chamber before depositing the tungsten film, using a target maintained in a multi-target turret. Claim 7 A method for forming a low resistivity interconnect structure, wherein, in claim 6, the step of depositing the semiconductor, dielectric, or metal sacrificial layer comprises depositing a plurality of semiconductor, dielectric, or metal sacrificial layers. Claim 8 A method for forming a low resistivity interconnect structure according to claim 7, wherein depositing a plurality of semiconductor, dielectric, or metal sacrificial layers includes depositing sacrificial layers from different targets in a multi-target turret. Claim 9 A method for forming a low resistivity interconnect structure according to claim 8, wherein after depositing a plurality of sacrificial layers, the plurality of sacrificial layers are etched or mixed with each other by irradiating at least some of the plurality of sacrificial layers with an auxiliary ion beam in a process chamber. Claim 10 A method for forming a low resistivity interconnect structure according to claim 6, further comprising the step of etching a sacrificial layer using an auxiliary ion beam in a process chamber prior to the step of depositing the tungsten film. Claim 11 A tungsten film manufactured by the method described in any one of claims 1 to 10, wherein the tungsten film has a thickness (110) and comprises a crystal structure including alpha BCC crystal grains having an orientation; and an average crystal grain size that is at least 5 times the thickness. Claim 12 A tungsten film according to claim 11, wherein the thickness is less than 50 nm. Claim 13 In claim 11, the tungsten film is a tungsten film having a resistivity according to film thickness as follows: a resistivity in the range of 7 to 8 μΩ-cm when the thickness is 40 to 50 nm; a resistivity in the range of 8 to 9 μΩ-cm when the thickness is 20 to 40 nm; a resistivity in the range of 9 to 11 μΩ-cm when the thickness is 10 to 20 nm; and a resistivity in the range of 11 to 20 μΩ-cm when the thickness is 1 to 10 nm. Claim 14 In claim 11, a tungsten film having a thickness of 50 nm or less and a resistivity in the range of 7-8 μΩ-cm. Claim 15 In claim 11, the tungsten film comprises at least 95% alpha BCC crystal grains having (110) orientation. Claim 16 A low resistivity interconnection structure manufactured by a method described in any one of claims 1 to 10, wherein the structure comprises: a substrate; a lower layer having a thickness of less than 150 Å and comprising an electrically conductive metal, semiconductor, or dielectric; a tungsten film having a crystal structure having a thickness of 50 nm or less and comprising alpha BCC crystal grains having (110) orientation; and an insertion layer existing between the lower layer and the tungsten film, wherein the insertion layer comprises a metal, semiconductor, or dielectric and has a thickness of 50 Å or less. Claim 17 In claim 16, the above-mentioned insert layer has a gradient composition, a low resistivity interconnect structure. Claim 18 In claim 16, the low resistivity interconnect structure, wherein the resistivity of the tungsten film can be described as follows depending on the thickness: a resistivity in the range of 7 to 8 μΩ-cm when the thickness is 40 to 50 nm; a resistivity in the range of 8 to 9 μΩ-cm when the thickness is 20 to 40 nm; a resistivity in the range of 9 to 11 μΩ-cm when the thickness is 10 to 20 nm; and a resistivity in the range of 11 to 20 μΩ-cm when the thickness is 1 to 10 nm. Claim 19 In paragraph 16, the above structure is a low-resistivity interconnect structure, wherein the structure is a memory structure or a logic structure. Claim 20 In paragraph 19, the memory is a low resistivity interconnect structure that is a DRAM structure.

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