Semiconductor device and method of manufacturing the same

Abstract

A memory device and a method for manufacturing the same are disclosed. In some embodiments, the disclosed memory device comprises a capacitor stacking structure and an array of transistors. The capacitor stacking structure comprises first electrode plates and second electrode plates alternately stacked along a vertical direction, a common electrode extending vertically through the capacitor stacking structure and in contact with the first electrode plate, and a selection electrode, each extending through the capacitor stacking structure and in contact with a corresponding one of the second electrode plates. Each transistor of the array of transistors is coupled to a corresponding one of the selection electrodes.

Description

Technology Field

[0001] The present disclosure generally relates to the field of semiconductor technology, and more specifically to semiconductor devices and methods for manufacturing the same. Background Technology

[0002] Planar memory cells are reduced in size through improvements in process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells reaches a lower limit, planar process and manufacturing technologies become demanding and costly. Consequently, the memory density of planar memory cells reaches an upper limit.

[0003] A three-dimensional (3D) memory architecture can overcome the density limitations of planar memory cells. A 3D memory architecture includes a memory array and peripheral circuitry to facilitate the operation of the memory array.

[0004] One aspect of the present disclosure provides a semiconductor device, the semiconductor device comprising: a stacked structure comprising a first conductive layer and a second conductive layer alternately stacked along a vertical direction; a conductive wall extending vertically through the stacked structure and in contact with the first conductive layer but isolated from the second conductive layer; and a conductive via, each extending vertically through the stacked structure and electrically connected to a corresponding one of the second conductive layers but electrically isolated from the first conductive layer and the other second conductive layer within the stacked structure.

[0005] In some embodiments, the semiconductor device further includes an isolation structure located between a conductive via and another second conductive layer to isolate the conductive via and the other second conductive layer.

[0006] In some embodiments, the semiconductor device further includes a conductive connection structure, each of which is positioned between one of the conductive vias and a corresponding one of the second conductive layers to connect one of the conductive vias to the corresponding one of the second conductive layers.

[0007] In some embodiments, the isolation structure comprises silicon oxide; and the conductive connection structure comprises a metal silicide material.

[0008] In some embodiments, the isolation structure and the conductive connection structure each have a ring structure that laterally surrounds a corresponding one of the conductive vias.

[0009] In some embodiments, the second conductive layer and the first conductive layer comprise the same conductive material.

[0010] In some embodiments, the first conductive layer and the conductive wall comprise a first conductive material; and the second conductive layer and the conductive via comprise a second conductive material different from the first conductive material.

[0011] In some embodiments, the semiconductor device further comprises a dielectric layer, wherein the dielectric layer comprises: a horizontal portion between an adjacent first conductive layer and a second conductive layer; a first vertical portion between a conductive wall and a second conductive layer; and a second vertical portion between a conductive via and a first conductive layer.

[0012] In some embodiments, the dielectric layer includes a high-dielectric (high-K) material.

[0013] In some embodiments, the dielectric layer is in contact with the side of the conductive wall and the side of the conductive via, and with the horizontal plane of the first conductive layer and the horizontal plane of the second conductive layer.

[0014] In some embodiments, the semiconductor device further includes an array of transistors each coupled to a conductive via.

[0015] In some embodiments, the transistor is a vertical gate transistor comprising a channel structure extending along the vertical direction and a gate structure on the side of the channel structure.

[0016] In some embodiments, the semiconductor device further includes an insulating layer between the stacked structure and the array of transistors, and each conductive via extends through the insulating layer and is coupled to a corresponding one of the array of transistors.

[0017] In some embodiments, the first thickness of the first conductive layer is different from the second thickness of the second conductive layer.

[0018] In some embodiments, the semiconductor device further includes a slit structure that extends vertically through a stacked structure and extends laterally along a first direction between rows of adjacent conductive vias, and a conductive wall extends laterally along a second direction to block the slit structure.

[0019] Another aspect of the present disclosure provides a memory device, the memory device comprising: a capacitor stacking structure comprising a first electrode plate and a second electrode plate alternately stacked along a vertical direction, a common electrode extending vertically through the capacitor stacking structure and in contact with the first electrode plate, and a selection electrode each extending through the capacitor stacking structure and in contact with a corresponding one of the second electrode plates; said capacitor stacking structure; and an array of transistors each coupled to a corresponding one of the selection electrodes.

[0020] In some embodiments, the memory device further includes a high-dielectric constant (high-K) layer between adjacent first electrode plates and second electrode plates, between the first electrode plate and a common electrode, and between the second electrode plate and a select electrode.

[0021] In some embodiments, the memory device further comprises: a conductive connection structure, each positioned between one of the selection electrodes and a corresponding one of the second electrode plates to electrically connect one of the selection electrodes and a corresponding one of the second electrode plates; and an isolation structure between one of the selection electrodes and another second electrode plate that is different from the corresponding one of the second electrode plates.

[0022] In some embodiments, the isolation structure comprises silicon oxide, and the conductive connection structure comprises a metal silicide material.

[0023] In some embodiments, the isolation structure and the conductive connection structure each have a ring structure that laterally surrounds a corresponding one of the selection electrodes.

[0024] In some embodiments, the first electrode plate and the second electrode plate include the same conductive material.

[0025] In some embodiments, the first electrode plate and the common electrode comprise a first conductive material; and the second electrode plate and the selection electrode comprise a second conductive material different from the first conductive material.

[0026] In some embodiments, the memory device further includes an insulating layer between a capacitor stacking structure and an array of transistors, and a select electrode extends through the insulating layer.

[0027] In some embodiments, the transistor is a two-dimensional transistor or a vertical gate transistor.

[0028] In some embodiments, the memory device further comprises a slit structure that extends vertically through a capacitor stacking structure and extends laterally along a first direction between rows of adjacent selection electrodes, and a common electrode extends laterally along a second direction to block the slit structure.

[0029] Another aspect of the present disclosure provides a method for forming a semiconductor device, the method comprising: forming a stacked structure on an array of transistors, wherein the stacked structure comprises semiconductor layers and sacrificial layers alternately stacked along a vertical direction; forming an isolation structure and a conductive connection structure on an exposed sidewall of a semiconductor layer within a through hole, wherein each of which forms a through hole extending vertically through the stacked structure and each through hole has a conductive connection structure in contact with a corresponding one of the semiconductor layers, wherein the sidewall of the other semiconductor layer is covered by the isolation structure; forming a conductive via within the through hole to connect the array of transistors; replacing a semiconductor layer with a second conductive layer; and replacing a sacrificial layer with a first conductive layer.

[0030] In some embodiments, the method further comprises the step of forming an insulating layer on an array of transistors, and a stacked structure is formed on the insulating layer.

[0031] In some embodiments, forming through holes, isolation structures, and conductive connection structures comprises the step of forming via holes having different depths within a stacked structure, wherein each via hole stops at a corresponding one of the sacrificial layers; and the step of forming isolation structures by oxidizing the exposed surface of a semiconductor layer through the via holes.

[0032] In some embodiments, forming through holes, isolation structures, and conductive connection structures comprises: a first step of extending the depth of a via hole such that each via hole exposes a lower semiconductor layer without an isolation structure; and a step of forming a conductive connection structure on the exposed sidewall of the semiconductor layer without an isolation structure through the first extended via hole.

[0033] In some embodiments, forming through holes, isolation structures, and conductive connection structures further comprises: a step of extending the depth of a via hole a second time so that each via hole stops at an insulating layer; and a step of oxidizing the exposed surface of a semiconductor layer through the second extended via hole to form an additional isolation structure.

[0034] In some embodiments, forming through holes, isolation structures, and conductive connection structures further includes the step of forming through holes by extending the depth of via holes a third time so that each through hole extends through an insulating layer and exposes a corresponding one of the transistors.

[0035] In some embodiments, the step of replacing the semiconductor layer with a second conductive layer comprises: forming a vertical trench that extends vertically through the stacked structure and stops at an insulating layer; removing the semiconductor layer through the vertical trench to form a first horizontal trench; and forming a second conductive layer within the first horizontal trench.

[0036] In some embodiments, the step of replacing the sacrificial layer with the first conductive layer comprises: removing a portion of the second conductive layer exposed by a vertical trench; removing the sacrificial layer through the vertical trench to form a second horizontal trench; forming a dielectric layer in the second horizontal trench and on the sidewall of the vertical trench to cover the exposed surface of the second conductive layer; and forming the first conductive layer in the second horizontal trench.

[0037] In some embodiments, the method further comprises the step of forming a slit structure that extends vertically through a laminated structure and extends laterally along a first direction, and a row of through holes is formed between adjacent first slit structures. Brief explanation of the drawing

[0038] The accompanying drawings included in this specification and forming part of the specification serve to illustrate embodiments of the present disclosure, explain the principles of the present disclosure together with the description, and enable a person skilled in the art to manufacture and use the present disclosure. FIG. 1 illustrates a schematic circuit diagram of a memory device including a vertical transistor according to some embodiments of the present disclosure. FIG. 2 illustrates a schematic side cross-sectional view of a 3D memory device according to some embodiments of the present disclosure. FIG. 3 illustrates a schematic planar cross-sectional view of a memory device according to some embodiments of the present disclosure. FIG. 4 illustrates a block diagram of a system having a memory device according to some embodiments of the present disclosure. FIG. 5 illustrates a flowchart of a manufacturing method for forming a 3D memory device according to some embodiments of the present disclosure. FIG. 6a illustrates a schematic side cross-sectional view of a 3D memory device at a specific step of a manufacturing method according to some embodiments of the present disclosure. FIG. 6b illustrates a schematic planar cross-sectional view of a 3D memory device at a specific step of a manufacturing method according to some embodiments of the present disclosure. FIG. 7a illustrates a schematic side cross-sectional view of a 3D memory device at a specific step of a manufacturing method according to some embodiments of the present disclosure. FIG. 7b illustrates a schematic planar cross-sectional view of a 3D memory device at a specific step of a manufacturing method according to some embodiments of the present disclosure. FIG. 8a illustrates a schematic side cross-sectional view of a 3D memory device at a specific step of a manufacturing method according to some embodiments of the present disclosure. FIG. 8b illustrates a schematic planar cross-sectional view of a 3D memory device at a specific step of a manufacturing method according to some embodiments of the present disclosure. FIG. 9a illustrates a schematic side cross-sectional view of a 3D memory device at a specific step of a manufacturing method according to some embodiments of the present disclosure. FIG. 9b illustrates a schematic planar cross-sectional view of a 3D memory device at a specific step of a manufacturing method according to some embodiments of the present disclosure. FIG. 10 illustrates a schematic side cross-sectional view of a 3D memory device at a specific step of a manufacturing method according to some embodiments of the present disclosure. FIG. 11 illustrates a schematic side cross-sectional view of a 3D memory device at a specific step of a manufacturing method according to some embodiments of the present disclosure. FIG. 12a illustrates a schematic side cross-sectional view of a 3D memory device at a specific step of a manufacturing method according to some embodiments of the present disclosure. FIG. 12b illustrates a schematic planar cross-sectional view of a 3D memory device at a specific step of a manufacturing method according to some embodiments of the present disclosure. FIG. 13a illustrates a schematic side cross-sectional view of a 3D memory device at a specific step of a manufacturing method according to some embodiments of the present disclosure. FIG. 13b illustrates a schematic planar cross-sectional view of a 3D memory device at a specific step of a manufacturing method according to some embodiments of the present disclosure. FIG. 14 illustrates a schematic side cross-sectional view of a 3D memory device at a specific step of a manufacturing method according to some embodiments of the present disclosure. FIG. 15a illustrates a schematic side cross-sectional view of a 3D memory device at a specific step of a manufacturing method according to some embodiments of the present disclosure. FIG. 15b illustrates a schematic planar cross-sectional view of a 3D memory device at a specific step of a manufacturing method according to some embodiments of the present disclosure. The present disclosure will be described with reference to the accompanying drawings. Specific details for implementing the invention

[0039] While specific configurations and arrangements are discussed, it should be understood that this is done merely for illustrative purposes. Accordingly, other configurations and arrangements may be used without departing from the scope of this disclosure. Furthermore, this disclosure may be adopted in various other applications. The functional and structural features described in this disclosure may be combined, adjusted, and modified with one another, and such combinations, adjustments, and modifications are within the scope of this disclosure, as they may be done in ways not specifically depicted in the drawings.

[0040] Generally, terms may be understood at least in part from their contextual use. For example, the term “one or more” as used herein may, at least in part depending on the context, be used to describe any feature, structure, or characteristic in a singular sense or to describe a combination of features, structures, or characteristics in a plural sense. Likewise, terms written in the singular may be understood, at least in part depending on the context, to convey a singular usage or a plural usage. Furthermore, the term “based on” may not be understood as intended to convey an exclusive set of factors, but instead, at least in part depending on the context, may allow for the existence of additional factors not explicitly described.

[0041] It should be readily understood that the meanings of “on,” “above,” and “over” in this disclosure should be interpreted in the broadest sense, so that “on” means not only “directly on” something, but also includes the meaning of being “on” something that has an intermediate feature or layer between them, and “above” or “over” means not only being “on” or “over” something, but also includes the meaning of being “on” or “over” something that does not have an intermediate feature or layer between them (i.e., directly on something).

[0042] Additionally, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein for convenience of description to explain the relationship between one element or feature and another element(s) or feature(s), as illustrated in the drawings. Spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientations depicted in the drawings. The device may be oriented differently (rotated 90 degrees or in a different orientation), and spatially relative descriptors used herein may likewise be interpreted accordingly.

[0043] As used herein, the term “substrate” refers to a material to which a subsequent layer of material is added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Additionally, the substrate may comprise a wide range of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of electrically nonconductive materials such as glass, plastic, or sapphire wafers.

[0044] As used herein, the term “layer” refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have a range smaller than that of the underlying or overlying structure. Additionally, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness smaller than that of the continuous structure. For example, a layer may be located between the upper and lower surfaces of the continuous structure or between any pair of horizontal planes on those surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer and may include one or more layers within it and / or, have one or more layers on, above, and / or below it. A layer may include a plurality of layers. For example, an interconnect layer may include one or more conductor and contact layers (on which interconnect lines and / or vertical interconnect access (via) contacts are formed) and one or more dielectric layers.

[0045] Transistors are used as switch or select devices in memory cells of some memory devices, such as dynamic random access memory (DRAM). In a one-transistor-one-capacitor (1T1C) DRAM structure, data is stored in the capacitor. Vertical transistors can have different gate structure architecture designs, such as single metal gate (SMG), double metal gate (DMG), triple metal gate (TMG), and gate all around (GAA). Vertical capacitors are typically formed by a drilling process to create a vertical tube with a limited aperture size. Due to the limitations of the drilling process, it is difficult to increase capacitance with conventional manufacturing processes, and the process window is very small.

[0046] To address one or more of the aforementioned problems, the present disclosure introduces a novel design of a capacitor architecture. Conventional vertically positioned tubular capacitors are changed to planar laminated capacitors. Vertical conductive vias are used to connect the transistor and the capacitor. Polyoxide is used to form an isolation structure between the vertical conductive vias and the planar laminate. Additionally, a silicide structure (e.g., Ti / Co / Ni) can be used to select the capacitor layer to be connected to the vertical conductive vias, thereby avoiding the use of any recessing process. Thus, the goal of layer selection can be achieved by avoiding the problem of conventional capacitors shrinking due to limited aperture sizes resulting from the use of a recessing process, as well as size and uniformity requirements for the vertical holes. Accordingly, the disclosed capacitor stacked structure can achieve large capacitance and size reduction by cooperating with the miniaturization of the transistor.

[0047] FIG. 1 illustrates a schematic diagram of a memory device (100) having a memory cell array, each having a vertical transistor, according to some embodiments of the present disclosure. The memory device (100) may include a memory cell array in which each memory cell (110) comprises a vertical transistor (120) and a storage unit coupled to the vertical transistor (120). In some embodiments as illustrated in FIG. 1, the memory cell array is a DRAM cell array, and the storage unit is a capacitor (130) for storing charge as binary information stored by each DRAM cell. In some other embodiments not illustrated in the drawings, the memory cell array is a PCM cell array, and the storage unit may be a PCM element (e.g., including a chalcogenide alloy) for storing binary information of each PCM cell based on different resistivityes of the PCM element in an amorphous phase and a crystalline phase.

[0048] As illustrated in FIG. 1, memory cells (110) may be arranged in a two-dimensional (2D) array having rows and columns. The memory device (100) may include word lines (150) for controlling switches of vertical transistors (120) within memory cells (110) located in rows by coupling the memory cell array to a peripheral circuit, as well as bit lines (160) for transmitting data to memory cells (110) located in columns and / or receiving data from memory cells (110) by coupling the memory cell array to a peripheral circuit. That is, each word line (150) is coupled to each row of memory cells (110), and each bit line (160) is coupled to each logic column of one or more memory cells (110).

[0049] In some embodiments of the present disclosure, the vertical transistor (120) may be a vertical metal-oxide-semiconductor field-effect transistor (MOSFET). The gate of the vertical transistor (120) is coupled to a word line (150), one of the source and drain of the vertical transistor (120) is coupled to a bit line (160), the other of the source and drain of the vertical transistor (120) is coupled to one electrode of a capacitor (130), and the other electrode of the capacitor (130) is coupled to ground. In some embodiments, the capacitor (130) may have a stacked structure as described in detail below.

[0050] FIG. 2 illustrates a schematic side cross-sectional view of a 3D memory device according to some embodiments of the present disclosure. FIG. 3 illustrates a schematic plan cross-sectional view of a memory device according to some embodiments of the present disclosure. Note that FIG. 3 illustrates a plan cross-section (300) of the memory device illustrated in FIG. 2 along the line AA', whereas FIG. 2 illustrates a cross-section 200 of the 3D memory device illustrated in FIG. 2 along the line BB'.

[0051] As illustrated in FIG. 2, the disclosed memory device may include a transistor layer (220) on a substrate (210). The substrate (210) may be a semiconductor substrate and may include silicon (e.g., single-crystal silicon (c-Si)), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material. In some other embodiments, the substrate (210) may be a carrier substrate and may include any suitable semiconductor material or an electrically non-conductive material such as glass, plastic, or a sapphire wafer.

[0052] The transistor layer (220) may include an array of gate-all-around (GAA) type vertical transistors, or an array of vertical transistors such as a single metal gate (SMG) type vertical transistor, a double metal gate (DMG) type vertical transistor, a triple metal gate (TMG) type vertical transistor, etc. Specifically, the transistor layer (220) may include an array (222) of channel structures, each extending along the vertical direction (as shown in FIG. 2 and FIG. 3), and a gate structure layer (225) along the lateral direction. The gate structure layer (225) may include a plurality of gate structures, each located on one or more sides of the corresponding channel structure (222). Each gate structure may include a gate electrode and a gate dielectric. In some embodiments, the gate structures of the row of vertical transistors along the first lateral direction may form a word line. Thus, the first lateral direction (x direction) may also be referred to as the word line direction. Although not illustrated in FIG. 2, the disclosed memory device may further include a plurality of bit lines extending in a second lateral direction (referred to as the y-direction, bit line direction) which is perpendicular to the first lateral direction. Each bit line may be connected to a corresponding column of vertical transistors along the second lateral direction (y-direction).

[0053] As illustrated in FIG. 2, the disclosed memory device may further include a capacitor stacking structure (240) comprising a first conductive layer (269) (also referred to as the first electrode plate (269)) and a second conductive layer (259) (also referred to as the second electrode plate (259)) alternately stacked along the vertical direction (z direction). In some embodiments, the first thickness of the first conductive layer (269) is different from the second thickness of the second conductive layer (259). As illustrated in FIG. 2 and FIG. 3, one or more conductive walls (260) (also referred to as common electrodes (260)) may extend vertically through the capacitor stacking structure (240) and may be in contact with the first conductive layer (269) but isolated from the second conductive layer (259). A plurality of conductive vias (250) (also referred to as selection electrodes (250)) may each extend vertically through the capacitor stacking structure (240) and may be electrically connected to a corresponding one of the second conductive layers (259) but electrically isolated from the first conductive layer (269) and the other second conductive layer (259) within the capacitor stacking structure (240).

[0054] The first conductive layer (269), the second conductive layer (259), the conductive wall (260) and / or the conductive via (250) may comprise any suitable conductive material such as polysilicon, a metal (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), a metal compound (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.), or a silicide. In some embodiments, the first conductive layer (269), the second conductive layer (259), the conductive wall (260) and / or the conductive via (250) may comprise multiple conductive layers, such as a W layer above a TiN layer. In some embodiments, the second conductive layer (259) and the first conductive layer (269) may comprise the same conductive material. In some other embodiments, the first conductive layer (269) and the conductive wall (260) may comprise a first conductive material, and the second conductive layer (259) and the conductive via (250) may comprise a second conductive material different from the first conductive material.

[0055] In some embodiments, a conductive connection structure (256) may be positioned between one of the conductive vias (250) and one of the corresponding second conductive layers (259) to connect one of the conductive vias (250) to one of the corresponding second conductive layers (259). For example, as shown in FIG. 2, a conductive via (250-1) is electrically coupled to a corresponding conductive layer (259-1) through a conductive connection structure (256-1), a conductive via (250-2) is electrically coupled to a corresponding conductive layer (259-2) through a conductive connection structure (256-2), and a conductive via (250-3) is electrically coupled to a corresponding conductive layer (259-3) through a conductive connection structure (256-3). In some embodiments, the conductive connection structure (256) may comprise a metal silicide material. In some embodiments, each conductive connection structure (256) has a ring structure that laterally surrounds one of the corresponding conductive vias (250).

[0056] In some embodiments, a plurality of isolation structures (280) may be located between a second conductive layer (259) other than the corresponding conductive layer (259) connected to the conductive via (250) and the conductive via (250). Accordingly, the conductive via (250) may be isolated from the unrelated second conductive layer (259). For example, as shown in FIG. 2, the conductive via (250-1) is isolated from the second conductive layer (259) other than the corresponding conductive layer (259-1), the conductive via (250-2) is isolated from the second conductive layer (259) other than the corresponding conductive layer (259-2), and the conductive via (250-3) is isolated from the second conductive layer (259) other than the corresponding conductive layer (259-3). In some embodiments, the isolation structures (280) may comprise any suitable insulating material such as silicon oxide. In some embodiments, each isolation structure (280) has a ring structure that laterally surrounds one of the corresponding conductive vias (250).

[0057] In some embodiments, as illustrated in FIGS. 2 and FIGS. 3, the capacitor stacked structure (240) may further include a dielectric layer (270). The dielectric layer (270) may include a horizontal portion between adjacent first conductive layer (269) and second conductive layer (259), a first vertical portion between a conductive wall (260) and second conductive layer (259), and a second vertical portion between a conductive via (250) and first conductive layer (269). In some embodiments, the dielectric layer comprises any suitable high-K dielectric constant material. In some embodiments, the dielectric layer (270) contacts the side of the conductive wall (260) and the side of the conductive via (250), and the horizontal plane of the first conductive layer (269) and the horizontal plane of the second conductive layer (259).

[0058] As illustrated in FIG. 3, the disclosed memory device may further include a plurality of slit structures (380), each of which extends vertically through a capacitor stack structure (240) and extends laterally along a first direction (x direction) between adjacent rows of conductive vias (250). Each conductive wall (260) may extend laterally along a second direction (y direction) to block the slit structures (380).

[0059] In summary, the conductive wall (260) connected to the first conductive layer (269) together forms a common first electrode (or upper electrode) of the capacitor of the capacitor stacking structure (240), and the conductive via (250) connected to the second conductive layer (259) together forms a plurality of individual second electrodes (or lower electrodes) each connected to a corresponding transistor in the array of transistors within the transistor layer (220) through a corresponding storage node contact (SNC) structure.

[0060] In some embodiments, one or more peripheral circuits (not shown) may be coupled to the disclosed memory device illustrated in FIG. 2 and FIG. 3 through bit lines, word lines, a common electrode of a capacitor, a select electrode of a capacitor, and any other suitable metal wiring. It should be noted that one or more peripheral circuits may include any suitable circuits for facilitating the operation of the disclosed memory device by applying and detecting voltage signals and / or current signals to and from each memory cell through word lines and bit lines. One or more peripheral circuits may include various types of peripheral circuits formed using CMOS technology.

[0061] FIG. 4 illustrates a block diagram of a system (400) having a memory device according to some embodiments of the present disclosure. The system (400) may be a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device inside. As illustrated in FIG. 4, the system (400) may include a memory system (402) having one or more memory devices (404) and a memory controller (406) and a host (408). The host (408) may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host (408) may be configured to transmit data to the memory device (404) or receive data from the memory device (404). The memory device (404) may be any memory device disclosed in this specification, such as the memory device shown in FIG. 2 and FIG. 3.

[0062] A memory controller (406) is coupled to a memory device (404) and a host (408) and is configured to control the memory device (404) according to some embodiments. The memory controller (406) can manage data stored in the memory device (404) and communicate with the host (408). The memory controller (406) may be configured to control operations of the memory device (404), such as read, write, and refresh operations. The memory controller (406) may also be configured to manage various functions related to data stored or to be stored in the memory device (404), including but not limited to refresh and timing control, command / request conversion, buffer and scheduling, and power management. In some embodiments, the memory controller (406) is additionally configured to determine the maximum memory capacity available to the computer system, the number of memory banks, memory type and speed, memory particle data depth and data width, and other important parameters. Other appropriate functions may also be performed by the memory controller (406). The memory controller (406) can communicate with an external device (e.g., a host (408)) according to a specific communication protocol.For example, the memory controller (406) can communicate with an external device through at least one of various interface protocols such as the USB protocol, MMC protocol, peripheral component interconnection (PCI) protocol, PCI-express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer small interface (SCSI) protocol, enhanced small disk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, FireWire protocol, etc.

[0063] FIG. 5 illustrates a flowchart of a manufacturing method (500) for forming a 3D memory device according to some embodiments of the present disclosure. FIGS. 6a–6b, FIGS. 7a–7b, FIGS. 8a–8b, FIGS. 9a–9b, FIGS. 10–11, FIGS. 12a–12b, FIGS. 13a–13b, FIGS. 14, and FIGS. 15a–15b illustrate schematic side cross-sectional views and / or plan cross-sectional views of a 3D memory device at a specific manufacturing step of the method (500) illustrated in FIG. 5 according to various embodiments of the present disclosure. It should be understood that the operations illustrated in the method (500) are not exhaustive and that other operations may be performed before, after, or between the illustrated operations. Additionally, some operations may be performed in a different order or simultaneously than those illustrated in FIG. 5.

[0064] As illustrated in FIG. 5, the method (500) may begin with an operation (510), wherein a stacked structure may be formed on an array of transistors. The stacked structure may include semiconductor layers and sacrificial layers alternately stacked along a vertical direction. FIG. 6a illustrates a schematic side cross-sectional view of a 3D memory device after the operation (510) of the method (500). FIG. 6b illustrates a schematic plan cross-sectional view of a 3D memory device after the operation (510) of the method (500). Note that FIG. 6a illustrates a schematic side cross-sectional view of the 3D memory device illustrated in FIG. 6b along the line BB' in the yz plane, and FIG. 6b illustrates a schematic plan cross-sectional view of the 3D memory device illustrated in FIG. 6a along the line AA' in the xy plane.

[0065] In some embodiments as illustrated in FIG. 6a, a transistor layer may be formed on a substrate (610). The substrate (610) may be a semiconductor substrate and may comprise silicon (e.g., single-crystal silicon (c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material. In some other embodiments, the substrate (610) may be a carrier substrate and may comprise any suitable semiconductor material or an electrically non-conductive material such as glass, plastic, or a sapphire wafer.

[0066] In some embodiments as illustrated in FIG. 6a, the formed transistor layer (620) may include an array of vertical transistors. Specifically, the step of forming the transistor layer (220) may include the step of forming an array of channel structures (622) on a substrate (610), each extending along a vertical direction (z direction). The array of channel structures (622) may be formed by any suitable process. For example, a semiconductor layer may be formed on the substrate (610) by performing a deposition process (e.g., chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc.). A subsequent lithography process can be applied to pattern the semiconductor layer using an etching mask (e.g., a photoresist mask and / or a hard mask), and one or more dry etching and / or wet etching processes, such as RIE, are performed on the semiconductor layer to etch parts of the semiconductor layer to form an array of channel structures (622).

[0067] In some embodiments, the material of the channel structure (622) may include any suitable semiconductor material. For example, the material of the channel structure (622) may be polysilicon. As another example, the material of the channel structure (622) may be a metal oxide semiconductor material such as IGZO. It is understood that the cross-section of each channel structure (622) may have any suitable shape, such as a square shape, a rectangular shape (or a trapezoidal shape), a circular shape, a partially circular shape, an elliptical shape, a partially elliptical shape, or any other suitable shape.

[0068] In some embodiments, the step of forming the transistor layer (620) may further include the step of forming a gate structure layer (625) along the lateral direction. The gate structure layer (625) may be formed to include a plurality of gate structures each located on one or more sides of the corresponding channel structure (622). Thus, the array of vertical transistors formed may be a gate-all-around (GAA) type vertical transistor, a single metal gate (SMG) type vertical transistor, a double metal gate (DMG) type vertical transistor, or a triple metal gate (TMG) type vertical transistor, etc. Although not shown in FIG. 6a, each gate structure may include a gate electrode and a gate dielectric. The gate electrode may include any suitable conductive material such as polysilicon, a metal (e.g., W, Cu, Al, etc.), a metal compound (e.g., TiN, TaN, etc.), or a silicide. For example, the gate electrode may comprise doped polysilicon, i.e., gate poly. In some other embodiments, the gate electrode may comprise multiple conductive layers, such as a W layer on a TiN layer. The gate dielectric may comprise any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-dielectric constant (high-k) dielectric. In some embodiments, the gate structures of a vertical transistor row along a first lateral direction may be formed to be connected to each other to form a word line extending along the first lateral direction (x direction).

[0069] In some embodiments, although not shown in FIG. 6a, the step of forming the transistor layer (620) may further include the step of forming a plurality of storage node contact (SNC) structures (not shown), each of which contacts an end (e.g., an upper end) of a corresponding channel structure among an array of channel structures (622). The SNC structures may include any suitable conductive material such as polysilicon, a metal (e.g., W, Cu, Al, etc.), a metal compound (e.g., TiN, TaN, etc.), a silicide, and / or a combination thereof. Additionally, the step of forming the transistor layer (620) may further include the step of forming a plurality of bit lines (not shown), each extending in a second lateral direction (y-direction) and connected to an end (e.g., a lower end) of a corresponding column of vertical transistors along the second lateral direction (y-direction). For example, the substrate (610) may be thinned, and a conductive layer may be formed and patterned to form the bit lines. The bit line may include any suitable conductive material such as polysilicon, metals (e.g., W, Cu, Al, etc.), metal compounds (e.g., TiN, TaN, etc.), or silicides. For example, the bit line may include multiple conductive layers, such as a W layer above a TiN layer.

[0070] As illustrated in FIG. 6a, an etch stop layer (630) may be formed on the transistor layer (620), and a stacked structure (640) may be formed on the etch stop layer (630). In some embodiments, the etch stop layer (630) may be formed by a thin film deposition process such as CVD, PVD, ALD, etc. The etch stop layer (630) may include any suitable dielectric material such as silicon nitride, silicon oxynitride, or a high-dielectric constant (high-k) dielectric. The stacked structure (640) may include semiconductor layers (644) and sacrificial layers (642) alternately stacked along the vertical direction (z direction). In some embodiments, the alternately stacked semiconductor layers (644) and sacrificial layers (642) may be formed by a plurality of thin film deposition processes such as CVD, PVD, ALD, etc. The semiconductor layer (644) may comprise any suitable semiconductor material such as Si (e.g., c-Si, poly-Si), SiGe, GaAs, Ge, etc. The sacrificial layer (642) may be an insulating layer comprising any suitable insulating material having an etching rate different from the etching rate of the material of the semiconductor layer (644) during one or more optional etching processes. In some embodiments, the sacrificial layer (642) comprises silicon nitride.

[0071] Referring again to FIG. 5, the method (500) may proceed to operation (520), where a slit structure may be formed within a stacked structure. Each slit structure may extend vertically through the stacked structure and extend laterally along a first direction. FIG. 7a illustrates a schematic side cross-sectional view of a 3D memory device after operation (520) of the method (500). FIG. 7b illustrates a schematic plan cross-sectional view of a 3D memory device after operation (520) of the method (500). Note that FIG. 7a illustrates a schematic side cross-sectional view of the 3D memory device illustrated in FIG. 7b along the line BB' in the yz plane, and FIG. 7b illustrates a schematic plan cross-sectional view of the 3D memory device illustrated in FIG. 7a along the line AA' in the xy plane.

[0072] As illustrated in FIGS. 6a and 6b, the stacked structure (640) may be patterned to form a plurality of first slits (650), each extending along a first lateral direction (x direction) and arranged parallel to a second lateral direction (y direction). The plurality of first slits (650) may extend vertically through the stacked structure (640) and stop at an etching stop layer (630), and may extend laterally along the first lateral direction (x direction). The plurality of first slits (650) may be formed by any suitable etching process (e.g., photolithography, dry etching, wet etching, cleaning, etc.).

[0073] As illustrated in FIGS. 7a and 7b, a plurality of slit structures (750) may be formed within the first slit (650). The slit structures (750) may comprise any suitable dielectric material, such as silicon oxide, silicon oxynitride, or a high-dielectric constant (high-k) dielectric. In some embodiments, the slit structures (750) may be formed by any suitable deposition process, such as CVD, PVD, ALD, etc., followed by a chemical mechanical polishing (CMP) process. The formed slit structures (750) may extend laterally parallel to the first lateral direction (x direction).

[0074] Referring again to FIG. 5, the method (500) may proceed to operation (530), where a plurality of via holes having different depths may be formed within the stacked structure. Each via hole may stop at a corresponding one of the sacrificial layers. FIG. 8a illustrates a schematic side cross-sectional view of a 3D memory device after operation (530) of the method (500). FIG. 8b illustrates a schematic plan cross-sectional view of a 3D memory device after operation (530) of the method (500). Note that FIG. 8a illustrates a schematic side cross-sectional view of the 3D memory device illustrated in FIG. 8b along the CC' line in the xz plane, and FIG. 8b illustrates a schematic plan cross-sectional view of the 3D memory device illustrated in FIG. 8a along the AA' line in the xy plane.

[0075] As illustrated in FIGS. 8a and 8b, an array of via holes (850) may be formed in a stacked structure (640). Each via hole (850) may be stopped at a corresponding one of the sacrificial layers (642). In this way, each individual via hole (e.g., via hole (850-1), via hole (850-2), via hole (850-3), etc.) may have different depths in the vertical direction (z direction). As illustrated in the plan view of FIG. 8b, the array of via holes (850) may be arranged in rows extending parallel along a first lateral direction (x direction) and columns extending parallel along a second lateral direction (y direction). In some embodiments, one or more rows of via holes (850) may be located between adjacent slit structures (750). In some embodiments, the array of via holes (850) may be formed by any suitable etching process.

[0076] Referring again to FIG. 5, the method (500) can proceed to operation (540), whereby an isolation structure can be formed by oxidizing the exposed surface of the semiconductor layer through a via hole. FIG. 9a illustrates a schematic side cross-sectional view of a 3D memory device after operation (540) of the method (500). FIG. 9b illustrates a schematic plan cross-sectional view of a 3D memory device after operation (540) of the method (500). Note that FIG. 9a illustrates a schematic side cross-sectional view of the 3D memory device illustrated in FIG. 9b along the CC' line in the xz plane, and FIG. 9b illustrates a schematic plan cross-sectional view of the 3D memory device illustrated in FIG. 9a along the AA' line in the xy plane.

[0077] As illustrated in FIG. 9a and FIG. 9b, the exposed surface of the sidewall of the semiconductor layer (644) by the via hole (850) can be oxidized to form an isolation structure (960). As illustrated in FIG. 9b, each isolation structure (960) has a ring-shaped structure that laterally surrounds the corresponding via hole (850). Since the via holes (850) have different depths in the vertical direction (z direction) and expose different numbers of semiconductor layers (644) in the stacked structure (640), the number of isolation structures (960) formed in different via holes (850) corresponds to the number of semiconductor layers (644) penetrated by each via hole (850). For example, as illustrated in FIG. 9a, the via holes (850-1), via holes (850-2), and via holes (850-3) each expose a different number of semiconductor layers (644) in the stacked structure (640), so the number of isolation structures (960) formed in the via holes (850-1), via holes (850-2), and via holes (850-3) is also different.

[0078] Referring again to FIG. 5, the method (500) can proceed to operation (550), wherein the via holes are further etched to extend the depth of the via holes to a first extent, so that each first extended via hole exposes a lower semiconductor layer without an isolation structure, and through the first extended via holes, a conductive connection structure can be formed on the exposed sidewall of the semiconductor layer without an isolation structure. FIG. 10 illustrates a schematic side cross-sectional view of a 3D memory device after operation (550) of the method (500).

[0079] As illustrated in FIG. 10, the via hole (850) may be further etched to extend the depth to a first extent, so that each first extended via hole (1050) (e.g., first extended via holes (1050-1, 1050-2, 1050-3)) may expose one lower semiconductor layer (644) without an isolation structure (960). A conductive connection structure (1070) (e.g., conductive connection structures (1070-1, 1070-2, 1070-3)) may each be formed on the exposed sidewall of the semiconductor layer (644) without an isolation structure (960) through the first extended via hole (1050). In some embodiments, the conductive connection structure (1070) may comprise a metal silicide material such as titanium silicide, nickel silicide, cobalt silicide, etc. A conductive connection structure (1070) may be formed by performing metal ion implantation and / or thermal diffusion to modify the exposed surface of the exposed sidewall of the semiconductor layer (644) without the isolation structure (960) through the first extended via hole (1050). In some embodiments, each conductive connection structure (1070) may have a ring structure that laterally surrounds one of the first extended via holes (1050).

[0080] Referring again to FIG. 5, the method (500) can proceed to operation (560), wherein the depth of the first extended via hole is further extended by etching the first extended via hole, so that the formed second extended via hole stops at the etching stop layer, and the exposed surface of the semiconductor layer is oxidized through the second extended via hole to form an additional isolation structure. FIG. 11 illustrates a schematic side cross-sectional view of a 3D memory device after operation (560) of the method (500).

[0081] As illustrated in FIG. 11, the first extended via hole (1050) may be further etched to extend the depth to a second extent, so that each second extended via hole (1150) (e.g., second extended via holes (1150-1, 1150-2, 1150-3)) may expose one lower semiconductor layer (644) without an isolation structure (960). Since the second extended via hole (1150) may stop at the etch stop layer (630), it has the same depth. The second extended via hole (1150) may expose the sidewall of the semiconductor layer (644) below the conductive connection structure (1070) at each of the second extended via holes (1050). The exposed surface of the sidewall of the semiconductor layer (644) below the conductive connection structure (1070) in the second extended via hole (1050) may be oxidized to form an additional isolation structure (1160). Each additional isolation structure (1160) has a ring-shaped structure that laterally surrounds one of the second extended via holes (1150).

[0082] Referring again to FIG. 5, the method (500) can proceed to operation (570), wherein the second extended via hole is further etched to extend the depth of the second extended via hole to a third, so that the formed third extended via hole extends through the etch stop layer to expose the transistor layer, and a plurality of conductive vias can be formed within the third extended via hole to be coupled with the transistor layer. FIG. 12a illustrates a schematic side cross-sectional view of a 3D memory device after operation (570) of the method (500). FIG. 12b illustrates a schematic plan cross-sectional view of a 3D memory device after operation (570) of the method (500). Note that FIG. 12a illustrates a schematic side cross-sectional view of the 3D memory device illustrated in FIG. 12b along the CC' line in the xz plane, and FIG. 12b illustrates a schematic plan cross-sectional view of the 3D memory device illustrated in FIG. 12a along the AA' line in the xy plane.

[0083] As illustrated in FIG. 12a and FIG. 12b, the second extended via hole (1150) may be further etched to extend its depth to a third, and the third extended via hole formed thereby extends through the etch stop layer (630) to expose the transistor layer (620). In some embodiments, any suitable etching process, such as a punch operation, may be performed to remove a portion of the etch stop layer (630) thereby exposing the SNC structure of the array of vertical transistors within the transistor layer (620). Then, a deposition process such as CVD, PVD, ALD, etc., may be performed to fill the third extended via hole, thereby forming a plurality of conductive vias (1250) (e.g., conductive vias (1250-1, 1250-2, 1250-3)) within the third extended via hole. Each conductive via (1250) can extend vertically through the stacked structure (640) and the etching stop layer (630) and can come into contact with the SNC structure of the array of vertical transistors within the transistor layer (620).

[0084] Referring again to FIG. 5, the method (500) may proceed to operation (580), wherein the semiconductor layer may be replaced with a plurality of second conductive layers. In some embodiments, the step of replacing the semiconductor layer with the second conductive layer includes forming one or more slits that extend vertically through the stacked structure and stop at an insulating layer, removing the semiconductor layer through the slits to form a first horizontal trench, and forming a second conductive layer within the first horizontal trench. FIG. 13a illustrates a schematic side cross-sectional view of a 3D memory device after operation (580) of the method (500). FIG. 13b illustrates a schematic plan cross-sectional view of a 3D memory device after operation (580) of the method (500). Note that FIG. 13a illustrates a schematic side cross-sectional view of the 3D memory device illustrated in FIG. 13b along the CC' line in the xz plane, and FIG. 13b illustrates a schematic plan cross-sectional view of the 3D memory device illustrated in FIG. 13a along the AA' line in the xy plane.

[0085] As illustrated in FIGS. 13a and 13b, the stacked structure (640) may be patterned to form a plurality of second slits (1360), each extending along a second lateral direction (y direction) and arranged parallel to a first lateral direction (x direction). The plurality of second slits (1360) may extend vertically through the stacked structure (640) and stop at an etching stop layer (630), and may extend laterally along the second lateral direction (y direction). The plurality of second slits (1360) may be formed by any suitable etching process (e.g., photolithography, dry etching, wet etching, cleaning, etc.). The semiconductor layer (644) of the stacked structure (640) may be removed through the second slit (1360) to form a first horizontal trench (not shown), and a second conductive layer (1344) may be formed within the first horizontal trench by any suitable deposition process such as CVD, PVD, ALD, etc. In some embodiments, the second conductive layer (1344) may comprise any suitable conductive material such as a metal (e.g., W, Cu, Al, etc.) or a metal compound (e.g., TiN, TaN, etc.).

[0086] Referring again to FIG. 5, the method (500) may proceed to operation (590), wherein a sacrificial layer may be replaced with a plurality of first conductive layers and one or more conductive walls may be formed. In some embodiments, the step of replacing the sacrificial layer with the first conductive layer includes removing a portion of the second conductive layer exposed by the second slit, removing the sacrificial layer through the second slit to form a second horizontal trench, forming a dielectric layer within the second horizontal trench and on the side wall of the vertical trench to cover the exposed surface of the second conductive layer, and forming the first conductive layer within the second horizontal trench. One or more conductive walls may be formed within the second slit. FIG. 14 illustrates a schematic side cross-sectional view of a 3D memory device during operation (590) of the method (500). FIG. 15a illustrates a schematic side cross-sectional view of a 3D memory device after operation (590) of the method (500). FIG. 15b illustrates a schematic planar cross-sectional view of a 3D memory device after the operation (590) of the method (500). Note that FIG. 15a illustrates a schematic side cross-sectional view of the 3D memory device illustrated in FIG. 15b along the CC' line in the xz plane, and FIG. 15b illustrates a schematic planar cross-sectional view of the 3D memory device illustrated in FIG. 15a along the AA' line in the xy plane.

[0087] As illustrated in FIG. 14, a portion of the conductive material deposited in the second slit (1360) and a portion of the second conductive layer (1344) adjacent to the second slit (1360) may first be removed by any suitable etching / cleaning process, and the sacrificial layer (642) may be removed through the second slit (1360) to form a plurality of second horizontal trenches (1442). The sacrificial layer (642) may be removed by any suitable selective etching process. The formed plurality of second horizontal trenches (1442) may expose the upper and lower surfaces of the second conductive layer (1344) and portions of the sidewalls of the plurality of conductive vias (1250).

[0088] As illustrated in FIGS. 15a and 15b, a dielectric layer (1548) may be formed within the second horizontal trench (1442) and on the sidewall of the second slit (1360) to cover the exposed surface of the second conductive layer (1344) and the exposed sidewall of the plurality of conductive vias (1250). In some embodiments, the dielectric layer (1548) may include any suitable high-k dielectric material, including but not limited to Al2O3, HfO2, Ta2O5, ZrO2, TiO2, or any combination thereof, and may be formed by any suitable thin film deposition process (e.g., CVD, PVD, ALD, etc.). In some embodiments, a conductive material may then be deposited within the second horizontal trench (1442) and the second slit (1360) to form the first conductive layer (1542) and the conductive wall (1560), respectively. The first conductive layer (1542) and the conductive wall (1560) can be formed by any suitable deposition process such as CVD, PVD, ALD, etc. and may include any suitable conductive material such as a metal (e.g., W, Cu, Al, etc.) or a metal compound (e.g., TiN, TaN, etc.).

[0089] The foregoing description of specific embodiments may be readily modified and / or adapted for various applications. Accordingly, such adaptations and modifications are intended to be within the meaning and scope of equivalents of the disclosed embodiments, based on the teachings and guidelines set forth in this specification.

[0090] The breadth and scope of the present disclosure shall not be limited by any of the embodiments described above, but shall be defined only by the following claims and their equivalents.

Claims

Claim 1 A semiconductor device comprising: a stacked structure including a first conductive layer and a second conductive layer alternately stacked along a vertical direction; a conductive wall extending vertically through the stacked structure and in contact with the first conductive layer but isolated from the second conductive layer; and a conductive via, each extending vertically through the stacked structure and electrically connected to a corresponding one of the second conductive layers but electrically isolated from the first conductive layer and the other second conductive layer within the stacked structure. Claim 2 A semiconductor device according to claim 1, further comprising an isolation structure positioned between the conductive via and the other second conductive layer to isolate the conductive via and the other second conductive layer. Claim 3 A semiconductor device according to paragraph 2, further comprising a conductive connection structure, each positioned between one of the conductive vias and a corresponding one of the second conductive layers, and connecting one of the conductive vias to the corresponding one of the second conductive layers. Claim 4 A semiconductor device according to paragraph 3, wherein the isolation structure comprises silicon oxide and the conductive connection structure comprises a metal silicide material. Claim 5 A semiconductor device according to paragraph 3, wherein each of the isolation structure and the conductive connection structure has a ring structure that laterally surrounds a corresponding one of the conductive vias. Claim 6 A semiconductor device according to claim 1, wherein the second conductive layer and the first conductive layer comprise the same conductive material. Claim 7 A semiconductor device according to claim 1, wherein the first conductive layer and the conductive wall comprise a first conductive material, and the second conductive layer and the conductive via comprise a second conductive material different from the first conductive material. Claim 8 A semiconductor device according to claim 1, further comprising a dielectric layer, wherein the dielectric layer comprises: a horizontal portion between an adjacent first conductive layer and a second conductive layer; a first vertical portion between the conductive wall and the second conductive layer; and a second vertical portion between the conductive via and the first conductive layer. Claim 9 A semiconductor device according to claim 8, wherein the dielectric layer comprises a high-dielectric (high-K) material. Claim 10 A semiconductor device according to claim 8, wherein the dielectric layer contacts the side of the conductive wall and the side of the conductive via, and the horizontal plane of the first conductive layer and the horizontal plane of the second conductive layer. Claim 11 A semiconductor device according to claim 1, further comprising an array of transistors each coupled to the conductive vias. Claim 12 A semiconductor device according to claim 11, wherein the transistor is a vertical gate transistor comprising a channel structure extending along a vertical direction and a gate structure on the side of the channel structure. Claim 13 A semiconductor device according to claim 11, further comprising an insulating layer between the stacked structure and the array of transistors, wherein each conductive via extends through the insulating layer and is coupled to a corresponding transistor among the array of transistors. Claim 14 A semiconductor device according to claim 1, wherein the first thickness of the first conductive layer is different from the second thickness of the second conductive layer. Claim 15 A semiconductor device according to claim 1, further comprising a slit structure that extends vertically through the stacked structure and extends laterally along a first direction between adjacent rows of conductive vias, wherein the conductive wall extends laterally along a second direction to block the slit structure. Claim 16 As a memory device, as a capacitor stacked structure, First electrode plates and second electrode plates alternately stacked along the vertical direction, A common electrode that extends vertically through the capacitor stacked structure and contacts the first electrode plate, and A memory device comprising: a capacitor stacking structure, each comprising a selection electrode that extends through the capacitor stacking structure and contacts a corresponding one of the second electrode plates; and an array of transistors each coupled to a corresponding one of the selection electrodes. Claim 17 A memory device according to claim 16, further comprising a high-dielectric (high-K) layer between adjacent first electrode plates and second electrode plates, between the first electrode plate and the common electrode, and between the second electrode plate and the select electrode. Claim 18 A memory device according to claim 16, further comprising: a conductive connection structure, each positioned between one of the selection electrodes and a corresponding one of the second electrode plates, electrically connecting one of the selection electrodes and the corresponding one of the second electrode plates; and an isolation structure between one of the selection electrodes and another second electrode plate that is different from the corresponding one of the second electrode plates. Claim 19 A memory device according to claim 18, wherein the isolation structure comprises silicon oxide and the conductive connection structure comprises a metal silicide material. Claim 20 A memory device according to claim 18, wherein each of the isolation structure and the conductive connection structure has a ring structure that laterally surrounds a corresponding one of the selection electrodes. Claim 21 In claim 16, the memory device wherein the first electrode plate and the second electrode plate comprise the same conductive material. Claim 22 A memory device according to claim 16, wherein the first electrode plate and the common electrode comprise a first conductive material, and the second electrode plate and the selection electrode comprise a second conductive material different from the first conductive material. Claim 23 A memory device according to claim 16, further comprising an insulating layer between the capacitor stacking structure and the array of transistors, wherein the selection electrode extends through the insulating layer. Claim 24 In claim 16, the memory device wherein the transistor is a two-dimensional transistor or a vertical gate transistor. Claim 25 A memory device according to claim 16, further comprising a slit structure that extends vertically through the capacitor stacking structure between adjacent rows of selection electrodes and extends laterally along a first direction, wherein the common electrode extends laterally along a second direction to block the slit structure. Claim 26 A method for forming a semiconductor device, comprising: forming a stacked structure on an array of transistors, wherein the stacked structure comprises semiconductor layers and sacrificial layers alternately stacked along a vertical direction; forming an isolation structure and a conductive connection structure on an exposed sidewall of a semiconductor layer within the through hole, wherein each through hole is formed to extend vertically through the stacked structure and each through hole has a conductive connection structure in contact with a corresponding one of the semiconductor layers, wherein the sidewall of another semiconductor layer is covered by the isolation structure; forming a conductive via within the through hole to connect the array of transistors; replacing the semiconductor layer with a second conductive layer; and replacing the sacrificial layer with a first conductive layer. Claim 27 A method for forming a semiconductor device according to claim 26, further comprising the step of forming an insulating layer on an array of transistors, wherein the stacked structure is formed on the insulating layer. Claim 28 A method for forming a semiconductor device according to claim 27, wherein forming the through hole, the isolation structure, and the conductive connection structure comprises forming via holes having different depths within the stacked structure, wherein each via hole stops at a corresponding one of the sacrificial layers; and forming the isolation structure by oxidizing the exposed surface of the semiconductor layer through the via hole. Claim 29 A method for forming a semiconductor device according to claim 28, wherein forming the through hole, the isolation structure, and the conductive connection structure comprises: extending the depth of the via hole first such that each via hole exposes a lower semiconductor layer without the isolation structure; and forming the conductive connection structure on the exposed sidewall of the semiconductor layer without the isolation structure through the first extended via hole. Claim 30 A method for forming a semiconductor device according to claim 29, wherein forming the through hole, the isolation structure, and the conductive connection structure comprises: extending the depth of the via hole a second time so that each via hole stops at the insulating layer; and oxidizing the exposed surface of the semiconductor layer through the second extended via hole to form an additional isolation structure. Claim 31 A method for forming a semiconductor device according to claim 30, wherein forming the through hole, the isolation structure, and the conductive connection structure comprises forming the through hole by extending the depth of the via hole a third time so that each through hole extends through the insulating layer and exposes a corresponding one of the transistors. Claim 32 A method for forming a semiconductor device according to claim 31, wherein the step of replacing the semiconductor layer with a second conductive layer comprises: forming a vertical trench that extends vertically through the stacked structure and stops at the insulating layer; removing the semiconductor layer through the vertical trench to form a first horizontal trench; and forming the second conductive layer within the first horizontal trench. Claim 33 A method for forming a semiconductor device according to claim 32, wherein the step of replacing the sacrificial layer with the first conductive layer comprises: removing a portion of the second conductive layer exposed by the vertical trench; removing the sacrificial layer through the vertical trench to form a second horizontal trench; forming a dielectric layer in the second horizontal trench and on the sidewall of the vertical trench to cover the exposed surface of the second conductive layer; and forming the first conductive layer in the second horizontal trench. Claim 34 A method for forming a semiconductor device according to claim 26, further comprising the step of forming a slit structure that extends vertically through the stacked structure and extends laterally along a first direction, wherein a row of through holes is formed between adjacent first slit structures.

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