Display device and electronic device
Patent Information
- Application Number
- KR1020250031056
- Authority / Receiving Office
- KR · KR
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2025-03-11
- Publication Date
- 2026-09-21
Smart Images
Figure PAT00006_ABST
Abstract
Description
Technology Field
[0001] The present invention relates to a display device, and in particular to a display device and an electronic device in which the area of the display region can be expanded. Background Technology
[0002] An organic light emitting display apparatus includes a display element whose brightness changes with current, such as an organic light emitting diode. The problem to be solved
[0003] The purpose of the present invention is to provide a display device and an electronic device in which the area of the display region can be expanded.
[0004] The problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below. means of solving the problem
[0005] A display device according to one embodiment for achieving the above-mentioned purpose comprises: a substrate having a display area and a non-display area; and a driving circuit layer, a pixel circuit layer, and a display element layer disposed on the substrate, wherein the driving circuit layer is connected to a pixel circuit of the pixel circuit layer, and the pixel circuit of the pixel circuit layer is connected to a light-emitting element of the display element layer, and the driving circuit layer, the pixel circuit layer, and the display element layer are disposed on the display area of the substrate so as to overlap in a direction perpendicular to the extension direction of the substrate, wherein the driving circuit layer includes a first transistor, and the pixel circuit layer includes a second transistor provided in the pixel circuit and connected to the first transistor, wherein the first transistor is a MOSFET and the second transistor is an oxide semiconductor transistor.
[0006] A display device according to one embodiment for achieving the above-mentioned purpose comprises: a substrate having a display area and a non-display area; and a driving circuit layer, a pixel circuit layer, and a display element layer disposed on the substrate, wherein the driving circuit layer is connected to a pixel circuit of the pixel circuit layer, and the pixel circuit of the pixel circuit layer is connected to a light-emitting element of the display element layer, and the driving circuit layer, the pixel circuit layer, and the display element layer are disposed on the display area of the substrate so as to overlap in a direction perpendicular to the extension direction of the substrate, wherein the driving circuit layer includes a first transistor, and the pixel circuit layer includes a second transistor provided in the pixel circuit and connected to the first transistor, and the first transistor and the second transistor are each oxide semiconductor transistors.
[0007] In addition, an electronic device according to one embodiment for achieving the above-mentioned purpose includes a display device that provides a display screen, wherein the display device includes a substrate having a display area and a non-display area; and a driving circuit layer, a pixel circuit layer, and a display element layer disposed on the substrate, wherein the driving circuit layer is connected to a pixel circuit of the pixel circuit layer, and the pixel circuit of the pixel circuit layer is connected to a light-emitting element of the display element layer, and the driving circuit layer, the pixel circuit layer, and the display element layer are disposed on the display area of the substrate so as to overlap in a direction perpendicular to the extension direction of the substrate, wherein the driving circuit layer includes a first transistor, and the pixel circuit layer includes a second transistor provided in the pixel circuit and connected to the first transistor, wherein the first transistor is a MOSFET and the second transistor is an oxide semiconductor transistor.
[0008] Specific details of other embodiments are included in the detailed description and drawings. Effects of the invention
[0009] According to one embodiment, the area of the display area can be expanded.
[0010] For example, since the driving circuit and pixels are formed in a vertically stacked form in the display area, the area of the non-display area is reduced, while the area of the display area can be expanded.
[0011] Meanwhile, the effects obtainable from the present invention are not limited to those mentioned above, and other unmentioned effects will be clearly understood by those skilled in the art to which the present invention belongs from the description below. Brief explanation of the drawing
[0012] FIG. 1 is an exploded perspective view showing a display device according to one embodiment. FIG. 2 is a block diagram showing a display device according to one embodiment. FIG. 3 is a layout diagram showing an example of a display panel according to one embodiment. FIGS. 4 and FIGS. 5 are layout drawings showing embodiments of the display area of FIG. 3. FIG. 6 is a cross-sectional view of a display panel of a display device according to one embodiment. FIG. 7 is a layout diagram showing an example of a display panel according to another embodiment. FIG. 8 is a cross-sectional view of a display panel of a display device according to one embodiment. FIG. 9 is a diagram illustrating the connection between a scan driving unit and a scan line according to one embodiment. FIG. 10 is a layout diagram showing an example of a display panel according to another embodiment. FIG. 11 is a block diagram of an electronic device according to one embodiment. FIGS. 12, FIGS. 13 and FIGS. 14 are schematic diagrams of electronic devices according to various embodiments. Specific details for implementing the invention
[0013] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims.
[0014] When elements or layers are referred to as being "on" another element or layer, this may include cases where another layer or element is interposed directly on or in the middle of another element. Throughout the specification, the same reference numerals refer to the same components. Shapes, sizes, ratios, angles, numbers, etc., disclosed in the drawings for describing embodiments are exemplary, and therefore the present invention is not limited to the depicted details.
[0015] Although terms such as "first," "second," etc., are used to describe various components, it goes without saying that these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, it goes without saying that the first component mentioned below may also be the second component within the technical scope of the present invention.
[0016] The features of each of the various embodiments of the present invention may be combined or combined with one another, either partially or wholly, and may technically enable various interlocking and operation. Each embodiment may be implemented independently of one another or may be implemented together in an associated relationship.
[0017] Specific embodiments will be described below with reference to the attached drawings.
[0018] FIG. 1 is an exploded perspective view showing a display device according to one embodiment. FIG. 2 is a block diagram showing a display device according to one embodiment.
[0019] Referring to FIGS. 1 and 2, a display device (10) according to one embodiment is a device for displaying video or still images. The display device (10) according to one embodiment can be applied to portable electronic devices such as mobile phones, smartphones, tablet personal computers, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation systems, and ultra mobile PCs (UMPCs). For example, the display device (10) according to one embodiment can be applied to a television, laptop, monitor, billboard, or display unit of the Internet of Things (IOT). Alternatively, the display device (10) according to one embodiment can be applied to a smart watch, a watch phone, or a head-mounted display (HMD) for implementing virtual reality and augmented reality.
[0020] A display device (10) according to one embodiment includes a display panel (100), a heat dissipation layer (200), a circuit board (300), a timing control circuit (400), and a power supply circuit (500).
[0021] The display panel (100) may be formed in a planar shape similar to a rectangle. For example, the display panel (100) may have a planar shape similar to a rectangle having a short side in a first direction (DR1) and a long side in a second direction (DR2) that intersects the first direction (DR1). The corners where the short side in the first direction (DR1) and the long side in the second direction (DR2) meet in the display panel (100) may be formed rounded to have a predetermined curvature or formed at a right angle. The planar shape of the display panel (100) is not limited to a rectangle and may be formed similarly to other polygons, circles, or ellipses. The planar shape of the display device (10) may follow the planar shape of the display panel (100), but the embodiments of the present specification are not limited thereto.
[0022] The display panel (100) includes a plurality of pixels (PX), a plurality of scan lines (SL), a plurality of light emission control lines (EL), and a plurality of data lines (DL), a scan driving unit (610), a light emission driving unit (620), and a data driving unit (700). As shown in FIG. 2, the display panel (100) may be divided into a display area (DAA) that displays an image and a non-display area (NDA) that does not display an image.
[0023] Multiple pixels (PX) may be placed in a display area (DAA). Multiple pixels (PX) may be arranged in a matrix form in a first direction (DR1) and a second direction (DR2). Multiple scan lines (SL) and multiple light emission control lines (EL) may extend in the first direction (DR1) and be placed in the second direction (DR2). Multiple data lines (DL) may extend in the second direction (DR2) and be placed in the first direction (DR1).
[0024] A plurality of scan lines (SL) include a plurality of write scan lines (GWL), a plurality of control scan lines (GCL), and a plurality of bias scan lines (GBL). A plurality of light emission control lines (EL) include a plurality of first light emission control lines (EL1) and a plurality of second light emission control lines (EL2).
[0025] A plurality of pixels (PX) include a plurality of subpixels (SP1, SP2, SP3). The plurality of subpixels (SP1, SP2, SP3) may include transistors.
[0026] Each of the plurality of subpixels (SP1, SP2, SP3) can be connected to one of the plurality of write scan lines (GWL), one of the plurality of control scan lines (GCL), one of the plurality of bias scan lines (GBL), one of the plurality of first light emission control lines (EL1), one of the plurality of second light emission control lines (EL2), and one of the plurality of data lines (DL). Each of the plurality of subpixels (SP1, SP2, SP3) receives a data voltage of the data line (DL) according to the write scan signal of the write scan line (GWL), and can emit light from the light-emitting element according to the data voltage.
[0027] The scan driver (610) and the light-emitting driver (620) may be placed in the display area (DAA). A plurality of pixels, the scan driver (610) and the light-emitting driver (620) may overlap in a third direction (DR3) in the display area (DAA).
[0028] The scan driving unit (610) includes a plurality of scan transistors, and the light-emitting driving unit (620) may include a plurality of light-emitting transistors.
[0029] The scan driving unit (610) may include a write scan signal output unit (611), a control scan signal output unit (612), and a bias scan signal output unit (613). Each of the write scan signal output unit (611), the control scan signal output unit (612), and the bias scan signal output unit (613) may receive a scan timing control signal (SCS) from the timing control circuit (400). The write scan signal output unit (611) may generate write scan signals according to the scan timing control signal (SCS) of the timing control circuit (400) and output them sequentially to the write scan lines (GWL). The control scan signal output unit (612) may generate control scan signals according to the scan timing control signal (SCS) and output them sequentially to the control scan lines (GCL). The bias scan signal output unit (613) may generate bias scan signals according to the scan timing control signal (SCS) and output them sequentially to the bias scan lines (EBL).
[0030] The light-emitting driver (620) may include a first light-emitting control driver (621) and a second light-emitting control driver (622). Each of the first light-emitting control driver (621) and the second light-emitting control driver (622) may receive a light-emitting timing control signal (ECS) from the timing control circuit (400). The first light-emitting control driver (621) may generate first light-emitting control signals according to the light-emitting timing control signal (ECS) and output them sequentially to the first light-emitting control lines (EL1). The second light-emitting control driver (622) may generate second light-emitting control signals according to the light-emitting timing control signal (ECS) and output them sequentially to the second light-emitting control lines (EL2).
[0031] The data driver (700) may be placed in the non-display area (NDA). The data driver (700) may include a plurality of data transistors. The data driver (700) may receive digital video data (DATA) and a data timing control signal (DCS) from the timing control circuit (400). The data driver (700) converts the digital video data (DATA) into analog data voltages according to the data timing control signal (DCS) and outputs them to the data lines (DL). In this case, subpixels (SP1, SP2, SP3) are selected by the write scan signal of the scan driver (610), and data voltages may be supplied to the selected subpixels (SP1, SP2, SP3).
[0032] The heat dissipation layer (200) may overlap with the display panel (100) in a third direction (DR3), which is the thickness direction of the display panel (100). The heat dissipation layer (200) may be placed on one side of the display panel (100), for example, on the back side. The heat dissipation layer (200) serves to dissipate heat generated from the display panel (100). The heat dissipation layer (200) may include a metal layer such as graphite, silver (Ag), copper (Cu), or aluminum (Al), which has high thermal conductivity.
[0033] The circuit board (300) can be electrically connected to a first plurality of pads (PD1 in FIG. 4) of a first pad portion (PDA1 in FIG. 4) of a display panel (100) using a conductive adhesive member such as an anisotropic conductive film. The circuit board (300) may be a flexible printed circuit board having a flexible material or a flexible film. Although FIG. 1 illustrates the circuit board (300) unfolded, the circuit board (300) may be bent. In this case, one end of the circuit board (300) may be placed on the back surface of the display panel (100) and / or the back surface of the heat dissipation layer (200). The other end of the circuit board (300) may be connected to a plurality of first pads (PD1 in FIG. 4) of a first pad portion (PDA1 in FIG. 4) of the display panel (100) using a conductive adhesive member. One end of the circuit board (300) can be the opposite end of the other end of the circuit board (300).
[0034] The timing control circuit (400) can receive digital video data and timing signals from an external source. The timing control circuit (400) can generate a scan timing control signal (SCS), a light emission timing control signal (ECS), and a data timing control signal (DCS) to control the display panel (100) according to the timing signals. The timing control circuit (400) can output the scan timing control signal (SCS) to the scan driver (610) and the light emission timing control signal (ECS) to the light emission driver (620). The timing control circuit (400) can output the digital video data and the data timing control signal (DCS) to the data driver (700).
[0035] The power supply circuit (500) can generate a plurality of panel driving voltages according to the power supply voltage from an external source. For example, the power supply circuit (500) can generate a first driving voltage (VSS), a second driving voltage (VDD), and a third driving voltage (VINT) and supply them to the display panel (100).
[0036] The timing control circuit (400) and the power supply circuit (500) can each be formed as an integrated circuit (IC) and attached to one side of the circuit board (300). In this case, the scan timing control signal (SCS), light emission timing control signal (ECS), digital video data (DATA), and data timing control signal (DCS) of the timing control circuit (400) can be supplied to the display panel (100) through the circuit board (300). Additionally, the first driving voltage (VSS), the second driving voltage (VDD), and the third driving voltage (VINT) of the power supply circuit (500) can be supplied to the display panel (100) through the circuit board (300).
[0037] Alternatively, the timing control circuit (400) and the power supply circuit (500) may each be placed in the non-display area (NDA) of the display panel (100), similar to the scan driver (610), the light-emitting driver (620), and the data driver (700). In this case, the timing control circuit (400) may include a plurality of timing transistors, and each of the power supply circuits (500) may include a plurality of power transistors. The timing control circuit (400) and the power supply circuit (500) may each be placed between the data driver (700) and the first pad section (PDA1 of FIG. 4).
[0038] FIG. 3 is a layout diagram showing an example of a display panel according to one embodiment.
[0039] Referring to FIG. 3, a plurality of pixels (PX), a scan driving unit (610), and a light-emitting driving unit (620) may be arranged in a display area (DAA) of a display panel (100) according to one embodiment. The plurality of pixels (PX) may be arranged in a matrix form in the display area (DAA). For example, a plurality of sub-pixels (SP1, SP2, SP3) may be arranged in a matrix form in the display area (DAA).
[0040] The scan driver (610) and the light-emitting driver (620) may be arranged to overlap with pixels (PX; or sub-pixels (SP1, SP2, SP3)). For example, in a display area (DAA), the scan driver (610) and the light-emitting driver (620) may be arranged to overlap with pixels (PX; or sub-pixels (SP1, SP2, SP3)). Here, when the area of the display area (DAA) that overlaps with the scan driver (610) and the light-emitting driver (620) is defined as the overlap area, and the area of the display area (DAA) that does not overlap with the scan driver (610) and the light-emitting driver (620) is defined as the non-overlap area, the area of the overlap area may be smaller than the area of the non-overlap area.
[0041] A data driving unit (700), a first distribution circuit (710), a second distribution circuit (720), a first pad unit (PDA1), and a second pad unit (PDA2) may be disposed in the non-display area (NDA) of the display panel (100).
[0042] The first pad portion (PDA1) may include a plurality of first pads (PD1) connected to pads or bumps of the circuit board (300) through a conductive adhesive member. The first pad portion (PDA1) may be positioned on the third side of the display area (DAA). For example, the first pad portion (PDA1) may be positioned on one side of the second direction (DR2) of the display area (DAA). The first pad portion (PDA1) may be positioned outside the data driver (700) in the second direction (DR2). For example, the first pad portion (PDA1) may be positioned closer to the edge of the display panel (100) than the data driver (700).
[0043] The second pad section (PDA2) may include a plurality of second pads (PD2) corresponding to test pads that test whether the display panel (100) operates normally. The plurality of second pads (PD2) may be connected to a jig or probe pin in the inspection process or connected to a test circuit board. The test circuit board may be a printed circuit board made of a rigid material or a flexible printed circuit board having a flexible material.
[0044] The second pad portion (PDA2) may be positioned on the fourth side of the display area (DAA). For example, the second pad portion (PDA2) may be positioned on the other side of the second direction (DR2) of the display area (DAA). The second pad portion (PDA2) may be positioned outside the second distribution circuit (720) in the second direction (DR2). That is, the second pad portion (PDA2) may be positioned closer to the edge of the display panel (100) than the second distribution circuit (720).
[0045] The first distribution circuit (710) distributes data voltages applied through the first pad section (PDA1) to a plurality of data lines (DL). For example, the first distribution circuit (710) can distribute data voltages applied through one first pad (PD1) of the first pad section (PDA1) to P data lines (DL) (where P is a positive integer greater than or equal to 2), thereby reducing the number of multiple first pads (PD1). The first distribution circuit (710) may be placed on the third side of the display area (DAA) of the display panel (100). For example, the first distribution circuit (710) may be placed on one side of the second direction (DR2) of the display area (DAA). That is, the first distribution circuit (710) may be placed on the lower side of the display area (DAA). The first distribution circuit (710) may include a plurality of first distribution transistors. The first distribution circuit (710) can be connected to the data driver (700) and the data lines (DL). For example, the first distribution circuit (710) can provide data voltage from the data driver (700) to the data lines (DL).
[0046] The second distribution circuit (720) distributes signals applied through the second pad section (PDA2) to the scan driver (610), the light-emitting driver (620), and the data lines (DL). The second pad section (PDA2) and the second distribution circuit (720) may be configured to inspect the operation of each pixel (PX) of the display area (DAA). The second distribution circuit (720) may be placed on the fourth side of the display area (DAA) of the display panel (100). For example, the second distribution circuit (720) may be placed on the other side of the second direction (DR2) of the display area (DAA). For example, the second distribution circuit (720) may be placed on the upper side of the display area (DAA). The second distribution circuit (720) may include a plurality of second distribution transistors.
[0047] FIGS. 4 and FIGS. 5 are layout drawings showing embodiments of the display area of FIG. 3.
[0048] Referring to FIGS. 4 and FIGS. 5, each of the plurality of pixels (PX) may include a first light-emitting region (EA1) which is a light-emitting region of the first subpixel (SP1), a second light-emitting region (EA2) which is a light-emitting region of the second subpixel (SP2), and a third light-emitting region (EA3) which is a light-emitting region of the third subpixel (SP3).
[0049] Each of the first light-emitting region (EA1), the second light-emitting region (EA2), and the third light-emitting region (EA3) may have a polygonal, circular, elliptical, or irregular planar shape.
[0050] The maximum length of the first direction (DR1) of the first light-emitting region (EA1) may be smaller than the maximum length of the first direction (DR1) of the second light-emitting region (EA2) and the maximum length of the first direction (DR1) of the third light-emitting region (EA3). The maximum length of the first direction (DR1) of the second light-emitting region (EA2) and the maximum length of the first direction (DR1) of the third light-emitting region (EA3) may be substantially the same.
[0051] The maximum length of the second direction (DR2) of the first light-emitting region (EA1) may be longer than the maximum length of the second direction (DR2) of the second light-emitting region (EA2) and the maximum length of the second direction (DR2) of the third light-emitting region (EA3). The maximum length of the second direction (DR2) of the second light-emitting region (EA2) may be longer than the maximum length of the second direction (DR2) of the third light-emitting region (EA3). The maximum length of the second direction (DR2) of the first light-emitting region (EA1) may be shorter than the maximum length of the second direction (DR2) of the second light-emitting region (EA2).
[0052] The first light-emitting region (EA1), the second light-emitting region (EA2), and the third light-emitting region (EA3) may have a hexagonal planar shape consisting of six straight lines as shown in FIGS. 4 and 5, but the embodiments of the present specification are not limited thereto. The first light-emitting region (EA1), the second light-emitting region (EA2), and the third light-emitting region (EA3) may have a polygonal, circular, elliptical, or irregular planar shape other than a hexagon.
[0053] As shown in FIG. 4, in each of the plurality of pixels (PX), the first light-emitting region (EA1) and the second light-emitting region (EA2) may be adjacent in the first direction (DR1). Additionally, the first light-emitting region (EA1) and the third light-emitting region (EA3) may be adjacent in the first direction (DR1). Additionally, the second light-emitting region (EA2) and the third light-emitting region (EA3) may be adjacent in the second direction (DR2). The area of the first light-emitting region (EA1), the area of the second light-emitting region (EA2), and the area of the third light-emitting region (EA3) may be different.
[0054] Alternatively, as shown in FIG. 5, the first light-emitting region (EA1) and the second light-emitting region (EA2) may be adjacent in the first direction (DR1), the second light-emitting region (EA2) and the third light-emitting region (EA3) may be adjacent in the first diagonal direction (DD1), and the first light-emitting region (EA1) and the third light-emitting region (EA3) may be adjacent in the second diagonal direction (DD2). The first diagonal direction (DD1) is a direction between the first direction (DR1) and the second direction (DR2), and is a direction tilted 45 degrees relative to the first direction (DR1) and the second direction (DR2), and the second diagonal direction (DD2) may be a direction orthogonal to the first diagonal direction (DD1).
[0055] The first subpixel (SP1) emits first light that has passed through a first color filter among the light emitted from the first light-emitting region (EA1), the second subpixel (SP2) emits second light that has passed through a second color filter among the light emitted from the second light-emitting region (EA2), and the third subpixel (SP3) can emit third light that has passed through a third color filter among the light emitted from the third light-emitting region (EA3).
[0056] The aforementioned first light, second light, and third light may be lights of different wavelength bands. For example, any one of the first to third lights may be light of the blue wavelength band, another may be light of the green wavelength band, and the remaining one may be light of the red wavelength band. Here, the blue wavelength band refers to a wavelength band in which the main peak wavelength of the light is included in the wavelength band of approximately 370 nm to 460 nm, the green wavelength band refers to a wavelength band in which the main peak wavelength of the light is included in the wavelength band of approximately 480 nm to 560 nm, and the red wavelength band refers to a wavelength band in which the main peak wavelength of the light is included in the wavelength band of approximately 600 nm to 750 nm.
[0057] FIGS. 4 and 5 illustrate that each of the plurality of subpixels (SP1, SP2, SP3) includes three light-emitting regions (EA1, EA2, EA3), but the embodiments of the present specification are not limited thereto.
[0058] In addition, the arrangement of the light-emitting regions of the plurality of pixels (PX) is not limited to that shown in FIGS. 4 and FIGS. 5. For example, the light-emitting regions of the plurality of pixels (PX) may be arranged in a stripe structure in which the light-emitting regions are arranged in a first direction (DR1), a PenTile® structure in which the light-emitting regions have a diamond arrangement, or a hexagonal structure in which the light-emitting regions have a hexagonal planar shape as shown in FIG. 5.
[0059] FIG. 6 is a cross-sectional view of a display panel (100) of a display device (10) according to one embodiment. For example, FIG. 6 may be a cross-sectional view of the display panel (100) of FIG. 3.
[0060] A display panel (100) according to one embodiment may include a substrate (SUB; e.g., a semiconductor substrate (SUB)), a driving circuit layer (DCL), a pixel circuit layer (PCL), and a display element layer (EMTL), as shown in FIG. 6.
[0061] The driving circuit layer (DCL), pixel circuit layer (PCL), and display element layer (EMTL) may be arranged on the display area (DAA) of the semiconductor substrate (SUB) so as to overlap in a direction perpendicular to the extension direction of the semiconductor substrate (SUB) (e.g., first direction (DR1) and second direction (DR2)).
[0062] The pixel circuit layer (PCL) can be placed between the semiconductor substrate (SUB) and the driving circuit layer (DCL).
[0063] The driving circuit layer (DCL) can be placed between the pixel circuit layer (PCL) and the display element layer (EMTL).
[0064] The semiconductor substrate (SUB) may be a wafer substrate. The semiconductor substrate (SUB) may be a substrate doped with Type 1 impurities.
[0065] The driving circuit layer (DCL) may be placed on the display area (DAA) of the semiconductor substrate (SUB). The driving circuit layer (DCL) may include a scan driving unit (610) and a light-emitting driving unit (620).
[0066] The driving circuit layer (DCL) may include a plurality of first transistors (TR1). The first transistor (TR1) may be, for example, a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). In this case, the plurality of first transistors (TR1) may be formed in the form of CMOS (Complementary Metal-Oxide-Semiconductor). The first transistor (TR1) may be, for example, at least one of the scan transistor of the aforementioned scan driving unit (610) and the light-emitting transistor of the light-emitting driving unit (620). In other words, the scan driving unit (610) may include a plurality of first transistors (TR1), and the light-emitting driving unit (620) may include a plurality of first transistors (TR1).
[0067] A well region (WA) may be disposed on the upper surface of a semiconductor substrate (SUB) in a display area (DAA). The well region (WA) may be a region doped with a second type impurity. The second type impurity may be different from the first type impurity described above. For example, if the first type impurity is a p-type impurity, the second type impurity may be an n-type impurity. Or, if the first type impurity is an n-type impurity, the second type impurity may be a p-type impurity.
[0068] The well region (WA) may include a source region (SA) corresponding to the source electrode of the first transistor (TR1) and a drain region (DA) corresponding to the drain electrode.
[0069] A gate insulating layer (GI) may be disposed between the gate electrode (GE) and the well region (WA). A side insulating layer (SW) may be disposed on the side of the gate electrode (GEE).
[0070] The first transistor (TR1) may include a gate electrode (GEE), a source region (SA), and a drain region (DA).
[0071] A pixel circuit layer (PCL) may be disposed on a driving circuit layer (DCL). For example, the pixel circuit layer (PCL) may be disposed on the driving circuit layer (DCL) in a display area (DAA) of a semiconductor substrate (SUB). The pixel circuit layer (PCL) may include a plurality of second transistors (TR2). Here, the second transistor (TR2) may be the aforementioned pixel transistor. A plurality of subpixels may each include a plurality of second transistors (TR2), and the plurality of second transistors (TR2) may be disposed on the pixel circuit layer (PCL). The second transistors (TR2) of the pixel circuit layer (PCL) may be connected to the first transistors (TR1) of the driving circuit layer (DCL) (e.g., a scan transistor and a light-emitting transistor).
[0072] The second transistor (TR2) may include a gate electrode (GE), a source electrode (SE) of the active layer (ACT), and a drain electrode (DE) of the active layer (ACT). The aforementioned second transistor (TR2) may be an oxide-based transistor (e.g., an oxide semiconductor transistor). For example, the second transistor (TR2) may be an N-type oxide-based transistor. In other words, the second transistor (TR2) may include an oxide semiconductor (or an oxide semiconductor material). Since oxide semiconductors have high carrier mobility and low leakage current, the voltage drop is not significant even with a long driving time. For example, in the case of oxide semiconductors, the color change of the image due to voltage drop is not significant even during low-frequency driving, so low-frequency driving is possible. Therefore, by having the second transistor (TR2) include an oxide semiconductor material, it is possible to implement a display device that prevents the occurrence of leakage current while simultaneously reducing power consumption.
[0073] The display element layer (EMTL) may be disposed on the pixel circuit layer (PCL). For example, the display element layer (EMTL) may be disposed on the pixel circuit layer (PCL) in the display area (DAA) of the semiconductor substrate (SUB). A plurality of subpixels (SP1, SP2, SP3) may each include a plurality of light-emitting elements (ED), and the plurality of light-emitting elements (ED) may be disposed on the display element layer (EMTL). One subpixel (e.g., SP1) may include a pixel circuit of the pixel circuit layer (PCL) and a light-emitting element (ED) connected to the pixel circuit. The light-emitting element (ED) may include a first electrode (AND; e.g., an anode electrode), a light-emitting layer (LE; e.g., an organic light-emitting layer), and a second electrode (CAT; e.g., a cathode electrode).
[0074] A first insulating layer (INS1) can be disposed on a semiconductor substrate (SUB).
[0075] A first conductive layer (ML1) may be disposed on the first insulating layer (INS1). The first conductive layer (ML1) may be connected to the drain region (DA) of the first transistor (TR1) through an intermediate connecting electrode (CTE) penetrating the first insulating layer (INS1).
[0076] A second insulating layer (INS2) may be disposed on the first conductive layer (ML1).
[0077] A second conductive layer (ML2) may be disposed on the second insulating layer (INS2). The second conductive layer (ML2) may be connected to the first conductive layer (ML1) through a first via electrode (VA1) that penetrates the second insulating layer (INS2).
[0078] A third insulating layer (INS3) can be disposed on the second conductive layer (ML2).
[0079] A third conductive layer (ML3) may be disposed on the third insulating layer (INS3). The third conductive layer (ML3) may be connected to the second conductive layer (ML2) through a second via electrode (VA2) that penetrates the third insulating layer (INS3).
[0080] A fourth insulating layer (INS4) can be disposed on the third conductive layer (ML3).
[0081] A fourth conductive layer (ML4) may be disposed on the fourth insulating layer (INS4). The fourth conductive layer (ML4) may be connected to the third conductive layer (ML3) through a third via electrode (VA3) that penetrates the fourth insulating layer (INS4).
[0082] A fifth insulating layer (INS5) can be disposed on the fourth conductive layer (ML4).
[0083] A fifth conductive layer (ML5) may be disposed on the fifth insulating layer (INS5). The fifth conductive layer (ML5) may be connected to the fourth conductive layer (ML4) through a fourth via electrode (VA4) that penetrates the fifth insulating layer (INS5).
[0084] A sixth insulating layer (INS6) can be disposed on the fifth conductive layer (ML5).
[0085] A sixth conductive layer (ML6) may be disposed on the sixth insulating layer (INS6). The sixth conductive layer (ML6) may be connected to the fifth conductive layer (ML5) through a fifth via electrode (VA5) that penetrates the sixth insulating layer (INS6).
[0086] A seventh insulating layer (INS7) can be disposed on the sixth conductive layer (ML6).
[0087] An eighth insulating layer (INS8) may be disposed on the seventh insulating layer (INS7).
[0088] An active layer (ACT) may be disposed on the eighth insulating layer (INS8). The active layer (ACT) may include a drain electrode (DE) and a source electrode (SE). The active layer (ACT) may include an oxide. For example, the active layer (ACT) may be a semiconductor layer including indium-gallium-zinc oxide (IGZO) or indium-gallium-zinc-tin oxide (IGZTO). However, it is not limited thereto, and the active layer may include amorphous silicon.
[0089] A gate insulating layer (GI) may be placed on the active layer (ACT).
[0090] A gate electrode (GE) can be placed on the gate insulating layer (GI).
[0091] A ninth insulating layer (INS9) may be disposed on the gate electrode (GE), gate insulating layer (GI), active layer (ACT), and eighth insulating layer (INS8).
[0092] A seventh conductive layer (ML7) may be disposed on the ninth insulating layer (INS9). The seventh conductive layer (ML7) may be connected to the sixth conductive layer (ML6), the gate electrode (GE) of the second transistor (TR2), and the source electrode (SE) of the second transistor (TR2). For example, one of the seventh conductive layers (ML7) may be connected to the sixth conductive layer (ML6) through a sixth via electrode (VA6) penetrating the ninth insulating layer (INS9) and the eighth insulating layer (INS8), another seventh conductive layer (ML7) may be connected to the gate electrode (GE) through a sixth via electrode (VA6) penetrating the ninth insulating layer (INS9), and yet another seventh conductive layer (ML7) may be connected to the source electrode (SE) through a sixth via electrode (VA6) penetrating the ninth insulating layer (INS9).
[0093] A tenth insulating layer (INS10) can be disposed on the seventh conductive layer (ML7).
[0094] An eighth conductive layer (ML8) may be disposed on the tenth insulating layer (INS10). The eighth conductive layer (ML8) may be connected to the seventh conductive layer (ML7) through a seventh via electrode (VA7) that penetrates the tenth insulating layer (INS10).
[0095] An 11th insulating layer (INS11) can be disposed on the 8th conductive layer (ML8).
[0096] A ninth conductive layer (ML9) may be disposed on the eleventh insulating layer (INS11). The ninth conductive layer (ML9) may be connected to the eighth conductive layer (ML8) through an eighth via electrode (VA8) that penetrates the eleventh insulating layer (INS11).
[0097] A 12th insulating layer (INS12) can be disposed on the 9th conductive layer (ML9).
[0098] A 10th conductive layer (ML10) may be disposed on the 12th insulating layer (INS12). The 10th conductive layer (ML10) may be connected to the 9th conductive layer (ML9) through a 9th via electrode (VA9) penetrating the 12th insulating layer (INS12).
[0099] A 13th insulating layer (INS13) may be disposed on the 10th conductive layer (ML10).
[0100] A first electrode (AND) may be disposed on the 13th insulating layer (INS13). The first electrode may be connected to the 10th conductive layer (ML10) through a 10th via electrode (VA10) that penetrates the 13th insulating layer (INS13).
[0101] A pixel definition layer (PDL) may be disposed on the first electrode (AND). The pixel definition layer (PDL) may be disposed on the edge of the first electrode (AND) so as to overlap with the edge of the first electrode (AND). The pixel definition layer (PDL) may define a light-emitting region (EA) of a subpixel. The first electrode (AND) may be exposed to the outside of the pixel definition layer (PDL) by the light-emitting region (EA) of the pixel definition layer (PDL).
[0102] A light-emitting layer (LE) may be disposed on the first electrode (AND) and the pixel definition layer (PDL).
[0103] A second electrode (CAT) may be disposed on the light-emitting layer (LE) and the pixel definition layer (PDL).
[0104] An encapsulation layer (TFE) may be disposed on the second electrode (CAT). The encapsulation layer (TFE) may be composed of a composite film including an inorganic layer, an organic layer, and an inorganic layer. The encapsulation layer (TFE) can prevent moisture from penetrating into the light-emitting layer (LE). Meanwhile, a color filter may be disposed on the encapsulation layer (TFE).
[0105] The drain region (DA) of the first transistor (TR1) can be connected to the gate electrode (GE) of the second transistor (TR2) through the intermediate connection electrode (CTE), the first to seventh conductive layers (ML1-ML7), and the first to sixth via electrodes (VA1-VA6). Accordingly, a scan signal (or light emission control signal) output through the first transistor (TR1) can be applied to the gate electrode (GE) of the second transistor (TR2). For example, a write scan signal output through the scan transistor can be applied to the gate electrode (GE) of the second transistor (TR2). Here, the seventh conductive layer (ML7) connected to the gate electrode (GE) of the second transistor (TR2) can be a scan line (e.g., a write scan line (GWL)).
[0106] A signal (e.g., data voltage) output through the second transistor (TR2) can be applied to the first electrode (AND) through the seventh to tenth conductive layers (ML1-ML10) and the seventh to tenth via electrodes (VA7-VA10).
[0107] According to one embodiment, the driving circuit layer (DCL), pixel circuit layer (PCL), and display element layer (EMTL) are arranged in an overlapping manner within the display area (DAA), so the area of the non-display area (NDA) can be reduced. Additionally, since the driving circuit layer (DCL) is placed in the display area (DAA) rather than the non-display area (NDA), the available area of the non-display area (NDA) can be increased, and the display area (DAA) can be expanded using that available area.
[0108] FIG. 7 is a layout diagram showing an example of a display panel (100) according to another embodiment.
[0109] The display panel (100) of FIG. 7 differs from the display panel (100) of FIG. 3 described above in terms of the size of the overlapping area of the display area (DAA). This difference is explained in detail as follows.
[0110] As illustrated in FIG. 7, a plurality of pixels (PX; or a plurality of subpixels (SP1, SP2, SP3), a scan driver (610), and a light-emitting driver (620) may be placed in a display area (DAA). Here, when the area of the display area (DAA) that overlaps with the scan driver (610) and the light-emitting driver (620) is defined as an overlapping area, and the area of the display area (DAA) that does not overlap with the scan driver (610) and the light-emitting driver (620) is defined as a non-overlapping area, the area of the overlapping area may be larger than the area of the non-overlapping area.
[0111] FIG. 8 is a cross-sectional view of a display panel (100) of a display device (10) according to one embodiment. For example, FIG. 8 may be a cross-sectional view of the display panel (100) of FIG. 7.
[0112] A display panel (100) according to one embodiment may include a substrate (SUB; e.g., a semiconductor substrate (SUB)), a driving circuit layer (DCL), a pixel circuit layer (PCL), and a display element layer (EMTL), as shown in FIG. 8.
[0113] The driving circuit layer (DCL), pixel circuit layer (PCL), and display element layer (EMTL) may be arranged on the display area (DAA) of the semiconductor substrate (SUB) so as to overlap in a direction perpendicular to the extension direction of the semiconductor substrate (SUB) (e.g., first direction (DR1) and second direction (DR2)).
[0114] The pixel circuit layer (PCL) can be placed between the semiconductor substrate (SUB) and the driving circuit layer (DCL).
[0115] The driving circuit layer (DCL) can be placed between the pixel circuit layer (PCL) and the display element layer (EMTL).
[0116] The semiconductor substrate (SUB) may be a wafer substrate. The semiconductor substrate (SUB) may be a substrate doped with Type 1 impurities.
[0117] The driving circuit layer (DCL) may be placed on the display area (DAA) of the semiconductor substrate (SUB). The driving circuit layer (DCL) may include a scan driving unit (610) and a light-emitting driving unit (620).
[0118] The driving circuit layer (DCL) may include a plurality of first transistors (TR1). The first transistor (TR1) may include a first gate electrode (GE1), a first source electrode (SE1) of the first active layer (ACT1), and a first drain electrode (DE1) of the first active layer (ACT1). The aforementioned first transistor (TR1) may be an oxide-based transistor (e.g., an oxide semiconductor transistor). For example, the first transistor (TR1) may be an N-type oxide-based transistor. In other words, the first transistor (TR1) may include an oxide semiconductor (or an oxide semiconductor material). The first transistor (TR1) may be, for example, at least one of the scan transistor of the aforementioned scan driving unit (610) and the light-emitting transistor of the aforementioned light-emitting driving unit (620). In other words, the scan driving unit (610) may include a plurality of first transistors (TR1), and the light-emitting driving unit (620) may include a plurality of first transistors (TR1).
[0119] A pixel circuit layer (PCL) may be disposed on a driving circuit layer (DCL). For example, the pixel circuit layer (PCL) may be disposed on the driving circuit layer (DCL) in a display area (DAA) of a semiconductor substrate (SUB). The pixel circuit layer (PCL) may include a plurality of second transistors (TR2). Here, the second transistor (TR2) may be the aforementioned pixel transistor. A plurality of sub-pixels (SP1, SP2, SP3) may each include a plurality of second transistors (TR2), and the plurality of second transistors (TR2) may be disposed on the pixel circuit layer (PCL). The pixel circuits may be connected to the first transistors (TR1) of the driving circuit layer (DCL) (e.g., a scan transistor and a light-emitting transistor).
[0120] The second transistor (TR2) may include a second gate electrode (GE2), a second source electrode (SE2) of the second active layer (ACT2), and a second drain electrode (DE2) of the second active layer (ACT2). The aforementioned second transistor (TR2) may be an oxide-based transistor (e.g., an oxide semiconductor transistor). For example, the second transistor (TR2) may be an N-type oxide-based transistor. In other words, the second transistor (TR1) may include an oxide semiconductor (or an oxide semiconductor material).
[0121] The display element layer (EMTL) may be disposed on the pixel circuit layer (PCL). For example, the display element layer (EMTL) may be disposed on the pixel circuit layer (PCL) in the display area (DAA) of the semiconductor substrate (SUB). A plurality of subpixels (SP1, SP2, SP3) may each include a plurality of light-emitting elements (ED), and the plurality of light-emitting elements (ED) may be disposed on the display element layer (EMTL). One subpixel (e.g., SP1) may include a pixel circuit of the pixel circuit layer (PCL) and a light-emitting element (ED) connected to the pixel circuit. The light-emitting element (ED) may include a first electrode (e.g., an anode electrode), a light-emitting layer (e.g., an organic light-emitting layer), and a second electrode (e.g., a cathode electrode).
[0122] A first conductive layer (ML1) can be disposed on a semiconductor substrate (SUB).
[0123] A first insulating layer (INS1) may be disposed on the first conductive layer (ML1).
[0124] A second conductive layer (ML2) may be disposed on the first insulating layer (INS1). The second conductive layer (ML2) may be connected to the first conductive layer (ML1) through a first via electrode (VA1) that penetrates the first insulating layer (INS1).
[0125] A second insulating layer (INS2) may be disposed on the second conductive layer (ML2).
[0126] A third conductive layer (ML3) may be disposed on the second insulating layer (INS2). The third conductive layer (ML3) may be connected to the second conductive layer (ML2) through a second via electrode (VA2) that penetrates the second insulating layer (INS2).
[0127] A third insulating layer (INS3) may be disposed on the third conductive layer (ML3).
[0128] A fourth conductive layer (ML4) may be disposed on the third insulating layer (INS3). The fourth conductive layer (ML4) may be connected to the third conductive layer (ML3) through a third via electrode (VA3) that penetrates the third insulating layer (INS3).
[0129] A fourth insulating layer (INS4) may be disposed on the fourth conductive layer (ML4).
[0130] A fifth conductive layer (ML5) may be disposed on the fourth insulating layer (INS4). The fifth conductive layer (ML5) may be connected to the fourth conductive layer (ML4) through a fourth via electrode (VA4) that penetrates the fourth insulating layer (INS4).
[0131] A fifth insulating layer (INS5) may be disposed on the fifth conductive layer (ML5).
[0132] A sixth conductive layer (ML6) may be disposed on the fifth insulating layer (INS5). The sixth conductive layer (ML6) may be connected to the fifth conductive layer (ML5) through a fifth via electrode (VA5) that penetrates the fifth insulating layer (INS5).
[0133] A sixth insulating layer (INS6) may be disposed on the sixth conductive layer (ML6).
[0134] A first active layer (ACT1) may be disposed on the sixth insulating layer (INS6). The first active layer (ACT1) may include a first drain electrode (DE1) and a first source electrode (SE1). The first active layer (ACT1) may include an oxide. For example, the first active layer (ACT1) may be a semiconductor layer including indium-gallium-zinc oxide (IGZO) or indium-gallium-zinc-tin oxide (IGZTO). However, it is not limited thereto, and the first active layer (ACT1) may include amorphous silicon.
[0135] A first gate insulating layer (GI1) may be disposed on the first active layer (ACT1).
[0136] A first gate electrode (GE1) may be disposed on the first gate insulating layer (GI1).
[0137] A seventh insulating layer (INS7) may be disposed on the first gate electrode (GE1), the first gate insulating layer (GI1), the first active layer (ACT1), and the sixth insulating layer (INS6).
[0138] A seventh conductive layer (ML7) may be disposed on the seventh insulating layer (INS7). The seventh conductive layer (ML7) may be connected to the sixth conductive layer (ML6) and the first source electrode (SE1) of the first transistor (TR1). For example, one of the seventh conductive layers (ML7) may be connected to the sixth conductive layer (ML6) through a sixth via electrode (VA6) penetrating the seventh insulating layer (INS7) and the sixth insulating layer (INS6), and the other seventh conductive layer (ML7) may be connected to the first source electrode (SE1) through a sixth via electrode (VA6) penetrating the seventh insulating layer (INS7).
[0139] An eighth insulating layer (INS8) can be disposed on the seventh conductive layer (ML7).
[0140] An eighth conductive layer (ML8) may be disposed on the eighth insulating layer (INS8). The eighth conductive layer (ML8) may be disposed between the first transistor (TR1) and the second transistor (TR2). For example, the eighth conductive layer (ML8) may be a light-blocking layer disposed between the first transistor (TR1) and the second transistor (TR2).
[0141] A ninth insulating layer (INS9) can be disposed on the eighth conductive layer (ML8).
[0142] A ninth conductive layer (ML9) may be disposed on the ninth insulating layer (INS9). The ninth conductive layer (ML9) may be connected to the seventh conductive layer (ML7) through a seventh via electrode (VA7) that penetrates the ninth insulating layer (INS9) and the eighth insulating layer (INS8). Meanwhile, the ninth conductive layer (ML9) disposed between the first transistor (TR1) and the second transistor (TR2) among the ninth conductive layers (ML9) may be a light-blocking layer.
[0143] A 10th insulating layer (INS10) can be disposed on the 9th conductive layer (ML9).
[0144] A second active layer (ACT2) may be disposed on the tenth insulating layer (INS10). The second active layer (ACT2) may include a second drain electrode (DE2) and a second source electrode (SE2). The second active layer (ACT2) may include an oxide. For example, the second active layer (ACT) may be a semiconductor layer including indium-gallium-zinc oxide (IGZO) or indium-gallium-zinc-tin oxide (IGZTO). However, it is not limited thereto, and the second active layer (ACT2) may include amorphous silicon.
[0145] A second gate insulating layer (GI2) may be disposed on the second active layer (ACT2).
[0146] A second gate electrode (GE2) can be placed on the second gate insulating layer (GI2).
[0147] A 11th insulating layer (INS11) may be disposed on the 2nd gate electrode (GE2), the 2nd gate insulating layer (GI2), the 2nd active layer (ACT2), and the 10th insulating layer (INS10).
[0148] A tenth conductive layer (ML10) may be disposed on the eleventh insulating layer (INS11). The tenth conductive layer (ML10) may be connected to the ninth conductive layer (ML9), the second gate electrode (GE2) of the second transistor (TR2), and the second drain electrode (DE2) of the second transistor (TR2). For example, one side of any one 10th conductive layer (ML10) may be connected to the 9th conductive layer (ML9) through the 8th via electrode (VA8) penetrating the 11th insulating layer (INS11) and the 10th insulating layer (INS10), the other side of any one 10th conductive layer (ML10) may be connected to the 2nd gate electrode (GE2) through the 8th via electrode (VA8) penetrating the 11th insulating layer (INS11), and another 10th conductive layer (ML10) may be connected to the 2nd drain electrode (DE2) through the 8th via electrode (VA8) penetrating the 11th insulating layer (INS11).
[0149] A 12th insulating layer (INS12) may be disposed on the 10th conductive layer (ML10).
[0150] A 11th conductive layer (ML11) may be disposed on the 12th insulating layer (INS12). The 11th conductive layer (ML11) may be connected to the 10th conductive layer (ML10) through a 9th via electrode (VA9) penetrating the 12th insulating layer (INS12).
[0151] A 13th insulating layer (INS13) may be disposed on the 11th conductive layer (ML11).
[0152] A 12th conductive layer (ML12) may be disposed on the 13th insulating layer (INS13). The 12th conductive layer (ML12) may be connected to the 11th conductive layer (ML11) through a 10th via electrode (VA10) penetrating the 13th insulating layer (INS13).
[0153] A 14th insulating layer (INS14) may be disposed on the 12th conductive layer (ML12).
[0154] A 13th conductive layer (ML13) may be disposed on the 14th insulating layer (INS14). The 13th conductive layer (ML13) may be connected to the 12th conductive layer (ML12) through a 11th via electrode (VA11) penetrating the 14th insulating layer (INS14).
[0155] A 15th insulating layer (INS15) can be disposed on the 13th conductive layer (ML13).
[0156] A first electrode (AND) may be disposed on the 15th insulating layer (INS15). The first electrode (AND) may be connected to the 13th conductive layer (ML13) through a 12th via electrode (VA12) that penetrates the 15th insulating layer (INS15).
[0157] A pixel definition layer (PDL) may be disposed on the first electrode (AND). The pixel definition layer (PDL) may be disposed on the edge of the first electrode (AND) so as to overlap with the edge of the first electrode (AND). The pixel definition layer (PDL) may define a light-emitting region (EA) of a subpixel. The first electrode (AND) may be exposed to the outside of the pixel definition layer (PDL) by the light-emitting region (EA) of the pixel definition layer (PDL).
[0158] A light-emitting layer (LE) may be disposed on the first electrode (AND) and the pixel definition layer (PDL).
[0159] A second electrode (CAT) may be disposed on the light-emitting layer (LE) and the pixel definition layer (PDL).
[0160] An encapsulation layer (TFE) may be disposed on the second electrode (CAT). The encapsulation layer (TFE) may be composed of a composite film including an inorganic layer, an organic layer, and an inorganic layer. The encapsulation layer (TFE) can prevent moisture from penetrating into the light-emitting layer (LE). Meanwhile, a color filter may be disposed on the encapsulation layer (TFE).
[0161] The first source electrode (SE1) of the first transistor (TR1) can be connected to the second gate electrode (GE2) of the second transistor (TR2) through the seventh conductive layer (ML7), the ninth conductive layer (ML9), the tenth conductive layer (ML10), the sixth via electrode (VA6), the seventh via electrode (VA7), and the eighth via electrode (VA8). Accordingly, a scan signal (or light emission control signal) output through the first transistor (TR1) can be applied to the second gate electrode (GE2) of the second transistor (TR2). For example, a write scan signal output through a scan transistor can be applied to the second gate electrode (GE2) of the second transistor (TR2). Here, the tenth conductive layer (ML10) connected to the second gate electrode (GE2) of the second transistor (TR2) can be a scan line (e.g., a write scan line (GWL)).
[0162] A signal (e.g., data voltage) output through the second transistor (TR2) can be applied to the first electrode (AND) through the 10th to 13th conductive layers (ML10-ML13) and the 8th to 12th via electrodes (VA8-VA12).
[0163] According to one embodiment, the driving circuit layer (DCL), pixel circuit layer (PCL), and display element layer (EMTL) are arranged in an overlapping manner within the display area (DAA), so the area of the non-display area (NDA) can be reduced. Additionally, since the driving circuit layer (DCL) is placed in the display area (DAA) rather than the non-display area (NDA), the available area of the non-display area (NDA) can be increased, and the display area (DAA) can be expanded using that available area.
[0164] FIG. 9 is a diagram illustrating the connection between a scan driving unit and a scan line according to one embodiment.
[0165] As illustrated in FIG. 9, scan drivers (610) may be placed in a display area (DAA), and a plurality of scan lines (SL1, SL2, SL3) may be placed on the scan drivers (610). Here, the first scan line (SL1) may be the aforementioned write scan line (GWL), the second scan line (SL2) may be the control scan line (GCL), and the third scan line (SL3) may be the bias scan line (GBL).
[0166] Multiple scan lines (SL1, SL2, SL3) can be connected to multiple scan drivers (610) through via electrodes (VA) penetrating an insulating layer.
[0167] Meanwhile, a plurality of light-emitting driving units (620) and a plurality of light-emitting control lines (EL1, EL2) can be connected to each other through via electrodes.
[0168] FIG. 10 is a layout diagram showing an example of a display panel (100) according to another embodiment.
[0169] The display panel (100) of FIG. 10 has a difference from the display panel (100) of FIG. 7 described above in terms of the location of the first distribution circuit (710), and this difference is explained in detail as follows.
[0170] As illustrated in FIG. 10, a plurality of pixels (PX; or a plurality of subpixels (SP1, SP2, SP3), a scan driver (610), a light-emitting driver (620), and a first distribution circuit (710) may be placed in a display area (DAA). For example, the first distribution transistors of the first distribution circuit (710) may be placed in the display area (DAA). In this case, the first distribution circuit (710) may be placed between the scan driver (610) and the light-emitting driver (620) in the display area (DAA). In this case, the driving circuit layer (DCL) may further include the first distribution transistors of the first distribution circuit (710). In this case, the first distribution transistor may be a MOSFET in an embodiment such as FIG. 6, and the first distribution transistor may be an oxide-based transistor in an embodiment such as FIG. 8.
[0171] Meanwhile, the first distribution circuit (710) described above may also be placed in the display area (DAA) of FIG. 3. For example, the first distribution circuit (710) of FIG. 3 may be placed in the display area (DAA) rather than the non-display area (NDA). In this case, the first distribution circuit (710) placed in the display area (DAA) of FIG. 3 may be placed between the scan driving unit (610) and the light-emitting driving unit (620).
[0172] In this way, when the first distribution circuit (710) is further placed in the display area (DAA), the area of the non-display area (NDA) can be further reduced.
[0173] The display device (10) according to the embodiment can be applied to various electronic devices. An electronic device according to one embodiment includes the display device (10) described above and may further include a module or device having other additional functions in addition to the display device (10).
[0174] FIG. 11 is a block diagram of an electronic device according to one embodiment. Referring to FIG. 11, an electronic device (50) according to one embodiment may include a display module (11), a processor (12), a memory (13), and a power module (14). The electronic device (50) may further include an input module (14), a non-image output module (15) and / or a communication module (16).
[0175] The electronic device (50) can output various information in the form of images through the display module (11). When the processor (12) executes an application stored in memory (13), the image information provided by the application can be provided to the user through the display module (11). The power module (14) may include a power supply module, such as a power adapter or battery device, and a power conversion module that converts the power supplied by the power supply module to generate power necessary for the operation of the electronic device (50). The input module (14) can provide input information to the processor (12) and / or the display module (11). The non-image output module (15) can receive information other than images received from the processor (12), such as sound, haptics, light emission, etc., and provide this information to the user. The communication module (16) is a module responsible for the transmission and reception of information between the electronic device (50) and an external device, and may include a receiving unit and a transmitting unit.
[0176] At least one of each component of the electronic device (50) described above may be included in a display device according to the embodiments described above. Additionally, some of the individual modules functionally included in one module may be included in the display device, while others may be provided separately from the display device. For example, the display device may include a display module (11), and the processor (12), memory (13), and power module (14) may be provided in the form of other devices within the electronic device (11) other than the display device.
[0177] FIGS. 12, FIGS. 13 and FIGS. 14 are schematic diagrams of electronic devices according to various embodiments. FIGS. 12 to 14 illustrate examples of various electronic devices to which a display device (10) according to embodiments is applied.
[0178] FIG. 12 illustrates examples of electronic devices, including a smartphone (10_1a), a tablet PC (10_1b), a laptop (10_1c), a TV (10_1d), and a desktop monitor (10_1e).
[0179] The smartphone (10_1a) may include an input module, such as a touch sensor, and a communication module in addition to the display module (11). The smartphone (10_1a) can process information received through the communication module or other input modules and display information through the display module of the display device.
[0180] In the case of a tablet PC (10_1b), laptop (10_1c), TV (10_1d), and desk monitor (10_1e), it also includes a display module and an input module similar to a smartphone (10_1a), and may additionally include a communication module depending on the case.
[0181] FIG. 13 illustrates a case where an electronic device including a display module is applied to a wearable electronic device. The wearable electronic device may be smart glasses (10_2a), a head-mounted display (10_2b), a smart watch (10_2c), etc.
[0182] Smart glasses (10_2a) and a head-mounted display (10_2b) may include a display module that emits a display image and a reflector that reflects the emitted display screen to provide it to the user's eyes, thereby providing a virtual reality or augmented reality screen to the user.
[0183] The smart watch (10_2c) includes a bio-sensor as an input device and can provide bio-information recognized through the bio-sensor to the user through a display module.
[0184] FIG. 14 illustrates a case where an electronic device including a display module is applied to a vehicle. For example, the electronic device (10_3) may be applied to the instrument panel, center fascia, etc. of a vehicle, or may be applied to a Center Information Display (CID) placed on the dashboard of a vehicle or a room mirror display that replaces a side mirror.
[0185] A person skilled in the art to which this specification pertains will understand that this specification may be implemented in other specific forms without altering its technical concept or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. The scope of this specification is defined by the claims set forth below rather than by the detailed description above, and all modifications or variations derived from the meaning and scope of the claims and equivalent concepts should be interpreted as being included within the scope of this specification.
[0186] Meanwhile, the present specification and drawings disclose preferred embodiments of the present specification. Although specific terms have been used, they are used only in a general sense to facilitate the explanation of the technical content of the present specification and to aid in understanding the invention, and are not intended to limit the scope of the present specification. It is obvious to those skilled in the art that, in addition to the embodiments disclosed herein, other variations based on the technical concept of the present specification are possible. Explanation of the symbols
[0187] ML1-ML10: 1st to 10th conductive layers INS1-INS13: 1st to 13th insulating layers SUB: semiconductor substrate VA1-VA10: 1st to 10th via electrodes ED: light-emitting element AND: First electrode LE: light-emitting layer CAT: Second electrode TFE: Bag layer EA: light-emitting region DCL: Driving circuit layer PCL: Pixel circuit layer EMTL: Display layer DAA: Display area TR1-TR2: 1st to 2nd transistors
Claims
Claim 1 A display device comprising: a substrate having a display area and a non-display area; and a driving circuit layer, a pixel circuit layer, and a display element layer disposed on the substrate, wherein the driving circuit layer is connected to a pixel circuit of the pixel circuit layer, and the pixel circuit of the pixel circuit layer is connected to a light-emitting element of the display element layer, and the driving circuit layer, the pixel circuit layer, and the display element layer are disposed on the display area of the substrate so as to overlap in a direction perpendicular to the extension direction of the substrate, wherein the driving circuit layer includes a first transistor, and the pixel circuit layer includes a second transistor provided in the pixel circuit and connected to the first transistor, wherein the first transistor is a MOSFET and the second transistor is an oxide semiconductor transistor. Claim 2 In claim 1, the source region of the first transistor is a display device connected to the gate electrode of the second transistor. Claim 3 In claim 1, the pixel circuit layer is a display device disposed between the driving circuit layer and the display element layer. Claim 4 In claim 1, the oxide semiconductor transistor is a display device comprising indium-gallium-zinc oxide or indium-gallium-zinc-tin oxide. Claim 5 In claim 1, the driving circuit layer is a display device comprising a scan driving unit and a light-emitting driving unit. Claim 6 In claim 5, the overlapping area among the display areas that overlaps with the scan driving unit and the light-emitting driving unit has a smaller area than the non-overlapping area among the display areas that does not overlap with the scan driving unit and the light-emitting driving unit. Claim 7 In claim 5, the scan driving unit and the light-emitting driving unit each comprise the first transistor in a display device. Claim 8 A display device according to claim 5, further comprising a distribution circuit disposed in the display area. Claim 9 In claim 8, the distribution circuit in the display area is a display device disposed between the scan driving unit and the light-emitting driving unit. Claim 10 A display device comprising: a substrate having a display area and a non-display area; and a driving circuit layer, a pixel circuit layer, and a display element layer disposed on the substrate, wherein the driving circuit layer is connected to a pixel circuit of the pixel circuit layer, and the pixel circuit of the pixel circuit layer is connected to a light-emitting element of the display element layer, and the driving circuit layer, the pixel circuit layer, and the display element layer are disposed on the display area of the substrate so as to overlap in a direction perpendicular to the extension direction of the substrate, wherein the driving circuit layer includes a first transistor, and the pixel circuit layer includes a second transistor provided in the pixel circuit and connected to the first transistor, and wherein the first transistor and the second transistor are each oxide semiconductor transistors. Claim 11 In claim 10, the source electrode of the first transistor is connected to the gate electrode of the second transistor in a display device. Claim 12 In claim 10, the pixel circuit layer is a display device disposed between the driving circuit layer and the display element layer. Claim 13 In claim 10, the oxide semiconductor transistor is a display device comprising indium-gallium-zinc oxide or indium-gallium-zinc-tin oxide. Claim 14 In claim 10, the driving circuit layer is a display device comprising a scan driving unit and a light-emitting driving unit. Claim 15 In claim 14, the overlapping area among the display areas that overlaps with the scan driving unit and the light-emitting driving unit has a larger area than the non-overlapping area among the display areas that does not overlap with the scan driving unit and the light-emitting driving unit. Claim 16 In claim 14, the scan driving unit and the light-emitting driving unit each comprise the first transistor in a display device. Claim 17 A display device according to claim 14, further comprising a distribution circuit disposed in the display area. Claim 18 In claim 17, the distribution circuit in the display area is a display device disposed between the scan driving unit and the light-emitting driving unit. Claim 19 An electronic device comprising a display device that provides a display screen, wherein the display device comprises: a substrate having a display area and a non-display area; and a driving circuit layer, a pixel circuit layer, and a display element layer disposed on the substrate, wherein the driving circuit layer is connected to a pixel circuit of the pixel circuit layer, and the pixel circuit of the pixel circuit layer is connected to a light-emitting element of the display element layer, and wherein the driving circuit layer, the pixel circuit layer, and the display element layer are disposed on the display area of the substrate so as to overlap in a direction perpendicular to the extension direction of the substrate, wherein the driving circuit layer comprises a first transistor, and the pixel circuit layer comprises a second transistor provided in the pixel circuit and connected to the first transistor, wherein the first transistor is a MOSFET and the second transistor is an oxide semiconductor transistor. Claim 20 In claim 19, the electronic device comprises a smartphone, tablet, laptop, TV, desk monitor, smart glasses, smart watch, head-mounted display, and vehicle.