Display device and electronic device including the same
Patent Information
- Application Number
- KR1020250031300
- Authority / Receiving Office
- KR · KR
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2025-03-11
- Publication Date
- 2026-09-21
Smart Images
Figure PAT00008_ABST
Abstract
Description
Technology Field
[0001] The present invention relates to a display device and an electronic device including the same. More specifically, the present invention relates to a display device that provides visual information and an electronic device including the same. Background Technology
[0002] A display device is a device that displays images to provide visual information to users. Among display devices, organic light-emitting diode display devices have recently been attracting attention.
[0003] Recently, head-mounted displays (HMDs) containing such display devices are being developed. A head-mounted display is a glasses-type monitor device for virtual reality (VR) or augmented reality (AR) that is worn in the form of glasses, helmets, etc., and forms a focus at a close distance in front of the user's eyes. OLEDoS (organic light emitting diode on Silicon) displays can be used in products such as head-mounted displays. The problem to be solved
[0004] One objective of the present invention is to provide a high-resolution display device.
[0005] Another objective of the present invention is to provide an electronic device including the above-mentioned display device.
[0006] However, the objectives of the present invention are not limited to the objectives described above and may be extended in various ways without departing from the spirit and scope of the invention. means of solving the problem
[0007] To achieve one objective of the present invention as described above, a display device according to one embodiment of the present invention may include a substrate including a first well region comprising a first contact region, a second contact region spaced apart from the first contact region in a plane, and a first channel region disposed between the first contact region and the second contact region; a first gate pattern disposed on the substrate and comprising a first portion that at least partially overlaps with the first channel region in a plane and a second portion that protrudes from the first portion; and a first contact pattern disposed on the first gate pattern and connected to the second portion of the first gate pattern through a first contact hole.
[0008] In one embodiment, the width of the first portion of the first gate pattern in the first direction may be greater than the width of the second portion of the first gate pattern in the first direction.
[0009] In one embodiment, the second portion of the first gate pattern may be spaced apart from the first channel region in a plane.
[0010] In one embodiment, a portion of the first well region and a portion of the first gate pattern may form a first transistor that provides a driving current to a light-emitting element.
[0011] In one embodiment, the substrate may further include a second well region comprising a third contact region, a fourth contact region spaced apart from the third contact region in a plane, and a second channel region disposed between the third contact region and the fourth contact region.
[0012] In one embodiment, the display device may further include a second gate pattern disposed on the substrate, spaced apart from the first gate pattern in a plane, and at least partially overlapping with the second channel region in a plane.
[0013] In one embodiment, the first well region may be extended in a first direction, and the second well region may be extended in a second direction that intersects the first direction.
[0014] In one embodiment, the second contact area may be spaced apart from the first contact area in the first direction, and the fourth contact area may be spaced apart from the third contact area in the second direction.
[0015] In one embodiment, a portion of the first well region and a portion of the first gate pattern may form a first transistor that provides a driving current to a light-emitting element, and a portion of the second well region and a portion of the second gate pattern may form a second transistor that provides a data voltage to a first node.
[0016] In one embodiment, the substrate may further include a third well region comprising a fifth contact region, a sixth contact region spaced apart from the fifth contact region in a plane, and a third channel region disposed between the fifth contact region and the sixth contact region.
[0017] In one embodiment, the display device may further include a third gate pattern disposed on the substrate, spaced apart in a plane from the first gate pattern and the second gate pattern, and at least partially overlapping in a plane with the third channel region.
[0018] In one embodiment, the first well region is extended in a first direction, and each of the second well region and the third well region may be extended in a second direction that intersects the first direction.
[0019] In one embodiment, the first contact pattern may be connected through the third contact area and the third contact hole.
[0020] In one embodiment, the substrate may further include a fourth well region spaced apart from the first well region in a plane.
[0021] In one embodiment, the display device may further include a second contact pattern disposed on the first gate pattern and connected through the fourth well region and the fifth contact hole, and a fourth contact line disposed on the second contact pattern, to which a first power supply voltage is applied, and connected through the second contact pattern and the eleventh contact hole.
[0022] In one embodiment, the first well region and the fourth well region may each be extended in a first direction.
[0023] In one embodiment, the first gate pattern is placed in a display area where a pixel is placed, the width of the pixel in the first direction is greater than the width in the second direction intersecting the first direction of the pixel, and the first well area may be extended in the first direction.
[0024] To achieve one objective of the present invention as described above, a display device according to one embodiment of the present invention may include a substrate comprising a first contact area, a second contact area spaced apart from the first contact area in a plane and a first channel area disposed between the first contact area and the second contact area, a first well area and a third contact area extending in a first direction, a fourth contact area spaced apart from the third contact area in a plane and a second channel area disposed between the third contact area and the fourth contact area, and a second well area extending in a second direction intersecting the first direction, a first gate pattern disposed on the substrate and at least partially overlapping with the first channel area in a plane, and a second gate pattern disposed on the substrate, spaced apart from the first gate pattern in a plane and at least partially overlapping with the second channel area in a plane.
[0025] In one embodiment, a portion of the first well region and a portion of the first gate pattern may form a first transistor that provides a driving current to a light-emitting element, and a portion of the second well region and a portion of the second gate pattern may form a second transistor that provides a data voltage to a first node.
[0026] In one embodiment, the substrate may further include a third well region that extends in the second direction and includes a fifth contact region, a sixth contact region spaced apart from the fifth contact region in a plane, and a third channel region disposed between the fifth contact region and the sixth contact region.
[0027] In one embodiment, the display device may further include a third gate pattern disposed on the substrate, spaced apart in a plane from the first gate pattern and the second gate pattern, and at least partially overlapping in a plane with the third channel region.
[0028] To achieve one objective of the present invention as described above, an electronic device according to one embodiment of the present invention may include a substrate including a first well region comprising a first contact region, a second contact region spaced apart from the first contact region in a plane, and a first channel region disposed between the first contact region and the second contact region; a first gate pattern disposed on the substrate and comprising a first portion that at least partially overlaps with the first channel region in a plane and a second portion that protrudes from the first portion; a first contact pattern disposed on the first gate pattern and connected to the second portion of the first gate pattern through a first contact hole; and a memory in which data information is stored.
[0029] In one embodiment, the width of the first portion of the first gate pattern in the first direction may be greater than the width of the second portion of the first gate pattern in the first direction.
[0030] In one embodiment, the second portion of the first gate pattern may be spaced apart from the first channel region in a plane. Effects of the invention
[0031] A display device according to embodiments of the present invention may include a substrate comprising a first well region including a first contact region, a second contact region spaced apart from the first contact region in a plane, and a first channel region disposed between the first contact region and the second contact region; a first gate pattern disposed on the substrate and comprising a first portion that at least partially overlaps with the first channel region in a plane and a second portion that protrudes from the first portion; and a first contact pattern disposed on the first gate pattern and connected to the second portion of the first gate pattern through a first contact hole.
[0032] Accordingly, sufficient space can be secured for the placement of the second transistor and the third transistor. Therefore, the planar separation distance between the first transistor and the second transistor can be reduced. Additionally, the planar separation distance between the first transistor and the third transistor can be reduced. Thus, a pixel driving circuit suitable for a high-resolution display device can be provided.
[0033] However, the effects of the present invention are not limited to the effects described above and may be extended in various ways without departing from the spirit and scope of the present invention. Brief explanation of the drawing
[0034] FIG. 1 is a plan view showing a display device according to one embodiment of the present invention. Figure 2 is a block diagram showing the display device of Figure 1. Figure 3 is a circuit diagram showing a pixel included in the display device of Figure 1. FIGS. 4 to 10 are layout drawings showing parts of the display device of FIG. 1. Figure 11 is a cross-sectional view of the display device of Figure 10 cut along line II'. FIG. 12 is a block diagram of an electronic device according to one embodiment of the present invention. FIG. 13 is a schematic diagram of an electronic device according to various embodiments. Specific details for implementing the invention
[0035] Hereinafter, embodiments of the present invention will be described in more detail with reference to the attached drawings. Identical components in the drawings are given the same reference numerals, and redundant descriptions of identical components are omitted.
[0036] FIG. 1 is a plan view showing a display device according to one embodiment of the present invention.
[0037] Referring to FIG. 1, a display device (DD) according to one embodiment of the present invention may include a display area (DA) and a non-display area (NDA).
[0038] The display area (DA) can be defined as an area capable of displaying an image by generating light or adjusting the transmittance of light provided from an external light source. The non-display area (NDA) may be an area that does not display an image. Additionally, the non-display area (NDA) may surround at least a portion of the display area (DA). For example, the non-display area (NDA) may surround the entire display area (DA).
[0039] A plurality of pixels (PX) may be arranged in a display area (DA). The plurality of pixels (PX) may be repeatedly arranged along a first direction (DR1) and a second direction (DR2) that intersects the first direction (DR1). Each of the plurality of pixels (PX) may emit light. A plurality of driving units may be arranged in a non-display area (NDA). The plurality of driving units will be described later with reference to FIG. 2.
[0040] In one embodiment, a first direction (DR1) and a second direction (DR2) intersecting the first direction (DR1) may be defined. For example, the second direction (DR2) may be substantially perpendicular to the first direction (DR1). However, the present invention is not necessarily limited thereto, and the second direction (DR2) may form an acute or obtuse angle with the first direction (DR1). Additionally, a third direction (DR3) intersecting the plane formed by the first direction (DR1) and the second direction (DR2) may be defined. For example, the third direction (DR3) may be substantially perpendicular to the plane formed by the first direction (DR1) and the second direction (DR2). However, the present invention is not necessarily limited thereto, and the third direction (DR3) may form an acute or obtuse angle with the plane formed by the first direction (DR1) and the second direction (DR2).
[0041] Figure 2 is a block diagram showing the display device of Figure 1.
[0042] Referring to FIG. 2, the display device (DD) may include a driving control unit (100), a scan driving unit (200), a gamma reference voltage generating unit (300), a data driving unit (400), a light emission control driving unit (500), and a voltage generating unit (600). As described above, the plurality of driving units may be disposed in a non-display area (e.g., the non-display area (NDA) of FIG. 1), and the plurality of driving units may include a driving control unit (100), a scan driving unit (200), a gamma reference voltage generating unit (300), a data driving unit (400), a light emission control driving unit (500), and a voltage generating unit (600).
[0043] The drive control unit (100) can receive input image data (IMG) and input control signals (CONT) from an external device. In one embodiment, the input image data (IMG) may include red image data, green image data, and blue image data. In another embodiment, the input image data (IMG) may include white image data. In yet another embodiment, the input image data (IMG) may include magenta image data, yellow image data, and cyan image data. The input control signals (CONT) may include a master clock signal, a data enable signal, etc. The input control signals (CONT) may further include a vertical synchronization signal and a horizontal synchronization signal.
[0044] The drive control unit (100) receives an input control signal (CONT), generates a first control signal (CONT1), and can output the first control signal (CONT1) to the scan drive unit (200). The first control signal (CONT1) may include a vertical start signal and a gate clock signal. The drive control unit (100) receives an input control signal (CONT), generates a second control signal (CONT2), and can output the second control signal (CONT2) to the data drive unit (400). The second control signal (CONT2) may include a horizontal start signal and a load signal. The drive control unit (100) receives an input control signal (CONT), generates a third control signal (CONT3), and can output the third control signal (CONT3) to the gamma reference voltage generator (300). The driving control unit (100) can receive an input control signal (CONT), generate a fourth control signal (CONT4), and output the fourth control signal (CONT4) to the light emission control driving unit (500). The driving control unit (100) can receive an input control signal (CONT), generate a fifth control signal (CONT5), and output the fifth control signal (CONT5) to the voltage generating unit (600). The driving control unit (100) can receive input image data (IMG), generate a data signal (DATA), and output the data signal (DATA) to the data driving unit (400).
[0045] The scan driving unit (200) can receive a first control signal (CONT1) and output a scan signal to scan lines. For example, the scan driving unit (200) can output a first scan signal (GW) to a first scan line (e.g., the first scan line (GWL) of FIG. 3) and output a second scan signal (EB) to a second scan line (e.g., the second scan line (EBL) of FIG. 3). The scan driving unit (200) can provide the first scan signal (GW) and the second scan signal (EB) to a plurality of pixels (PX).
[0046] The gamma reference voltage generation unit (300) can generate a gamma reference voltage (VGREF) by receiving a third control signal (CONT3) from the driving control unit (100). The gamma reference voltage generation unit (300) can provide the gamma reference voltage (VGREF) to the data driving unit (400). The gamma reference voltage (VGREF) can have a value corresponding to the data signal (DATA).
[0047] The data driving unit (400) can receive a second control signal (CONT2) and a data signal (DATA) from the driving control unit (100). Additionally, the data driving unit (400) can receive a gamma reference voltage (VGREF) from the gamma reference voltage generation unit (300). The data driving unit (400) can convert the data signal (DATA) into an analog data voltage (DT) using the gamma reference voltage (VGREF). The data driving unit (400) can provide the data voltage (DT) to a plurality of pixels (PX).
[0048] The light emission control driving unit (500) can receive a fourth control signal (CONT4) from the driving control unit (100) and generate a light emission control signal (EM). The light emission control driving unit (500) can provide the light emission control signal (EM) to a plurality of pixels (PX).
[0049] The voltage generation unit (600) can receive a fifth control signal (CONT5) from the driving control unit (100) and generate a reference voltage (VREF), an initialization voltage (VINT), a first power supply voltage (ELVDD), and a second power supply voltage (ELVSS). The voltage generation unit (600) can provide the reference voltage (VREF), the initialization voltage (VINT), the first power supply voltage (ELVDD), and the second power supply voltage (ELVSS) to a plurality of pixels (PX).
[0050] FIG. 2 may show an example of the positions of the plurality of driving units. For example, as shown in FIG. 2, the scan driving unit (200) may be spaced apart from the display area (DA) and the second direction (DR2), the data driving unit (400) may be spaced apart from the display area (DA) and the first direction (DR1), the light emission control driving unit (500) may be spaced apart from the display area (DA) and the second direction (DR2), and the voltage generating unit (600) may be spaced apart from the display area (DA) and the first direction (DR1). However, the present invention is not necessarily limited thereto, and the positions of the plurality of driving units may be varied according to embodiments.
[0051] Figure 3 is a circuit diagram showing a pixel included in the display device of Figure 1.
[0052] Referring to FIG. 3, each of the plurality of pixels (PX) may include a light-emitting element (LED) and a pixel driving circuit (PXC) electrically connected to the light-emitting element (LED).
[0053] In one embodiment, the pixel driving circuit (PXC) may include a first transistor (T1), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), a first capacitor (CST1), a second capacitor (CST2), and a third capacitor (CST3).
[0054] In one embodiment, the first transistor (T1), the second transistor (T2), and the third transistor (T3) may each be PMOS transistors, and the fourth transistor (T4) may be NMOS transistors. However, the present invention is not necessarily limited thereto, and the types of each of the first transistor (T1), the second transistor (T2), the third transistor (T3), and the fourth transistor (T4) may be varied according to the embodiments. For example, the first transistor (T1), the second transistor (T2), the third transistor (T3), and the fourth transistor (T4) may each be PMOS transistors.
[0055] The pixel driving circuit (PXC) can be electrically connected to the first voltage line (VL1), the second voltage line (VL2), the third voltage line (VL3), the fourth voltage line (VL4), the first scan line (GWL), the second scan line (EBL), the data line (DL), and the light emission control line (EL).
[0056] The first voltage line (VL1) can provide a first power supply voltage (ELVDD) to the pixel driving circuit (PXC). The second voltage line (VL2) can provide a second power supply voltage (ELVSS) to the pixel driving circuit (PXC). In one embodiment, the voltage level of the first power supply voltage (ELVDD) may be higher than the voltage level of the second power supply voltage (ELVSS). The third voltage line (VL3) can provide an initialization voltage (VINT) to the pixel driving circuit (PXC). The fourth voltage line (VL4) can provide a reference voltage (VREF) to the pixel driving circuit (PXC). The first scan line (GWL) can provide a first scan signal (GW) to the pixel driving circuit (PXC). The second scan line (EBL) can provide a second scan signal (EB) to the pixel driving circuit (PXC). The light emission control line (EL) can provide a light emission control signal (EM) to the pixel driving circuit (PXC).
[0057] The first transistor (T1) may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the first transistor (T1) may be connected to a first node (N1). The first electrode of the first transistor (T1) may be connected to a second node (N2). The second electrode of the first transistor (T1) may be connected to a third node (N3). The first transistor (T1) may provide a driving current (ID) to a light-emitting element (LED).
[0058] The second transistor (T2) may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the second transistor (T2) may be connected to a first scan line (GWL). The first electrode of the second transistor (T2) may be connected to a data line (DL). The second electrode of the second transistor (T2) may be connected to a first node (N1).
[0059] The gate electrode of the second transistor (T2) may receive a first scan signal (GW) through the first scan line (GWL). The second transistor (T2) may be turned on or turned off in response to the first scan signal (GW). For example, if the second transistor (T2) is a PMOS transistor, the second transistor (T2) may be turned off when the first scan signal (GW) has a positive voltage level and turned on when the first scan signal (GW) has a negative voltage level. Also, if the second transistor (T2) is an NMOS transistor, the second transistor (T2) may be turned off when the first scan signal (GW) has a negative voltage level and turned on when the first scan signal (GW) has a positive voltage level. The first electrode of the second transistor (T2) may receive a data voltage (DT) through the data line (DL). The second electrode of the second transistor (T2) can provide a data voltage (DT) to the first node (N1) during the period when the second transistor (T2) is turned on. Accordingly, the second transistor (T2) can drive the first transistor (T1).
[0060] The third transistor (T3) may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the third transistor (T3) may be connected to a light emission control line (EL). The first electrode of the third transistor (T3) may be connected to a first voltage line (VL1). The second electrode of the third transistor (T3) may be connected to a third node (N3).
[0061] The gate electrode of the third transistor (T3) may receive a light emission control signal (EM) through a light emission control line (EL). The third transistor (T3) may be turned on or turned off in response to the light emission control signal (EM). For example, if the third transistor (T3) is a PMOS transistor, the third transistor (T3) may be turned off when the light emission control signal (EM) has a positive voltage level and turned on when the light emission control signal (EM) has a negative voltage level. Additionally, if the third transistor (T3) is an NMOS transistor, the third transistor (T3) may be turned off when the light emission control signal (EM) has a negative voltage level and turned on when the light emission control signal (EM) has a positive voltage level. The first electrode of the third transistor (T3) may receive a first power supply voltage (ELVDD) through a first voltage line (VL1). During the period when the third transistor (T3) is turned on, the third transistor (T3) can provide a first power supply voltage (ELVDD) to the third node (N3).
[0062] The fourth transistor (T4) may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the fourth transistor (T4) may be connected to a second scan line (EBL). The first electrode of the fourth transistor (T4) may be connected to a third voltage line (VL3). The second electrode of the fourth transistor (T4) may be connected to a second node (N2).
[0063] The gate electrode of the fourth transistor (T4) may receive a second scan signal (EB) through the second scan line (EBL). The fourth transistor (T4) may be turned on or turned off in response to the second scan signal (EB). For example, if the fourth transistor (T4) is an NMOS, the fourth transistor (T4) may be turned off when the second scan signal (EB) has a negative voltage level and turned on when the second scan signal (EB) has a positive voltage level. Also, if the fourth transistor (T4) is a PMOS, the fourth transistor (T4) may be turned off when the second scan signal (EB) has a positive voltage level and turned on when the second scan signal (EB) has a negative voltage level. The first electrode of the fourth transistor (T4) may receive an initialization voltage (VINT) through the third voltage line (VL3). During the period when the fourth transistor (T4) is turned on, the fourth transistor (T4) can provide an initialization voltage (VINT) to the second node (N2).
[0064] The first capacitor (CST1) may include a first electrode and a second electrode. The first electrode of the first capacitor (CST1) may be connected to a third node (N3). The second electrode of the first capacitor (CST1) may be connected to a first node (N1).
[0065] The second capacitor (CST2) may include a first electrode and a second electrode. The first electrode of the second capacitor (CST2) may be connected to a fourth voltage line (VL4). The first electrode of the second capacitor (CST2) may receive a reference voltage (VREF) through the fourth voltage line (VL4). The second electrode of the second capacitor (CST2) may be connected to a first node (N1).
[0066] The third capacitor (CST3) may include a first electrode and a second electrode. The first electrode of the third capacitor (CST3) may be connected to a second node (N2). The second electrode of the third capacitor (CST3) may be connected to a first node (N1).
[0067] A light-emitting element (LED) may include a first electrode and a second electrode. The first electrode of the light-emitting element (LED) may be connected to a second node (N2). The second electrode of the light-emitting element (LED) may be connected to a second voltage line (VL2). The second electrode of the light-emitting element (LED) may receive a second power supply voltage (ELVSS) through the second voltage line (VL2). For example, the first electrode of the light-emitting element (LED) may be an anode electrode and the second electrode of the light-emitting element (LED) may be a cathode electrode, but the present invention is not necessarily limited thereto.
[0068] As shown in FIG. 3, the pixel driving circuit (PXC) may include four transistors and three capacitors. However, the present invention is not necessarily limited thereto, and the number of transistors and capacitors included in the pixel driving circuit (PXC) may be varied according to the embodiments.
[0069] FIGS. 4 to 10 are layout drawings showing parts of the display device of FIG. 1.
[0070] Referring to FIG. 4, a display device (e.g., the display device (DD) of FIG. 1) may include a substrate (SUB). The substrate (SUB) may form the base of the display device. In one embodiment, the substrate (SUB) may be a silicon substrate. For example, the substrate (SUB) may be a p-type silicon substrate or an n-type silicon substrate. In this case, p may mean a hole and n may mean an electron.
[0071] The substrate (SUB) may include a first well region (W1), a second well region (W2), a third well region (W3), a fourth well region (W4), and a fifth well region (W5). The first well region (W1) may be a p-well or an n-well depending on the type of the first transistor (e.g., the first transistor (T1) in FIG. 6) and the type of the substrate (SUB). The second well region (W2) may be a p-well or an n-well depending on the type of the second transistor (e.g., the second transistor (T2) in FIG. 6) and the type of the substrate (SUB). The third well region (W3) may be a p-well or an n-well depending on the type of the third transistor (e.g., the third transistor (T3) in FIG. 6) and the type of the substrate (SUB). The fifth well region (W5) may be a p-well or an n-well depending on the type of the fourth transistor (e.g., the fourth transistor (T4) of FIG. 6) and the type of the substrate (SUB). In one embodiment, the fourth well region (W4) may be a p-well. However, the present invention is not necessarily limited thereto, and the fourth well region (W4) may be an n-well.
[0072] The first well region (W1) may include a first contact region (SA1), a second contact region (DA1), and a first channel region (CH1) disposed between the first contact region (SA1) and the second contact region (DA1). The first contact region (SA1) and the second contact region (DA1) may be spaced apart in a plane. For example, the second contact region (DA1) may be spaced apart from the first contact region (SA1) in a first direction (DR1). In one embodiment, the first well region (W1) may extend in the first direction (DR1). For example, the first well region (W1) may have a rectangular shape extending in the first direction (DR1) in a plane, but the present invention is not necessarily limited thereto.
[0073] In one embodiment, the first contact region (SA1) and the second contact region (DA1) may each be a p-source region and a p-drain region, respectively, but the present invention is not necessarily limited thereto, and the first contact region (SA1) and the second contact region (DA1) may each be an n-source region and an n-drain region.
[0074] The second well region (W2) may include a third contact region (SA2), a fourth contact region (DA2), and a second channel region (CH2) disposed between the third contact region (SA2) and the fourth contact region (DA2). The third contact region (SA2) and the fourth contact region (DA2) may be spaced apart from each other in a plane. For example, the fourth contact region (DA2) may be spaced apart from the third contact region (SA2) in a second direction (DR2). In one embodiment, the second well region (W2) may extend in a second direction (DR2). For example, the second well region (W2) may have a rectangular shape extending in a second direction (DR2) in a plane, but the present invention is not necessarily limited thereto.
[0075] In one embodiment, the third contact region (SA2) and the fourth contact region (DA2) may each be a p-source region and a p-drain region, respectively, but the present invention is not necessarily limited thereto, and the third contact region (SA2) and the fourth contact region (DA2) may each be an n-source region and an n-drain region.
[0076] The third well region (W3) may include a fifth contact region (SA3), a sixth contact region (DA3), and a third channel region (CH3) disposed between the fifth contact region (SA3) and the sixth contact region (DA3). The fifth contact region (SA3) and the sixth contact region (DA3) may be spaced apart from each other in a plane. For example, the sixth contact region (DA3) may be spaced apart from the fifth contact region (SA3) in a second direction (DR2). In one embodiment, the third well region (W3) may extend in the second direction (DR2). For example, the third well region (W3) may have a rectangular shape extending in the second direction (DR2) in a plane, but the present invention is not necessarily limited thereto.
[0077] In one embodiment, the fifth contact region (SA3) and the sixth contact region (DA3) may each be a p-source region and a p-drain region, respectively, but the present invention is not necessarily limited thereto, and the fifth contact region (SA3) and the sixth contact region (DA3) may each be an n-source region and an n-drain region.
[0078] The fifth well region (W5) may include a seventh contact region (SA4), an eighth contact region (DA4), and a fourth channel region (CH4) disposed between the seventh contact region (SA4) and the eighth contact region (DA4). The seventh contact region (SA4) and the eighth contact region (DA4) may be spaced apart from each other in a plane. For example, the eighth contact region (DA4) may be spaced apart from the seventh contact region (SA4) in a second direction (DR2). In one embodiment, the fifth well region (W5) may extend in the second direction (DR2). For example, the fifth well region (W5) may have a rectangular shape extending in the second direction (DR2) in a plane, but the present invention is not necessarily limited thereto.
[0079] In one embodiment, the seventh contact region (SA4) and the eighth contact region (DA4) may each be an n-source region and an n-drain region, respectively, but the present invention is not necessarily limited thereto, and the seventh contact region (SA4) and the eighth contact region (DA4) may each be a p-source region and a p-drain region.
[0080] Referring to FIG. 5, the display device may further include a gate layer (GEL). The gate layer (GEL) may be disposed on a substrate (e.g., the substrate (SUB) of FIG. 4). The gate layer (GEL) may include a first gate pattern (1010), a second gate pattern (1020), a third gate pattern (1030), and a fourth gate pattern (1040). The first gate pattern (1010), the second gate pattern (1020), the third gate pattern (1030), and the fourth gate pattern (1040) may be spaced apart from each other on a plane.
[0081] In one embodiment, the first gate pattern (1010) may include a first portion (1011) and a second portion (1012). The second portion (1012) may be a portion protruding from the first portion (1011). For example, the second portion (1012) may be a portion protruding from the first portion (1011) in a direction opposite to the second direction (DR2). In one embodiment, the width (PW1) of the first portion (1011) in the first direction (DR1) may be greater than the width (PW1) of the second portion (1012) in the first direction (DR1). Additionally, the width of the first portion (1011) in the second direction (DR2) may be greater than the width of the second portion (1012) in the second direction (DR2).
[0082] The gate layer (GEL) may include metals, alloys, metal nitrides, conductive metal oxides, transparent conductive materials, etc. Examples of the metals include silver (Ag), molybdenum (Mo), aluminum (Al), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), etc. These may be used alone or in combination with one another. Examples of the conductive metal oxides include indium tin oxide and indium zinc oxide. These may be used alone or in combination with one another. Examples of the metal nitrides include aluminum nitride (AlN x ), tungsten nitride (WN x ), chromium nitride (CrN x Examples include ) etc. These can be used individually or in combination with each other.
[0083] Referring to FIGS. 4 through 6, the first transistor (T1) may include a portion of the first well region (W1) and a portion of the first gate pattern (1010). For example, the first transistor (T1) may include a first contact region (SA1), a second contact region (DA1), a first channel region (CH1), and a portion of the first gate pattern (1010) that overlaps the first channel region (CH1) in a plane.
[0084] In one embodiment, the first transistor (T1) may include a first contact region (SA1), a second contact region (DA1), a first channel region (CH1), and a portion of a first part (1011) that overlaps with the first channel region (CH1) in a plane. For example, the first part (1011) may overlap at least partially with the first channel region (CH1) in a plane. The second part (1012) may be spaced apart from the first channel region (CH1) in a plane. The portion of the first part (1011) that overlaps with the first channel region (CH1) in a plane may be referred to as the gate electrode of the first transistor (T1).
[0085] The second transistor (T2) may include a portion of the second well region (W2) and a portion of the second gate pattern (1020). For example, the second transistor (T2) may include a third contact region (SA2), a fourth contact region (DA2), a second channel region (CH2), and a portion of the second gate pattern (1020) that overlaps the second channel region (CH2) in a plane. The portion of the second gate pattern (1020) that overlaps the second channel region (CH2) in a plane may be referred to as the gate electrode of the second transistor (T2).
[0086] The third transistor (T3) may include a portion of the third well region (W3) and a portion of the third gate pattern (1030). For example, the third transistor (T3) may include a fifth contact region (SA3), a sixth contact region (DA3), a third channel region (CH3), and a portion of the third gate pattern (1030) that overlaps the third channel region (CH3) in a plane. The portion of the third gate pattern (1030) that overlaps the third channel region (CH3) in a plane may be referred to as the gate electrode of the third transistor (T3).
[0087] The fourth transistor (T4) may include a portion of the fifth well region (W5) and a portion of the fourth gate pattern (1040). For example, the fourth transistor (T4) may include a seventh contact region (SA4), an eighth contact region (DA4), a fourth channel region (CH4), and a portion of the fourth gate pattern (1040) that overlaps the fourth channel region (CH4) in a plane. The portion of the fourth gate pattern (1040) that overlaps the fourth channel region (CH4) in a plane may be referred to as the gate electrode of the fourth transistor (T4).
[0088] The first transistor (T1) of FIG. 6 corresponds substantially to the first transistor (T1) of FIG. 3, the second transistor (T2) of FIG. 6 corresponds substantially to the second transistor (T2) of FIG. 3, the third transistor (T3) of FIG. 6 corresponds substantially to the third transistor (T3) of FIG. 3, and the fourth transistor (T4) of FIG. 6 corresponds substantially to the fourth transistor (T4) of FIG. 3, but the present invention is not necessarily limited thereto.
[0089] Referring to FIGS. 1 and FIGS. 6, in one embodiment, each of the plurality of pixels (PX) may have a first width (XW1) in a first direction (DR1) and a second width (XW2) in a second direction (DR2). For example, the area where one of the plurality of pixels (PX) is placed may correspond to the pixel area (PXA) of FIG. 6, and the pixel area (PXA) may have a first width (XW1) in a first direction (DR1) and a second width (XW2) in a second direction (DR2). In one embodiment, a first transistor (T1), a second transistor (T2), a third transistor (T3), and a fourth transistor (T4) may be placed in the pixel area (PXA). For example, the pixel area (PXA) may refer to an area where the first transistor (T1), the second transistor (T2), the third transistor (T3), and the fourth transistor (T4) are placed. In one embodiment, a light-emitting element (e.g., a light-emitting element (LED) of FIG. 3) may be disposed in a pixel area (PXA). In one embodiment, the first width (XW1) in the first direction (DR1) of each of the plurality of pixels (PX) may be larger than the second width (XW2) in the second direction (DR2).
[0090] Referring to FIG. 7, the display device may further include a first contact layer (SDL1). The first contact layer (SDL1) may be disposed on a gate layer (e.g., the gate layer (GEL) of FIG. 6). The first contact layer (SDL1) may include a first contact pattern (2010), a second contact pattern (2020), a third contact pattern (2030), a fourth contact pattern (2040), a fifth contact pattern (2050), a sixth contact pattern (2060), a seventh contact pattern (2070), an eighth contact pattern (2080), and a ninth contact pattern (2090). The first contact pattern (2010), the second contact pattern (2020), the third contact pattern (2030), the fourth contact pattern (2040), the fifth contact pattern (2050), the sixth contact pattern (2060), the seventh contact pattern (2070), the eighth contact pattern (2080), and the ninth contact pattern (2090) may be spaced apart from each other on a plane.
[0091] A first scan signal (e.g., the first scan signal (GW) of FIG. 3) may be applied to the third contact pattern (2030). For example, the third contact pattern (2030) may substantially correspond to the first scan line (e.g., the first scan line (GWL) of FIG. 3), but the present invention is not necessarily limited thereto. The third contact pattern (2030) may be extended in a second direction (DR2).
[0092] A light emission control signal (e.g., the light emission control signal (EM) of FIG. 3) may be applied to the fifth contact pattern (2050). For example, the fifth contact pattern (2050) may substantially correspond to a light emission control line (e.g., the light emission control line (EL) of FIG. 3), but the present invention is not necessarily limited thereto. The fifth contact pattern (2050) may be extended in a second direction (DR2).
[0093] A second scan signal (e.g., the second scan signal (EB) of FIG. 3) may be applied to the eighth contact pattern (2080). For example, the eighth contact pattern (2080) may substantially correspond to a second scan line (e.g., the second scan line (EBL) of FIG. 3), but the present invention is not necessarily limited thereto.
[0094] Referring to FIGS. 4, 5 and 8, the first contact pattern (2010) can be connected to the first gate pattern (1010). In one embodiment, the first contact pattern (2010) can be connected to the second part (1012). For example, the first contact pattern (2010) can be connected to the second part (1012) through a first contact hole (CNT1) and a second contact hole (CNT2). Each of the first contact hole (CNT1) and the second contact hole (CNT2) can penetrate a portion of the second insulating layer (e.g., the second insulating layer (IL2) in FIG. 11). The first contact pattern (2010) can be connected to the gate electrode of the first transistor (T1). For example, the first contact pattern (2010) can be connected to the gate electrode of the first transistor (T1) through the second part (1012), the first contact hole (CNT1), and the second contact hole (CNT2).
[0095] The first contact pattern (2010) can be connected to the second transistor (T2). For example, the first contact pattern (2010) can be connected to the third contact region (SA2). For example, the first contact pattern (2010) can be connected to the third contact region (SA2) through the third contact hole (CNT3) and the fourth contact hole (CNT4). Each of the third contact hole (CNT3) and the fourth contact hole (CNT4) can penetrate the second insulating layer. The gate electrode of the first transistor (T1) and the second transistor (T2) can be connected to each other through the first contact pattern (2010). For example, the gate electrode of the first transistor (T1) and the third contact region (SA2) of the second transistor (T2) can be connected to each other through the first contact pattern (2010).
[0096] The second contact pattern (2020) can be connected to the fourth well region (W4). For example, the second contact pattern (2020) can be connected to the fourth well region (W4) through the fifth contact hole (CNT5), the sixth contact hole (CNT6), the seventh contact hole (CNT7), and the eighth contact hole (CNT8). Each of the fifth contact hole (CNT5), the sixth contact hole (CNT6), the seventh contact hole (CNT7), and the eighth contact hole (CNT8) can penetrate the second insulating layer.
[0097] The third contact pattern (2030) can be connected to the gate electrode of the second transistor (T2). For example, the third contact pattern (2030) can be connected to the second gate pattern (1020). For example, the third contact pattern (2030) can be connected to the second gate pattern (1020) through a contact hole. The gate electrode of the second transistor (T2) can receive the first scan signal through the third contact pattern (2030).
[0098] The fourth contact pattern (2040) can be connected to the second transistor (T2). For example, the fourth contact pattern (2040) can be connected to the fourth contact region (DA2) of the second transistor (T2). For example, the fourth contact pattern (2040) can be connected to the fourth contact region (DA2) of the second transistor (T2) through a contact hole.
[0099] The fifth contact pattern (2050) can be connected to the gate electrode of the third transistor (T3). For example, the fifth contact pattern (2050) can be connected to the third gate pattern (1030). For example, the fifth contact pattern (2050) can be connected to the third gate pattern (1030) through a contact hole. The gate electrode of the third transistor (T3) can receive the light emission control signal through the fifth contact pattern (2050).
[0100] The sixth contact pattern (2060) can be connected to the first transistor (T1). For example, the sixth contact pattern (2060) can be connected to the second contact area (DA1). For example, the sixth contact pattern (2060) can be connected to the second contact area (DA1) through the ninth contact hole (CNT9) and the tenth contact hole (CNT10).
[0101] The sixth contact pattern (2060) can be connected to the third transistor (T3). For example, the sixth contact pattern (2060) can be connected to the fifth contact area (SA3). For example, the sixth contact pattern (2060) can be connected to the fifth contact area (SA3) through a contact hole. The first transistor (T1) and the third transistor (T3) can be connected to each other through the sixth contact pattern (2060). For example, the second contact area (DA1) and the fifth contact area (SA3) can be connected to each other through the sixth contact pattern (2060).
[0102] The seventh contact pattern (2070) can be connected to the third transistor (T3). For example, the seventh contact pattern (2070) can be connected to the sixth contact area (DA3). For example, the seventh contact pattern (2070) can be connected to the sixth contact area (DA3) through a contact hole.
[0103] The eighth contact pattern (2080) can be connected to the gate electrode of the fourth transistor (T4). For example, the eighth contact pattern (2080) can be connected to the fourth gate pattern (1040). For example, the eighth contact pattern (2080) can be connected to the fourth gate pattern (1040) through a contact hole. The gate electrode of the fourth transistor (T4) can receive the second scan signal through the eighth contact pattern (2080).
[0104] The ninth contact pattern (2090) can be connected to the fourth transistor (T4). For example, the ninth contact pattern (2090) can be connected to the seventh contact region (DA4). For example, the ninth contact pattern (2090) can be connected to the seventh contact region (DA4) through a contact hole.
[0105] The first contact layer (SDL1) may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. Examples of the metal include silver (Ag), molybdenum (Mo), aluminum (Al), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), etc. These may be used alone or in combination with one another. Examples of the conductive metal oxide include indium tin oxide, indium zinc oxide, etc. These may be used alone or in combination with one another. Examples of the metal nitride include aluminum nitride (AlN x ), tungsten nitride (WN x ), chromium nitride (CrN xExamples include ) etc. These can be used individually or in combination with each other.
[0106] Referring to FIG. 9, the display device may further include a second contact layer (SDL2). The second contact layer (SDL2) may be disposed on a first contact layer (e.g., the first contact layer (SDL1) of FIG. 8). The second contact layer (SDL2) may include a first contact line (3010), a second contact line (3020), a third contact line (3030), and a fourth contact line (3040). The first contact line (3010), the second contact line (3020), the third contact line (3030), and the fourth contact line (3040) may be spaced apart from each other in a plane.
[0107] A reference voltage (e.g., the reference voltage (VREF) of FIG. 3) may be applied to the first contact line (3010). For example, the first contact line (3010) may substantially correspond to a fourth voltage line (e.g., the fourth voltage line (VL4) of FIG. 3), but the present invention is not necessarily limited thereto. In one embodiment, the first contact line (3010) may include a first portion extending in a first direction (DR1) and a second portion extending from the first portion in a second direction (DR2).
[0108] An initialization voltage (e.g., the initialization voltage (VINT) of FIG. 3) may be applied to the second contact line (3020). For example, the second contact line (3020) may substantially correspond to a third voltage line (e.g., the third voltage line (VL3) of FIG. 3), but the present invention is not necessarily limited thereto. The second contact line (3020) may extend in a first direction (DR1).
[0109] A data voltage (e.g., the data voltage (DT) of FIG. 3) may be applied to the third contact line (3030). For example, the third contact line (3030) may substantially correspond to a data line (e.g., the data line (DL) of FIG. 3), but the present invention is not necessarily limited thereto. The third contact line (3030) may extend in a first direction (DR1).
[0110] A first power supply voltage (e.g., the first power supply voltage (ELVDD) of FIG. 3) may be applied to the fourth contact line (3040). For example, the fourth contact line (3040) may substantially correspond to a first voltage line (e.g., the first voltage line (VL1) of FIG. 3), but the present invention is not necessarily limited thereto. The fourth contact line (3040) may extend in a first direction (DR1).
[0111] Referring to FIGS. 4, 8, and 10, the second contact line (3020) can be connected to the fourth transistor (T4). For example, the second contact line (3020) can be connected to the seventh contact area (SA4). For example, the second contact line (3020) can be connected to the ninth contact pattern (2090) through a contact hole, and as described above, the ninth contact pattern (2090) can be connected to the seventh contact area (SA4) through the contact hole. The fourth transistor (T4) can receive the initialization voltage through the second contact line (3020). For example, the seventh contact area (SA4) of the fourth transistor (T4) can receive the initialization voltage through the second contact line (3020).
[0112] The third contact line (3030) can be connected to the second transistor (T2). For example, the third contact line (3030) can be connected to the fourth contact area (DA2). For example, the third contact line (3030) can be connected to the fourth contact pattern (2040) through a contact hole, and as described above, the fourth contact pattern (2040) can be connected to the fourth contact area (DA2) through the contact hole. The second transistor (T2) can receive the data voltage through the third contact line (3030). For example, the fourth contact area (DA2) of the second transistor (T2) can receive the data voltage through the third contact line (3030).
[0113] The fourth contact line (3040) can be connected to the third transistor (T3). For example, the fourth contact line (3040) can be connected to the sixth contact area (DA3). For example, the fourth contact line (3040) can be connected to the seventh contact pattern (2070) through a contact hole, and as described above, the seventh contact pattern (2070) can be connected to the sixth contact area (DA3) through the contact hole. The third transistor (T3) can receive the first power supply voltage through the fourth contact line (3040). For example, the sixth contact area (DA3) of the third transistor (T3) can receive the first power supply voltage through the fourth contact line (3040).
[0114] The fourth contact line (3040) can be connected to the second contact pattern (2020). For example, the fourth contact line (3040) can be connected to the second contact pattern (2020) through the first contact hole (CNT11) and the second contact hole (CNT12). Each of the first contact hole (CNT11) and the second contact hole (CNT12) can penetrate a portion of the second insulating layer (e.g., the second insulating layer (IL2) in FIG. 11). The fourth well region (W4) can be connected to the fourth contact line (3040) through the second contact pattern (2020). The fourth well region (W4) can receive the first power supply voltage through the second contact pattern (2020) and the fourth contact line (3040). Accordingly, it is possible to prevent some areas of the substrate (SUB) from being affected by unintended electrical signals. For example, it is possible to prevent the substrate (SUB) from being affected by the initialization voltage, the data voltage, etc., around the fourth well area (W4).
[0115] The second contact layer (SDL2) may include metals, alloys, metal nitrides, conductive metal oxides, transparent conductive materials, etc. Examples of the metals include silver (Ag), molybdenum (Mo), aluminum (Al), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), etc. These may be used alone or in combination with one another. Examples of the conductive metal oxides include indium tin oxide, indium zinc oxide, etc. These may be used alone or in combination with one another. Examples of the metal nitrides include aluminum nitride (AlN x ), tungsten nitride (WN x ), chromium nitride (CrN x Examples include ) etc. These can be used individually or in combination with each other.
[0116] Referring to FIGS. 1, 4, 5, 6, and 8, as described above, the first gate pattern (1010) may include a first portion (1011) and a second portion (1012). For example, the first gate pattern (1010) may include an uneven structure on one side. The uneven structure may correspond to the second portion (1012). A display device (DD) according to one embodiment of the present invention may include an uneven structure (i.e., the second portion (1012)) for connecting the first gate pattern (1010) and the first contact pattern (2010) to each other. The gate pattern (1010) may include an uneven structure only in the area where the first contact hole (CNT1) and the second contact hole (CNT2) are placed. For example, the gate pattern (1010) may have a shape in which the first pattern (SP1) and the second pattern (SP2) are removed from a rectangle. The first pattern (SP1) and the first part (1011) can overlap each other in the second direction (DR2), and the first pattern (SP1) and the second part (1012) can overlap each other in the first direction (DR1). The second pattern (SP2) and the first part (1011) can overlap each other in the second direction (DR2), and the second pattern (SP2) and the second part (1012) can overlap each other in the first direction (DR1). Since the gate pattern (1010) has a shape in which the first pattern (SP1) and the second pattern (SP2) are removed from the rectangle, sufficient space can be secured for the second transistor (T2) and the third transistor (T3) to be placed. For example, by removing the first pattern (SP1) and the second pattern (SP2), which are unnecessary parts other than the area where the first contact hole (CNT1) and the second contact hole (CNT2) are placed, sufficient space can be secured for placing the second transistor (T2) and the third transistor (T3). Accordingly, the planar separation distance between the first transistor (T1) and the second transistor (T2) can be reduced. Additionally, the planar separation distance between the first transistor (T1) and the third transistor (T3) can be reduced.Accordingly, a pixel driving circuit suitable for a high-resolution display device (DD) (e.g., the pixel driving circuit (PXC) of FIG. 3) may be provided.
[0117] As described above, the first well region (W1) constituting the first transistor (T1) may be extended in a first direction (DR1). For example, the width of the first well region (W1) in the first direction (DR1) may be greater than the width in the second direction (DR2). The fourth well region (W4) connected to the fourth contact line (e.g., the fourth contact line (3040) of FIG. 10) may be extended in a first direction (DR1). For example, the width of the fourth well region (W4) in the first direction (DR1) may be greater than the width in the second direction (DR2). The second well region (W2) constituting the second transistor (T2) may be extended in a second direction (DR2). For example, the width of the second well region (W2) in the second direction (DR2) may be greater than the width in the first direction (DR1). The third well region (W3) constituting the third transistor (T3) may be extended in a second direction (DR2). For example, the width of the third well region (W3) in the second direction (DR2) may be greater than the width in the first direction (DR1). The fifth well region (W5) constituting the fourth transistor (T4) may be extended in a second direction (DR2). For example, the width of the fifth well region (W5) in the second direction (DR2) may be greater than the width in the first direction (DR1). Additionally, as described above, the first width (XW1) in the first direction (DR1) of each of the plurality of pixels (PX) may be greater than the second width (XW2) in the second direction (DR2). The first well region (W1) may be extended in a direction parallel to the direction of the first width (XW1) (i.e., the first direction (DR1)). Accordingly, the first transistor (T1), the second transistor (T2), the third transistor, and the fourth transistor (T4) can be arranged in two rows. For example, the first transistor (T1) can be placed in the first row, and the second transistor (T2), the third transistor, and the fourth transistor (T4) can each be placed in the second row.Accordingly, a pixel driving circuit suitable for a high-resolution display device (DD) (e.g., the pixel driving circuit (PXC) of FIG. 3) may be provided.
[0118] Figure 11 is a cross-sectional view of the display device of Figure 10 cut along line II'.
[0119] Referring to FIG. 11, the substrate (SUB) may include a first well region (W1). The first well region (W1) may include a first channel region (CH1) and a second contact region (DA1). A first insulating layer (IL1) may be disposed on the substrate (SUB). The first insulating layer (IL1) may overlap the first gate pattern (1010) in a planar manner. The first insulating layer (IL1) is silicon oxide (SiO₂). x ), silicon nitride (SiN x ), silicon carbide (SiC x ), silicon oxynitride (SiO₂ x N y ), silicon oxycarbide (SiO₂ x C y It may include inorganic materials such as ). These may be used alone or in combination with each other. A first gate pattern (1010) may be placed on the first insulating layer (IL1).
[0120] A second insulating layer (IL2) may be disposed on a first insulating layer (IL1). The second insulating layer (IL2) may cover the first insulating layer (IL1) and the first gate pattern (1010). The second insulating layer (IL2) may include a first contact hole (CNT1) and a ninth contact hole (CNT9). The second insulating layer (IL2) is silicon oxide (SiO2). x ), silicon nitride (SiN x ), silicon carbide (SiC x ), silicon oxynitride (SiO₂ x N y ), silicon oxycarbide (SiO₂ x C yIt may include inorganic materials such as ). These can be used alone or in combination with each other.
[0121] A first contact pattern (2010), a fifth contact pattern (2050), and a sixth contact pattern (2060) may be disposed on the second insulating layer (IL2). The first contact pattern (2010) may be connected to the first gate pattern (1010) through the first contact hole (CNT1). For example, the first contact pattern (2010) may be connected to the first part (1011) through the first contact hole (CNT1). The sixth contact pattern (2060) may be connected to the second contact region (DA1) through the ninth contact hole (CNT9).
[0122] A third insulating layer (IL3) may be disposed on the second insulating layer (IL2). The third insulating layer (IL3) may cover the first contact pattern (2010), the fifth contact pattern (2050), and the sixth contact pattern (2060). The third insulating layer (IL3) is silicon oxide (SiO2). x ), silicon nitride (SiN x ), silicon carbide (SiC x ), silicon oxynitride (SiO₂ x N y ), silicon oxycarbide (SiO₂ x C y It may include inorganic materials such as ). These may be used alone or in combination with each other. In one embodiment, the third insulating layer (IL3) may further include organic materials such as phenolic resin, polyimide resin, polyamide resin, siloxane resin, epoxy resin, etc. These may be used alone or in combination with each other.
[0123] A first contact line (3010) may be disposed on the third insulating layer (IL3). A fourth insulating layer (IL4) may be disposed on the third insulating layer (IL3). The fourth insulating layer (IL4) may cover the first contact line (3010). The fourth insulating layer (IL4) is silicon oxide (SiO₂). x ), silicon nitride (SiN x ), silicon carbide (SiC x ), silicon oxynitride (SiO₂ x N y ), silicon oxycarbide (SiO₂ x C y It may include inorganic materials such as ). These may be used alone or in combination with each other. In one embodiment, the fourth insulating layer (IL4) may further include organic materials such as phenolic resin, polyimide resin, polyamide resin, siloxane resin, epoxy resin, etc. These may be used alone or in combination with each other.
[0124] A display device according to an embodiment (e.g., the display device (DD) of FIG. 1) can be applied to various electronic devices. An electronic device according to one embodiment includes the display device described above and may further include a module or device having additional functions other than the display device.
[0125] FIG. 12 is a block diagram of an electronic device according to one embodiment of the present invention.
[0126] Referring to FIG. 12, an electronic device (10) according to one embodiment may include a display module (11), a processor (12), a memory (13), and a power module (14).
[0127] The processor (12) may include at least one of a central processing unit (CPU), an application processor (AP), a graphic processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.
[0128] The memory (15) may store data information necessary for the operation of the processor (12) or the display module (11). When the processor (12) executes an application stored in the memory (15), a video data signal and / or an input control signal is transmitted to the display module (11), and the display module (11) can process the received signal and output video information through a display screen.
[0129] The power module (14) may include a power supply module, such as a power adapter or battery device, and a power conversion module that converts the power supplied by the power supply module to generate power required for the operation of the electronic device (10).
[0130] At least one of each component of the electronic device (10) described above may be included in a display device according to the embodiments described above. Additionally, some of the individual modules functionally included in one module may be included in the display device, while others may be provided separately from the display device. For example, the display device may include a display module (11), and the processor (12), memory (13), and power module (14) may be provided in the form of other devices within the electronic device (10) other than the display device.
[0131] FIG. 13 is a schematic diagram of an electronic device according to various embodiments.
[0132] Referring to FIG. 13, various electronic devices to which a display device according to the embodiments is applied may include not only image display electronic devices such as a smartphone (10_1a), tablet PC (10_1b), laptop (10_1c), TV (10_1d), and desk monitor (10_1e), but also wearable electronic devices including display modules such as smart glasses (10_2a), head-mounted display (10_2b), and smart watch (10_2c), and automotive electronic devices (10_3) including display modules such as a CID (Center Information Display) and room mirror display placed on the instrument panel, center fascia, and dashboard of a car.
[0133] Although the present invention has been described above with reference to exemplary embodiments, those skilled in the art will understand that various modifications and changes can be made to the invention without departing from the spirit and scope of the invention as set forth in the following claims. Industrial applicability
[0134] The present invention may be applied to display devices and electronic devices including the same. For example, the present invention may be applied to high-resolution smartphones, mobile phones, smartpads, smartwatches, tablet PCs, vehicle navigation systems, televisions, computer monitors, laptops, etc. Explanation of the symbols
[0135] DD: Display device DA: Display area NDA: Non-display area PX: Multiple pixels 100: Drive control unit 200: Scan drive unit 300: Gamma reference voltage generation unit 400: Data driver 500: Light emission control drive unit 600: Voltage generation unit PXC: Pixel driving circuit LED: Light-emitting element SUB: Substrate GEL: Gate layer SDL1: First contact layer SDL2: Second contact layer T1: First transistor T2: Second transistor T3: Third transistor T4: 4th transistor
Claims
Claim 1 A display device comprising: a substrate including a first well region comprising a first contact region, a second contact region spaced apart from the first contact region in a plane, and a first channel region disposed between the first contact region and the second contact region; a first gate pattern disposed on the substrate and comprising a first portion that at least partially overlaps with the first channel region in a plane and a second portion that protrudes from the first portion; and a first contact pattern disposed on the first gate pattern and connected to the second portion of the first gate pattern through a first contact hole. Claim 2 A display device according to claim 1, wherein the width of the first portion of the first gate pattern in the first direction is greater than the width of the second portion of the first gate pattern in the first direction. Claim 3 A display device according to claim 2, wherein the second portion of the first gate pattern is spaced apart from the first channel region in a plane. Claim 4 A display device according to claim 1, wherein a portion of the first well region and a portion of the first gate pattern constitute a first transistor that provides a driving current to a light-emitting element. Claim 5 A display device according to claim 1, wherein the substrate further comprises a second well region including a third contact region, a fourth contact region spaced apart from the third contact region in a plane, and a second channel region disposed between the third contact region and the fourth contact region, and further comprises a second gate pattern disposed on the substrate, spaced apart from the first gate pattern in a plane, and at least partially overlapping with the second channel region in a plane. Claim 6 A display device according to claim 5, wherein the first well region extends in a first direction and the second well region extends in a second direction intersecting the first direction. Claim 7 A display device according to claim 6, wherein the second contact area is spaced apart from the first contact area in the first direction, and the fourth contact area is spaced apart from the third contact area in the second direction. Claim 8 A display device according to claim 6, wherein a portion of the first well region and a portion of the first gate pattern constitute a first transistor that provides a driving current to a light-emitting element, and a portion of the second well region and a portion of the second gate pattern constitute a second transistor that provides a data voltage to a first node. Claim 9 A display device according to claim 5, wherein the substrate further comprises a third well region including a fifth contact region, a sixth contact region spaced apart in a plane from the fifth contact region, and a third channel region disposed between the fifth contact region and the sixth contact region, and further comprises a third gate pattern disposed on the substrate, spaced apart in a plane from the first gate pattern and the second gate pattern, and at least partially overlapping in a plane with the third channel region. Claim 10 A display device according to claim 9, wherein the first well region extends in a first direction, and the second well region and the third well region each extend in a second direction intersecting the first direction. Claim 11 In claim 5, the display device wherein the first contact pattern is connected through the third contact area and the third contact hole. Claim 12 A display device according to claim 1, wherein the substrate further comprises a fourth well region spaced apart from the first well region in a plane, a second contact pattern disposed on the first gate pattern and connected to the fourth well region through a fifth contact hole, and a fourth contact line disposed on the second contact pattern, to which a first power supply voltage is applied, and connected to the second contact pattern through a first contact hole. Claim 13 In claim 12, the display device wherein each of the first well region and the fourth well region extends in a first direction. Claim 14 A display device according to claim 1, wherein the first gate pattern is placed in a display area where a pixel is placed, the width of the pixel in the first direction is greater than the width in the second direction intersecting the first direction of the pixel, and the first well area extends in the first direction. Claim 15 A display device comprising: a first well region extending in a first direction, including a first contact region, a second contact region spaced apart from the first contact region in a plane, and a first channel region disposed between the first contact region and the second contact region; a substrate including a third contact region, a fourth contact region spaced apart from the third contact region in a plane, and a second channel region disposed between the third contact region and the fourth contact region, and a second well region extending in a second direction intersecting the first direction; a first gate pattern disposed on the substrate and at least partially overlapping with the first channel region in a plane; and a second gate pattern disposed on the substrate, spaced apart from the first gate pattern in a plane, and at least partially overlapping with the second channel region in a plane. Claim 16 A display device according to claim 15, wherein a portion of the first well region and a portion of the first gate pattern constitute a first transistor that provides a driving current to a light-emitting element, and a portion of the second well region and a portion of the second gate pattern constitute a second transistor that provides a data voltage to a first node. Claim 17 A display device according to claim 15, wherein the substrate further comprises a third well region extending in the second direction and including a fifth contact region, a sixth contact region spaced apart in a plane from the fifth contact region, and a third channel region disposed between the fifth contact region and the sixth contact region, and further comprises a third gate pattern disposed on the substrate, spaced apart in a plane from the first gate pattern and the second gate pattern, and at least partially overlapping in a plane with the third channel region. Claim 18 An electronic device comprising: a substrate including a first well region comprising a first contact region, a second contact region spaced apart from the first contact region in a plane, and a first channel region disposed between the first contact region and the second contact region; a first gate pattern disposed on the substrate and comprising a first portion that at least partially overlaps with the first channel region in a plane and a second portion that protrudes from the first portion; a first contact pattern disposed on the first gate pattern and connected to the second portion of the first gate pattern through a first contact hole; and a memory in which data information is stored. Claim 19 An electronic device according to claim 18, wherein the width of the first portion of the first gate pattern in the first direction is greater than the width of the second portion of the first gate pattern in the first direction. Claim 20 An electronic device according to claim 19, wherein the second portion of the first gate pattern is spaced apart from the first channel region in a plane.