Source Driver Integrated Circuit and Display System Including The Same

Abstract

A source drive direct circuit according to one aspect of the present invention, capable of reducing the delay or distortion of a driving signal by reducing the resistance deviation between a plurality of routing metals, comprises: a first routing metal connecting a first channel driving circuit and a first pad; a second routing metal connecting a second channel driving circuit and a second pad and having a different length from the first routing metal; a first resistance deviation compensation circuit connected to the first routing metal and having a first compensation resistance value; and a second resistance deviation compensation circuit connected to the second routing metal and having a second compensation resistance value different from the first compensation resistance value, wherein the first channel resistance value obtained by summing the first resistance value of the first routing metal and the first compensation resistance value is the same as the second channel resistance value obtained by summing the second resistance value of the second routing metal and the second compensation resistance value.

Description

Technology Field

[0001] The present invention relates to a display device, and more specifically, to a source drive integrated circuit. Background Technology

[0002] As the information age advances, various display devices capable of visualizing information are being developed. Liquid Crystal Displays (LCDs), Organic Light Emitting Diodes (OLEDs), and Plasma Display Panels (PDPs) are examples of display devices that have been developed or are currently under development. These display devices are evolving to properly display high-resolution images.

[0003] The display device includes a display panel comprising a plurality of pixels defined by a plurality of gate lines and a plurality of data lines, a gate driving circuit that supplies a gate signal to the gate lines, a data driving circuit that supplies a data voltage to the data lines, and a timing controller that controls the operation of the gate driving circuit and the data driving circuit.

[0004] The data driver circuit includes multiple source driver integrated circuits (SDICs). The source driver integrated circuit converts a data signal corresponding to a digital video signal received from the timing controller into a data voltage corresponding to an analog video signal and outputs it to the data line.

[0005] A source drive integrated circuit includes a driving circuit, a multiplexer circuit, and multiple routing metals for connecting the multiplexer circuit to a pad. At this time, differences in the position of the pads may cause length differences between the multiple routing metals, and these length differences inevitably lead to resistance variations between the routing metals. If resistance variations occur between the multiple routing metals, delays or distortions in the driving signal may occur, resulting in a problem of degraded image quality.

[0006] To solve this problem, as shown in FIG. 1, in a general source drive integrated circuit (10), the lengths of the multiple routing metals (RM) are adjusted to eliminate resistance variation between the multiple routing metals (RM) for connecting each multiple circuit (14) to the pad (16), so that each routing metal (RM) has the same length. However, in the case of a source drive integrated circuit (10) having a structure as shown in FIG. 1, there is a problem that the chip size of the source drive integrated circuit (10) increases because space is required to form the routing metals (RM).

[0007] In addition, in the case of a general source drive direct circuit (10) shown in Fig. 1, if the length of the routing metal (RM) is increased to reduce the resistance variation between the routing metals (RM), the possibility of overlap between the routing metal (RM) and other circuits increases, and as a result, output noise affects other circuits, which may cause the performance of the source drive direct circuit (10) to deteriorate. The problem to be solved

[0008] The present invention aims to solve the aforementioned problems by providing a source drive integrated circuit capable of reducing the delay or distortion of a driving signal by reducing the resistance deviation between a plurality of routing metals, and a display device including the same. means of solving the problem

[0009] A source drive direct circuit according to one aspect of the present invention for achieving the above-described technical problem comprises: a first routing metal connecting a first channel driving circuit and a first pad; a second routing metal connecting a second channel driving circuit and a second pad and having a different length from the first routing metal; a first resistance deviation compensation circuit connected to the first routing metal and having a first compensation resistance value; and a second resistance deviation compensation circuit connected to the second routing metal and having a second compensation resistance value different from the first compensation resistance value, wherein the first channel resistance value obtained by summing the first resistance value of the first routing metal and the first compensation resistance value is the same as the second channel resistance value obtained by summing the second resistance value of the second routing metal and the second compensation resistance value.

[0010] A display device according to another aspect of the present invention for achieving the above-described technical problem comprises: a display panel; and a source drive direct circuit for driving the display panel, wherein the source drive direct circuit comprises: a first routing metal connecting a first channel driving circuit and a first pad; a second routing metal connecting a second channel driving circuit and a second pad and having a different length from the first routing metal; a first resistance deviation compensation circuit connected to the first routing metal and having a first compensation resistance value; and a second resistance deviation compensation circuit connected to the second routing metal and having a second compensation resistance value different from the first compensation resistance value, wherein the first channel resistance value obtained by summing the first resistance value of the first routing metal and the first compensation resistance value is the same as the second channel resistance value obtained by summing the second resistance value of the second routing metal and the second compensation resistance value. Effects of the invention

[0011] According to the present invention, in order to compensate for a resistance difference between a first routing metal and a second routing metal having different lengths, a first resistance difference compensation circuit having a first compensation resistance value is connected to the first routing metal and a second resistance difference compensation circuit having a second compensation resistance value is connected to the second routing metal. By determining the first and second compensation resistance values ​​such that the first channel resistance value, which is the sum of the first compensation resistance value and the first resistance value of the first routing metal, becomes equal to the second channel resistance value, which is the sum of the second compensation resistance value and the second resistance value of the second routing metal, the resistance difference caused by the difference in length between the routing metals can be eliminated, thereby providing the effect of reducing the delay or distortion of the driving signal.

[0012] In addition, according to the present invention, since there is no need to increase the length of the routing metal to improve resistance deviation, there is an effect of being able to reduce the chip size of the source drive direct circuit.

[0013] In addition, according to the present invention, since there is no need to increase the length of the routing metal to improve resistance deviation, the routing metal can be formed using only the metal on the same layer without the need to form the routing metal by penetrating multiple layers to secure the length of the routing metal, thus increasing the freedom of chip design. Brief explanation of the drawing

[0014] Figure 1 is a diagram showing the configuration of a typical source drive direct circuit formed so that a plurality of routing metals have the same length. FIG. 2 is a diagram showing the configuration of a display device to which a source drive direct circuit according to one embodiment of the present invention is applied. FIG. 3 is a diagram showing the configuration of a source drive direct circuit including a resistance deviation compensation circuit according to one embodiment of the present invention. Figure 4 is a diagram showing the configuration of a source drive direct circuit when the channel driving circuit is a data voltage output circuit. FIG. 5 is a diagram showing the configuration of a data voltage output circuit according to one embodiment of the present invention. Figure 6 is a diagram showing the connection between a subpixel of an organic light-emitting diode display panel and a sensing circuit. Figure 7 is a diagram showing the configuration of a source drive direct circuit when the channel driving circuit is a sensing circuit. Specific details for implementing the invention

[0015] Throughout the specification, identical reference numbers denote substantially identical components. In the following description, detailed descriptions of components and functions known in the art may be omitted if they are not related to the core components of the invention. The meanings of the terms described in this specification should be understood as follows.

[0016] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims.

[0017] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining embodiments of the present invention are exemplary, and therefore the present invention is not limited to the depicted details. Throughout the specification, the same reference numerals refer to the same components. Furthermore, in describing the present invention, if it is determined that a detailed description of related known technology may unnecessarily obscure the essence of the present invention, such detailed description is omitted.

[0018] Where terms such as 'comprising,' 'having,' 'consisting of,' etc. are used in this specification, other parts may be added unless 'only' is used. Where a component is expressed in the singular, it includes cases where it is included in the plural unless specifically stated otherwise.

[0019] In interpreting the components, they are interpreted to include a margin of error even in the absence of a separate explicit statement.

[0020] In the case of describing a positional relationship, for example, when the positional relationship between two parts is described using expressions such as 'on,' 'upper,' 'lower,' or 'next to,' one or more other parts may be located between the two parts unless 'immediately' or 'directly' is used.

[0021] Although terms such as "first," "second," etc. are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the technical scope of the present invention.

[0022] The term “at least one” should be understood to include all combinations that can be presented from one or more related items. For example, the meaning of “at least one of the first item, the second item, and the third item” may mean not only the first item, the second item, or the third item individually, but also all combinations of items that can be presented from two or more of the first item, the second item, and the third item.

[0023] The features of each of the various embodiments of the present invention may be combined or combined with one another, either partially or wholly, and may technically enable various interlocking and operation. Each embodiment may be implemented independently of one another or may be implemented together in an associated relationship.

[0025] Hereinafter, embodiments of the present specification will be described in detail with reference to the attached drawings.

[0026] FIG. 2 is a diagram showing the configuration of a display device to which a source drive direct circuit according to an embodiment of the present invention is applied. The display device (100) shown in FIG. 2 is an electronic device including a source drive direct circuit according to the present invention, and may be various display devices that use, for example, the voltage of a battery or an external power source as the operating voltage.

[0027] Referring to FIG. 2, a display device (100) according to the present invention includes a display panel (110) in which a plurality of gate lines (GL) and a plurality of data lines (DL) are connected and a plurality of subpixels (SP) are arranged in a matrix form, a gate driving circuit (120) for driving a plurality of gate lines (GL), a data driving circuit (130) for supplying a data voltage through a plurality of data lines (DL), and a timing controller (140) for controlling the gate driving circuit (120) and the data driving circuit (130).

[0028] The display panel (110) displays an image based on a scan signal transmitted from a gate driving circuit (120) through a plurality of gate lines (GL) and a data voltage transmitted from a data driving circuit (130) through a plurality of data lines (DL).

[0029] In one embodiment, the display panel (110) may be a liquid crystal display panel. When the display panel (110) is a liquid crystal display panel, the display panel (110) includes a liquid crystal layer formed between two substrates and may be operated in any known mode, such as a TN (Twisted Nematic) mode, a VA (Vertical Alignment) mode, an IPS (In Plane Switching) mode, or an FFS (Fringe Field Switching) mode.

[0030] In another embodiment, the display panel (110) may be an Organic Light Emitting Diode (OLED) display panel. When the display panel (110) is an OLED display panel, the display panel (110) may be implemented in a top emission method, a bottom emission method, or a dual emission method.

[0031] For convenience of explanation, the following description will assume that the display panel (110) is an organic light-emitting diode display panel.

[0032] A display panel (110) may have a plurality of pixels arranged in a matrix form, and each pixel may consist of subpixels (SP) of different colors, for example, a white subpixel, a red subpixel, a green subpixel, and a blue subpixel, and each subpixel (SP) may be defined by a plurality of data lines (DL) and a plurality of gate lines (GL).

[0033] A single subpixel (SP) may include a thin film transistor (TFT) formed in the region where a data line (DL) and a gate line (GL) intersect, an organic light-emitting diode, and a storage capacitor electrically connected to the organic light-emitting diode to maintain voltage. An image can be displayed by controlling the current flowing through the organic light-emitting diode placed in each subpixel (SP).

[0034] The gate driving circuit (120) is controlled by the timing controller (140). The gate driving circuit (120) controls the driving timing for a plurality of subpixels (SP) by sequentially outputting scan signals to a plurality of gate lines (GL) arranged on the display panel (110).

[0035] The gate driving circuit (120) may include at least one gate drive integrated circuit (GDIC) and, depending on the driving method, may be located on only one side of the display panel (110) or on both sides. In another embodiment, the gate driving circuit (120) may be embedded in the bezel area of ​​the display panel (110) and implemented in the form of a Gate In Panel (GIP).

[0036] The data driving circuit (130) receives image data (DATA) from the timing controller (140) and converts the received image data (DATA) into an analog data voltage. Then, by outputting the data voltage to each data line (DL) in accordance with the timing at which a scan signal is applied through the gate line (GL), each subpixel (SP) connected to the data line (DL) displays a light emission signal of brightness corresponding to the data voltage.

[0037] The data driving circuit (130) may include at least one source drive integrated circuit (SDIC). The source drive integrated circuit (SDIC) may be connected to a bonding pad of the display panel (110) using a tape-automated bonding (TAB) method or a chip-on-glass (COG) method, or may be placed directly on the display panel (110).

[0038] In one embodiment, each source drive integrated circuit (SDIC) may be integrated and placed on a display panel (110). Additionally, each source drive integrated circuit (SDIC) may be implemented using a Chip On Film (COF) method, and in accordance with this embodiment, each source drive integrated circuit (SDIC) may be mounted on a circuit film and electrically connected to a data line (DL) of the display panel (110) through the circuit film.

[0039] Hereinafter, a source drive direct circuit according to an embodiment of the present invention will be described in more detail with reference to FIGS. 3 to 7.

[0040] FIG. 3 is a diagram showing the configuration of a source drive direct circuit including a resistance deviation compensation circuit according to an embodiment of the present invention. As shown in FIG. 3, a source drive direct circuit (SDIC) according to an embodiment of the present invention includes a plurality of driving circuits (300), a plurality of multiplexer circuits (310), a plurality of routing metals (320), a plurality of pads (330), and a plurality of resistance deviation compensation circuits (340).

[0041] One driving circuit (300) and one multiplexer circuit (310) can be electrically connected to each other to form one channel driving circuit (CDC). According to this embodiment, the source drive direct circuit (SDIC) includes a plurality of channel driving circuits (CDC).

[0042] In one embodiment, the channel driving circuit (CDC) may be a data voltage output circuit that supplies a data voltage to a data line (DL). When the channel driving circuit (CDC) is a data voltage output circuit, the channel driving circuit (CDC) responds to a data control signal supplied from the timing controller (140) during display driving, converts the input image data (DATA) into an analog voltage (Vdata), and supplies it to the corresponding data line (DL).

[0043] Hereinafter, with further reference to FIGS. 4 and FIGS. 5, an embodiment in which the channel driving circuit (CDC) is a data voltage output circuit will be described in detail. FIGS. 4 is a diagram showing the configuration of a source drive direct circuit when the channel driving circuit is a data voltage output circuit, and FIGS. 5 is a diagram showing the configuration of a data voltage output circuit according to an embodiment of the present invention.

[0044] Since the configuration and driving method of each data voltage output circuit (400) are identical to one another, for the convenience of explanation below, the configuration and operation of the source drive direct circuit (SDIC) will be explained based on the first data voltage output circuit (400a) and the second data voltage output circuit (400b) among the plurality of data voltage output circuits.

[0045] As illustrated in FIG. 4, the first data voltage output circuit (400a) is connected to the first pad (330a) through the first routing metal (320a). The first data voltage output circuit (400a) may include a first driving circuit (300a) and a first multiplexer circuit (310a). In one embodiment, the first driving circuit (300a) may be positioned in the central part of the source drive direct circuit (SDIC), and the first multiplexer circuit (310a) may be positioned on one side of the first driving circuit (300a).

[0046] The second data voltage output circuit (400b) is connected to the second pad (330b) through the second routing metal (320b). The second data voltage output circuit (400b) may include a second driving circuit (300b) and a second multiplexer circuit (310b). In one embodiment, the second driving circuit (300b) may be positioned in the central part of the source drive direct circuit (SDIC), and the second multiplexer circuit (300b) may be positioned on one side of the second driving circuit (300a).

[0047] The first driving circuit (300a) and the second driving circuit (300b) may include a shift register (510), a latch circuit (520), a level shift circuit (530), a digital-to-analog conversion circuit (540), and an output buffer circuit (550) as shown in FIG. 5, in order to output a data voltage corresponding to the image data to the data lines (DL_1, DL_2), respectively.

[0048] The shift register circuit (510) is composed of a plurality of shift registers (not shown). Each shift register included in the shift register circuit (510) generates a sampling signal by sequentially shifting a source start pulse (SSP) using a source sampling clock (SSC) and inputs the sampling signal to a latch circuit (520).

[0049] The latch circuit (520) latches image data in a predetermined unit in response to a sampling signal and outputs it to a level shifter circuit (530). To this end, the latch circuit (520) may include a first latch circuit (not shown) and a second latch circuit (not shown). The first latch circuit may be composed of a plurality of sampling latches (not shown). The plurality of sampling latches included in the first latch circuit sample image data input serially in synchronization with the sampling signal input from the shift register circuit (510) connected to each sampling latch.

[0050] The second latch circuit may be composed of a plurality of holding latches (not shown). The holding latches included in the second latch circuit latch the video data output from the first latch circuit for each channel and output it to the level shifter circuit (530).

[0051] The level shifter circuit (530) may include a plurality of level shifters (not shown). Each level shifter included in the level shifter circuit (530) shifts the voltage level of the image data output from the second latch circuit to a predetermined voltage level.

[0052] The digital-to-analog conversion circuit (540) converts the video data for each channel, with the voltage level shifted, into an analog data voltage using a reference gamma voltage generated by a gamma voltage generation circuit (not shown).

[0053] The output buffer circuit (550) is composed of a plurality of output buffers (not shown). Each output buffer included in the output buffer circuit (550) buffers the data voltage for each channel converted by the digital-to-analog conversion circuit (540) and outputs it to the multiplexer circuit (310).

[0054] Referring again to FIG. 4, the first multiplexer circuit (310a) outputs a data voltage, which is output through an output buffer circuit (550) included in the first driving circuit (300a), to a subpixel (SP) of the display panel (110) through a first data line (DL_1). In one embodiment, the first multiplexer circuit (310a) may be composed of a plurality of switching elements (not shown), and the first data line (DL_1) to which the data voltage is to be output can be selected by controlling the switching elements.

[0055] The second multiplexer circuit (310b) outputs a data voltage, which is output through the output buffer circuit (550) included in the second driving circuit (300b), to a subpixel (SP) of the display panel (110) through the second data line (DL_2). In one embodiment, the second multiplexer circuit (310b) may be composed of a plurality of switching elements (not shown), and the second data line (DL_2) to which the data voltage is to be output can be selected by controlling the switching elements.

[0056] The first routing metal (320a) electrically connects the first multiplex circuit (310a) to the first pad (330a), and the second routing metal (320b) connects the second multiplex circuit (310b) to the second pad (330b). Since the first multiplex circuit (310a) is positioned close to the first pad (330a) and the second multiplex circuit (310b) is positioned far from the second pad (330b), the first routing metal (320a) that electrically connects the first multiplex circuit (310a) and the first pad (330a) is formed to have a shorter length than the second routing metal (320b) that electrically connects the second multiplex circuit (310b) and the second pad (330b).

[0057] Accordingly, since the first routing metal (320a) and the second routing metal (320b) have different lengths, the first resistance value of the first routing metal (320a) and the second resistance value of the second routing metal (320b) are also bound to be different. Additionally, since the length of the second routing metal (320b) is longer than the length of the first routing metal (320a), the second resistance value of the second routing metal (320b) is bound to be greater than the first resistance value of the first routing metal (320a).

[0058] Accordingly, the source drive direct circuit (SDIC) according to the present invention includes a first resistance deviation compensation circuit (340a) connected to the first routing metal (320a) and a second resistance deviation compensation circuit (340b) connected to the second routing metal (320b) to improve the resistance deviation between the first routing metal (320a) and the second routing metal (320b) having different lengths.

[0059] The first resistance deviation compensation circuit (340a) is connected to the first routing metal (320a) and is formed to have a first compensation resistance value.

[0060] The second resistance deviation compensation circuit (340b) is connected to the second routing metal (320b) and is formed to have a second compensation resistance value.

[0061] At this time, the first compensation resistance value and the second compensation resistance value are determined such that the first channel resistance value, which is the sum of the first compensation resistance value and the first resistance value of the first routing metal (320a), becomes equal to the second channel resistance value, which is the sum of the second compensation resistance value and the second resistance value of the second routing metal (320b).

[0062] In one embodiment, the first resistance deviation compensation circuit (340a) may be implemented with a first resistor having a first compensation resistance value, and the second resistance deviation compensation circuit (340b) may be implemented with a second resistor having a second compensation resistance value. At this time, the first compensation resistance value and the second compensation resistance value may be defined by the following mathematical formula 1.

[0063]

[0064] In mathematical formula 1, Rsp represents the resistivity of the first and second resistors, Rsp_LengthN represents the length of the Nth resistor, and Rsp_Width represents the width of the first and second resistors. Since the first and second resistors are formed from the same material and have the same width, Rsp and Rsp_Width have the same value.

[0065] Meanwhile, the first resistance value of the first routing metal (320a) and the second resistance value of the second routing metal (320b) can be defined by the following mathematical formula 2.

[0066]

[0067] In Equation 2, Rsm represents the resistivity of the first routing metal (320a) and the second routing metal (320b), Rsm_LengthN represents the length of the Nth routing metal, and Rsm_Width represents the width of the first routing metal (320a) and the second routing metal (320b). Since the first routing metal (320a) and the second routing metal (320b) are formed from the same material and have the same width, Rsm and Rsm_Width have the same value.

[0068] At this time, since the first routing metal (320a) and the second routing metal (320b) have different lengths, the first resistance value of the first routing metal (320a) and the second resistance value of the second routing metal (320b) have different values.

[0069] As described above, the resistance value of the first channel is determined according to the following mathematical formula 3, and the resistance value of the second channel can be determined according to the following mathematical formula 4.

[0070]

[0071]

[0072] As described above, the first channel resistance value and the second channel resistance value must be identical to each other, and since the first resistance value of the first routing metal (320a) and the second resistance value of the second routing metal (320b) are different from each other, the first compensation resistance value and the second compensation resistance value must inevitably be different. For example, if the first resistance value of the first routing metal (320a) is smaller than the second resistance value of the second routing metal (320b), the first compensation resistance value may be set to be larger than the second compensation resistance value.

[0073] According to the present invention, in order to improve the resistance difference between a first routing metal (320a) and a second routing metal (320b) formed to have different lengths, the first routing metal (320a) and the second routing metal (320b) are not made to have the same length, but the lengths of the first routing metal (320a) and the second routing metal (320b) are maintained as they are, and a first resistance difference compensation circuit (340a) having a first compensation resistance value is added to the first routing metal (320a) and a second resistance difference compensation circuit (340b) having a second compensation resistance value different from the first compensation resistance value is added to the second routing metal (320b) so that the total resistance value (i.e., channel resistance value) of the first routing metal (320a) and the second routing metal (320b) can be the same.

[0074] As described above, according to the present invention, by adding a resistance deviation compensation circuit (340), the resistance deviation caused by the difference in length between routing metals (320) can be eliminated, thereby reducing the delay or distortion of the driving signal.

[0075] In addition, according to the present invention, since there is no need to increase the length of the routing metal (320) to improve the resistance deviation of each routing metal (320), there is an effect of reducing the chip size of the source drive integrated circuit (SDIC).

[0076] In addition, as in conventional methods, when the length of the routing metal must be increased to improve resistance variation, the routing metal (320b) must be formed by penetrating multiple stacked layers to secure the length of the routing metal. However, according to the present invention, since there is no need to increase the length of the routing metal to improve resistance variation, the routing metal (320) can be formed using only the metal on the same layer among the multiple stacked layers (e.g., the top metal), thereby increasing the freedom of chip design.

[0077] Meanwhile, the source drive direct circuit (SIDC) according to the present invention may further include a first ESD diode (410a) connected to a first routing metal (320a) as shown in FIG. 4, and may further include a second ESD diode (410b) connected to a second routing metal (320b). In this embodiment, the first resistor constituting the first resistance deviation compensation circuit (340a) and the second resistor constituting the second resistance deviation compensation circuit (340b) may perform the function of an ESD resistor together. At this time, the first resistor and the second resistor may be configured to include the same resistance value corresponding to the ESD resistor.

[0078] The first ESD diode (410a) is configured to be connected to a high potential driving voltage (VDD) or a low potential driving voltage (VSS), respectively, at a location between the first resistance deviation compensation circuit (340a) and the pad (330a). The first ESD diode (410a) is a circuit element that prevents overcurrent from flowing into the chip from the outside. When a surge current is applied from outside the chip, the surge current flows out through the first ESD diode (410a), which has a relatively lower resistance compared to the first resistance deviation compensation circuit (340a), thereby protecting the internal components of the chip.

[0079] The second ESD diode (410b) is configured to be connected to a high potential driving voltage (VDD) or a low potential driving voltage (VSS) at a location between the second resistance deviation compensation circuit (340b) and the pad (330b). The second ESD diode (410b) is a circuit element that prevents overcurrent from flowing into the chip from the outside. When a surge current is applied from outside the chip, the surge current flows out through the second ESD diode (410b), which has a relatively lower resistance compared to the second resistance deviation compensation circuit (340b), thereby protecting the internal components of the chip.

[0080] In the above-described embodiment, the first resistance deviation compensation circuit (340a) and the second resistance deviation compensation circuit (340b) are described as performing the function of an ESD resistor together; however, in other embodiments, the source drive integrated circuit (SDIC) may additionally include a separate ESD resistor for each channel. In this case, the ESD resistors included in each channel may have the same resistance value.

[0081] Meanwhile, in the above-described embodiment, the channel driving circuit (CDC) was described as a data voltage output circuit (400). In another embodiment, the channel driving circuit (CDC) may be a sensing circuit. That is, one driving circuit (300) and one multiplexer circuit (310) shown in FIG. 3 are electrically connected to each other to form one sensing circuit. According to this embodiment, the source drive direct circuit (SDIC) may include a plurality of data voltage output circuits (400) and a plurality of sensing circuits.

[0082] Hereinafter, with reference to FIG. 6, the configuration of the source drive direct circuit when the channel driving circuit (CDC) is a sensing circuit will be described in detail. FIG. 6 is a diagram showing the connection between a subpixel of an organic light-emitting diode display panel (110) and a sensing circuit.

[0083] Referring to FIG. 6, the subpixel (SP) may include a driving transistor (DRT), a switching transistor (SWT), a sensing transistor (SENT), a storage capacitor (Cst), and an organic light-emitting diode (ED). A data voltage output circuit (400) is connected to the subpixel (SP) via a data line (DL), and a sensing circuit (600) is connected to the subpixel (SP) via a reference line (RVL).

[0084] The driving transistor (DRT) includes a first node (N1), a second node (N2), and a third node (N3). The first node (N1) of the driving transistor (DRT) may be a gate node to which a data voltage (Vdata) is applied from a data voltage output circuit (400) through a data line (DL) when the switching transistor (SWT) is turned on. The second node (N2) of the driving transistor (DRT) may be electrically connected to the anode electrode of an organic light-emitting diode (ED) and may be a source node or a drain node. The third node (N3) of the driving transistor (DRT) may be electrically connected to a driving voltage line (DVL) to which a driving voltage (EVDD) is applied and may be a drain node or a source node.

[0085] At this time, during the display driving period, the driving voltage (EVDD) required to display the image can be supplied through the driving voltage line (DVL).

[0086] The switching transistor (SWT) is electrically connected between the first node (N1) of the driving transistor (DRT) and the data line (DL), and the gate line (GL) is connected to the gate node and operates according to the scan signal (SCAN) supplied through the gate line (GL). In addition, when the switching transistor (SWT) is turned on, the operation of the driving transistor (DRT) is controlled by transmitting the data voltage (Vdata) supplied through the data line (DL) to the gate node of the driving transistor (DRT).

[0087] The sensing transistor (SENT) is electrically connected between the second node (N2) of the driving transistor (DRT) and the reference line (RVL), and the gate line (GL) is connected to the gate node and operates according to the sense signal (SENSE) supplied through the gate line (GL). When the sensing transistor (SENT) is turned on, the sensing reference voltage (VSEN) supplied through the reference line (RVL) is delivered to the second node (N2) of the driving transistor (DRT).

[0088] That is, by controlling the switching transistor (SWT) and the sensing transistor (SENT), the voltage at the first node (N1) and the voltage at the second node (N2) of the driving transistor (DRT) are controlled, thereby enabling the supply of current to drive the organic light-emitting diode (ED).

[0089] The gate nodes of the switching transistor (SWT) and the sensing transistor (SENT) may be connected together to a single gate line (GL) or to different gate lines (GL). Figure 6 shows an example of a structure in which the switching transistor (SWT) and the sensing transistor (SENT) are connected to different gate lines (GL). In this case, the switching transistor (SWT) and the sensing transistor (SENT) can be controlled independently by the scan signal (SCAN) and the sense signal (SENSE) transmitted through the different gate lines (GL).

[0090] On the other hand, when the switching transistor (SWT) and the sensing transistor (SENT) are connected to a single gate line (GL), the switching transistor (SWT) and the sensing transistor (SENT) can be controlled simultaneously by a scan signal (SCAN) or sense signal (SENSE) transmitted through the single gate line (GL), and the aperture ratio of the subpixel (SP) can be increased.

[0091] Meanwhile, the transistors placed in the subpixel (SP) can be composed of not only n-type transistors but also p-type transistors, and Figure 6 shows an example of a case composed of n-type transistors.

[0092] The storage capacitor (Cst) is electrically connected between the first node (N1) and the second node (N2) of the driving transistor (DRT) and maintains the data voltage (Vdata) for one frame.

[0093] These storage capacitors (Cst) may be connected between the first node (N1) and the third node (N3) of the driving transistor (DRT) depending on the type of driving transistor (DRT). The anode electrode of the organic light-emitting diode (ED) may be electrically connected to the second node (N2) of the driving transistor (DRT), and a base voltage (EVSS) may be applied to the cathode electrode of the organic light-emitting diode (ED).

[0094] Here, the base voltage (EVSS) may be a ground voltage or a voltage higher or lower than the ground voltage. Additionally, the base voltage (EVSS) may vary depending on the driving state, for example, the base voltage (EVSS) at the time of display driving and the base voltage (EVSS) at the time of sensing driving may be set differently from each other.

[0095] The structure of the subpixel (SP) described above as an example is a 3T (Transistor) 1C (Capacitor) structure, which is merely an example for illustrative purposes and may include one or more additional transistors, or, in some cases, one or more additional capacitors. Each of the multiple subpixels (SP) may be formed to have the same structure, and some of the multiple subpixels (SP) may be formed to have different structures.

[0096] The sensing circuit (600) may use a method of measuring the current flowing due to the voltage charged in the storage capacitor (Cst) during the characteristic value sensing period of the driving transistor (DRT) to sense the characteristic value of the driving transistor (DRT), for example, threshold voltage or mobility, which is called current sensing.

[0097] That is, the sensing circuit (600) can detect the characteristic value of the driving transistor (DRT) or a change in the characteristic value by measuring the current flowing due to the voltage charged in the storage capacitor (Cst) during the characteristic value sensing period of the driving transistor (DRT).

[0098] In this case, the reference line (RVL) not only serves to transmit the reference voltage (VSEN) for sensing but also acts as a sensing line to sense the characteristic value of the driving transistor (DRT) within the subpixel (SP); therefore, the reference line (RVL) can also be referred to as a sensing line.

[0099] Hereinafter, with further reference to FIG. 7, an embodiment in which the channel driving circuit (CDC) is a sensing circuit (600) will be described in more detail. FIG. 7 is a diagram showing the configuration of a source drive direct circuit when the channel driving circuit is a sensing circuit. Since the configuration and driving method of each sensing circuit (600) are identical to one another, for the convenience of explanation, the configuration and operation of the source drive direct circuit (SDIC) will be described below based on the first sensing circuit (600a) and the second sensing circuit (600b).

[0100] The first sensing circuit (600a) is connected to the first reference line (RVL_1) to supply a reference voltage (VSEN) for sensing to the first reference line (RVL_1) and senses the voltage of the first reference line (RVL_1). When the first sensing circuit (600a) generates sensing data (Sdata) corresponding to the sensed voltage and transmits it to the timing controller (140), the timing controller (140) can compare the data received from the first sensing circuit (600a) with a previously stored reference value to compensate for the deviation of the characteristic value of the driving transistor (DRT) of the subpixel to which the first sensing circuit (600a) is connected.

[0101] The second sensing circuit (600b) is connected to the second reference line (RVL_2) to supply a reference voltage (VSEN) for sensing to the second reference line (RVL_2) and senses the voltage of the second reference line (RVL_2). When the second sensing circuit (600b) generates sensing data (Sdata) corresponding to the sensed voltage and transmits it to the timing controller (140), the timing controller (140) can compare the data received from the second sensing circuit (600b) with a previously stored reference value to compensate for the deviation of the characteristic value of the driving transistor (DRT) of the subpixel to which the second sensing circuit (600b) is connected.

[0102] According to this embodiment, the characteristic value or change in the characteristic value of the driving transistor (DRT) may be reflected in the second node (N2) voltage of the driving transistor (DRT) as shown in FIG. 6 (e.g., Vdata - Vth). The second node (N2) voltage of the driving transistor (DRT) may correspond to the voltage of the reference line (RVL) shown in FIG. 6 when the sensing transistor (SENT) is in a turned-on state. Additionally, the line capacitor (Cline) of the reference line (RVL) shown in FIG. 6 may be charged by the second node (N2) voltage of the driving transistor (DRT), and the reference line (RVL) may have a voltage corresponding to the second node (N2) voltage of the driving transistor (DRT) by the sensing voltage (Vsen) charged in the line capacitor (Cline).

[0103] In one embodiment, the section in which the first sensing circuit (600a) and the second sensing circuit (600b) sense characteristic values ​​(threshold voltage and mobility) of the driving transistor (DRT) may proceed after the generation of a power-on signal and before the display driving starts, after the generation of a power-off signal of the display device (100), or in real time during the display driving.

[0104] To perform the sensing function as described above, as illustrated in FIG. 7, the first sensing circuit (600a) may include a first driving circuit (700a) and a first multiplexer circuit (710a), and the second sensing circuit (600b) may include a second driving circuit (700b) and a second multiplexer circuit (710b). Additionally, the first driving circuit (700a) may include a first reference voltage application node (605a) and a first analog-to-digital conversion circuit (607a), and the second driving circuit (700b) may include a second reference voltage application node (605b) and a second analog-to-digital conversion circuit (607b).

[0105] The first reference voltage application node (605a) applies a sensing reference voltage (VSEN) to the first reference line (RVL_1) to sense the characteristic value of a subpixel connected to the first reference line (RVL_1).

[0106] The first analog-to-digital conversion circuit (607a) receives a sensing voltage sensed from a subpixel through the first reference line (RVL_1) and converts it into sensing data in a digital form. That is, the first analog-to-digital conversion circuit (607a) measures the voltage of the first reference line (RVL_1) corresponding to the voltage of the second node (N2) of the driving transistor (DRT) and converts it into a digital value.

[0107] The first multiplexer circuit (710a) selectively connects the first reference voltage application node (605a) and the first analog-to-digital conversion circuit (607a) to the first reference line (RVL). To this end, the first multiplexer circuit (710a) may include at least one position circuit (not shown) for sensing characteristic values.

[0108] More specifically, the first multiplexer circuit (710a) may include a first sensing reference switch (not shown) that controls the connection between the first reference line (RVL_1) and the first reference voltage application node (605a), and a first sampling switch (not shown) that controls the connection between the first reference line (RVL_1) and the first analog-to-digital conversion circuit (607a). Here, the first sensing reference switch is a switch that controls the characteristic value sensing drive, and the sensing reference voltage (VSEN) is supplied to the first reference line (RVL_1) by the first sensing reference switch.

[0109] Meanwhile, the first reference switch for sensing may also perform the function of a reference switch for display driving. In this case, the first reference switch for sensing may supply a reference voltage for display driving having the same voltage value as the reference voltage for sensing (VSEN), or supply a reference voltage for display driving having a different voltage value from the reference voltage for sensing (VSEN).

[0110] The second reference voltage application node (605b) applies a sensing reference voltage (VSEN) to the second reference line (RVL_2) to sense the characteristic value of the driving transistor of the subpixel connected to the second reference line (RVL_2).

[0111] The second analog-to-digital conversion circuit (607b) receives a sensing voltage sensed from a subpixel through the second reference line (RVL_2) and converts it into sensing data in a digital form. That is, the second analog-to-digital conversion circuit (607b) measures the voltage of the second reference line (RVL_2) corresponding to the voltage of the second node (N2) of the driving transistor (DRT) and converts it into a digital value.

[0112] The second multiplexer circuit (710b) optionally connects the second reference voltage application node (605b) and the second analog-to-digital conversion circuit (607b) to the second reference line (RVL_2). To this end, the second multiplexer circuit (710b) may include at least one position circuit (not shown) for sensing characteristic values.

[0113] More specifically, the second multiplexer circuit (710b) may include a second sensing reference switch (not shown) that controls the connection between the second reference line (RVL_2) and the second reference voltage application node (605b), and a second sampling switch (not shown) that controls the connection between the second reference line (RVL_2) and the second analog-to-digital conversion circuit (607b). Here, the second sensing reference switch is a switch that controls the characteristic value sensing drive, and the sensing reference voltage (VSEN) is supplied to the second reference line (RVL_2) by the second sensing reference switch.

[0114] Meanwhile, the second sensing reference switch may also perform the function of a display driving reference switch. In this case, the second sensing reference switch may supply a display driving reference voltage having the same voltage value as the sensing reference voltage (VSEN), or supply a display driving reference voltage having a different voltage value from the sensing reference voltage (VSEN).

[0115] The first routing metal (620a) electrically connects the first multiplex circuit (710a) to the first pad (630a), and the second routing metal (620b) connects the second multiplex circuit (710b) to the second pad (630b). Since the first multiplex circuit (710a) is positioned close to the first pad (630a) and the second multiplex circuit (710b) is positioned far from the second pad (630b), the first routing metal (620a) that electrically connects the first multiplex circuit (710a) and the first pad (630a) is formed to have a shorter length than the second routing metal (620b) that electrically connects the second multiplex circuit (710b) and the second pad (630b).

[0116] Since the first routing metal (620a) and the second routing metal (620b) have different lengths, the first resistance value of the first routing metal (620a) and the second resistance value of the second routing metal (620b) are also bound to be different. Additionally, because the length of the second routing metal (620b) is longer than the length of the first routing metal (620a), the second resistance value of the second routing metal (620b) is bound to be greater than the first resistance value of the first routing metal (620a).

[0117] Accordingly, the present invention includes a first resistance deviation compensation circuit (640a) connected to the first routing metal (620a) and a second resistance deviation compensation circuit (640b) connected to the second routing metal (620b) to improve the resistance deviation between the first routing metal (620a) and the second routing metal (620b) having different lengths.

[0118] The first resistance deviation compensation circuit (640a) is connected to the first routing metal (620a) and is formed to have a first compensation resistance value. The second resistance deviation compensation circuit (640b) is connected to the second routing metal (620b) and is formed to have a second compensation resistance value.

[0119] The first resistance deviation compensation circuit (640a) and the second resistance deviation compensation circuit (640b) are identical to the first resistance deviation compensation circuit (340a) and the second resistance deviation compensation circuit (340b) shown in FIG. 4, so a detailed description is omitted.

[0120] Meanwhile, a source drive direct circuit (SDIC) according to another embodiment of the present invention may further include a first ESD diode (650a) connected to a first routing metal (620a) as shown in FIG. 7, and a second ESD diode (650b) connected to a second routing metal (620b). Since the first ESD diode (650a) and the second ESD diode (650b) are identical to the first ESD diode (610a) and the second ESD diode (610b) shown in FIG. 4, a detailed description is omitted.

[0121] Referring again to FIG. 1, the timing controller (140) supplies control signals to the gate driving circuit (120) and the data driving circuit (130) and controls the operation of the gate driving circuit (120) and the data driving circuit (130). That is, the timing controller (140) controls the gate driving circuit (120) to output a scan signal according to the timing implemented in each frame, and by transmitting image data (DATA) received from the outside to the data driving circuit (130), controls the data driving circuit (130) to output a data voltage corresponding to the image data (DATA) to the data line (EL).

[0122] At this time, the timing controller (140) can receive timing signals including a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a data enable signal (Data Enable; DE), a main clock (MCLK), etc., along with video data (DATA) from an external host system (200).

[0123] The host system (200) can be any one of a TV (Television) system, a set-top box, a navigation system, a personal computer (PC), a home theater system, a mobile device, or a wearable device.

[0124] Accordingly, the timing controller (140) generates a control signal using a timing signal received from the host system (200) and transmits it to the gate driving circuit (120) and the data driving circuit (130).

[0125] For example, the timing controller (140) outputs a gate control signal to the gate driving circuit (120), including a gate start pulse (GSP), a gate clock (GCLK), and a gate output enable signal (GOE), in order to control the gate driving circuit (120).

[0126] Here, the gate start pulse (GSP) controls the timing at least one gate drive integrated circuit (GDIC) constituting the gate drive circuit (120) to start operation. Additionally, the gate clock (GCLK) is a clock signal commonly input to at least one gate drive integrated circuit (GDIC) and controls the shift timing of the scan signal. Additionally, the gate output enable signal (GOE) specifies the timing information of at least one gate drive integrated circuit (GDIC).

[0127] Additionally, the timing controller (140) outputs a data control signal to the data driving circuit (130), including a Source Start Pulse (SSP), a Source Sampling Clock (SCLK), and a Source Output Enable Signal (SOE), in order to control the data driving circuit (130). Here, the Source Start Pulse (SSP) controls the timing at least one source drive integrated circuit (SDIC) constituting the data driving circuit (130) to start data sampling. The Source Sampling Clock (SCLK) is a clock signal that controls the timing of data sampling by at least one source drive integrated circuit (SDIC). The Source Output Enable Signal (SOE) controls the output timing of at least one source drive integrated circuit (SDIC).

[0128] Additionally, the timing controller (140) can compensate for deviations in the characteristic values ​​of the driving transistors of the subpixels to which the sensing circuit (600) is connected by comparing the sensing data received from the sensing circuit (600) with a previously stored reference value.

[0129] The above-described display device (100) may further include a Power Management Integrated Circuit (PMIC) that supplies various voltages or currents to a display panel (110), a gate driving circuit (120), a data driving circuit (130), etc., or controls various voltages or currents to be supplied.

[0130] Those skilled in the art to which the present invention pertains will understand that the above-described invention may be implemented in other specific forms without altering its technical concept or essential features.

[0131] Therefore, the embodiments described above should be understood as illustrative in all respects and not limiting. The scope of the invention is defined by the claims set forth below rather than by the detailed description above, and all modifications or variations derived from the meaning and scope of the claims and equivalent concepts thereof should be interpreted as being included within the scope of the invention. Explanation of the symbols

[0132] 100: Display device 110: Display panel 120: Gate driving circuit 130: Data driving circuit 140: Timing Controller 300: Driving circuit 310: Mux circuit CDC: Channel Driving Circuit 320: Routing Metal 330: Pad 340: Resistance deviation compensation circuit 400: Data voltage output circuit 600: Sensing circuit

Claims

Claim 1 A source drive direct circuit comprising: a first routing metal connecting a first channel driving circuit and a first pad; a second routing metal connecting a second channel driving circuit and a second pad and having a different length from the first routing metal; a first resistance deviation compensation circuit connected to the first routing metal and having a first compensation resistance value; and a second resistance deviation compensation circuit connected to the second routing metal and having a second compensation resistance value different from the first compensation resistance value, wherein the first channel resistance value obtained by summing the first resistance value of the first routing metal and the first compensation resistance value is the same as the second channel resistance value obtained by summing the second resistance value of the second routing metal and the second compensation resistance value. Claim 2 In claim 1, the first channel driving circuit and the second channel driving circuit are source drive direct circuits that are data voltage output circuits that supply a data voltage corresponding to image data to at least one data line. Claim 3 In claim 1, the first channel driving circuit and the second channel driving circuit each comprise: a shift register circuit that generates a sampling signal by sequentially shifting a source start pulse transmitted from a timing controller according to a source sampling clock; a latch circuit that sequentially samples and latches image data output from the timing controller in a predetermined unit in response to the sampling signal output from the shift register circuit; a digital-to-analog conversion circuit that converts the image data sampled by the latch circuit into an analog data voltage; an output buffer circuit that buffers the data voltage output from the digital-to-analog conversion circuit; and a multiplexer circuit that selectively outputs the data voltage buffered by the output buffer circuit to one of a plurality of data lines. Claim 4 A source drive direct circuit according to claim 1, further comprising a first ESD diode and a second ESD diode for preventing overcurrent inflow, wherein the first resistance deviation compensation circuit is connected between the first channel driving circuit and the first ESD diode, and the second resistance deviation compensation circuit is connected between the second channel driving circuit and the second ESD diode. Claim 5 In claim 1, the first resistance deviation compensation circuit and the second resistance deviation compensation circuit further include an ESD resistor having the same resistance value in a source drive direct circuit. Claim 6 In claim 1, the source drive direct circuit is formed using a metal on the same layer among a plurality of stacked layers, wherein the first routing metal and the second routing metal are the same layer. Claim 7 In claim 1, the source drive direct circuit drives an organic light-emitting diode display panel comprising a plurality of subpixels in which organic light-emitting diodes are arranged, and the source drive direct circuit is a sensing circuit that senses the characteristics of the plurality of subpixels included in the organic light-emitting diode display panel. Claim 8 In claim 7, the first channel driving circuit and the second channel driving circuit each comprise: a reference voltage application node that applies a sensing reference voltage for characteristic sensing of the subpixel to a reference line connected to the subpixel; an analog-to-digital conversion circuit that receives a sensing voltage sensed from the subpixel through the reference line and converts it into sensing data in a digital form; and a source drive direct circuit comprising a multiplexer circuit that selectively connects the reference voltage application node and the analog-to-digital conversion circuit to the reference line. Claim 9 A display device comprising: a display panel; a source drive direct circuit for driving the display panel, wherein the source drive direct circuit includes: a first routing metal connecting a first channel driving circuit and a first pad; a second routing metal connecting a second channel driving circuit and a second pad and having a different length from the first routing metal; a first resistance deviation compensation circuit connected to the first routing metal and having a first compensation resistance value; and a second resistance deviation compensation circuit connected to the second routing metal and having a second compensation resistance value different from the first compensation resistance value, wherein the first channel resistance value obtained by summing the first resistance value of the first routing metal and the first compensation resistance value is the same as the second channel resistance value obtained by summing the second resistance value of the second routing metal and the second compensation resistance value. Claim 10 In claim 9, the first channel driving circuit and the second channel driving circuit are a display device that is a data voltage output circuit supplying a data voltage corresponding to image data to a corresponding data line. Claim 11 In claim 9, the display panel is an organic light-emitting diode display panel comprising a plurality of subpixels in which organic light-emitting diodes are arranged, and the first channel driving circuit and the second channel driving circuit are sensing circuits that sense the characteristics of the plurality of subpixels included in the organic light-emitting diode display panel. Claim 12 In claim 9, the display device is formed using a metal on the same layer among a plurality of stacked layers, wherein the first routing metal and the second routing metal are the same layer.

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