Diode structures of stacked transistors and mehtods of manufacturing the same

Abstract

The technical concept of the present invention provides a three-dimensional transistor structure and a method for manufacturing the same, comprising: a first stacked transistor structure including a first lower source / drain region and a first upper source / drain region stacked with an insulating layer between the first lower source / drain region and the first upper source / drain region, wherein the first lower source / drain region has a first conductivity type and the first upper source / drain region has a second conductivity type opposite to the first conductivity type; a first contact connected to the first upper source / drain region; a second contact connected to the first lower source / drain region; and a shared contact connecting the first upper source / drain region and the first lower source / drain region.

Description

Technology Field

[0001] This application claims priority in the United States. Provisional application No. 63 / 770,490 was filed with the United States Patent and Trademark Office on March 12, 2025, and disclosures therein are incorporated by reference throughout this specification. Background Technology

[0002] The size of transistors in integrated circuit devices has continuously decreased due to the downscaling of logic devices. Technologies are continuously being developed to increase transistor density, concentrate more transistors within the same area, and improve transistor performance. For example, as transistor density increases, gate extensions that do not touch or connect to the gate contacts can become a factor affecting the generation of parasitic capacitance. In FinFETs, it can be difficult to reduce gate extensions without affecting the channel width. However, in Gate-All-Around (GAA) devices where the channels are vertically stacked, parasitic capacitance can be reduced or minimized without significantly reducing the channel width. Therefore, three-dimensional (3D) device structures and related fabrication processes are being considered.

[0003] Stacked transistors can be included as a type of three-dimensional device structure. Integrated circuit devices can use stacked transistors to increase density and improve performance. In some cases, stacked transistors can be complementary to each other (e.g., CMOS (complementary metal-oxide-semiconductor) transistors). For example, a CFET (complementary-FET) layout may include multiple pairs of vertically stacked gate-all-around field-effect transistors (GAAFETs), where a P-type GAAFET is at one level and an N-type GAAFET is at another level (i.e., above or below), and a shared gate can serve to extend and surround the channel patterns between the stacked pairs of N-type and P-type GAAFETs. In such a structure, the source / drain regions of the lower GAAFET may be electrically isolated from the source / drain regions of the upper GAAFET by a dielectric layer. The gates, channel patterns, and insulation structures may differ in dimensions between the upper and lower devices of the stacked transistors. The problem to be solved

[0004] The problem that the present invention aims to solve is to provide a three-dimensional transistor structure with improved electrical reliability and a method for manufacturing the same. means of solving the problem

[0005] The present invention provides a three-dimensional transistor structure comprising: a first stacked transistor structure comprising a first lower source / drain region and a first upper source / drain region stacked with an insulating layer between the first lower source / drain region and the first upper source / drain region, wherein the first lower source / drain region has a first conductivity type and the first upper source / drain region has a second conductivity type opposite to the first conductivity type; a first contact connected to the first upper source / drain region; a second contact connected to the first lower source / drain region; and a shared contact connecting the first upper source / drain region and the first lower source / drain region.

[0006] According to some embodiments, the shared contact may penetrate the first upper source / drain region and contact the first lower source / drain region.

[0007] According to some embodiments, the shared contact comprises a metal, and the first contact and the second contact may each be an anode contact and a cathode contact of a semiconductor-metal-semiconductor (SMS) diode.

[0008] According to some embodiments, the shared contact may not include a metal silicide.

[0009] According to some embodiments, the shared contact comprises a semiconductor material, and the first contact and the second contact may be the positive and negative contacts of a PIN diode.

[0010] According to some embodiments, the semiconductor material may include undoped silicon (intrinsic silicon).

[0011] According to some embodiments, the semiconductor material may include doped silicon.

[0012] According to some embodiments, the shared contact is a first shared contact, and further comprises a second stacked transistor structure including a second upper source / drain region stacked on the first lower source / drain region and having the second conductivity type; a second shared contact connecting the second upper source / drain region and the first lower source / drain region; and a third contact connected to the second upper source / drain region; wherein the first contact, the second contact, and the third contact may each be an emitter contact, a base contact, and a collector contact of a bipolar junction transistor.

[0013] According to some embodiments, the apparatus further comprises a substrate disposed below the first lower source / drain region, wherein the first lower source / drain region is positioned between the substrate and the first upper source / drain region; and the second contact may penetrate the substrate and be connected to the first lower source / drain region.

[0014] According to some embodiments, the substrate may include a bulk semiconductor substrate, an insulating substrate, and at least one selected from these.

[0015] According to some embodiments, the upper surface of the shared contact may be coplanar with the upper surface of the first contact and the upper surface of the second contact.

[0016] The present invention provides a three-dimensional transistor structure comprising: at least one lower source / drain region having a first conductivity type; an upper source / drain region including a first upper source / drain region and a second upper source / drain region stacked on the at least one lower source / drain region and having a second conductivity type opposite to the first conductivity type; a first shared contact connecting the first upper source / drain region and the at least one lower source / drain region; a second shared contact connecting the second upper source / drain region and the at least one lower source / drain region; a first collector contact and a first emitter contact connected to the first upper source / drain region; a second collector contact and a second emitter contact connected to the second upper source / drain region; and a base contact connected to the at least one lower source / drain region.

[0017] According to some embodiments, the first shared contact and the second shared contact may each penetrate the first upper source / drain region and the second upper source / drain region to contact the at least one lower source / drain region.

[0018] According to some embodiments, the first shared contact and the second shared contact may include metal.

[0019] According to some embodiments, the first shared contact and the second shared contact may include any one selected from a doped semiconductor material, an undoped semiconductor material, and a combination thereof.

[0020] According to some embodiments, the apparatus further comprises a substrate disposed below the at least one lower source / drain region, wherein the at least one lower source / drain region is disposed such that it is located between the substrate and the first upper source / drain region; and the base contact may penetrate the substrate and be connected to the at least one lower source / drain region.

[0021] The present invention provides a method for manufacturing a three-dimensional transistor structure comprising: forming a preliminary transistor structure on a substrate; removing a portion of the preliminary transistor structure to form an upper transistor structure disposed apart from at least one lower transistor structure; forming at least one lower source / drain region having a first conductivity type on the at least one lower transistor structure; forming an upper source / drain region of the upper transistor structure on the at least one lower source / drain region with an interlayer insulating layer in between, wherein the upper source / drain region has a second conductivity type opposite to the first conductivity type; and forming a shared contact connecting the upper source / drain region to the at least one lower source / drain region.

[0022] According to some embodiments, the step of forming the shared contact may include: forming a contact opening penetrating the upper source / drain region and the interlayer insulation layer; and filling the contact opening with the shared contact.

[0023] According to some embodiments, the step of forming the shared contact may be to fill the contact opening with a metallic material.

[0024] According to some embodiments, the step of forming the shared contact may be to fill the contact opening with a semiconductor material.

[0025] According to some embodiments, the semiconductor material may be an undoped silicon material.

[0026] According to some embodiments, the semiconductor material may be a doped silicon material.

[0027] According to some embodiments, the method may further include the step of forming a first contact on the upper source / drain region; and the step of forming a second contact on the at least one lower source / drain region.

[0028] According to some embodiments, the step of forming the first contact and the second contact may include: forming an insulating layer in the upper source / drain region and the at least one lower source / drain region; forming an opening in the insulating layer that exposes the upper source / drain region and the at least one lower source / drain region; and forming the first contact and the second contact in the opening.

[0029] According to some embodiments, the upper surface of the shared contact may be positioned in the same plane as the upper surface of the first contact.

[0030] According to some embodiments, the step of forming the second contact may include: forming an opening in the substrate that exposes the at least one lower source / drain region; and filling the opening with the second contact.

[0031] According to some embodiments, the substrate is a semiconductor substrate, and the method may further include the step of removing the semiconductor substrate after forming the first contact and the second contact; and the step of forming an insulating substrate on the at least one lower source / drain region. Effects of the invention

[0032] According to the present invention, a three-dimensional transistor structure with improved electrical reliability and stability can be manufactured. Brief explanation of the drawing

[0033] FIGS. 1a, FIGS. 1b, FIGS. 1c and FIGS. 1d are schematic cross-sectional views illustrating exemplary three-dimensional transistor structures including an integrated diode structure having a front contact on a bulk substrate according to some embodiments of the present disclosure. FIG. 2 is a schematic cross-sectional view illustrating an exemplary three-dimensional transistor structure including a front contact and an integrated diode structure without a bulk substrate according to some embodiments of the present disclosure. FIG. 3 is a schematic cross-sectional view illustrating an exemplary three-dimensional transistor structure including an integrated diode structure having front contacts and rear contacts through a bulk substrate according to some embodiments of the present disclosure. FIG. 4 is a schematic cross-sectional view illustrating an exemplary three-dimensional transistor structure including an integrated diode structure comprising a front contact and a rear contact through an insulating substrate according to some embodiments of the present disclosure. FIGS. 5A, FIGS. 5B, FIGS. 5C, FIGS. 5D, FIGS. 5E, FIGS. 5F, FIGS. 5G, FIGS. 5H, FIGS. 5I, FIGS. 5J, and FIGS. 5K are schematic cross-sectional views illustrating a method for manufacturing a three-dimensional transistor structure including an integrated diode structure according to some embodiments of the present disclosure. FIG. 6 is a flowchart illustrating a method for manufacturing a three-dimensional transistor structure including an integrated diode structure according to some embodiments of the present disclosure. FIG. 7 is a schematic cross-sectional view showing an exemplary three-dimensional transistor structure according to some embodiments of the present disclosure. Specific details for implementing the invention

[0034] Exemplary embodiments are described with reference to the accompanying drawings, which may include schematic cross-sectional views of idealized embodiments (and intermediate structures). The relative sizes of layers and regions may be exaggerated for clarity. Additionally, variations in the form of resulting illustrations are expected, such as manufacturing techniques and / or tolerances. In various embodiments, the same reference number may be used to refer to identical or similar elements, and may be followed by a dash (e.g., '-1', '-2', etc.). One or more decimal symbols (') may indicate specific variations of identical or similar elements.

[0035] In the embodiments described herein, the stacked transistor structure may include a first transistor and a second transistor. The first transistor may be a first type of transistor (e.g., an n-type metal oxide semiconductor (NMOS) transistor), and the second transistor may be a second type of transistor (e.g., a p-type metal oxide semiconductor (PMOS) transistor). The first type of transistor and the second type of transistor may be complementary to each other (e.g., a CMOS transistor), and in some implementations, the stacked transistor structure may be a stack of CMOS transistors or may include one. The first and second transistors may be stacked in any order (e.g., the first transistor is on top of the second transistor or the second transistor is on top of the first transistor), and as a result, a stack may be created comprising an upper device (also referred to as an upper device or upper transistor with respect to the base substrate) and a lower device (also referred to as a lower device or lower transistor with respect to the base substrate).

[0036] FIG. 7 is a schematic cross-sectional view illustrating an exemplary three-dimensional transistor structure (700) according to some embodiments of the present disclosure. As illustrated in FIG. 7, the integrated circuit device comprises a stacked transistor structure (102) comprising upper and lower transistors (102L, 102U) stacked vertically on a substrate (101). The lower transistor (102L) comprises at least one lower channel pattern (106L) between conductive gates (104). The upper transistor (102U) comprises at least one upper channel pattern (106U) between gates (104). In the example of FIG. 7, a plurality of upper channel patterns (106U) are stacked on a plurality of lower channel patterns (106L), and gates (104) are alternately stacked between channel patterns (106L, 106U) (collectively referred to as 106; also referred to herein as channel regions (106)). However, embodiments of the present disclosure may include fewer or more channel patterns than illustrated. The channel region (106) may be provided by a semiconductor material such as silicon (Si). The stacked transistor structure (102) may include an internal spacer (105) formed of an insulating or dielectric material, e.g., SiOCN or other low-dielectric material, and additional semiconductor (e.g., Si) and insulating (e.g., SiN, SiO) layers stacked on the channel region (106).

[0037] The lower source / drain region (108L) of the lower transistor (102L) is provided on the opposite side (or also referred to as the opposite end) of the lower channel pattern (106L), and the upper source / drain region (108U) of the upper transistor (102U) may be provided on the opposite side or end of the second channel pattern (106U). The lower source / drain region (108L) may be electrically isolated from the upper source / drain region (108U) by one or more interlayer insulating layers (109). An internal spacer (105) (e.g., silicon nitride pattern, also referred to as an internal spacer) may be provided on the opposite side of the gate (104) pattern to electrically isolate the gate (104) pattern from the source / drain region (108L, 108U) (total 108). In some embodiments, the lower source / drain region (108L) may comprise the same material or material composition as the lower channel pattern (106L) and / or the substrate (101). For example, the lower channel pattern (106L) and the lower source / drain region (108L) may be implemented with silicon layers. In some embodiments, the upper source / drain region (108U) may comprise a different material or composition from the lower source / drain region (108L). For example, the upper source / drain region (108U) may be implemented with silicon germanium (SiGe) layers.

[0038] In the example of FIG. 7, the lower transistor (102L) and the upper transistor (102U) have complementary conductivity types to provide a CMOS device. In particular, the lower transistor (102L) may have a first conductivity type (e.g., n-type), and the upper transistor (102U) may have a second conductivity type (e.g., p-type) opposite to the first conductivity type, and vice versa. That is, the stacked transistor structure (102) according to the embodiment of the present disclosure is not limited to a specific orientation of transistors having different conductivity types. Additionally, in some implementations, the lower transistor (102L) and the upper transistor (102U) may have the same conductivity type (for example, both the lower transistor (102L) and the upper transistor (102U) may be n-type, or both the lower transistor (102L) and the upper transistor (102U) may be p-type). Additionally, when describing with reference to the lower transistor (102L) and the upper transistor (102U), it will be understood that the stacked transistor structure (102) according to the embodiment of the present disclosure is not limited to an array of two transistors and may include additional transistors (e.g., a third transistor, a fourth transistor, etc.), and that the additional transistors are stacked vertically on the substrate (101).

[0039] That is, each lower transistor (102L) and upper transistor (102U) may include a transistor structure having one or more channel regions (106) (e.g., nanosheet channel regions) extending between source / drain regions (108). The gate (104), channel region (106), source / drain region (108), and internal spacers (105) of the upper and lower transistors (102U, 102L) may likewise be referred to by the terms “upper” and “lower” (e.g., upper / lower gate, upper / lower channel region, upper / lower source / drain region, upper / lower internal spacer). Exemplary stacked transistor structures may include a 3D stacked field-effect transistor (3DSFET) in CMOS configuration, a FIN transistor, a multibridge-channel field-effect transistor (MBCFET) in CMOS configuration, and a bulkless MBCFET that includes a limited shallow trench isolation (STI) region without including a bulk silicon substrate.

[0040] In some embodiments, the bulkless MBCFET may include a backside power distribution network (BSPDN) structure in which power rails can be formed on the back side rather than the front side of the semiconductor device. Thus, the power rails may be on one side of the semiconductor structure opposite to the active components of the semiconductor device (e.g., a stacked transistor such as an MBCFET) (e.g., the substrate side of the semiconductor device). Additionally, the conductive structure for data signals may be on the front side of the semiconductor device, and thus the BSPDN and the conductive structure for data signals may be on opposite sides of the semiconductor device. The BSPDN structure can improve power rail efficiency, voltage drop (i.e., IR drop), high power supply performance, and further expansion of standard cell height.

[0041] Some embodiments of the present disclosure may arise from recognizing that the electrical, performance, and / or operational characteristics of an integrated circuit device including a stacked transistor structure may be improved, which may mean, for example, that the implementation of a back-side power transmission network (BSPDN) is facilitated. In particular, an integrated circuit device (e.g., a single chip) may include a diode structure such as a bipolar junction transistor (BJT) and / or a PN junction diode, as well as a stacked field-effect transistor (FET). For example, a temperature sensing element or an electrostatic discharge element may include a BJT and / or a PN junction diode. In some implementations, the diode structure may be integrated with the stacked transistor structure. For example, the diode structure may include at least two regions having opposite conductivity types, which may be formed on a substrate having a thickness sufficient to arrange regions of opposite conductivity types in the thickness direction of the substrate. However, when implementing a BSPDN with an integrated circuit device including a stacked transistor structure (e.g., 3DSFET), a significant portion of the substrate is thinned, and the remaining portion of the substrate may not be thick enough to form a BJT and / or PN junction diode. Therefore, it may be more difficult to integrate a PNP BJT structure and / or PN diode structure with a BSPDN in a stacked transistor structure (e.g., compared to bulk silicon).

[0042] Embodiments of the present disclosure include three-dimensional transistor structures, which may include some features of a stacked FET structure (e.g., alternately stacked channels and gates), but may or may not operate as field-effect transistors. For example, the three-dimensional transistor structures described herein may include a positive junction transistor structure and / or diode structure in which top and bottom epitaxial structures or layers (e.g., stacked source / drain regions) have opposite polarities (i.e., opposite conductivity types) and come into contact with each other to define respective junction regions. That is, elements of a PN junction diode (e.g., positive region and negative region) and / or elements of a BJT (e.g., emitter, collector, and base) may be formed on a substrate, and a BJT and / or PN junction diode may be formed in an integrated circuit device even when the substrate is thinned to include a BSPDN. In addition, elements of the BJT and / or PN junction diode can be formed simultaneously with elements of the stacked FET (e.g., channel layer and / or source / drain regions) using part of the same manufacturing process. Thus, elements of the BJT and / or PN junction diode can be formed without significantly increasing the number of manufacturing processes.

[0043] Some embodiments of the present disclosure implement a diode structure of a stacked transistor structure by providing a shared contact (e.g., a metal or semiconductor contact plug) between one or more opposite conductivity source / drain regions of the stacked transistor structure. For example, a three-dimensional transistor structure may include a stacked (e.g., vertically superimposed) configuration of transistor structures having lower and upper source / drain regions of opposite conductivity types (e.g., p-type and n-type). The stacked lower source / drain region and the upper source / drain region may each be connected to each other through a shared contact. This structure may differ from the structure of a conventional 3DSFET transistor in which the upper and lower source / drain regions of the stacked transistor structure are electrically isolated.

[0044] In some implementations, the covalent contact may be metal, which allows the upper source / drain region, the covalent metal contact, and the lower source / drain region to provide a three-dimensional transistor structure that functions as a semiconductor-metal-semiconductor (SMS) diode. The SMS diode may include a p-type region, an n-type region, and a metal region that form a Schottky barrier at the metal-semiconductor interface. In the energy band diagram of the SMS diode, the conduction band is closer to the Fermi level due to an excess of free electrons in the n-type region, and the conduction band may be further from the Fermi level in the p-type region due to an excess of holes (or a lack of excess electrons).

[0045] In some implementation examples, the shared contact may be a semiconductor material, such as a doped or undoped (i.e. intentionally undoped) semiconductor layer, to provide a three-dimensional transistor structure in which the upper source / drain region, the shared semiconductor contact, and the lower source / drain region act as a PIN diode. The PIN diode typically includes an undoped intrinsic semiconductor layer sandwiched between a P-type semiconductor region and an N-type semiconductor region. The intrinsic semiconductor layer provides a higher resistance region between the p-type and n-type regions.

[0046] In some embodiments, the 3D transistor structure may include adjacent first and second transistor structures, each comprising first and second upper source / drain regions electrically connected by one or more lower source / drain regions by a shared (metal or semiconductor) contact. Collector contacts and emitter contacts may be provided in the first and second upper source / drain regions, and base contacts may be provided in the lower source / drain regions to provide a three-dimensional transistor structure that functions as a bipolar junction transistor.

[0047] More generally, as described in detail below, the upper and lower source / drain regions of opposite conductivity types in a three-dimensional transistor structure can be connected by covalent (metal or semiconductor) contacts to form a diode structure. Additional contacts (e.g., positive and negative contacts or emitter, base, and collector contacts) can be formed to provide a diode or bipolar junction transistor. That is, the stacked n-type and p-type epitaxial regions of a 3DSFET structure can be connected by covalent contacts to form an SMS diode (where the covalent contacts contain metal), a PIN diode (where the covalent contacts contain a semiconductor such as undoped or doped polysilicon), or a BJT (which may include an SMS or PIN diode).

[0048] FIGS. 1a, FIGS. 1b, FIGS. 1c, and FIGS. 1d are schematic cross-sectional views illustrating exemplary three-dimensional transistor structures (100a, 100b, 100c, 100d), which may include an integrated diode structure having a front contact on a bulk substrate according to some embodiments of the present disclosure. Referring to FIGS. 1a through 1d, the three-dimensional transistor structures (100a, 100b, 100c, 100d) according to some embodiments of the present disclosure include a first stacked transistor structure (102-1) comprising a first lower source / drain region (108L-1) and a first upper source / drain region (108U-1), and may include a liner insulating layer (109L) and an equilateral insulating layer (109N) between them. A first lower source / drain region (108L-1) has a first conductivity type (e.g., n-type), and a first upper source / drain region (108U-1) has a second conductivity type (e.g., p-type) opposite to the first conductivity type. The three-dimensional transistor structure (100a, 100b, 100c, 100d) also includes a second stacked transistor structure (102-2) comprising a second upper source / drain region (108U-2) stacked on the first lower source / drain region (108L-1). The second upper source / drain region (108U-2) has a second conductivity type (e.g., p-type). The first contact (110-1) may be connected to the first upper source / drain region (108U-1), and the second contact (112) may be connected to the first lower source / drain region (108L-1). The third contact (110-2) may be connected to the second upper source / drain region (108U-2). The contacts (110-1, 110-2, 112) may be extended to contact the first upper source / drain region (108U-1), the second upper source / drain region (108U-2), and the first lower source / drain region (108L-1), respectively, through an additional interlayer insulating layer (111) which may include a liner insulating layer (111L) and a non-conformal insulating layer (111N).The front contact (124) can penetrate the additional interlayer insulation layer (111) and contact the contacts (110-1, 110-2, 112).

[0049] The substrate (101) may include semiconductor materials such as group IV semiconductors, group III-V compound semiconductors, or group II-VI compound semiconductors. For example, group IV semiconductors may include silicon (Si), germanium (Ge), or silicon-germanium (SiGe). In some embodiments, the substrate (101) may be a bulk substrate (e.g., silicon wafer), a semiconductor-on-insulator (SOI) substrate, an insulating layer (e.g., a monolithic insulating layer), a bulkless substrate (e.g., 200 in FIG. 2), etc. That is, the substrate (101) may include semiconductor materials such as, for example, Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, and / or InP, and may include, for example, silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride, and / or low-k materials. Here, the low-k material may be a material having a dielectric constant lower than that of silicon oxide. Low-k materials may include, for example, SiCOH, fluorine-doped silicon oxide, organosilicon glass, carbon-doped oxide, porous silicon dioxide, porous organosilicon glass, spin-on organic polymer dielectrics and / or spin-on silicon-based polymer dielectrics. The active region may be defined by a device isolation layer (114) on the substrate (101).

[0050] As illustrated in FIGS. 1A to 1D, the three-dimensional transistor structure (100a, 100b, 100c, 100d) may further include one or more shared contacts (120-1, 120-2 (collectively, contact (120))) connecting an upper source / drain region (108U) and a lower source / drain region (108L), respectively. In particular, the three-dimensional transistor structure (100a, 100b, 100c, 100d) further includes a first shared contact (120-1) connecting a first upper source / drain region (108U-1) and a first lower source / drain region (108L-1), and a second shared contact (120-2) connecting a second upper source / drain region (108U-2) and a first lower source / drain region (108L-1). For example, the shared contact (120-1, 120-2) may pass through the upper source / drain (108U-1, 108U-2) and contact the first lower source / drain region (108L-1). In some embodiments, the upper surface of the shared contact (120) may be substantially coplanar with the upper surface of the first contact (110-1), the second contact (112), and / or the third contact (110-2).

[0051] In some embodiments illustrated in FIG. 1a, the shared contacts (120-1, 120-2) may be formed of a metal material (e.g., cobalt (Co), tungsten (W), ruthenium (Ru) and / or molybdenum (Mo)) connecting the upper source / drain regions (108U-1, 108U-2) to the first lower source / drain region (108L-1). The shared contacts (120-1, 120-2) of the three-dimensional transistor structure (100a) provide a semiconductor-metal-semiconductor (SMS) junction between the first upper source / drain region (108U-1) and the first lower source / drain region (108L-1), and between the second upper source / drain region (108U-2) and the first lower source / drain region (108L-1). The SMS joint may each include a P-type region (108U-1 or 108U-2), an N-type region (108U-1), and a covalent contact (120-1 or 120-2) forming a Schottky barrier between them. The covalent contact (120-1, 120-2) may be formed after one or more annealing or other high-temperature processes, thereby ensuring that the covalent contact (120-1, 120-2) does not contain silicides of the metal material.

[0052] In some embodiments illustrated in FIG. 1b, the shared contacts (120-1', 120-2') (collectively 120') may be formed of an undoped (i.e., intentionally undoped) semiconductor material (e.g., undoped polysilicon) connecting the upper source / drain regions (108U-1, 108U-2) to the first lower source / drain region (108L-1). In some embodiments illustrated in FIG. 1C, the shared contacts (120-1", 120-2") (collectively 120") may be formed of a doped semiconductor material (e.g., doped polysilicon) connecting the upper source / drain regions (108U-1, 108U-2) to the first lower source / drain region (108L-1). The shared contacts (120′, 120'′) of the three-dimensional transistor structure (100b, 100c) provide PIN junctions between the first upper source / drain region (108U-1) and the first lower source / drain region (108L-1), and between the second upper source / drain region (108U-2) and the first lower source / drain region (108L-1). The upper source / drain region (108U), the shared contacts (120', 120"), and the lower source / drain The region (108L) provides a three-dimensional transistor structure that operates as a PIN diode. The PIN junction includes a P-type region (108U-1 or 108U-2), an N-type region (108L-1), and a shared contact (120' or 120") of a semiconductor region that provides a high-resistance region between the P-type region (108U-1 or 108U-2) and the N-type region (108L-1).

[0053] In some embodiments illustrated in FIG. 1d, the three-dimensional transistor structure (100d) may include several stacked transistor structures (102) adjacent to each other (e.g., in the Y direction), and several upper source / drain regions (108U) of adjacent stacked transistor structures (102) are electrically connected to each other, and several lower source / drain regions (108L) of adjacent stacked transistor structures (102) are electrically connected to each other. Shared contacts (120-1, 120-2) may connect one or more of the upper source / drain regions (108U) to one or more of the lower source / drain regions (108L) to provide an SMS junction if the shared contact (120) is a metal, or a PIN junction if the shared contact (120) is a doped or undoped semiconductor material. One of the upper source / drain regions (108U) and / or the channel structure may be removed or omitted so that a base contact (112) is provided in one of the lower source / drain regions (108L).

[0054] FIGS. 1a through 1d illustrate the incorporation of a bipolar junction transistor (BJT) structure into an exemplary three-dimensional transistor structure (100a, 100b, 100c, 100d) by connecting the upper source / drain regions (108U-1, 108U-2) of adjacent first and second transistor structures to one or more lower source / drain regions (108L-1) by means of respective shared contacts (120-1, 120-2). The first contact (110-1), the second contact (112), and the third contact (110-2) may each provide the emitter, base, and collector contacts of the positive junction transistor. That is, the first collector / emitter contact (110-1) is connected to the first upper source / drain region (108U-1), the second collector / emitter contact (110-2) is connected to the second upper source / drain region (108U-2), and the base contact (112) is connected to at least one lower source / drain region (108L) to provide a three-dimensional transistor structure that acts as a BJT.

[0055] However, in some embodiments, each source / drain region (108U or 108L) may include a respective contact (110 or 112), and it will be understood that this may provide an integrated diode structure in which the first contact (110) provides a positive contact and the second contact (112) provides a negative contact of the diode structure. In some embodiments, the shared contact (120) is formed of metal, and the first contact (110) and the second contact (112) provide the positive and negative contacts of the semiconductor-metal-semiconductor diode, respectively. That is, the upper source / drain region (108U) of the second conductivity type, the shared contact (120), and the lower source / drain region (108U) of the first conductivity type provide a three-dimensional transistor structure that functions as a semiconductor-metal-semiconductor (SMS) diode. In some embodiments, the shared contact (120) is formed of a semiconductor material, and the first contact (110) and the second contact (112) each provide the positive and negative contacts of the PIN diode. That is, the upper source / drain region (108U) of the second conductivity type, the shared contact (120), and the lower source / drain region (108U) of the first conductivity type provide a three-dimensional transistor structure that functions as a PIN diode. In other words, while the present specification describes primarily in relation to integrating a BJT structure into an exemplary three-dimensional transistor structure (100a, 100b, 100c, 100d), it will be understood that a component SMS or PIN diode structure may be implemented alternatively.

[0056] FIG. 2 is a schematic cross-sectional view illustrating an exemplary three-dimensional transistor structure (200) including a front contact and an integrated diode structure without a bulk substrate according to some embodiments of the present disclosure. As shown in FIG. 2, the three-dimensional transistor structure (200) includes at least one lower source / drain region (108L-1) of a first conductivity type and an upper source / drain region (108U) of a second conductivity type opposite to the first conductivity type, stacked on at least one lower source / drain region (108L-1). The upper source / drain region (108U) includes a first upper source / drain region (108U-1) and a second upper source / drain region (108U-2). The first contact (110-1) can be connected to the first upper source / drain region (108U-1), the second contact (112) can be connected to the lower source / drain region (108L-1), and the third contact (110-2) can be connected to the second upper source / drain region (108U-2). The front contact (124) can penetrate the additional interlayer insulation layer (111) and contact the contacts (110-1, 110-2, 112). The first shared contact (120-1) connects the first upper source / drain region (108U-1) to at least one lower source / drain region (108L-1), and the second shared contact (120-2) connects the second upper source / drain region (108U-2) to at least one lower source / drain region (108L-1). The shared contacts (120-1, 120-2) may be formed of a metal or semiconductor material and may each provide an SMS or PIN diode structure or provide a BJT including a diode structure.

[0057] Therefore, since the three-dimensional transistor structure (200) of FIG. 2 may be similar to the three-dimensional transistor structures (100a, 100b, 100c) of FIG. 1a to 1c, repetitive descriptions of similar elements may be omitted. However, unlike the three-dimensional transistor structures (100a, 100b, 100c) of FIG. 1a to 1c, the substrate (101) is omitted in the three-dimensional transistor structure (200), so that the three-dimensional transistor structure (200) may be free from the basic bulk substrate (i.e., "bulkless" implementation) (201). Additionally, although it is exemplified as having a covalent contact (120) formed of a metal material similar to the three-dimensional transistor structure (100a) of FIG. 1a, the covalent contact (120) of FIG. 2 may be formed of a semiconductor material, which may be undoped (similar to the three-dimensional transistor structure (100b) of FIG. 1b) or doped (similar to the three-dimensional transistor structure (100c) of FIG. 1c).

[0058] FIG. 3 is a schematic cross-sectional view illustrating an exemplary three-dimensional transistor structure (300) comprising an integrated diode structure having front contacts and rear contacts through a bulk substrate according to some embodiments of the present disclosure. As shown in FIG. 3, the three-dimensional transistor structure (300) comprises at least one lower source / drain region (108L-1) of a first conductivity type and an upper source / drain region (108U) of a second conductivity type opposite to the first conductivity type, stacked on at least one lower source / drain region (108L-1). The upper source / drain region (108U) comprises a first upper source / drain region (108U-1) and a second upper source / drain region (108U-2). A first contact (110-1) may be connected to a first upper source / drain region (108U-1), a second contact (112) may be connected to a lower source / drain region (108L-1), and a third contact (110-2) may be connected to a second upper source / drain region (108U-2). A first shared contact (120-1) connects the first upper source / drain region (108U-1) to at least one lower source / drain region (108L-1), and a second shared contact (120-2) connects the second upper source / drain region (108U-2) to at least one lower source / drain region (108L-1). The shared contacts (120-1, 120-2) may be formed of a metal or semiconductor material and may each provide an SMS or PIN diode structure or provide a BJT including a diode structure. The three-dimensional transistor structure (300) may further include a bulk semiconductor substrate (101) having a first lower source / drain region (108L-1) between the substrate (101) and the first upper source / drain region (108U-1).

[0059] Since the three-dimensional transistor structure (300) of FIG. 3 may be similar to the three-dimensional transistor structures (100a, 100b, 100c) of FIG. 1a to 1c, a repetitive description of similar elements may be omitted. However, unlike the three-dimensional transistor structures (100a, 100b, 100c) of FIG. 1a to 1c, the second contact (112) may penetrate the bulk substrate (101) and contact the first lower source / drain region (108L-1) in the three-dimensional transistor structure (300) of FIG. 3 (also referred to as the rear contact). The front contact (124) may penetrate the additional interlayer insulating layer (111) and contact the first and third contacts (110-1, 110-2), and one or more rear contacts (126) may contact the second contact (112). In some implementations, the second contact (112) can electrically connect an SMS or PIN diode structure (or a BJT including a diode structure) to a rear power distribution network (BSPDN).

[0060] FIG. 4 is a schematic cross-sectional view illustrating an exemplary three-dimensional transistor structure (400) comprising an integrated diode structure having front contacts and rear contacts through an insulating substrate according to some embodiments of the present disclosure. As illustrated in FIG. 4, the three-dimensional transistor structure (400) may include at least one lower source / drain region (108L-1) of a first conductivity type and an upper source / drain region (108U) of a second conductivity type opposite to the first conductivity type, stacked on at least one lower source / drain region (108L-1). The upper source / drain region (108U) includes a first upper source / drain region (108U-1) and a second upper source / drain region (108U-2). A first contact (110-1) may be connected to a first upper source / drain region (108U-1), a second contact (112) may be connected to a lower source / drain region (108L-1), and a third contact (110-2) may be connected to a second upper source / drain region (108U-2). A first shared contact (120-1) connects the first upper source / drain region (108U-1) to at least one lower source / drain region (108L-1), and a second shared contact (120-2) connects the second upper source / drain region (108U-2) to at least one lower source / drain region (108L-1). The shared contacts (120-1, 120-2) may be formed of a metal or semiconductor material and may each provide an SMS or PIN diode structure or provide a BJT including a diode structure.

[0061] The three-dimensional transistor structure (400) of FIG. 4 may be similar to the three-dimensional transistor structures (100a, 100b, 100c) of FIG. 1a to 1c, so a repetitive description of similar elements may be omitted. However, unlike the three-dimensional transistor structures (100a, 100b, 100c) of FIG. 1A to 1C, the bulk substrate (101) is removed, and the three-dimensional transistor structure (400) may additionally include an insulating substrate (101'). The second contact (112) may be a rear contact penetrating the insulating substrate (101') to contact the first lower source / drain region (108L-1) in the three-dimensional transistor structure (400) of FIG. 4. The front contact (124) can penetrate the additional interlayer insulation layer (111) to contact the first and third contacts (110-1, 110-2), and one or more rear contacts (126) can contact the second contact (112). In some embodiments, the second contact (112) can electrically connect an SMS or PIN diode structure (or a BJT including a diode structure) to the BSPDN.

[0062] That is, the three-dimensional transistor structures (300, 400) of FIGS. 3 and 4 each include a bulk substrate (101) and an insulating substrate (101'), and a base contact (112) can penetrate the bulk substrate (101) or the insulating substrate (101') to contact at least one lower source / drain region (108L). Embodiments of the present disclosure provide a diode structure on the base substrate, thereby integrating the diode structure and / or BJT structure into the 3D transistor structure to provide a BSPDN structure even if the base substrate is thinned or removed. Additionally, although it is exemplified as having a covalent contact (120) formed of a metal material similar to the three-dimensional transistor structure (100a) of FIG. 1A, the covalent contact (120) of FIG. 3 and FIG. 4 may be formed of a semiconductor material, which may be undoped (similar to the three-dimensional transistor structure (100b) of FIG. 1B) or doped (similar to the three-dimensional transistor structure (100c) of FIG. 1C).

[0063] FIGS. 5a, 5b, 5c, 5d, 5e, 5f, 5g, 5h, 5i, 5j, and 5k are schematic cross-sectional views illustrating a method for manufacturing a 3D transistor structure including an integrated diode structure according to some embodiments of the present disclosure. FIGS. 5a through 5c are cross-sectional views along the YY line of FIG. 7, and FIGS. 5d through 5k may be cross-sectional views along the Y'-Y' line of FIG. 7. FIG. 6 is a flowchart illustrating a method for manufacturing a three-dimensional transistor structure including an integrated diode structure according to some embodiments of the present disclosure.

[0064] Referring to FIG. 5a and FIG. 6, a method for manufacturing a three-dimensional transistor structure comprises forming a preliminary transistor structure (500) on a substrate (101) (S605). The preliminary transistor structure comprises a plurality of channel regions (106) and gate sacrificial layers (104') alternately stacked on the substrate (101). An intermediate sacrificial layer (103) may be provided between each stack of channel regions (106) and gate sacrificial layers (104').

[0065] As shown in FIGS. 5b and FIGS. 6, a portion of the preliminary transistor structure (500) may be removed to form a three-dimensional transistor structure (100). The three-dimensional transistor structure (100) may include one or more lower transistors (102L) and upper transistors (102U) spaced apart from each other (e.g., in the Y direction) (S610). Each of the upper transistors (102U) and lower transistors (102L) may include some features of a stacked FET structure, but may or may not operate as a field-effect transistor.

[0066] As illustrated in FIG. 5c, a device isolation layer (114) may be formed on the substrate (101) to form, for example, a shallow trench isolation (STI) region. The STI region may combine or define the active region of each transistor structure and / or diode structure described herein, for example, in the Y direction. FIG. 5d is a cross-sectional view along the line Y'-Y' (separated in the X direction from the cross-sectional view of FIG. 5c, as illustrated in FIG. 7). It may show the X-direction boundary of the upper transistor (102U) and the lower transistor (102L).

[0067] As illustrated in FIGS. 5e and FIGS. 6, one or more lower source / drain regions (108L) may be formed in at least one lower transistor (102L) (S615). The lower source / drain region (108L) may have a first conductivity type (e.g., n-type). For example, the lower source / drain region (108L) may be formed as a single or single epitaxial region formed on the side or end face of the channel region (106) of the lower stacked transistor structure (102-1) (i.e., formed by epitaxial growth). In some embodiments, the lower source / drain region (108L) may be formed as a unit implantation region formed on the side face of the channel region (106) of the lower transistor structure (102L) (i.e., by ion implantation).

[0068] As illustrated in FIGS. 5e and 5f, one or more interlayer insulating layers (109) may be formed in the lower source / drain region (108L). For example, the interlayer insulating layer (109) may include a liner insulating layer (109L) extending equilaterally along the upper surface and side of the lower source / drain region (108L) and a non-equilateral insulating layer (109N) on top of the liner insulating layer.

[0069] As illustrated in FIG. 5g and FIG. 6, an upper source / drain region (108U) of an upper transistor (102U) is formed in one or more lower source / drain regions (108L) (S620). The upper source / drain region (108U) may have a second conductivity type opposite to the first conductivity type. For example, the upper source / drain region (108U) may be formed as respective epitaxial regions on the side of the channel region (106) of the upper transistor (102U) (i.e., formed by epitaxial growth). In some embodiments, the upper source / drain region (108U) may be formed as respective implanted regions on the side of the channel region (106) of the upper transistor (102U) (i.e., formed by ion implantation).

[0070] As illustrated in FIG. 5h, an additional interlayer insulating layer (111) may be formed in the upper source / drain region (108U). For example, the additional interlayer insulating layer (111) may include a liner insulating layer (111L) extending equilaterally along the upper surface and side of the upper source / drain region (108U) and a non-equilateral insulating layer (111N) on top of the liner insulating layer.

[0071] As illustrated in FIGS. 5i, 5j, 5k and 6, a shared contact (120) is formed to connect an upper source / drain region (108U) to one or more lower source / drain regions (108L) (S625). In particular, as illustrated in FIG. 5I, a contact opening (120op) may be formed to penetrate the upper source / drain region (108U) and the interlayer insulation layer (109). As illustrated in FIGS. 5j and 5k, the shared contact (120) may be provided at the contact opening (120op). In some embodiments, as illustrated in FIG. 5j, the shared contact (120) may be formed by providing one or more metal layers at the contact opening (120op). The shared contact (120) may be formed after one or more annealing or other high-temperature processes without silicide in the metal layer. In some embodiments, as shown in FIG. 5k, the covalent contact (120', 120") may be formed by providing one or more semiconductor layers at the contact opening (120op). The semiconductor layer(s) may be undoped (intrinsic) silicon as shown in FIG. 5k and FIG. 1b, or may be doped silicon (e.g., P, N, As, Ga, etc.) (as shown in FIG. 1C).

[0072] As illustrated in FIGS. 1a to 1c, FIGS. 2, and FIGS. 6, the method may further include the step (S635) of forming a first contact (110-1, 110-2) in each upper source / drain region (108U) and forming a second contact (112) in one or more lower source / drain regions (108L). For example, forming the first contact (110-1, 110-2) and the second contact (112) may include forming an opening in an additional interlayer insulating layer (111) that exposes the upper source / drain region (108U) and the lower source / drain region (108L), respectively, and forming the first contact (110-1, 110-2) and the second contact (112) in the opening. In some embodiments, the upper surface of the shared contact (120) may be substantially coplanar with the upper surface of the first contact (110-1, 110-2) and the second contact (112).

[0073] Alternatively, as illustrated in FIGS. 3 and 4, the second contact (112) may be formed as a rear contact (e.g., for BSPDN). For example, as illustrated in FIGS. 3 and 6, forming the second contact (112) (S635) may include forming an opening in the substrate (101) that exposes the lower source / drain region (108L) and forming the second contact (112) in the opening. As another example, as illustrated in FIGS. 4 and 6, the semiconductor substrate (101) can be removed after forming the first contact (110-1, 110-2), the insulating substrate (101') can be formed in the lower source / drain region (108L), the insulating substrate (101') can have an opening formed that exposes the lower source / drain region (108L), and the second contact (112) can be formed in the opening.

[0074] According to the embodiments described herein, a three-dimensional transistor structure including an integrated diode structure having shared contacts may be formed on a bulk substrate (in some embodiments, this may be removed or replaced with an insulating substrate). The transistor may include base, collector, and emitter regions located on a first surface of the bulk substrate and shared contacts (metal or semiconductor) located on a first surface of the bulk substrate, and may electrically connect the respective opposite-direction conductivity source / drain regions to form an SMS or PIN diode structure. The elements of the diode structure (e.g., SMS or PIN junctions) may be formed simultaneously with the elements of a stacked field-effect transistor (e.g., channel layer and / or source / drain regions) using the same manufacturing process, and each contact may be formed on a first surface and / or a second surface of the bulk substrate to provide a BJT (or diode including positive and negative terminals) including collector / emitter and base terminals, and this may also be the case even when the base substrate is removed or thinned to provide a back-side power distribution network structure. That is, one or more source / drain regions of the 3DSFET structure can form the emitter, base, and collector regions of a BJT (or PN junction of a diode).

[0075] Unless otherwise defined, all terms used in this document have the same meaning as generally understood by a person skilled in the art. Furthermore, all terms should be interpreted in a meaning consistent with their meaning in the context of the relevant technology and this disclosure, and should not be interpreted in an idealized or overly formal sense unless explicitly defined herein. For example, as mentioned herein, an "insulating layer" or liner may comprise a dielectric material (which may be polarized by an applied electric field).

[0076] In the above description, each embodiment is described with reference to a specific region of conductivity type. It will be understood that in each of the above embodiments, a conductive device of the opposite direction can be formed by simply reversing the conductivity of the n-type and p-type layers. Therefore, it will be understood that the present disclosure includes both n-channel and p-channel devices for each different device structure.

[0077] The terms used herein are intended to describe specific embodiments only and are not intended to limit the embodiments. Singular expressions may include plural forms unless the context clearly indicates otherwise. The terms “composition” and / or “inclusion” specify the presence of the stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof.

[0078] Throughout this specification, terms such as “first,” “second,” etc. are used to describe various elements, but it will be understood that these elements should not be limited by these terms. These terms may be used only to distinguish one element from another. For example, a first element may be called a second element, and likewise, a second element may be called a first element without departing from the scope of this disclosure. The term “and / or” includes all combinations of one or more of the related list items.

[0079] When an element, such as a layer, region, or substrate, is considered to be "on" or "extending over" another element, it can be understood that it may be directly on or directly extending over another element, and that intermediate elements may also exist. In contrast, when an element is said to be "directly on" or "extending directly over" another element, there may be no intervening elements. Furthermore, when an element is referred to as being "connected" or "coupled" to another element, it can be understood that it may be directly connected or coupled to another element, or that intervening elements may exist. In contrast, when an element is said to be "directly connected" or "directly coupled" to another element, there are no intervening elements. As described herein, "connected" elements may be physically and / or electrically connected.

[0080] Spatially relative terms such as "below," "above," "lower," "upper," "subordinate," or "superior" may be used to describe the relationship between an element, layer, or region based on a reference frame (e.g., a substrate) and another element, layer, or region. It will be understood that these terms are intended to include various orientations of the device in addition to the orientations depicted in the figure.

[0081] Various forms and implementations are possible without departing from the teachings of this disclosure. Accordingly, the disclosure should not be interpreted as being limited to the exemplary embodiments specified in this document. Therefore, it will be understood by those skilled in the art that various forms and changes in details may be made without departing from the technical spirit and scope defined herein.

[0082] Embodiments of the present invention are also described with reference to the manufacturing operation and flowchart diagrams. It will be understood that the steps indicated in the manufacturing operation and flowchart diagrams do not necessarily need to be performed in the order indicated.

[0083] The subject matter disclosed above is to be considered illustrative and not limiting, and the appended claims are to include all modifications, improvements, and other embodiments falling within the scope of disclosure. Accordingly, the scope is determined by the broadest interpretation of the following claims and corresponding claims to the maximum extent permitted by law, and is not or is not limited by the foregoing detailed description.

Claims

Claim 1 A three-dimensional transistor structure comprising: a first stacked transistor structure including a first lower source / drain region and a first upper source / drain region stacked with an insulating layer between the first lower source / drain region and the first upper source / drain region, wherein the first lower source / drain region has a first conductivity type and the first upper source / drain region has a second conductivity type opposite to the first conductivity type; a first contact connected to the first upper source / drain region; a second contact connected to the first lower source / drain region; and a shared contact connecting the first upper source / drain region and the first lower source / drain region. Claim 2 In claim 1, the shared contact is a three-dimensional transistor structure that penetrates the first upper source / drain region and contacts the first lower source / drain region. Claim 3 A three-dimensional transistor structure according to claim 1, wherein the shared contact comprises a metal, and the first contact and the second contact are the anode contact and the cathode contact of a semiconductor-metal-semiconductor (SMS) diode, respectively. Claim 4 In paragraph 3, the shared contact is a three-dimensional transistor structure that does not include metal silicide. Claim 5 In claim 1, the shared contact comprises a semiconductor material, and the first contact and the second contact are a positive contact and a negative contact of a PIN diode, respectively, in a three-dimensional transistor structure. Claim 6 In claim 5, the semiconductor material is a three-dimensional transistor structure comprising undoped silicon (intrinsic silicon). Claim 7 In claim 5, the semiconductor material is a three-dimensional transistor structure comprising doped silicon. Claim 8 The three-dimensional transistor structure according to claim 1, wherein the shared contact is a first shared contact and includes a second stacked transistor structure comprising a second upper source / drain region stacked on the first lower source / drain region and having the second conductivity type; a second shared contact connecting the second upper source / drain region and the first lower source / drain region; and a third contact connected to the second upper source / drain region; wherein the first contact, the second contact, and the third contact are each an emitter contact, a base contact, and a collector contact of a bipolar junction transistor. Claim 9 A three-dimensional transistor structure according to claim 1, further comprising: a substrate disposed below the first lower source / drain region, wherein the first lower source / drain region is positioned between the substrate and the first upper source / drain region; and wherein the second contact penetrates the substrate and is connected to the first lower source / drain region. Claim 10 In claim 9, the substrate comprises a bulk semiconductor substrate, an insulating substrate, and at least one selected from these, forming a three-dimensional transistor structure. Claim 11 A three-dimensional transistor structure according to claim 1, wherein the upper surface of the shared contact is coplanar with the upper surface of the first contact and the upper surface of the second contact. Claim 12 A three-dimensional transistor structure comprising: at least one lower source / drain region having a first conductivity type; an upper source / drain region including a first upper source / drain region and a second upper source / drain region stacked on the at least one lower source / drain region and having a second conductivity type opposite to the first conductivity type; a first shared contact connecting the first upper source / drain region and the at least one lower source / drain region; a second shared contact connecting the second upper source / drain region and the at least one lower source / drain region; a first collector contact and a first emitter contact connected to the first upper source / drain region; a second collector contact and a second emitter contact connected to the second upper source / drain region; and a base contact connected to the at least one lower source / drain region. Claim 13 In claim 12, the three-dimensional transistor structure wherein the first shared contact and the second shared contact each penetrate the first upper source / drain region and the second upper source / drain region and contact the at least one lower source / drain region. Claim 14 In claim 12, the first shared contact and the second shared contact are three-dimensional transistor structures comprising metal. Claim 15 In claim 12, the first shared contact and the second shared contact comprise a three-dimensional transistor structure selected from a doped semiconductor material, an undoped semiconductor material, and a combination thereof. Claim 16 In claim 12, a substrate disposed below the at least one lower source / drain region, wherein the at least one lower source / drain region is disposed such that it is located between the substrate and the first upper source / drain region; further comprising a three-dimensional transistor structure in which the base contact penetrates the substrate and is connected to the at least one lower source / drain region. Claim 17 A method for manufacturing a three-dimensional transistor structure comprising: forming a preliminary transistor structure on a substrate; removing a portion of the preliminary transistor structure to form an upper transistor structure disposed apart from at least one lower transistor structure; forming at least one lower source / drain region having a first conductivity type on the at least one lower transistor structure; forming an upper source / drain region of the upper transistor structure on the at least one lower source / drain region with an interlayer insulating layer in between, wherein the upper source / drain region has a second conductivity type opposite to the first conductivity type; and forming a shared contact connecting the upper source / drain region to the at least one lower source / drain region. Claim 18 A method for manufacturing a three-dimensional transistor structure according to claim 17, wherein the step of forming the shared contact comprises: forming a contact opening penetrating the upper source / drain region and the interlayer insulating layer; and filling the contact opening with the shared contact. Claim 19 A method for manufacturing a three-dimensional transistor structure, wherein the step of forming the shared contact is to fill the contact opening with a metal material. Claim 20 In claim 18, the step of forming the shared contact is to fill the contact opening with a semiconductor material, a method for manufacturing a three-dimensional transistor structure. Claim 21 A method for manufacturing a three-dimensional transistor structure in which the semiconductor material is an undoped silicon material. Claim 22 In claim 20, the semiconductor material is a doped silicon material, and the method for manufacturing a three-dimensional transistor structure. Claim 23 A method for manufacturing a three-dimensional transistor structure according to claim 18, further comprising: a step of forming a first contact on the upper source / drain region; and a step of forming a second contact on at least one lower source / drain region. Claim 24 A method for manufacturing a three-dimensional transistor structure according to claim 23, wherein the step of forming the first contact and the second contact comprises: forming an insulating layer in the upper source / drain region and the at least one lower source / drain region; forming an opening in the insulating layer that exposes the upper source / drain region and the at least one lower source / drain region; and forming the first contact and the second contact in the opening. Claim 25 A method for manufacturing a three-dimensional transistor structure in which, in claim 24, the upper surface of the shared contact is placed in the same plane as the upper surface of the first contact. Claim 26 A method for manufacturing a three-dimensional transistor structure according to claim 23, wherein the step of forming the second contact comprises: forming an opening in the substrate that exposes the at least one lower source / drain region; and filling the opening with the second contact. Claim 27 A method for manufacturing a three-dimensional transistor structure according to claim 23, wherein the substrate is a semiconductor substrate, and further comprising the steps of: removing the semiconductor substrate after forming the first contact and the second contact; and forming an insulating substrate on the at least one lower source / drain region.

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