Display apparatus

Abstract

The present specification relates to a display device, and more specifically, to a display device capable of blocking light incident on a thin-film transistor by forming a light-blocking layer on a thin-film transistor for driving the display device.

Description

Technology Field

[0001] This specification relates to a display device, and more specifically, to a display device capable of blocking light incident on a thin-film transistor. Background Technology

[0002] Display devices that display images on TVs, monitors, smartphones, tablet PCs, laptops, etc., are used in various methods and forms.

[0003] Among various types of display devices, Liquid Crystal Displays (LCDs) are still in use, and the scope of use and application for Organic Light Emitting Displays (OLEDs) is also rapidly expanding.

[0004] Display devices include a display panel having a plurality of light-emitting elements or liquid crystals for displaying an image, and driving transistors for individually controlling the operation of each light-emitting element or liquid crystal.

[0005] Among these, liquid crystal displays (LCDs) are not self-emissive, so they require a light source such as a backlight that supplies light from the rear. Backlights increase the thickness of the LCD and limit the implementation of displays that can be bent or have various design shapes.

[0006] Organic light-emitting display devices with self-emissive elements can be implemented thinner than display devices that have an embedded light source, and since a separate light source is not required, bendable or display devices of various designs can be implemented.

[0007] In order to drive the light-emitting elements of such an organic light-emitting display device, a pixel driving circuit composed of a plurality of thin-film transistors and capacitors is formed in the display device, and the organic light-emitting display device is driven by applying voltage to the driving elements. The problem to be solved

[0008] Thin-film transistors that drive a display device can easily degrade when exposed to light incident from outside the display device into the display device or light generated by a light-emitting element inside the display device.

[0009] When a thin-film transistor degrades, the threshold voltage value decreases, and as the current or voltage delivered to the light-emitting device through the thin-film transistor fluctuates, the brightness of the light-emitting device may decrease.

[0010] The present specification provides a display device that blocks light incident on a thin-film transistor, thereby preventing a decrease in brightness.

[0011] The present specification provides a display device with improved display quality by applying a uniform common voltage to a plurality of light-emitting elements arranged in the display device.

[0012] The problems to be solved according to the embodiments of this specification are not limited to those mentioned above, and other unmentioned problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0013] A display device according to an embodiment of the present specification may include: a gate line and a data line intersecting the gate line, disposed on a substrate including a display area and a non-display area; a plurality of light-emitting elements disposed on the gate line and the data line, each comprising a first electrode, a light-emitting layer, and a second electrode; and a first thin-film transistor and a second thin-film transistor disposed below the plurality of light-emitting elements.

[0014] In addition, on the first thin-film transistor or the second thin-film transistor, a light-blocking layer may be further included that is disposed on the same layer as the first electrode and overlaps with one or more of the first thin-film transistor and the second thin-film transistor.

[0015] A display device according to another embodiment of the present specification may include: a substrate comprising a display area and a non-display area; a gate line and a data line intersecting the gate line, disposed on the substrate; a plurality of light-emitting elements disposed on the gate line and the data line, each comprising a first electrode, a light-emitting layer, and a second electrode; and a driving transistor and a plurality of switching transistors disposed below the plurality of light-emitting elements.

[0016] In addition, on a driving transistor or a plurality of switching transistors, a light-blocking layer may be further included that is disposed on the same layer as the first electrode and overlaps with one of the plurality of switching transistors.

[0017] Specific details of other embodiments are included in the detailed description and drawings. Effects of the invention

[0018] According to an embodiment of the present specification, light that may be incident on a thin-film transistor can be blocked by a light-blocking layer disposed on the thin-film transistor, thereby preventing degradation of the thin-film transistor and preventing a decrease in brightness of the display device. Accordingly, the display quality of the display device can be improved and reliability can be enhanced.

[0019] In addition, the light-blocking layer is connected to the second electrode of the light-emitting element, so that a common voltage can be applied to the second electrode through the common voltage line and the light-blocking layer. Accordingly, a uniform common voltage can be applied to the entire area of ​​the display device to display uniform brightness and improve display quality.

[0020] The effects of this specification are not limited to those mentioned above, and other unmentioned effects will be clearly understood by those skilled in the art from the description below. Brief explanation of the drawing

[0021] FIG. 1 is a plan view of a display device according to an embodiment of the present specification. FIG. 2 is a circuit diagram showing a pixel driving circuit according to an embodiment of the present specification. FIG. 3 is a waveform diagram of gate signals and voltage of a specific node of a pixel driving circuit according to one embodiment of the present specification. FIG. 4 is a plan view showing a thin-film transistor and a light-shielding layer according to an embodiment of the present specification. FIG. 5 is a plan view showing a thin-film transistor and a light-shielding layer according to another embodiment of the present specification. FIG. 6 is a cross-sectional view along the line I-I' of FIG. 1, and is a cross-sectional view showing a thin-film transistor and a light-shielding layer according to the embodiment of FIG. 4. FIG. 7 is a cross-sectional view along the line I-I' of FIG. 1, and is a cross-sectional view showing a thin-film transistor and a light-shielding layer according to the embodiment of FIG. 5. Specific details for implementing the invention

[0022] Specific details for implementing the present invention will become clear by referring to the embodiments described below together with the drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. The embodiments are provided merely to ensure that the disclosure of this specification is complete and to fully inform those skilled in the art of the scope of the invention, and the claims are not limited to the embodiments of the present invention.

[0023] Shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for describing embodiments of the present invention are exemplary, and therefore the present invention is not limited to the depicted details. Throughout the specification, the same reference numerals refer to the same components. Furthermore, in describing the present invention, if it is determined that a detailed description of related prior art could unnecessarily obscure the gist of the present specification, such detailed description is omitted. Where terms such as "includes," "has," or "is made up" are used in the present specification, other parts may be added unless "only" is used. Where a component is expressed in the singular, it includes cases where it is included in the plural unless specifically stated otherwise.

[0024] In interpreting the components, they are interpreted to include a margin of error even in the absence of a separate explicit statement.

[0025] In the case of describing a positional relationship, for example, when the positional relationship between two parts is described using expressions such as 'on,' 'upper,' 'lower,' or 'next to,' one or more other parts may be located between the two parts unless 'immediately' or 'directly' is used.

[0026] When an element or layer is referred to as "on" another element or layer, it includes cases where another layer or element is placed directly on top of or in between.

[0027] Although terms such as "first," "second," etc. are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the technical scope of this specification.

[0028] Throughout the specification, the same reference numerals refer to the same components.

[0029] The size and thickness of each component shown in the drawings are illustrated for convenience of explanation, and the present invention is not necessarily limited to the size and thickness of the illustrated components.

[0030] The features of each of the various embodiments of this specification may be combined or combined with one another, either partially or wholly, and as will be fully understood by those skilled in the art, various technical interlocking and operation are possible, and each embodiment may be implemented independently of one another or together in an interlocking relationship.

[0031] The display device of this specification may be applied to liquid crystal display devices and organic light-emitting display devices, but is not limited thereto, and may be applied to various display devices such as LED display devices or quantum dot display devices.

[0032] Hereinafter, a display device according to an embodiment of the present specification will be described with reference to the drawings.

[0033] FIG. 1 is a plan view of a display device according to an embodiment of the present specification.

[0034] Referring to FIG. 1, the display device (10) may include elements such as a gate driver (115) and a data driver (117) on a substrate (110). The substrate (110) may be divided into a display area (AA) in which an image is displayed and which includes a light-emitting element, and a non-display area (NA) including the gate driver (115) and the data driver (117).

[0035] The substrate (110) may be made of glass or plastic, or may be made of a semiconductor material such as a silicon wafer.

[0036] The substrate (110) may be formed from a flexible plastic material. For example, the substrate (110) may be formed in a single layer or multilayer form from materials such as PI (Polyimide), PET (polyethylene terephthalate), PEN (polyethylene naphthalate), PC (polycarbonate), PES (polyethersulfone), PAR (polyarylate), PSF (polysulfone), and COC (cyclic-olefin copolymer), but is not limited thereto.

[0037] The display area (AA) may be an area where an image is displayed by arranging a plurality of subpixels (PX). Each of the plurality of subpixels (PX) is an individual unit that emits light, and a light-emitting element and a pixel driving circuit may be arranged in each of the plurality of subpixels (PX). For example, if the display device (10) is an organic light-emitting display device, the light-emitting element may include an organic light-emitting element, and if the display device (10) is a liquid crystal display device, the light-emitting element may include a liquid crystal element. The plurality of subpixels (PX) may include a red subpixel, a green subpixel, a blue subpixel, and / or a white subpixel, but are not limited thereto.

[0038] The non-display area (NA) may be an area where an image is not displayed. Various wiring and driving ICs for driving a plurality of subpixels (PX) placed in the display area (AA) may be placed in the non-display area (NA). For example, at least one of a gate driving unit (115) and a data driving unit (117) may be placed in the non-display area (NA).

[0039] The non-display area (NA) may be an area surrounding the display area (AA). For example, the non-display area (NA) may be an area extending from the display area (AA) and may be an area where multiple subpixels (PX) are not placed. The non-display area (NA), where an image is not displayed, may be a bezel area and may further include a bending area (BA) where the substrate (110) is bent.

[0040] A subpixel (PX) of a display area (AA) may include a thin-film transistor. The thin-film transistor within the display area (AA) may include a polycrystalline semiconductor material and / or an oxide semiconductor material.

[0041] A thin-film transistor may be included in the gate driver (115) of the non-display area (NA). The thin-film transistor within the non-display area (NA) may include a semiconductor layer formed of a polycrystalline semiconductor material.

[0042] The gate driving unit (115) may apply a Gate In Panel (GIP) method in which a gate driving chip is directly mounted on the substrate (110) or a gate driving circuit is formed directly on the substrate (110). The Gate In Panel (GIP) method in which a gate driving circuit is formed directly on the substrate (110) can be formed by configuring a thin-film transistor using a polycrystalline semiconductor material as a semiconductor layer and a thin-film transistor using an oxide semiconductor material as a semiconductor layer as a C-MOS. As a result, the electron mobility in the channel within the thin-film transistor can be increased, thereby enabling the implementation of a display device with high resolution and low power consumption.

[0043] A plurality of data lines (DL) and a plurality of gate lines (GL) may be arranged in a display area (AA). For example, a plurality of data lines (DL) may be arranged in rows or columns, and a plurality of gate lines (GL) may be arranged in columns or rows. Subpixels (PX) may be arranged on the area where a plurality of data lines (DL) and a plurality of gate lines (GL) are arranged in the display panel.

[0044] A gate driver (115) placed in a non-display area (NA) may include a gate driving circuit (or a scan driving circuit). The gate driving circuit sequentially drives each row of subpixels (PX) of a display area (AA) by sequentially supplying scan signals to a plurality of gate lines (GL).

[0045] The gate driving circuit of the gate driving unit (115) may be composed of a thin-film transistor having a polycrystalline semiconductor layer, may be composed of a thin-film transistor having an oxide semiconductor layer, and may be composed including a thin-film transistor having a polycrystalline semiconductor layer and a thin-film transistor having an oxide semiconductor layer.

[0046] The gate driving circuit may include a shift register, a level shifter, etc. The gate driving unit (115) including the gate driving circuit may sequentially supply scan signals of an on voltage or an off voltage to a plurality of gate lines (GL).

[0047] The data driving unit (117) converts image data into an analog data voltage and supplies it to a plurality of data lines (DL) when a specific gate line (GL) is opened by a gate driving unit (115) including a gate driving circuit.

[0048] The display device (10) may include a plurality of scan lines and a plurality of light emission control lines, etc. The plurality of scan lines and the plurality of light emission control lines may be wiring that transmits different types of gate signals (scan signals, light emission control signals) to the gate nodes of different types of thin-film transistors (switching transistors, driving transistors).

[0049] A gate driving unit (115) including a gate driving circuit may include a scan driving circuit that outputs scan signals to a plurality of scan lines, which are one type of gate line (GL), and a light-emitting driving circuit that outputs light-emitting control signals to a plurality of light-emitting control lines, which are another type of gate line.

[0050] Data lines (DL) can be positioned to pass through a bending area (BA), and various data lines (DL) can be positioned to be connected to data pads.

[0051] The bending region (BA) may be an area where the substrate (110) is bent. The substrate (110) may be maintained in a flat state in areas excluding the bending region (BA).

[0052] FIG. 2 is a circuit diagram showing a pixel driving circuit according to an embodiment of the present specification.

[0053] Referring to FIG. 2, each of the plurality of subpixels (PX) of the display device (10) may include a light-emitting element (ED) and a pixel driving circuit for driving the light-emitting element (ED).

[0054] The pixel driving circuit of a subpixel (PX) may be composed of 6T1C (6 Transistors and 1 Capacitor), but is not limited thereto. The transistors placed in the pixel driving circuit may be N-type transistors, P-type transistors, or N-type and P-type transistors, and the pixel driving circuit of the subpixel (PX) may be composed of these transistors.

[0055] The pixel driving circuit of the subpixel (PX) may include a driving element for supplying driving current to a light-emitting element (ED), a scan element for transmitting a voltage (Vini, etc.) required for display driving into the subpixel (PX) at a predetermined timing according to a scan signal, a light-emitting control element for controlling whether the light-emitting element (ED) emits light, and a storage capacitor (Cst) for storing the voltage (Vini, etc.) required for display driving.

[0056] The driving element may include a driving transistor (DT). The driving transistor (DT) may be a first thin-film transistor. The scanning element may include a first switching transistor (T1), a second switching transistor (T2), and a third switching transistor (T3). The light emission control element may include a fourth switching transistor (T4) (or a first light emission control transistor) and a fifth switching transistor (T5) (or a second light emission control transistor). The first to fifth switching transistors may be second thin-film transistors.

[0057] According to an embodiment of the present specification, a pixel driving circuit may include a first thin-film transistor which is a driving transistor (DT) and a plurality of second thin-film transistors which are switching transistors (T1 to T5).

[0058] The light-emitting element (ED) may include a first electrode (anode electrode or pixel electrode) and a second electrode (cathode electrode or common electrode). The first electrode may correspond to or be connected to the fourth node (N4). A second driving voltage (EVSS) (or common voltage), which is a low potential voltage, may be applied to the second electrode. For example, the light-emitting element (ED) may be electrically connected by being placed between the fourth node (N4) and a line to which the second driving voltage (EVSS) is applied.

[0059] The driving transistor (DT) is connected to a first node (N1), a second node (N2), and a third node (N3), and can be controlled according to the voltage of the node (N1). The driving transistor (DT) may include a first gate electrode, a first drain electrode, and a first source electrode. The first gate electrode of the driving transistor (DT) may be connected to the first node (N1), the first drain electrode (or drain node) may be connected to the second node (N2), and the first source electrode may be connected to the third node (N3). For example, a first driving voltage (EVDD), which is a high potential voltage, may be applied to the first drain electrode of the driving transistor (DT). The first source electrode of the driving transistor (DT) may be electrically connected to the first electrode (or anode electrode) of the light-emitting element (ED).

[0060] The first switching transistor (T1) is controlled by a first scan signal (SC1) and can be connected between a first node (N1) and a second node (N2). The first switching transistor (T1) may include a second gate electrode, a second drain electrode, and a second source electrode. The first scan signal (SC1) may be applied to the second gate electrode of the first switching transistor (T1), the second drain electrode may be connected to the second node (N2), and the second source electrode may be connected to the first node (N1).

[0061] The second switching transistor (T2) is controlled by the second scan signal (SC2) and can be connected between the line to which the data voltage (Data) is applied and the third node (N3). The second scan signal (SC2) can be applied to the gate electrode of the second switching transistor (T2), the data voltage (Data) can be applied to the drain electrode, and the source electrode can be connected to the third node (N3).

[0062] The third switching transistor (T3) is controlled by the first scan signal (SC1) and can be connected between the line to which the initialization voltage (Vini) is applied and the fourth node (N4). The first scan signal (SC1) can be applied to the gate electrode of the third switching transistor (T3), the initialization voltage (Vini) can be applied to the drain electrode, and the source electrode can be connected to the fourth node (N4).

[0063] A storage capacitor (Cst) can be connected between the first node (N1) and the fourth node (N4). The storage capacitor (Cst) can store and maintain data voltage (Data) for one frame.

[0064] The fourth switching transistor (T4) is controlled by the second light emission control signal (EM2) and can be connected between the line to which the first driving voltage (EVDD), which is a high potential voltage, is applied and the second node (N2). The second light emission control signal (EM2) can be applied to the gate electrode of the fourth switching transistor (T4), the first driving voltage (EVDD) can be applied to the drain electrode, and the source electrode can be connected to the second node (N2).

[0065] The fifth switching transistor (T5) is controlled by a first light emission control signal (EM1) and can be connected between the third node (N3) and the fourth node (N4). The fifth switching transistor (T5) may include a third gate electrode, a third drain electrode, and a third source electrode. The first light emission control signal (EM1) may be applied to the third gate electrode of the fifth switching transistor (T5), the third drain electrode may be connected to the third node (N3), and the third source electrode may be connected to the fourth node (N4).

[0066] FIG. 3 is a waveform diagram of gate signals and voltage of a specific node of a pixel driving circuit according to an embodiment of the present specification.

[0067] Referring to the waveform diagram of FIG. 3 according to the pixel driving circuit of FIG. 2, the pixel driving circuit according to the embodiment of the present specification can be driven by dividing it into a first section (①), a second section (②), a third section (③), a fourth section (④), a fifth section (⑤), and a sixth section (⑥). For example, each of the sub-pixels (PX) arranged on the nth horizontal line may have a data voltage (Data) written through the first to sixth sections (①, ②, ③, ④, ⑤, ⑥), and each sub-pixel (PX) may emit light. The time for each of the first to sixth sections (①, ②, ③, ④, ⑤, ⑥) may vary depending on the embodiment.

[0068] The gate signals input to the pixel driving circuit may include a first light emission control signal (EM1), a second light emission control signal (EM2), a first scan signal (SC1), and a second scan signal (SC2) applied through the gate lines (GL).

[0069] The first light emission control signal (EM1) may have a gate high voltage of a first driving voltage level in the 5th and 6th sections (⑤, ⑥), and may have a gate low voltage of a second driving voltage level different from the first driving voltage level in the 1st to 4th sections (①, ②, ③, ④).

[0070] The second light emission control signal (EM2) may have a gate high voltage of the first driving voltage level in the first and sixth sections (①, ⑥), and may have a gate low voltage of the second driving voltage level in the second to fifth sections (②, ③, ④, ⑤).

[0071] The first scan signal (SC1) may have a gate high voltage of the first driving voltage level in the first to third intervals (①, ②, ③) and may have a gate low voltage of the second driving voltage level in the fourth to sixth intervals (④, ⑤, ⑥).

[0072] The second scan signal (SC2) may have a gate high voltage of the first driving voltage level in the second section (②) and may have a gate low voltage of the second driving voltage level in the first and third to sixth sections (①, ③, ④, ⑤, ⑥).

[0073] At the moment the first section (①) begins, the first scan signal (SC1) rises to have a gate high voltage, and the second light emission control signal (EM2) is maintained at a gate high voltage, and the first light emission control signal (EM1) and the second scan signal (SC2) can be maintained at a gate low voltage.

[0074] During the first interval (①), the fourth switching transistor (T4) is turned on as the second light emission control signal (EM2) is maintained in a state of gate high voltage, and as the first scan signal (SC1) changes to a gate high voltage, the first switching transistor (T1) is turned on, and the first driving voltage (EVDD) can be applied to the first node (N1), which is the gate node of the driving transistor (DT), through the fourth switching transistor (T4) and the first switching transistor (T1). Accordingly, the driving transistor (DT) can be turned on.

[0075] Additionally, during the first interval (①), as the first scan signal (SC1) changes to a gate high voltage, the third switching transistor (T3) is turned on, and the initialization voltage (Vini) can be applied to the fourth node (N4) through the third switching transistor (T3).

[0076] Accordingly, the anode electrode of the light-emitting element (ED) connected to the fourth node (N4) is initialized by the initialization voltage (Vini), and the first driving voltage (EVDD) and the initialization voltage (Vini) can be applied to both ends of the storage capacitor (Cst) connected between the first node (N1) and the fourth node (N4).

[0077] At the moment the second section (②) begins, the second scan signal (SC2) rises to have a gate high voltage, the first scan signal (SC1) is maintained at a gate high voltage, the first light emission control signal (EM1) is maintained at a gate low voltage, and the second light emission control signal (EM2) can be polled to a gate low voltage.

[0078] During the second interval (②), as the first scan signal (SC1) is maintained in a state of gate high voltage, the first switching transistor (T1) and the third switching transistor (T3) are turned on, and as the second scan signal (SC2) changes to a gate high voltage, the second switching transistor (T2) is turned on, and the data voltage (Data) can be applied to the third node (N3), which is the source node of the driving transistor (DT), through the second switching transistor (T2).

[0079] Since the driving transistor (DT) is in a diode-connection state where the first node (N1) and the second node (N2) are connected, sampling of the threshold voltage of the driving transistor (DT) begins, and the voltage of the first node (N1) rises above the data voltage (Data).

[0080] At the moment the third section (③) begins, while the first scan signal (SC1) is maintained at a gate high voltage, the second scan signal (SC2) is polled to have a gate low voltage, and the first and second light emission control signals (EM1, EM2) can be maintained at a gate low voltage.

[0081] During the third interval (③), the second scan signal (SC2) is converted to a gate low voltage state, but the first scan signal (SC1) maintains a gate high voltage state, and the diode connection state in which the first node (N1) and the second node (N2) of the driving transistor (DT) are connected is maintained, thereby increasing the period during which the threshold voltage of the driving transistor (DT) is sampled. Accordingly, the gate node of the driving transistor (DT) becomes a state of the sum voltage of the data voltage (Data) and the threshold voltage of the driving transistor (DT), and as the second switching transistor (T2) is turned off, the voltage of the floating third node (N3) can rise to a certain level.

[0082] And, during the third period (③), the storage capacitor (Cst) can be charged by the potential difference between the sum of the data voltage (Data) and the threshold voltage and the initialization voltage (Vini).

[0083] At the moment the fourth section (④) begins, the first scan signal (SC1) is polled to have a gate low voltage, and the first and second light emission control signals (EM1, EM2) and the second scan signal (SC2) can be maintained in a state of gate low voltage. During the fourth section (④), the first to fifth thin-film transistors (T1, T2, T3, T4, T5) in the pixel driving circuit can all be turned off.

[0084] Accordingly, each of the first node (N1), second node (N2), third node (N3), and fourth node (N4) sampled or written in the second and third sections (②, ③) is floated, and the voltage of each node can be maintained.

[0085] At the moment the 5th section (⑤) begins, the 1st and 2nd scan signals (SC1, SC2) and the 2nd light emission control signal (EM2) maintain a state of gate low voltage, and the 1st light emission control signal (EM1) rises to have a gate high voltage.

[0086] During the fifth section (⑤), the fifth switching transistor (T5) can be turned on as the first light-emitting control signal (EM1) changes to a gate high voltage. At this time, while maintaining the potential difference (Data+Vth-Vini) across the storage capacitor (Cst), the voltage of the fourth node (N4) connected to the anode electrode of the light-emitting element (ED) can be boosted.

[0087] When the boosted voltage of the fourth node (N4) exceeds a voltage value at which a driving current can flow through the light-emitting element (ED) (when it becomes capable of emitting light), the light-emitting element (ED) may emit light. The minimum voltage value at which a driving current can flow through the light-emitting element (ED) may be a voltage (EVSS+Vth) that is higher than the threshold voltage of the light-emitting element (ED) at the second driving voltage (EVSS). At this time, if the applied data voltage (Data) is a black signal, the boosted voltage of the fourth node (N4) does not exceed the threshold voltage of the light-emitting element (ED), so the light-emitting element (ED) may not emit light.

[0088] At the moment the 6th section (⑥) begins, the second light emission control signal (EM2) rises to have a gate high voltage, the first light emission control signal (EM1) is maintained at a gate high voltage, and the first and second scan signals (SC1, SC2) can be maintained at a gate low voltage.

[0089] During the 6th interval (⑥), the 4th switching transistor (T4) can be turned on as the 2nd light emission control signal (EM2) changes to a gate high voltage. Accordingly, a driving current is supplied to the light-emitting element (ED) through the 4th switching transistor (T4), the driving transistor (DT), and the 5th switching transistor (T5), so that the light-emitting element (ED) can emit light. As previously explained, if the applied data voltage (Data) is a black signal, the boosted voltage of the 4th node (N4) does not exceed the threshold voltage of the light-emitting element (ED), so the light-emitting element (ED) may not emit light.

[0090] According to an embodiment of the present specification, by maintaining the gate high voltage of the first scan signal (SC1) for a certain period of time in the third section (③), the period during which the threshold voltage of the driving transistor (DT) is sampled can be extended, and thereby, image quality defects such as screen stains, afterimages, and crosstalk can be improved.

[0091] FIG. 4 is a plan view showing a thin-film transistor and a light-shielding layer according to an embodiment of the present specification. FIG. 4 is an enlarged plan view of a certain area including a plurality of thin-film transistors and a light-shielding layer in a display area (AA).

[0092] Referring to FIG. 4, a subpixel (PX) may include a light-emitting element and a pixel driving circuit. The light-emitting element may include a first electrode (410), a light-emitting layer (420), and a second electrode (430), and the pixel driving circuit may include a driving transistor (DT) and a plurality of switching transistors (T1 to T5). The driving transistor (DT) may be a first thin-film transistor, the first switching transistor (T1) may be a second thin-film transistor, and the fifth switching transistor (T5) may be a third thin-film transistor.

[0093] The driving transistor (DT) and the plurality of switching transistors (T1 to T5) each include a gate electrode, a semiconductor layer, a source electrode, and a drain electrode, and the size of each thin-film transistor can be formed differently depending on the size of the semiconductor layer.

[0094] Since the driving transistor (DT) and the first switching transistor (T1) are connected to a plurality of wires and a storage capacitor (Cst) to drive the light-emitting element (ED), they operate continuously according to fluctuations in the driving voltage and the storage capacitor (Cst), so a large load can be applied compared to other switching transistors (T2 to T5). Therefore, the driving transistor (DT) and the first switching transistor (T1) can degrade faster than other switching transistors (T2 to T5).

[0095] When the driving transistor (DT) and the first switching transistor (T1) use an oxide semiconductor layer, the thin film transistor may undergo further degradation due to light incident on the oxide semiconductor layer.

[0096] The light incident on the oxide semiconductor layer may be external light entering the display device (10) from the outside or internal light generated from a light-emitting element inside the display device (10). In the case of a thin-film transistor using an oxide semiconductor layer, it may have superior leakage current characteristics compared to a thin-film transistor using a polycrystalline semiconductor layer, but the characteristics may be easily degraded by light and altered.

[0097] The driving transistor (DT) and the first switching transistor (T1), which are prone to degradation, may have a fluctuating threshold voltage (Vth), and the driving transistor (DT) and the first switching transistor (T1) may be driven even when a low voltage is applied. The light-emitting element (ED) connected to the first switching transistor (T1) may emit light at a low brightness or may emit light even when no driving signal is applied.

[0098] Accordingly, in order to prevent deterioration caused by incident light, the driving transistor (DT) and the first to fifth switching transistors (T1 to T5) need to block incident light, and the driving transistor (DT) and the first to fifth switching transistors (T1 to T5) can block incident light by forming a light-blocking layer (500) on the upper surface.

[0099] The light-blocking layer (500) may be formed on the driving transistor (DT) or the first to fifth switching transistors (T1 to T5). The light-blocking layer (500) may be arranged to overlap with one or more of the driving transistor (DT) and the first to fifth switching transistors (T1 to T5).

[0100] The light-blocking layer (500) can be formed of the same material as the first electrode (410) and placed on the same layer as the first electrode (410) so as to be formed on the driving transistor (DT) and the first to fifth switching transistors (T1 to T5). The light-blocking layer (500) can be formed separately from the first electrode (410) so as not to have an electrical effect on the first electrode (410).

[0101] Since the driving transistor (DT) and the first switching transistor (T1) have a higher degree of degradation compared to other switching transistors, the light-blocking layer (500) can be positioned to overlap the driving transistor (DT) and the first switching transistor (T1), and can be positioned so as not to overlap the other switching transistors (T2~T5). The light-blocking layer (500) can be selectively positioned on the thin-film transistors so that the degradation rate of each thin-film transistor becomes similar, taking into account the degree of degradation of each thin-film transistor.

[0102] Since the degree of degradation of the first switching transistor (T1) may be higher than that of the driving transistor (DT), the light-blocking layer (500) may be arranged to overlap only with the first switching transistor (T1). For example, the light-blocking layer (500) may overlap with the driving transistor (DT) or one of the plurality of switching transistors, and may not overlap with the remaining plurality of switching transistors excluding one of the plurality of switching transistors.

[0103] The arrangement structure of the shading layer (500) is not limited to this, and various types of arrangement structures may be applied.

[0104] The light-blocking layer (500) has a line shape and can be arranged continuously without any breaks between a plurality of light-emitting elements, and can be arranged to overlap with one or more of the driving transistor (DT) and the first to fifth switching transistors (T1 to T5).

[0105] In FIG. 4, only one line-shaped light-blocking layer (500) is shown, but the arrangement structure of the light-blocking layer (500) is not limited thereto. The line-shaped light-blocking layer (500) can be arranged between each subpixel (PX), and multiple layers can be arranged between subpixels (PX). The light-blocking layer (500) can be arranged in various forms along the horizontal and vertical directions.

[0106] A line-shaped light-blocking layer (500) can be connected to a second electrode of a light-emitting element to apply a common voltage. For example, the line-shaped light-blocking layer (500) can be arranged to extend from a non-display area (NA) to a display area (AA) of the substrate (110), and the light-blocking layer (500) placed in the non-display area (NA) can be connected to a common voltage line, and the light-blocking layer (500) placed in the display area (AA) can be connected to a second electrode.

[0107] The light-blocking layer (500) and the second electrode can be connected in multiple areas at a certain distance apart, and the second electrode can be connected to the common voltage line and the light-blocking layer (500) to receive a common voltage, so that a uniform common voltage can be formed in the entire area.

[0108] A common voltage line is formed in the non-display area (NA) to apply a common voltage to the second electrode, and the common voltage line can be connected to both the second electrode and the light-shielding layer (500).

[0109] FIG. 5 is a plan view showing a thin-film transistor and a light-shielding layer according to another embodiment of the present specification. FIG. 5 is an enlarged plan view of a certain area including a plurality of thin-film transistors and a light-shielding layer in a display area (AA).

[0110] Referring to FIG. 5, a subpixel (PX) may include a light-emitting element (ED) and a pixel driving circuit. The light-emitting element (ED) may include a first electrode (410), a light-emitting layer (420), and a second electrode, and the pixel driving circuit may include a driving transistor (DT) and first to fifth switching transistors (T1 to T5).

[0111] The light-blocking layer (550) can be formed from the same material as the first electrode (410) so as to be formed on the driving transistor (DT) and the first to fifth switching transistors (T1 to T5), and can be placed on the same layer as the first electrode (410). The light-blocking layer (550) can be formed separately from the first electrode (410) so as not to electrically affect the first electrode (410).

[0112] The light-blocking layer (550) may be arranged to overlap with one or more of the driving transistor (DT) and the first to fifth switching transistors (T1 to T5).

[0113] The light-blocking layer (550) may be superimposed on the driving transistor (DT) and the first switching transistor (T1), which may be easily degraded by applying a large load. The arrangement structure of the light-blocking layer (550) is not limited to this, and may be superimposed on the entire thin-film transistor.

[0114] According to an embodiment of the present specification, the light-blocking layer (550) may be positioned without being connected to a common voltage line and a second electrode in order to effectively block light incident from the outside to the inside or light generated from a light-emitting element inside the display device, and may be positioned in a free shape compared to the embodiment of FIG. 4.

[0115] In FIG. 5, the light-blocking layer (550) is implemented in a cross shape to block light incident on each transistor, but it is not limited to this and can be applied in various shapes.

[0116] Although only one light-blocking layer (550) is shown in FIG. 5, the arrangement structure of the light-blocking layer (550) is not limited thereto. The light-blocking layer (550) can be arranged between each subpixel (PX), and multiple layers can be arranged between subpixels (PX). The light-blocking layer (550) can be arranged in various forms depending on the purpose of blocking light.

[0117] The first electrode (410) is formed to be larger than the light-emitting layer (420), and since the second switching transistor (T2) or the fourth switching transistor (T4) can be placed below the first electrode (410), the second switching transistor (T2) or the fourth switching transistor (T4) can block light with the first electrode (410) rather than the light-blocking layer (550). Therefore, the light-blocking layer (550) may not be placed on the upper side of the second switching transistor (T2) or the fourth switching transistor (T4).

[0118] The third switching transistor (T3) and the fifth switching transistor (T5) may have a smaller degree of degradation compared to other thin-film transistors, and a light-blocking layer (550) may not be placed on the third switching transistor (T3) and the fifth switching transistor (T5) in order to match the degradation rate of each thin-film transistor. In order to match the uniformity of the degree of degradation of each transistor, the light-blocking layer (550) may be placed so as to overlap only a portion of the third switching transistor (T3) and the fifth switching transistor (T5).

[0119] FIG. 6 is a cross-sectional view along the line I-I' of FIG. 1. FIG. 6 shows a thin-film transistor and a light-shielding layer according to the embodiment of FIG. 4.

[0120] Referring to FIG. 6, the pixel driving circuit of the display area (AA) may include a first thin-film transistor (310) (or driving transistor (DT)), a second thin-film transistor (320) (or first switching transistor (T1)), a third thin-film transistor (330) (or fifth switching transistor (T5)), and a storage capacitor (340, Cst), and the gate driving unit (115) of the non-display area (NA) may include at least one switching transistor (or fourth thin-film transistor (350)).

[0121] To describe the configuration of a single subpixel (PX), it consists of a pixel driving circuit formed on a substrate (110) and a light-emitting element electrically connected to the pixel driving circuit. The pixel driving circuit refers to an array portion that drives a single subpixel (PX), including a driving transistor (DT, 310), a switching transistor (T1, T5, 320, 330), and a storage capacitor (340, Cst). The light-emitting element (ED) refers to an array portion for light emission, including an anode electrode (410), a cathode electrode (430), and a light-emitting layer (420) disposed between them. The pixel driving circuit and the light-emitting element (ED) may be insulated from each other by a planarization layer.

[0122] According to an embodiment of the present specification, the driving transistor (DT) (or the first thin-film transistor (310)) and the first switching transistor (T1) (or the second thin-film transistor (320)) use an oxide semiconductor material (or a semiconducting oxide material) as the semiconductor layer (322). A thin-film transistor using an oxide semiconductor material as the semiconductor layer has an excellent leakage current blocking effect, which can reduce power consumption, and has a relatively lower manufacturing cost compared to a thin-film transistor using a polycrystalline semiconductor material as the semiconductor layer.

[0123] The substrate (110) may be composed of a multi-layer in which an organic film and an inorganic film are alternately stacked. For example, the substrate (110) may be composed of an organic film (111, 113), such as polyimide, and an inorganic film (112), such as silicon oxide (SiO2), alternately stacked, and the embodiments of the present specification are not limited thereto.

[0124] A lower buffer layer (120) is formed on a substrate (110). The lower buffer layer (120) is intended to block moisture that may penetrate from the outside and may be formed as a single layer or stacked in multiple layers, such as a silicon oxide (SiO2) film or a silicon nitride (SiN) film, and the embodiments of this specification are not limited thereto. For example, the lower buffer layer (120) may be formed as a stacked structure of a first lower buffer layer (130) and a second lower buffer layer (140) to increase the blocking power against moisture that penetrates from the outside.

[0125] A fourth thin-film transistor (350) may be formed in the gate driver (115) of the non-display area (NA) of the substrate (110). The fourth thin-film transistor (350) may include a fourth semiconductor layer (352) having a channel for electron or hole movement, a fourth gate electrode (351), a fourth source electrode (354), and a fourth drain electrode (355). The fourth thin-film transistor (350) may have the fourth semiconductor layer (352) configured as a polycrystalline semiconductor layer.

[0126] The fourth semiconductor layer (352) is composed of a polycrystalline semiconductor material, and a fourth channel region (352C) is formed in the center of the fourth semiconductor layer (352), and a fourth source region (352S) and a fourth drain region (352D) may be arranged on both sides with the fourth channel region (352C) in between.

[0127] The fourth channel region (352C) is a polycrystalline semiconductor material that maintains an intrinsic state and can provide a path for electrons or holes to move.

[0128] The fourth source region (352S) and the fourth drain region (352D) may be regions that are made conductive by doping a group 5 or group 3 impurity ion, for example, phosphorus (P) or boron (B), into an intrinsic polycrystalline semiconductor material at a predetermined concentration.

[0129] The fourth thin-film transistor (350) may include a fourth gate electrode (351) configured to overlap with the fourth channel region (352C) of the fourth semiconductor layer (352). A first gate insulating layer (210) is interposed between the fourth gate electrode (351) and the fourth semiconductor layer (352).

[0130] According to an embodiment of the present specification, the fourth thin-film transistor (350) adopts a top-gate method in which the fourth gate electrode (351) is located on top of the fourth semiconductor layer (352). By doing so, the first capacitor electrode (341) and the light-blocking layer (321, 321), which are composed of the same material as the fourth gate electrode (351), can be formed through a single mask process, thereby achieving the effect of shortening the process.

[0131] The fourth gate electrode (351), the first capacitor electrode (341), or the light-blocking layer (321, 331) may be composed of a metallic material. For example, the fourth gate electrode (351), the first capacitor electrode (341), or the light-blocking layer (321, 331) may be a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof, but is not limited thereto.

[0132] A first interlayer insulating layer (220) is disposed on the fourth gate electrode (351). The first interlayer insulating layer (220) may be composed of silicon nitride (SiNx). For example, the first interlayer insulating layer (220) composed of silicon nitride (SiNx) may contain hydrogen particles. When the fourth semiconductor layer (352) is formed and the first interlayer insulating layer (220) is deposited thereon, and a heat treatment process is performed, the hydrogen particles contained in the first interlayer insulating layer (220) can penetrate into the fourth source region (352S) and the fourth drain region (352D), thereby contributing to improving and stabilizing the conductivity of the polycrystalline semiconductor material. This can be referred to as a hydrogenation process.

[0133] The fourth thin-film transistor (350) may further include a first upper buffer layer (230), a second upper buffer layer (240), a second gate insulating layer (250), and a second interlayer insulating layer (260) in sequence on the first interlayer insulating layer (220), and may include a fourth source electrode (354) and a fourth drain electrode (355) formed on the second interlayer insulating layer (260) and connected to a fourth source region (352S) and a fourth drain region (352D), respectively.

[0134] The first upper buffer layer (230) can separate the fourth semiconductor layer (352) of the non-display area (NA), which is composed of a polycrystalline semiconductor material, from the semiconductor layers (312, 322, 332) of the thin-film transistors of the display area (AA), which is composed of an oxide semiconductor material, and provide a base for forming the semiconductor layers (312, 322, 332) of the thin-film transistors of the display area (AA).

[0135] The second interlayer insulating layer (260) is an interlayer insulating layer covering the first gate electrode (313) of the first thin-film transistor (310), the second gate electrode (323) of the second thin-film transistor (320), and the third gate electrode (333) of the third thin-film transistor (330). Since the second interlayer insulating layer (260) or the second gate insulating layer (250) is formed on the first semiconductor layer (312), the second semiconductor layer (322), and the third semiconductor layer (332), which are composed of oxide semiconductor material, it can be composed of an inorganic film that does not contain hydrogen particles.

[0136] The fourth source electrode (354) and the fourth drain electrode (355) may be a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof, but are not limited thereto.

[0137] A first thin-film transistor (310), a second thin-film transistor (320), a third thin-film transistor (330), and a storage capacitor (340, Cst) may be formed in the pixel driving circuit of the substrate (110).

[0138] A first thin-film transistor (310) according to an embodiment of the present specification is configured on a first upper buffer layer (230). The first thin-film transistor (310) can provide a driving current to a light-emitting element (ED) according to a data voltage applied from a data line (DL). The first thin-film transistor (310) may include an oxide semiconductor layer or a polycrystalline semiconductor layer as a first semiconductor layer (312).

[0139] A thin-film transistor containing a polycrystalline semiconductor layer may have higher power consumption than a thin-film transistor containing an oxide semiconductor layer because leakage current occurs in the off state. In the case of a thin-film transistor using an oxide semiconductor layer as the semiconductor layer, degradation may occur due to light incident on the semiconductor layer due to the material properties of the oxide semiconductor. The display device according to the embodiment of this specification proposes a structure in which the semiconductor layer of the thin-film transistor in the display area (AA) is composed of an oxide semiconductor layer that has a very small leakage current to reduce power consumption, and which reduces degradation caused by light incident on the semiconductor layer.

[0140] The first thin-film transistor (310) according to the embodiment of the present specification may have the first semiconductor layer (312) configured as an oxide semiconductor layer. The first thin-film transistor (310) includes a first semiconductor layer (312) configured as an oxide semiconductor layer, a second gate insulating layer (250) covering the first semiconductor layer (312), a first upper gate electrode (313) formed on the second gate insulating layer (250) and overlapping with the first semiconductor layer (312), a second interlayer insulating layer (260) formed on the second gate insulating layer (250) covering the first upper gate electrode (313), and a first source electrode (314) and a first drain electrode (315) disposed on the second interlayer insulating layer (260).

[0141] The first thin-film transistor (310) further includes a first lower gate electrode (or first lower light-blocking layer) (311) that overlaps with the first semiconductor layer (312) while being disposed between the first upper buffer layer (230) and the second upper buffer layer (240). The first lower gate electrode (311) may be inserted into the interior of the first upper buffer layer (230). For example, the first lower gate electrode (311) is formed on the first upper buffer layer (230) disposed on the first interlayer insulating layer (220), and the second upper buffer layer (240) is formed on the first lower gate electrode (311) and the first upper buffer layer (230).

[0142] The first upper buffer layer (230) may be composed of silicon oxide (SiO2). Since the first upper buffer layer (230) is composed of silicon oxide (SiO2) that does not contain hydrogen particles, it may be configured as the base of a first thin-film transistor (310) that uses an oxide semiconductor layer, whose reliability may be compromised by hydrogen particles, as the first semiconductor layer (312).

[0143] The second upper buffer layer (240) may be composed of silicon nitride (SiNx) or silicon oxide (SiO2). The second upper buffer layer (240) may cover both the upper and side surfaces of the first lower gate electrode (311) to completely seal the first lower gate electrode (311).

[0144] A first interlayer insulating layer (220) containing hydrogen particles is located at the bottom of the first upper buffer layer (230). Hydrogen particles generated during the hydrogenation process of the fourth thin-film transistor (350), in which the fourth semiconductor layer (352) is configured as a polycrystalline semiconductor layer, can pass through the first upper buffer layer (230) and impair the reliability of the oxide semiconductor layer located above the first upper buffer layer (230). For example, if hydrogen particles penetrate the oxide semiconductor layer, the thin-film transistors may have different threshold voltages depending on their formation location or may cause problems such as changes in channel conductivity. In the case of the driving transistor, it directly contributes to the operation of the light-emitting device, so ensuring the reliability of the device is important.

[0145] The first thin-film transistor (310) according to the embodiment of the present specification may have a first lower gate electrode (311) composed of a metal layer including a titanium (Ti) material having excellent hydrogen particle capture ability. For example, it may be a single layer of titanium (Ti), a multilayer of molybdenum (Mo) and titanium (Ti), or an alloy of molybdenum (Mo) and titanium (Ti), but is not limited thereto.

[0146] Titanium (Ti) captures hydrogen particles diffusing within the first upper buffer layer (230) to prevent the hydrogen particles from reaching the first semiconductor layer (312). The first thin-film transistor (310) according to the embodiment of the present specification can improve the problem of the reliability of the oxide semiconductor layer being compromised by hydrogen particles by forming the first lower gate electrode (311) with a metal layer such as titanium (Ti) having the ability to capture hydrogen particles, and also forming the second upper buffer layer (240) with silicon nitride (SiNx) having the ability to capture hydrogen particles to surround the first lower gate electrode (311).

[0147] The first source electrode (314) of the first thin-film transistor (310) can be electrically connected to the first lower gate electrode (311). Since the effective voltage applied to the first semiconductor layer channel region (312C) of the first semiconductor layer (312) is inversely proportional to the parasitic capacitance between the first semiconductor layer (312) and the first lower gate electrode (311), the effective voltage applied to the first semiconductor layer (312) can be controlled. For example, if the first lower gate electrode (311) is placed close to the first semiconductor layer (312) to increase the parasitic capacitance value between them, the actual current flowing through the first semiconductor layer (312) can be reduced, and this can widen the control range of the first thin-film transistor (310) that can be controlled through the voltage applied to the first upper gate electrode (313). This allows for precise control of light-emitting elements even at low gradations, thereby resolving the problem of screen stains.

[0148] The pixel driving circuit of the display area (AA) according to the embodiment of the present specification may include a storage capacitor (340, Cst). The storage capacitor (340) stores a data voltage applied through the data line (DL) for a certain period and then provides it to the light-emitting element (ED).

[0149] The storage capacitor (340) consists of two corresponding electrodes and a dielectric material disposed between them. The storage capacitor (340) may include a first capacitor electrode (341) disposed on the same layer with the same material as the fourth gate electrode (351), and a second capacitor electrode (343) disposed with the same material as the first lower gate electrode (311). A first interlayer insulating layer (220) may be disposed between the first capacitor electrode (341) and the second capacitor electrode (343). The second capacitor electrode (343) of the storage capacitor (340) may be electrically connected to the first source electrode (314).

[0150] The pixel driving circuit of the display area (AA) according to the embodiment of the present specification may include a second thin-film transistor (320) (or a first switching transistor (T1)).

[0151] The second thin-film transistor (320) is turned on by a first scan signal (SC1) through a gate line (GL), and the first thin-film transistor (310) can be operated by applying an operation signal to a first node (N1), which is the gate node of the first thin-film transistor (310).

[0152] The second thin-film transistor (320) may include a second semiconductor layer (322) formed on the first upper buffer layer (230) and composed of an oxide semiconductor layer, a second gate insulating layer (250) covering the second semiconductor layer (322), a second interlayer insulating layer (260) formed on the second gate insulating layer (250), and a second source electrode (324) and a second drain electrode (325) formed on the second interlayer insulating layer (260).

[0153] The second thin-film transistor (320) is positioned below the first upper buffer layer (230) and may further include a second lower gate electrode (321) (or second lower light-blocking layer) that overlaps with the second semiconductor layer (322). For example, the second lower gate electrode (321) may be formed on the upper surface of the first gate insulating layer (210) while being composed of the same material as the fourth gate electrode (351). The second lower gate electrode (321) may be electrically connected to the second upper gate electrode (323) to form a dual gate (or dual gate). By having the second thin-film transistor (320) have a dual gate structure, the flow of current flowing in the second channel region (322C) of the second semiconductor layer (322) can be controlled more precisely, and the second thin-film transistor (320) can be positioned in a smaller area, thereby enabling the realization of a high-resolution display device.

[0154] The second semiconductor layer (322) is composed of an oxide semiconductor material and includes an intrinsic second channel region (322C) that is not doped with impurities, and a second source region (322S) and a second drain region (322D) that are doped with impurities and made conductive.

[0155] The distance between the second semiconductor layer (322) and the second lower gate electrode (321) may be greater than the distance between the first semiconductor layer (312) and the first lower gate electrode (311). Each thin-film transistor may have a different need for precise control through dual gates depending on its unique function.

[0156] The second source electrode (324) and the second drain electrode (325) may be a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof, but are not limited thereto.

[0157] The number of mask processes can be reduced by simultaneously forming the second source electrode (324), the second drain electrode (325), the fourth source electrode (354), and the fourth drain electrode (355) with the same material on the second interlayer insulating layer (260).

[0158] The pixel driving circuit of the display area (AA) according to the embodiment of the present specification may include a third thin-film transistor (330) (or a fifth switching transistor (T5)).

[0159] The third thin-film transistor (330) may include a third semiconductor layer (332) formed on the second upper buffer layer (240) and composed of an oxide semiconductor layer, a second gate insulating layer (250) covering the third semiconductor layer (332), a third upper gate electrode (333) formed on the second gate insulating layer (250) and overlapping with the third semiconductor layer (332), a second interlayer insulating layer (260) covering the third upper gate electrode (333), and a third source electrode (334) and a third drain electrode (335) formed on the second interlayer insulating layer (260).

[0160] The third drain electrode (335) is electrically connected to the first source electrode (314) of the first thin-film transistor (310), and the third source electrode (334) is electrically connected to the light-emitting element (ED), so that a driving current can be supplied to the light-emitting element (ED) through the third thin-film transistor (330). The third thin-film transistor (330) is controlled by the first light-emitting control signal (EM1) and may block the supply of a driving current to the light-emitting element (ED).

[0161] The third thin-film transistor (330) is positioned below the first upper buffer layer (230) and may further include a third lower gate electrode (or third lower light-blocking layer) (331) that overlaps with the third semiconductor layer (332). In particular, the third lower gate electrode (331) may be formed on the upper surface of the first gate insulating layer (210) while being composed of the same material as the fourth gate electrode (351). The third lower gate electrode (331) may be electrically connected to the third upper gate electrode (333) to form a dual gate. By having the third thin-film transistor (330) have a dual gate structure, the flow of current flowing in the third channel region (332C) of the third semiconductor layer (332) can be controlled more precisely, and the third thin-film transistor (330) can be positioned in a smaller area, thereby enabling the realization of a high-resolution display device.

[0162] The third semiconductor layer (332) is composed of an oxide semiconductor material and includes an intrinsic third channel region (332C) that is not doped with impurities, and a third source region (332S) and a third drain region (332D) that are doped with impurities and made conductive.

[0163] The distance between the third semiconductor layer (332) and the third lower gate electrode (331) may be greater than the distance between the first semiconductor layer (312) and the first lower gate electrode (311). Each thin-film transistor may require different levels of precise control through dual gates depending on its unique function. For example, the third thin-film transistor (330) requires more precise control because the ratio of the change in current of the light-emitting element (ED) to the change in threshold voltage is higher than the ratio of the change in current of the light-emitting element (ED) to the change in threshold voltage of a plurality of first thin-film transistors (310). To precisely control the current of the light-emitting element (ED), the distance between the first semiconductor layer (312) and the first lower gate electrode (311) may be configured to be smaller than the distance between the third semiconductor layer (332) and the third lower gate electrode (331).

[0164] The third source electrode (334) and the third drain electrode (335) may be a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof, as with the fourth source electrode (354) and the fourth drain electrode (355), but are not limited thereto.

[0165] According to the embodiments of the present specification, the first upper gate electrode (313), the second upper gate electrode (323), and the third upper gate electrode (333) may include titanium (Ti) in the lower portion and be formed with a metal different from titanium (Ti), such as molybdenum (Mo), in the upper portion, and may be configured as a multilayer structure, but the embodiments of the present specification are not limited thereto.

[0166] If each upper gate electrode (313, 323, 333) is composed of a plurality of metal layers including titanium (Ti), the metal layers including titanium (Ti) can block hydrogen particles that may come down from the top of each thin-film transistor (310, 320, 330), thereby protecting each semiconductor layer (312, 322, 332).

[0167] A first flattening layer (270) and a second flattening layer (280) may be formed sequentially on the top of the pixel driving circuit according to the embodiment of the present specification to flatten the steps caused by height differences of various components. The first flattening layer (270) and the second flattening layer (280) may be composed of organic films such as polyimide or acrylic resin, and the embodiments of the present specification are not limited thereto.

[0168] A light-emitting element (ED) is formed on the second planarization layer (280). The light-emitting element (ED) may include a first electrode (or anode electrode) (410), a second electrode (or cathode electrode) (430) corresponding to the first electrode (410), and a light-emitting layer (420) located between the first electrode (410) and the second electrode (430). The first electrode (410) and the light-emitting layer (420) may be formed for each subpixel (PX), and the second electrode (430) may be formed over the entire area of ​​the display area (AA).

[0169] The light-emitting element (ED) is connected to the pixel driving circuit through a first connecting electrode (360) formed on the first planarization layer (270). For example, the first electrode (410) of the light-emitting element (ED) and the first drain electrode (315) of the first thin-film transistor (310) or the third source electrode (334) of the third thin-film transistor (330) constituting the pixel driving circuit are connected to each other by the first connecting electrode (360).

[0170] The first electrode (410) is connected to the first connecting electrode (360) through a contact hole penetrating the second flattening layer (280), and the first connecting electrode (360) is connected to the third source electrode (334) through a contact hole penetrating the first flattening layer (270).

[0171] The first electrode (410) may be formed as a multilayer structure including a transparent conductive film or an opaque conductive film with high reflection efficiency. The transparent conductive film may be made of a material with a relatively high work function value, such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO), and the opaque conductive film may be formed as a single layer or multilayer structure including aluminum (Al), silver (Ag), copper (Cu), lead (Pb), molybdenum (Mo), titanium (Ti), or an alloy thereof, and the embodiments of the present specification are not limited thereto. For example, the first electrode (410) may be formed as a structure in which a transparent conductive film, an opaque conductive film, and a transparent conductive film are sequentially stacked, or as a structure in which a transparent conductive film and an opaque conductive film are sequentially stacked, and the embodiments of the present specification are not limited thereto.

[0172] The light-emitting layer (420) can be formed by stacking a hole-related layer, an organic light-emitting layer, and an electron-related layer in that order or in reverse order on the first electrode (410).

[0173] The bank layer (290) may be a pixel defining film that exposes the first electrode (410) of each subpixel (PX). The bank layer (290) may be formed of an opaque material to prevent light interference between adjacent subpixels (PX). For example, the bank layer (290) may include a light-blocking material consisting of any one of color pigment, organic black, and carbon. A spacer (440) may be further disposed on the bank layer (290).

[0174] The second electrode (430) may be formed on the upper and side surfaces of the light-emitting layer (420) with the light-emitting layer (420) in between, facing the first electrode (410). The second electrode (430) may be formed integrally on the entire surface of the display area (AA). When applied to a top-emission organic light-emitting display device, the second electrode (430) may be composed of a transparent conductive film such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0175] A sealing portion (600) that inhibits moisture penetration may be further disposed on the second electrode (430). The sealing portion (600) may include a first sealing layer (610), a second sealing layer (620), and a third sealing layer (630) that are stacked in sequence, and the embodiments of the present specification are not limited thereto.

[0176] The first sealing layer (610) and the third sealing layer (630) of the sealing portion (600) may be formed of an inorganic material such as silicon oxide (SiOx). The second sealing layer (620) of the sealing portion (600) may be formed of an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin, and the embodiments of this specification are not limited thereto.

[0177] A touch portion (or touch sensor portion) may be further disposed on the packaging portion (600). The touch portion is composed of a touch buffer layer, a touch insulating layer, and a touch protective layer, and includes a plurality of touch electrodes and a plurality of connecting electrodes.

[0178] External light (or light (L)) or internal light (L) may be incident on the pixel driving circuit inside the display device (10). Although the light (L) in FIG. 6 represents light incident from outside the display device (10), the light (L) may be light emitted from a light-emitting element (ED) inside the display device (10) and reflected or transmitted, but is not limited thereto.

[0179] In the case of thin-film transistors using oxide semiconductor materials as the semiconductor layer, degradation can occur due to light incident on the semiconductor layer, given the characteristics of the oxide semiconductor material. Although oxide semiconductor thin-film transistors possess superior leakage current characteristics compared to polycrystalline semiconductor thin-film transistors, degradation caused by light can lead to changes in the threshold voltage and deformation of the leakage current characteristics.

[0180] The path through which light (L) is incident and travels may include entering through the front surface of the display device (10) and entering through the substrate (110) on the back surface of the display device (10). The light entering the interior of the display device (10) passes through the first and second planarization layers (270, 280), the second interlayer insulating layer (260), the second gate insulating layer (250), the first and second upper buffer layers (230, 240), the first interlayer insulating layer (220), the first gate insulating layer (210), etc., and some of it may be transmitted and some of it may be reflected at each boundary surface. Some of the light reflected at each boundary surface may affect the semiconductor layer of each thin-film transistor by repeatedly reflecting back.

[0181] According to an embodiment of the present specification, a light-blocking layer (500) may be formed to prevent light (L) from being incident on a semiconductor layer. The light-blocking layer (500) may be disposed on the same layer as the first electrode (410) on the first thin-film transistor (310) or the second thin-film transistor (320), and may be disposed to overlap with one or more of the first thin-film transistor (310) and / or the second thin-film transistor (320).

[0182] The light-blocking layer (500) may be formed as a single layer or multilayer structure including aluminum (Al), silver (Ag), copper (Cu), lead (Pb), molybdenum (Mo), titanium (Ti), or an alloy thereof, which is the same material as the first electrode (410), so as to reflect or absorb light (L). The material of the light-blocking layer (500) does not limit the contents of this specification.

[0183] The light-blocking layer (500) can be connected to the second electrode (430) in the display area (AA). The second electrode (430) can be formed over the entire area of ​​the display area (AA), and the light-blocking layer (500) and the second electrode (430) can be electrically connected through the second electrode contact hole (430H) in the portion where the light-blocking layer (500) is placed.

[0184] The second electrode contact hole (430H) can be formed by removing a portion of the bank layer (290) that is placed between the second electrode (430) and the light-shielding layer (500). The second electrode contact hole (430H) can be formed in the bank layer (290), and the second electrode (430) can be formed in the second electrode contact hole (430H) to connect the second electrode (430) and the light-shielding layer (500).

[0185] In the non-display area (NA), the second electrode (430) is connected to the common voltage line (370) so that the second driving voltage (EVSS) can be applied. The common voltage line (370) can be connected to the end area of ​​the second electrode (430).

[0186] If the common voltage line (370) is connected only at the end region of the second electrode (430) without a portion connected to the light-blocking layer (500), the second driving voltage (EVSS), which is a low potential voltage, is not formed uniformly over the entire region of the second electrode (430), and a phenomenon may occur where the voltage decreases as it moves toward the central region.

[0187] In order to uniformly form a second driving voltage (EVSS) over the entire area of ​​the second electrode (430), a light-blocking layer (500) placed in the display area (AA) can be extended to the non-display area (NA) and connected to a common voltage line (370). Then, the light-blocking layer (500) can be electrically connected to the second electrode (430) in a plurality of areas in the display area (AA) to uniformly apply the second driving voltage (EVSS) to the second electrode (430).

[0188] For example, a common voltage line (370) placed in a non-display area (NA) may be connected to a second electrode (430) and a light-blocking layer (500), and a second driving voltage (EVSS) may be applied to the second electrode (430) through the light-blocking layer (500).

[0189] In order to connect the light-blocking layer (500) and the common voltage line (370), a second connecting electrode (380) may be formed in a portion of the first flattening layer (270) to connect the light-blocking layer (500) and the common voltage line (370). The second connecting electrode (380) may use the same material as the first connecting electrode (360) and may be formed by the same process as the first connecting electrode (360).

[0190] The light-blocking layer (500) and the second electrode (430) are formed over the entire display area (AA), and the light-blocking layer (500) and the second electrode (430) can be connected in multiple areas at uniform intervals over the entire display area (AA). By forming a second electrode contact hole (430H) in multiple areas to connect the light-blocking layer (500) and the second electrode (430) and applying a second driving voltage (EVSS), the second driving voltage (EVSS) can be uniformly formed on the second electrode (430).

[0191] FIG. 7 is a cross-sectional view along the line I-I' of FIG. 1. FIG. 7 shows a thin-film transistor and a light-shielding layer according to the embodiment of FIG. 5 of the present specification. The description of the components of FIG. 7 is substantially the same as the components of FIG. 6, so it may be omitted or simplified.

[0192] Referring to FIG. 7, the display device (10) includes a pixel driving circuit and a light-emitting element (ED) comprising a first thin-film transistor (310) (or driving transistor (DT)), a second thin-film transistor (320) (or first switching transistor (T1)), and a third thin-film transistor (330) (or third switching transistor (T5)), and the pixel driving circuit and the light-emitting element (ED) may have the same structure as FIG. 6.

[0193] The light-blocking layer (550) can be formed on the thin-film transistors (310, 320, 330) by overlapping with one or more of the thin-film transistors (310, 320, 330). The light-blocking layer (550) can be formed with the same material as the first electrode (410) and can be formed on the same layer as the first electrode (410). The light-blocking layer (550) can be placed between the second planarization layer (280) and the bank layer (290), and can be formed larger than the thin-film transistor to block light (L) from being incident on the semiconductor layer (312, 322, 332).

[0194] According to an embodiment of the present specification, the light-blocking layer (550) can be freely formed without being connected to other components. For example, the light-blocking layer (550) may be superimposed on the first thin-film transistor (310) and the second thin-film transistor (320), which undergo significant degradation, but may not be superimposed on the third thin-film transistor (330), which undergoes relatively less degradation. By selectively superimposing the light-blocking layer (550) on each thin-film transistor, the degree of degradation of the entire thin-film transistor can be uniformly adjusted.

[0195] The location where the light-blocking layer (550) is placed is not limited to this, and can be freely formed to overlap one or more thin-film transistors that need to block light (L) primarily.

[0196] A display device according to the present specification may be described as follows.

[0197] A display device according to the present specification may include a substrate comprising a display area and a non-display area, a gate line and a data line intersecting the gate line disposed on the substrate, a plurality of light-emitting elements disposed on the gate line and the data line and comprising a first electrode, a light-emitting layer, and a second electrode, and a first thin-film transistor and a second thin-film transistor disposed below the plurality of light-emitting elements.

[0198] In addition, on the first thin-film transistor or the second thin-film transistor, a light-blocking layer may be further included that is disposed on the same layer as the first electrode and overlaps with one or more of the first thin-film transistor and the second thin-film transistor.

[0199] According to some embodiments of the present specification, the light-blocking layer may be separated from the first electrode.

[0200] According to some embodiments of the present specification, the light-blocking layer may include the same material as the first electrode.

[0201] According to some embodiments of the present specification, a light-blocking layer in the display area may be connected to a second electrode.

[0202] According to some embodiments of the present specification, a common voltage line disposed in a non-display area may be further included, and the common voltage line may be connected to a second electrode and a light-shielding layer.

[0203] According to some embodiments of the present specification, the light-blocking layer is arranged continuously between a plurality of light-emitting elements and may be in the form of a line.

[0204] According to some embodiments of the present specification, the light-blocking layer may be spaced apart from the first thin-film transistor and overlap with the second thin-film transistor.

[0205] According to some embodiments of the present specification, the first thin-film transistor may be a driving transistor, and the second thin-film transistor may be a switching transistor.

[0206] According to some embodiments of the present specification, the first thin-film transistor comprises a first semiconductor layer, and the second thin-film transistor comprises a second semiconductor layer, and the first semiconductor layer and the second semiconductor layer may be oxide semiconductor layers.

[0207] According to some embodiments of the present specification, a third thin-film transistor may be further included, which is connected to the first thin-film transistor and the light-emitting element and supplies a driving current to the light-emitting element.

[0208] According to some embodiments of the present specification, the device further comprises a gate driver disposed in a non-display area and supplying a gate signal to a gate line, and a fourth thin-film transistor having a fourth semiconductor layer included in the gate driver, wherein the fourth semiconductor layer may be a polycrystalline semiconductor layer.

[0209] A display device according to the present specification may include a substrate having a display area and a non-display area, a gate line and a data line intersecting the gate line disposed on the substrate, a plurality of light-emitting elements disposed on the gate line and the data line and including a first electrode, a light-emitting layer, and a second electrode, a driving transistor and a plurality of switching transistors disposed below the plurality of light-emitting elements.

[0210] In addition, on a driving transistor or a plurality of switching transistors, a light-blocking layer may be further included that is disposed on the same layer as the first electrode and overlaps with one of the plurality of switching transistors.

[0211] According to some embodiments of the present specification, the light-blocking layer may not overlap with the plurality of switching transistors except for one of the plurality of switching transistors.

[0212] Although embodiments of the present invention have been described in more detail with reference to the attached drawings, the present invention is not necessarily limited to these embodiments and may be modified in various ways within the scope of the technical spirit of the present invention. Accordingly, the embodiments disclosed in the present invention are intended to explain, not limit, the technical spirit of the present invention, and the scope of the technical spirit of the present invention is not limited by these embodiments. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. The scope of protection of the present invention shall be interpreted by the claims, and all technical spirits within an equivalent scope shall be interpreted as being included within the scope of rights of the present invention. Explanation of the symbols

[0213] 10 : Display device 110 : Substrate 115 : Gate driver 117 : Data driver NA : Non-display area AA : Display area BA: Bending area DL: Data line GL : Gate line PX: Subpixel ED: Light-emitting element 410: First electrode 420 : Emissive layer 430 : Second electrode 210: First gate insulating layer 220 : First interlayer insulation layer 230: First upper buffer layer 240: Second upper buffer layer 250 : Second gate insulating layer 260 : Second interlayer insulation layer 270 : First leveling layer 280 : Second leveling layer 290 : Bank layer 311, 321, 331: Lower gate electrode (lower light-shielding layer) 310: First thin-film transistor 320 : Second thin-film transistor 330 : Third thin-film transistor 340: Storage capacitor 350: 4th thin-film transistor 360 : First connecting electrode 370: Common voltage line 380 : Second connecting electrode 430H: Second electrode contact hole 500, 550: Shading layer Data : Data voltage SC1: First scan signal SC2: Second scan signal EVDD: First driving voltage EVSS: Second driving voltage N1~N4: 1st~4th nodes DT: Driving transistor T1~T5: 1st~5th switching transistors Cst: Storage capacitor

Claims

Claim 1 A display device comprising: a substrate including a display area and a non-display area; a plurality of light-emitting elements disposed in the display area and including a first electrode, a light-emitting layer, and a second electrode; a plurality of transistors disposed on the substrate; and a light-blocking layer disposed on the plurality of transistors, wherein the light-blocking layer overlaps with at least one first transistor having an oxide semiconductor layer and does not overlap with at least one second transistor having a polycrystalline semiconductor layer. Claim 2 A display device according to claim 1, wherein the at least one first transistor having the oxide semiconductor layer is a driving transistor. Claim 3 A display device according to claim 1, wherein the at least one second transistor having the polycrystalline semiconductor layer is a switching transistor. Claim 4 A display device according to claim 1, wherein the light-blocking layer is spaced apart from the first electrode. Claim 5 A display device according to claim 1, wherein the light-blocking layer and the first electrode comprise the same material. Claim 6 A display device according to claim 1, wherein the light-blocking layer is superimposed on two first transistors having an oxide semiconductor layer, and the two first transistors are a driving transistor and a switching transistor connected to the gate electrode and the drain electrode of the driving transistor. Claim 7 A display device according to claim 6, wherein each of the driving transistor and the switching transistor further comprises a lower light-blocking layer disposed below the oxide semiconductor layer. Claim 8 A display device according to claim 1, wherein at least one second transistor is located below the first electrode and overlaps with the first electrode. Claim 9 A display device according to claim 1, further comprising: gate lines and data lines disposed on the substrate and intersecting each other; a gate driver disposed in the non-display area and supplying a gate signal to the gate lines; and a thin-film transistor included in the gate driver and having a polycrystalline semiconductor layer. Claim 10 In claim 9, the display device wherein the light-blocking layer does not overlap with the thin-film transistor. Claim 11 A display device comprising: a substrate including a display area and a non-display area; a plurality of light-emitting elements disposed on the display area and including a first electrode, a light-emitting layer, and a second electrode; a driving transistor and a plurality of switching transistors disposed below each of the plurality of light-emitting elements; and a light-blocking layer disposed on the driving transistor and the plurality of switching transistors, wherein the light-blocking layer and the first electrode are disposed in the same vertical position, the light-blocking layer overlaps with one of the plurality of switching transistors and does not overlap with the remaining switching transistors excluding the one of the plurality of switching transistors, and the one of the plurality of switching transistors is connected to the gate electrode and the drain electrode of the driving transistor. Claim 12 A display device according to claim 11, wherein the light-blocking layer overlaps not only with any one of the plurality of switching transistors but also with the driving transistor, the driving transistor includes a first semiconductor layer, any one of the plurality of switching transistors includes a second semiconductor layer, and the first semiconductor layer and the second semiconductor layer are arranged in the same vertical position. Claim 13 In claim 11, the light-blocking layer extends between adjacent light-emitting elements among the plurality of light-emitting elements and has a linear shape, a display device.

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