Device and method for performing refresh rate change in adaptive synchronization operation

Abstract

According to various embodiments of the present disclosure, a method of operating a source device is provided, comprising: receiving a hot plug detection (HPD) signal from a sink device; receiving first information related to an Extended Display Identification (EDID) or Display ID (DPID) from the sink device; identifying information on the minimum number of frames related to an Adaptive-Sync operation based on the first information of the sink device; performing rendering for video information in which the refresh rate changes from a first refresh rate to a second refresh rate, such that the number of frames is greater than or equal to the minimum number information is maintained at a third refresh rate between the first refresh rate and the second refresh rate; and transmitting the rendered video information to the sink device.

Description

Technology Field

[0001] The present disclosure relates to an apparatus and method for performing a refresh rate change in an Adaptive-Sync operation. Specifically, the present disclosure relates to an apparatus and method for setting a minimum number of frames to be maintained when changing the refresh rate in an Adaptive-Sync operation. Background Technology

[0002] The Successive Frame Duration Increase / Decrease Tolerance parameter, located in the Adaptive-Sync Data block of DisplayID, can control the amount of refresh rate change based on the Max Single Frame Duration. However, since this method operates only on each individual frame, the slope of the brightness change can be abrupt.

[0003] However, if adaptive-sync operation is performed through a minimum frame operation setting based on the minimum adaptive-sync frame number proposed in various embodiments of the present invention, the slope of brightness change according to the frame can be made gentler compared to existing functions, thereby allowing the user to perceive less change in brightness when switching frame rates. The minimum frame operation setting based on the minimum adaptive-sync frame number proposed in various embodiments of the present invention can be used in conjunction with successive frame duration increase / decrease, as well as exert a technical effect independently.

[0004] The minimum frame operation setting based on the minimum adaptive-sync frame number proposed in various embodiments of the present invention can be used in conjunction with successive frame duration increase / decrease or can be used alone. The problem to be solved

[0005] To solve the aforementioned problems, the present disclosure provides an apparatus and method for performing a refresh rate change in an adaptive-sync operation.

[0006] The present disclosure provides an apparatus and method for setting a minimum number of frames to be maintained when changing the refresh rate in an adaptive synchronization operation.

[0007] The technical problems to be solved in this disclosure are not limited to those mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art to which this disclosure belongs from the description below. means of solving the problem

[0008] According to various embodiments of the present disclosure, a method of operating a source device is provided, comprising: receiving a hot plug detection (HPD) signal from a sink device; receiving first information related to an Extended Display Identification (EDID) or Display ID (DPID) from the sink device; identifying information on the minimum number of frames related to an Adaptive-Sync operation based on the first information of the sink device; performing rendering for video information in which the refresh rate changes from a first refresh rate to a second refresh rate, such that the number of frames is greater than or equal to the minimum number information is maintained at a third refresh rate between the first refresh rate and the second refresh rate; and transmitting the rendered video information to the sink device.

[0009] According to various embodiments of the present disclosure, a source device comprises: a processor; a memory; and a transceiver, wherein the memory stores instructions for performing operations based on execution by the processor, the operations comprising: receiving a hot plug detection (HPD) signal from a sink device; receiving first information related to an Extended Display Identification (EDID) or Display ID (DPID) from the sink device; identifying information on the minimum number of frames related to an Adaptive-Sync operation based on the first information from the sink device; performing rendering for video information in which the refresh rate changes from a first refresh rate to a second refresh rate, such that the number of frames is greater than or equal to the minimum number information at a third refresh rate between the first refresh rate and the second refresh rate; and transmitting the rendered video information to the sink device.

[0010] According to various embodiments of the present disclosure, a computer-readable medium is provided that stores one or more instructions, wherein the one or more instructions perform operations based on being executed by one or more processors, and the operations include: receiving a hot plug detection (HPD) signal from a sink device; receiving first information related to an Extended Display Identification (EDID) or Display ID (DPID) from the sink device; identifying information on a minimum number of frames related to an Adaptive-Sync operation based on the first information from the sink device; performing rendering for video information in which the refresh rate changes from a first refresh rate to a second refresh rate, such that the number of frames is greater than or equal to the minimum number information at a third refresh rate between the first refresh rate and the second refresh rate; and transmitting the rendered video information to the sink device. Effects of the invention

[0011] To solve the aforementioned problems, the present disclosure may provide an apparatus and method for performing a refresh rate change in an adaptive-sync operation.

[0012] The present disclosure may provide an apparatus and method for setting a minimum number of frames to be maintained when changing the refresh rate in an adaptive synchronization operation. Brief explanation of the drawing

[0013] The drawings attached below are intended to aid in understanding the present disclosure and may provide embodiments of the present disclosure together with the detailed description. However, the technical features of the present disclosure are not limited to specific drawings, and the features disclosed in each drawing may be combined with one another to form new embodiments. Reference numerals in each drawing may denote structural elements. FIG. 1 is a block diagram showing a system according to various embodiments of the present disclosure. FIG. 2 is a diagram illustrating an example of Adaptive-Sync SDP transmission timing according to various embodiments of the present disclosure. FIG. 3 is a drawing illustrating an example of the structure of a Display Range Limit Block in EDID 1.4 according to various embodiments of the present disclosure. FIG. 4 is a diagram illustrating an example of the structure of an Adaptive-Sync Data Block in DisplayID 2.0 / 2.1 / 2.1a according to various embodiments of the present disclosure. Figure 5 is a diagram illustrating an example of brightness change according to the frame when both the Maximum Single Frame Duration Increase function and the Minimum Frame number function are not applied. Figure 6 is a diagram illustrating an example of brightness change according to the frame when the Maximum Single Frame Duration Increase function is applied and the Minimum Frame number function is not applied. Figure 7 is a diagram illustrating an example of brightness change according to the frame when both the Maximum Single Frame Duration Increase function and the Minimum Frame number function are applied. FIG. 8 is a diagram illustrating an example of the process of determining the Frame Range when the Source device performs an Adaptive-Sync operation. FIG. 9 is a diagram illustrating an example of a process for determining a Frame Range when a Source device performs an Adaptive-Sync operation according to various embodiments of the present disclosure. FIG. 10 is a diagram illustrating an example of a signal flow diagram between a Source device and a Sink device according to various embodiments of the present disclosure. FIG. 11 is a diagram illustrating an example of a signal flow diagram between a Source device and a Sink device according to various embodiments of the present disclosure. FIG. 12 is a drawing illustrating an example of a method of operation of a Source device according to various embodiments of the present disclosure. Specific details for implementing the invention

[0014] In various embodiments of the present disclosure, "A or B" may mean "only A," "only B," or "both A and B." Alternatively, in various embodiments of the present disclosure, "A or B" may be interpreted as "A and / or B." For example, in various embodiments of the present disclosure, "A, B or C" may mean "only A," "only B," "only C," or "any combination of A, B and C."

[0015] In various embodiments of the present disclosure, a slash ( / ) or a comma used may mean "and / or." For example, "A / B" may mean "A and / or B." Accordingly, "A / B" may mean "only A," "only B," or "both A and B." For example, "A, B, C" may mean "A, B or C."

[0016] In various embodiments of the present disclosure, "at least one of A and B" may mean "only A," "only B," or "both A and B." Additionally, in various embodiments of the present disclosure, the expressions "at least one of A or B" or "at least one of A and / or B" may be interpreted as synonymous with "at least one of A and B."

[0017] Additionally, in various embodiments of the present disclosure, “at least one of A, B and C” may mean “only A,” “only B,” “only C,” or “any combination of A, B and C.” Also, “at least one of A, B or C” or “at least one of A, B and / or C” may mean “at least one of A, B and C.”

[0018] FIG. 1 is a block diagram showing a system according to various embodiments of the present disclosure.

[0019] Hereinafter, devices that transmit and receive video, audio, and control data will be collectively referred to as AV (audio / video) systems. Examples of AV systems include HDMI and DisplayPort.

[0020] Referring to FIG. 1, the AV system may include a source device (100) and a sink device (200). In particular, in the AV system, the device that transmits video / audio data corresponds to the source device (100), and the device that receives video / audio data corresponds to the sink device (200). At this time, cables and connectors may be provided as physical devices that connect the two devices to support data transmission and reception.

[0021] Cables and connectors can perform pairing of four channels providing TMDS (Transition Minimized Differential Signaling) data channels and TMDS clock channels. TMDS data channels can be used to transmit video data, audio data, and auxiliary data.

[0022] Additionally, the AV system provides the VESA (Video Electronics Standards Association) Display Data Channel (DDC). The DDC is used for exchanging configuration and status information between source and sink devices. The CEC protocol can provide high-level control functions between various audio-visual products in the user environment and may be used optionally. Furthermore, the optional HDMI Ethernet and Audio Return Channel (HEAC) may provide Ethernet-compatible data networking between the Audio Return Channel (ARC) and connected devices from the opposite direction from the TMDS.

[0023] Video data, audio data, and auxiliary data can be transmitted / received through three TMDS data channels. The TMDS clock typically runs the video pixel rate and is transmitted through the TMDS clock channel. The TMDS clock can be used as a frequency reference for data recovery in the three TMDS data channels at the receiver. At the source device, 8 bits of data per TMDS data channel can be converted into a 10-bit DC-balanced, transition-minimized sequence and transmitted serially at a rate of 10 bits per TMDS clock period.

[0024] To transmit audio data and auxiliary data through TMDS channels, AV systems use a packet structure. To achieve high reliability for audio data and control data, data can be transmitted as 10-bit words generated using BCH error correction codes and error reduction coding.

[0025] The source device can read the E-EDID (Enhanced Extended Display Identification Data) of the DDC (Display Data Channel) sink device to determine the configuration information and available functions of the sink device. The E-EDID may also be referred to as EDID information below.

[0026] The utility line can be used for optional extension functions such as HEAC.

[0027] The source device (100) can receive EDID (Extended Display Identification Data) information from the sink device (200) through a DDC channel. The source device (100) can parse the received EDID information to recognize configuration information and support functions of the sink device (200). The EDID information may include at least one block containing various information regarding the sink device (200).

[0028] In particular, EDID information according to one embodiment of the present invention may include information regarding the function and power supply capability of the sink device (200) in power transmission and reception. The source device (100) recognizes the power transmission / reception capability of the sink device (200) through this EDID information and, accordingly, can transmit power to the sink device (200) or receive power from the sink device (200).

[0029] The source device (100) includes at least one of a display unit (110), a user input interface unit (120), a control unit (180), a transmitter (Tx), a memory unit (140), a storage unit (150), a multimedia unit (160), a power control unit (130), and a power supply unit (170).

[0030] The sink device (200) includes at least one of an EDID EEPROM (210), a power control unit (220), a display unit (230), a user input interface unit (240), a receiver (Rx), a control unit (280), a power supply unit (250), a memory unit (260), and a multimedia unit (270). In the following description, the description of units performing the same operation will not be duplicated.

[0031] The source device (100) represents a physical device that transmits or streams content stored in the storage unit (150) to the sink device (200). The source device (100) can send a request message to the sink device (200) or receive and process a request message received from the sink device (200). The source device (100) can provide a UI that processes a response message sent by the sink device (200) in response to the transmitted request message and delivers it to the user, and if the source device (100) includes a display unit (110), this UI can be provided as a display. Additionally, the source device (100) can request power to be supplied from the sink device (200).

[0032] The sink device (200) receives content from the source device (100) and can send a request message to the source device (100) or process a message received from the source device (100) and send a response message. The sink device (200) can also provide a User Interface (UI) that processes a response message received from the source device (100) and delivers it to a user, and if the sink device (200) includes a display unit, it can provide this UI as a display. Additionally, the sink device (200) can supply power requested by the source device (100) to the source device (100).

[0033] The user input interface unit (120, 240) can receive user action or input, and as an example, the user input interface (120, 240) may correspond to a remote controller, a voice receiving / recognition device, a touch input sensing / receiving device, etc.

[0034] The control unit (180, 280) can control the overall operation of each device. In particular, the control unit (180, 280) can perform communication between the units included in each device and control the operation of each unit.

[0035] The memory unit (140, 260) represents a volatile physical device in which various types of data are temporarily stored.

[0036] A storage unit (150) represents a non-volatile physical device capable of storing various types of data.

[0037] The EDID EEPROM (210) represents an EEPROM that stores EDID information.

[0038] The memory unit (140, 260), storage unit (150), and EDID EEPROM (210) described above all serve the function of storing data, and they may all be collectively referred to as memory units.

[0039] The display unit (110, 230) can display received data or content, data stored in the memory unit, UI, etc., under the control of the control unit (180, 280).

[0040] The multimedia unit (160, 270) can play various types of multimedia. The multimedia unit (160, 270) may be implemented separately from the control unit (180, 280) or may be implemented as a single physical configuration with the control unit (180, 280).

[0041] The power supply unit (170, 250) can supply power required for the operation of the source device (100), the sink device (200), and the units included therein.

[0042] The transmitter (Tx) is a unit equipped in the source device (100) for transmitting and receiving data, and performs data transmission and reception including not only audio / video data but also messages such as commands, requests, actions, and responses between devices.

[0043] The receiver (Rx) is a unit equipped in the sink device (200) for transmitting and receiving data, and performs data transmission and reception including not only audio / video data but also messages such as commands, requests, actions, and responses between devices.

[0044] The power control unit (130, 220) can manage and control power transmission and reception between devices through the transceiver.

[0045] Among the units described above, units other than the transmitter (Rx), receiver (Tx), and control unit (180, 280) may be optionally included in the source device (100) or sink device (200) according to the embodiment and may not correspond to essential component units.

[0046] Previously, power transfer between source and sink devices was not supported in AV systems. As a result, when operating portable devices for extended periods, there was the inconvenience of having to constantly connect an external power cable to ensure optimal operation. To resolve this inconvenience, this specification proposes a method to ensure optimal operation of the AV system without the need for a separate external device by enabling a wired interface in the AV system to support a power transfer function.

[0047] For the sake of convenience of explanation, the device supplying (or transmitting) power will be referred to as the P-Source device, and the device receiving (or supplying) power will be referred to as the P-Sync device. Additionally, a device that simultaneously supports the functions of both the P-Source device and the P-Sync device will be referred to as a Dual device.

[0048] 본 개시의 다양한 실시 예들에 대한 배경기술

[0049] Adaptive-Sync 동작

[0050] Adaptive-Sync is a technology used in the field of computer graphics that eliminates screen flickering and tearing by synchronizing the graphics card and the monitor. Adaptive-Sync was standardized by the Video Electronics Standards Association (VESA) alongside DisplayPort Adaptive-Sync and HDMI VRR (Variable Refresh Rate) technologies.

[0051] Adaptive-Sync technology includes communication protocols for communication between the graphics card and the monitor, and time division technology for synchronization between the graphics card and the monitor. Therefore, Adaptive-Sync technology includes the following technological fields.

[0052] - Graphics Card Technology: To support Adaptive-Sync, the graphics card must support Variable Refresh Rate (VRR) technology. AMD provides its VRR technology through FreeSync, while NVIDIA provides it through G-Sync.

[0053] - Communication Protocol Technology: DisplayPort 1.2a or higher and HDMI 2.1 or higher are required as display connection interfaces that support Adaptive-Sync. Additionally, to use Adaptive-Sync, the graphics card and the monitor must use the same communication protocol.

[0054] - Monitor Technology: Monitors that support Adaptive-Sync must support the graphics card's VRR technology. Additionally, monitors that support Adaptive-Sync must support a protocol for communication with the graphics card.

[0055] - Time Division Technology: Adaptive-Sync uses time division technology to synchronize between the monitor and the graphics card. For this to work, the graphics card and the monitor must use the same time division technology.

[0056] Adaptive-Sync technology encompasses various technological fields, including graphics cards, communication protocols, monitors, and time division technology, and Adaptive-Sync is made possible when these technologies work together.

[0057] Source device operation during live frame transmission

[0058] The source device with the PANEL REPLAY ENABLE register (DPCD 001B0h[0] = 1) that enables the panel playback mode of the sink device and has set all ALPM enable bits (DPCD 00116h[0] = 1) of the RECEIVER_ALPM_CONFIGURATION register is as follows. It transmits the Adaptive-Sync SDP on the VBlank line corresponding to one of the following.

[0059] (1) The leading edge of the VSync pulse -or-

[0060] (2) One line ahead of the leading edge of the VSync pulse, starting from the first video frame as shown in Figure 2-155

[0061] If the source device does not set both bits (DPCD 001B0h[0] = 0 and / or DPCD 00116h[0] = 0), the source device may transmit on or before the line specified above during the VBlank period.

[0062] Source Device Operation during Live Frame Transmission

[0063] A Source device that has set both the Source Device Enables Panel Replay Mode in Sink Device bit in the PANEL REPLAY ENABLE register (DPCD 001B0h[0] = 1) and ALPM Enable bit in theRECEIVER_ALPM_CONFIGURATION register (DPCD 00116h[0] = 1) shall transmit the Adaptive-Sync SDP at the VBlank line that corresponds to either of the following:

[0064] (1) The VSync pulse's leading edge, -or-

[0065] (2) One line before the VSync pulse's leading edge, starting with the first video frame, as illustrated in Figure 2-155

[0066] When a Source device has not set both bits (DPCD 001B0h[0] = 0 and / or DPCD 00116h[0] = 0), the Source device may transmit at the line specified above -or- earlier during the VBlank period.

[0067] FIG. 2 is a diagram illustrating an example of Adaptive-Sync SDP transmission timing according to various embodiments of the present disclosure.

[0068] The following requirements apply to the source device regarding whether to transmit the Adaptive-Sync SDP on the leading edge of the VSync pulse or one line prior.

[0069] (1) When DPCD 02214h[1] = 0 of the sink device, the source device must maintain DPCD 0011Bh[7] = 0 and transmit the Adaptive-Sync SDP on the first one that comes from the line corresponding to the leading edge of the VSync pulse, either in the first half line or the first 3,840 pixel cycle.

[0070] (2) When DPCD 02214h[1] = 1 of the Sink device, the Source device can perform one of the following.

[0071] (3) During video mode setting, set DPCD 0011Bh[7] = 1 and then transmit the entire Adaptive-Sync SDP one line earlier at any time.

[0072] (4) During video mode setting, DPCD 0011Bh[7] = 0 is cleared and the Adaptive-Sync SDP is transmitted on the first line of the line corresponding to the leading edge of the VSync pulse or on the first 1,920 pixel cycle, whichever comes first.

[0073] As for whether to transmit the Adaptive-Sync SDP on the VSync pulse's leading edge or one line earlier, the following mandates apply for the Source device:

[0074] (1) When the Sink device's DPCD 02214h[1] = 0, the Source device shall keep DPCD 0011Bh[7] = 0 and transmit the Adaptive-Sync SDP in the first half line -or- the first 3,840 pixel cycles, whichever comes first, on the line that corresponds to the VSync pulse's leading edge

[0075] (2) When the Sink device's DPCD 02214h[1] = 1, the Source device may perform either of the following:

[0076] (3) Set DPCD 0011Bh[7] = 1 during video mode set, and then transmit the entire Adaptive-Sync SDP one line earlier, at any time during the line, -or-

[0077] (4) Clear DPCD 0011Bh[7] = 0 during video mode set, and then transmit the Adaptive-Sync SDP in the first half line -or- the first 1,920 pixel cycles, whichever comes first, on the line that corresponds to the VSync pulse's leading edge

[0078] Adaptive-Sync 동작 관련 DPCD

[0079] DPCD (DisplayPort Configuration Data Channel) is part of the DisplayPort connection interface and is a data channel for communication between a display device and a graphics card. DPCD is used for the graphics card to recognize the display device, configure its functions, and share the DP connection status with the monitor. The configurations related to Adaptive-Sync DPCD operation are as follows.

[0080] (1) Source device adaptive synchronization operation requirements

[0081] This section defines the source device specifications for the following Adaptive-Sync policies.

[0082] (1-1) Before and during video mode settings

[0083] (1-2) Live frame transmission in progress

[0084] Before setting the video mode, the source device must verify the following.

[0085] (1-3) The Stream Sink of the connected Sink device meets the following VESA AdaptiveSync requirements.

[0086] (1-3-1) DisplayID Adaptive-Sync Data Block Support

[0087] (1-3-2) CVT v2.0 supports detailed timing with RB v3 timing or a 350 ppm offset exposed in DisplayID.

[0088] (1-4) The DPRX of the connected sink device meets the VESA AdaptiveSync standard.

[0089] (1-4-1) DPCD 00007h[6] = 1 and DPCD 02207h[6] = 1

[0090] (1-4-2) DPCD 02214h[0] = 1

[0091] (1) Source Device Adaptive-Sync Operation Mandates

[0092] This section defines Source device mandates for the following Adaptive-Sync policies:

[0093] (1-1) Before and during video mode set

[0094] (1-2) During live frame transmission

[0095] Before video mode set operation, a Source device shall verify the following:

[0096] (1-3) Stream Sink in the connected Sink device meets the following VESA AdaptiveSync mandates:

[0097] (1-3-1) Supports the DisplayID Adaptive-Sync data block

[0098] (1-3-2) Supports the CVT v2.0 RB v3 timing -or- detailed timing with 350-ppm offset exposed in the DisplayID

[0099] (1-4) DPRX in the connected Sink device meets the VESA AdaptiveSync mandates:

[0100] (1-4-1) DPCD 00007h[6] = 1 and DPCD 02207h[6] = 1

[0101] (1-4-2) DPCD 02214h[0] = 1

[0102] (2) Requirements for adaptive synchronization operation of the sink device

[0103] This section defines the sync device specifications for the following Adaptive-Sync policies.

[0104] (2-1) Before and during video mode settings

[0105] (2-2) Live frame transmission in progress

[0106] The VESA AdaptiveSync sync device must meet the following requirements.

[0107] (2-3) DisplayID Adaptive-Sync Data Block Support

[0108] (2-4) CVT v2.0 RB v3 timing support or detailed timing support with a 350ppm offset exposed in DisplayID

[0109] (2-5) Adaptive-Sync SDP v2 support (HB2[4:0] = 02h)

[0110] (2-6) Set the following Adaptive-Sync DPCD function register bits to their default values.

[0111] (2-6-1) DPCD 00007h[6] = 1 and DPCD 02207h[6] = 1

[0112] (2-6-2) DPCD 02214h[0] = 1

[0113] (2-7) Set DPCD 02214h[1] = 1 as needed

[0114] (2-8) This is an Arm for Adaptive-Sync operation when the source device writes DPCD 00107h[7] = 1 while video mode is set.

[0115] (2-9) Since the sink device can be connected to a legacy source device that has set DPCD 00107h[7] = 1, it begins receiving the video stream after the video mode setup operation and must check for the Adaptive-Sync SDP, but does not transmit the Adaptive-Sync SDP. As long as all of the following conditions are met, the VESA AdaptiveSync Sink device must parse the Adaptive-Sync SDP payload data bytes and display the image within the latency limit while meeting the Adaptive-Sync display CTS visual performance requirements (e.g., flicker performance of -50dB or greater, panel overdrive compensation, responsive gray-to-gray transition that does not cause ghosting):

[0116] (2-10) The source device follows the frame duration increase and decrease limits of the sink device listed in the Adaptive-Sync data block (bytes 1 and 5, respectively).

[0117] (2-11) The Adaptive-Sync SDP payload content is true. The VESA AdaptiveSync sink device must also meet minimum visual performance requirements (e.g., -45dB flicker performance) as long as the source device adheres to the minimum-maximum refresh range. This is also true even if the Adaptive-Sync SDP payload content is false for one frame during the Adaptive-Sync operation mode transition.

[0118] (2) Sink Device Adaptive-Sync Operation Mandates

[0119] This section defines Sink device mandates for the following Adaptive-Sync policies:

[0120] (2-1) Before and during video mode set

[0121] (2-2) During live frame transmission

[0122] A VESA AdaptiveSync Sink device shall:

[0123] (2-3) Support the DisplayID Adaptive-Sync data block

[0124] (2-4) Support the CVT v2.0 RB v3 timing -or- detailed timing with 350-ppm offset exposed in the DisplayID

[0125] (2-5) Support Adaptive-Sync SDP v2 (HB2[4:0] = 02h)

[0126] (2-6) Set the following Adaptive-Sync DPCD capability register bits as default:

[0127] (2-6-1) DPCD 00007h[6] = 1 and DPCD 02207h[6] = 1

[0128] (2-6-2) DPCD 02214h[0] = 1

[0129] (2-7) Set DPCD 02214h[1] = 1, as needed

[0130] (2-8) Arm for Adaptive-Sync operation when a Source device writes DPCD 00107h[7] = 1 during video mode set

[0131] (2-9) Sink device shall check for the presence of an Adaptive-Sync SDP as the Sink device starts receiving a video stream after video mode set operation because the Sink device may be connected to a legacy Source device that sets DPCD 00107h[7] = 1 but does not transmit an Adaptive-Sync SDP A VESA AdaptiveSync Sink device shall parse Adaptive-Sync SDP payload data bytes and display an image within a latency limit while meeting Adaptive-Sync Display CTS visual performance mandates (e.g., flicker performance of -50 dB or better, a responsive gray-to-gray transition without causing panel overdrive compensation ghosting), as long as both of the following conditions are met:

[0132] (2-10) Source device honors the Sink device's Frame Duration Increase and Decrease Limits that are enumerated in the Adaptive-Sync data block (Bytes 1 and 5, respectively)

[0133] (2-11) Adaptive-Sync SDP payload content is true

[0134] The VESA AdaptiveSync Sink device shall also meet the minimum visual performance mandates (eg, a flicker performance of -45 dB) as long as the Source device honors the minimum-to-maximum refresh range even when the Adaptive-Sync SDP payload content is false for one frame during an Adaptive-Sync operation mode transition.

[0135] (3) DPCD register used for Adaptive-Sync

[0136] (3) DPCD Registers used for Adaptive-Sync

[0137] The following Table 1 shows Table 2-220: DPCD Registers Used for Adaptive-Sync.

[0138] Type DPCD Register Address Name Capability 0007h[6] DOWN_STREAM_PORT_COUNT register,MSA_TIMING_PAR_IGNORED bit Extended Capability 02207h[6] DOWN_STREAM_PORT_COUNT register,MSA_TIMING_PAR_IGNORED bit 02215h[2,1,0] DPRX_FREATURE_ENUMERATION_LIST_CONT_1 register,FAVT_PAYLOAD_FIELDS_PARSING_SUPPORTED,AS_SDP_FIRST_HALF_LINE_OR_3840_PIXEL_CYCLE_WINDOW_NOT_SUPPORTED, andADAPTIVE_SYNC_SDP_SUPPORTED bits, respectively 02218h[6] DPRX_FEATURE_ENUMERATION_LIST_CONT_2 register,ADAPTIVE SYNC SDP T2 SUPPORTED IN ALL PR ACTIVE STATES bit Configuration 00107h[7,6] DOWNSPREAD_CTRL register, MSA_TIMING_PAR_IGNORE_EN andFIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE bits 0011Ah[7:6] PANEL REPLAY CONFIGURATION 3 register,AS_SDP_SETUP_CONFIG_PR_ACTIVE field 0011Bh[7] ADAPTIVE_SYNC_SDP_TRANSMISSION_TIMING_CONFIG register,AS_SDP_ONE_LINE_EARLIER_ENABLE bit

[0139] Adaptive-Sync 동작 관련 EDID - DisplayID에서의 Adaptive-Sync Data Block

[0140] FIG. 3 is a drawing illustrating an example of the structure of a Display Range Limit Block in EDID 1.4 according to various embodiments of the present disclosure.

[0141] EDID (Extended Display Identification Data) is a data structure used by a Source device (e.g., GPU) to read information embedded in a Sink device (e.g., a monitor). When the Sink device (e.g., a monitor) provides EDID information, the Source device (e.g., GPU) can automatically recognize and set basic settings such as the optimal resolution and refresh rate of the Sink device (e.g., a monitor).

[0142] The EDID contains manufacturing information for the Sink device (e.g., a monitor), including the manufacturer, model name, date of manufacture, resolution, and supported refresh rate. A Source device (e.g., a GPU) that reads this information can automatically set the optimal resolution and refresh rate of the Sink device (e.g., a monitor), or the user can set them manually.

[0143] Blocks related to Adaptive-Sync operation can be represented as shown in Table 2 below.

[0144] The following Table 2 shows Table 3.26: Display Range Limits & Timing Descriptor Block Definition.

[0145] Byte # Value Display Range Limits Definitions 0, 1 (00 00)h Indicates that this 18 byte descriptor is a Display Descriptor 2 00h Reserved: Set to 00h when 18 byte descriptor is used as a Display Descriptor 3 FDh Tag Number for Display Range Limits Descriptor 4 7 6 5 4 3 2 1 0 Display Range Limits Offsets: FLAGs 0 0 0 0 _ _ 0 0 Vertical Rate Offsets are zero 0 0 0 0 _ _ 1 0 Max. Vertical Rate + 255 Hz Offset; Min. Vertical Rate is not offset 0 0 0 0 _ _ 1 1 Max. Vertical Rate + 255 Hz Offset; Min. Vertical Rate + 255 Hz Offset 0 0 0 0 0 0 Horizontal Rate Offsets are zero 0 0 0 0 1 0 _ _ Max. Horizontal Rate + 255 kHz Offset; Min. Horizontal Rate is not offset 0 0 0 0 1 1 _ _ Max. Horizontal Rate + 255 kHz Offset; Min. Horizontal Rate + 255 kHz Offset 01h, 04h → 07h, 09h,0Dh 10h → FFh Reserved: Do not use 5 01h → FFh Minimum Vertical Rate: (for interlace this refers to the field rate) [Byte 4, Bits 1, 0] ≠ 11 Binary coded rate in Hz, integer only (range is 1 Hz to 255 Hz) [Byte 4, Bits 1, 0] = 11 Binary coded rate in Hz, integer only (range is 256 Hz to 510 Hz) 00h Reserved: Do not use 6 01h → FFh Maximum Vertical Rate: (for interlace this refers to the field rate) [Byte 4, Bit 1] ≠ 11 Binary coded rate in Hz, integer only (range is 1 Hz to 255 Hz) [Byte 4, Bit 1] = 11 Binary coded rate in Hz, integer only (range is 256 Hz to 510 Hz) Note: Minimum rate value shall be less than or equal to maximum rate value 00h Reserved: Do not use 7 01h → FFh Minimum Horizontal Rate: [Byte 4, Bits 3, 2] ≠ 11 Binary coded rate in kHz, integer only (range is 1 kHz to 255 kHz) [Byte 4, Bits 3, 2] = 11 Binary coded rate in kHz, integer only (range is 256 kHz to 510 kHz) 00h Reserved: Do not use 8 01h → FFh Maximum Horizontal Rate: [Byte 4, Bit 3] ≠ 11 Binary coded rate in kHz, integer only (range is 1 kHz to 255 kHz) [Byte 4, Bit 3] = 11 Binary coded rate in kHz, integer only (range is 256 kHz to 510 kHz) Note: Minimum rate value shall be less than or equal to maximum rate value 00h Reserved: Do not use 9 01h → FFh Maximum Pixel Clock: Binary coded clock rate in MHz / 10, Example: 130MHz is '0Dh' Note: Maximum Pixel Clock shall be rounded to the nearest multiple of 10 MHz 00h Reserved: Do Not Use 10 Video Timing Support Flags: Bytes 10 → 17 indicate support for additional video timings 00h Default GTF supported if bit 0 in Feature Support Byte at address 18h = 1 01h Range Limits Only --- no additional timing information is provided 02h Secondary GTF supported --- requires support for Default GTF 04h CVT supported if bit 0 in Feature Support Byte at address 18h = 1 03h, 05h → FFh Reserved for future timing definitions --- Do Not Use 11 0Ah Line Feed (if Byte 10 = 00h or 01h) 00h → FFh Video Timing Data (if Byte 10 = 02h or 04h) --- Refer to Tables 3.27 → 3.28 12 20h Space (if Byte 10 = 00h or 01h) 00h → FFh Video Timing Data (if Byte 10 = 02h or 04h) --- Refer to Tables 3.27 → 3.28

[0146] DisplayID 2.0 / 2.1 / 2.1a에서의 Adaptive-Sync Data Block

[0147] FIG. 4 is a diagram illustrating an example of the structure of an Adaptive-Sync Data Block in DisplayID 2.0 / 2.1 / 2.1a according to various embodiments of the present disclosure.

[0148] The following Table 3 shows Table 4.51: Adaptive-Sync Data Block.

[0149] In Table 3, N represents the number of Detailed Timing descriptors in the data block. M represents the value of Offset 01h[6:4]. Source device implementation shall accommodate varying fields for future extensibility.

[0150] Offset Bit # Definition / Priority 00h 7:0 Adaptive-Sync Data Block2Bh 01h Block Revision and Other Data 2:0 Block RevisionRevision ranges from 0 through 7000b=Revision 0All other values are RESERVED 3 RESERVEDCleared to 0 6:4 Number of Payload Bytes (M) in an Adaptive-Sync Operation ModeAnd Range DescriptorWhere M (bytes) = 6 (initial descriptor size) + field value000b = 6 + 0 bytes / descriptor (defined as part of Adaptive0Sync, Revision 0)All other values are RESERVED 7 RESERVEDCleared to 0 02h 7:0 Number of Payload Bytes in BlockNumber of payload bytes within the block is based on the number of descriptors (N) * size of each descriptor (M) bytesAll other values are RESERVED 03h through03h+M-1 (M*8-1):0 First Adaptive-Sync Operation Mode and Range DescriptorM-byte descriptor 03h+M through 03h + 2M - 1 (M*8-1):0 Second Adaptive-Sync Operation Mode and Range DescriptorM-byte descriptor, if present ... ... 03h +(N-1) * M through03h+ (N*M) - 1 (M*8-1):0 Nth Adaptive-Sync Operation Mode and Range DescriptorM-byte descriptor, if present

[0151] The following Table 4 shows Table 4.52: Adaptive-Sync Operation Mode and Range Descriptor.

[0152] Byte # Bit # Definition 0 Adaptive-Sync Operation and Range Information 0 Adaptive-Sync Range0 = Non-native panel range. (The display implements buffering to support the declared Adaptive-Sync range, and may repeat frames as necessary.)1 = Native panel range. (The display does not implement buffering to support the declared Adaptive-Sync range, and does not repeat frames.) 1 Successive Frame Duration Increase Tolerance for Meeting VESA Adaptive Sync Flicker Performance0 = Flicker performance is met in any duration increase within the refresh rate range, but may cause up to a single base video frame period jitter impact.1 = Flicker performance is met in any duration increase within Byte 1.Note: Flicker performance is met in any duration increase within the refresh rate range without jitter impact when either of the following conditions are met:(1) Byte 1 = 00h, -or-(2) Byte 1 >= the delta between the maximum frame duration ( = minimum refresh rate) and the minimum frame duration (= maximum refresh rate) 3:2 Supported Adaptive-Sync Modes00b = Fixed-Average VTotal (FAVT) mode is supported01b = Both Fixed-Average VTotal and Adaptive VTotal modes (FAVT and AVT, respectively) are supportedAll other values are RESERVED 4 Seamless Transition of Adaptive-Sync Mode and Range Not Supportd0 = Seamless transition to and from current Adaptive-Sync mode and range is supported1 = Seamless transition to and from current Adaptive-Sync mode and range is not supported 5 Successive Frame Duration Decrease Tolerance for Meeting VESA Adaptive Sync Flicker Performance0 = Flicker performance is met in any duration decrease within the refresh rate range, but may cause up to a single base video frame period jitter impact1 = Flicker performance is met in any duration decrease within Byte 5Note: Flicker performance is met in any duration decrease within the refresh rate range without jitter impact when either of the following conditions are met:(1) Byte 5 = 00h, -or-(2) Byte 5 >= the delta between the maximum frame duration(= minimum refresh rate) and the minimum frame duration (= maximum refresh rate) 7:6 RESERVEDCleared to all 0s 1 7:0 Maximum Single Frame Duration Increase Allowed for Meeting VESA Adaptive Sync Flicker Performance6.2 format (six integer bits and two fractional bits) that results in a value range of 0.00 to 63.75 ms, inclusive00h = Flicker performance is met in any duration increase within the refresh rate range without jitter impact 2 7:0 Minimum Refresh RateMinimum refresh rate ranges from 0 through 255 Hz, divided by 1.00100h = 0 Hz01h = (1 / 1.001) Hz...FFh = (255 / 1.001) Hz 4:3 Maximum Refresh RateMaximum refresh rate ranges from 1 through 1,024 Hz, plus 350 ppm. Note that the value stored in this field shall match that of at least one CVT v2.0 RB Timing v3 timing supported by the Sink device000h = (1*1.00035) Hz...3FFh = (1,024 * 1.00035) Hz 3 7:0 Maximum Refresh Rate 7:0 4 1:0 Maximum Refresh Rate 9:8 7:2 RESERVEDCleared to all 0s 5 7:0 Maximum Single Frame Duration Decrease Allowed for Meeting VESA Adaptive Sync Flicker Performance6.2 format (six integer bits and two fractional bits) that results in a value range of 0.00 to 63.75 ms, inclusive00h = Flicker performance is met in any duration decrease within the refresh rate range without jitter impact

[0153] Adaptive-Sync SDP

[0154] The Adaptive-Sync Second data packet is used for communication between the graphics card and the display. The graphics card sends the Adaptive-Sync Second data packet to the display, and the display receives it to inform the graphics card of the supported refresh rate range and VRR mode. Based on this information, the graphics card synchronizes with the display to prevent screen tearing and stuttering, and enables smoother image display. The information and size of the Adaptive-Sync SDP may vary depending on the Adaptive-Sync operation parameters associated with each EDID Block.

[0155] The information regarding Adaptive-Sync SDP operation and Header and Payload Data Bytes is as follows.

[0156] An Adaptive-Sync enabled DP protocol converter indicates Adaptive-Sync SDP support by setting the ADAPTIVE_SYNC_SDP_SUPPORTED bit in the DPRX_FEATURE_ENUMERATION_LIST_CONT_1 register (DPCD 02214h[0] = 1 and DPCD 02207h[6] = 1), in addition to setting the MSA_TIMING_PAR_IGNORED bit in the DOWN_STREAM_PORT_COUNT register (DPCD 02214h[0] = 1 and DPCD 02207h[6] = 1). An Adaptive-Sync enabled DP protocol converter must support SDP splitting in SST and MST modes and indicate the splitting function by setting the SST_SPLIT_SDP_CAP bit in the DPRX_FEATURE_ENUMERATION_LIST register (DPCD 02210h[1] = 1). An Adaptive-Sync enabled DP source device may enable Adaptive-Sync video transmission to the connected DP protocol converter only after verifying the following.

[0157] (1) The connected DP protocol converter has DPCD 00007h[6] = 1 and DPCD 02214h[0] = 1.

[0158] (2) A stream sink connected to a DP protocol converter indicates support for the Adaptive-Sync refresh rate range in DisplayID or legacy EDID. As is always the case for Adaptive-Sync video transmission, an Adaptive-Sync capable DP source device must write 1 to the MSA_TIMING_PAR_IGNORE_EN bit of the DOWNSPREAD_CTRL register (DPCD 00107h[7] = 1) using an AUX write transaction before enabling Adaptive-Sync video transmission. If the connected DP device has DPCD 02214h[0] = 1, the DP source device must transmit the Adaptive-Sync SDP before enabling Adaptive-Sync video transmission.

[0159] When transmitting Adaptive-Sync SDP, the DP source device must perform the following:

[0160] (3) Transmit Adaptive-Sync SDP in every video frame. For multi-field video modes such as interlaced and 3D, Adaptive-Sync SDP must be transmitted in every video field.

[0161] (4) Check if the start and end of the Adaptive-Sync SDP transmission occur within the first half of the line (indicated by the BS symbol sequence) corresponding to the start of the VSync pulse.

[0162] (5) Send valid HTotal[15:0], HStart[15:0], HSyncPolarity[0](HSP), and HSyncWidth[14:0].

[0163] (HSW), VStart[15:0], VSyncPolarity[0](VSP) 및 VSyncWidth[14:0](VSW)는 Adaptive-Sync SDP를 전송하는 동안 유효한 HWidth[15:0] 및 VHeight[15:0]. 즉, Adaptive-Sync 가능 DP 프로토콜 변환기는 Adaptive-Sync SDP를 수신하는 동안 VTotal[15:0]만 무시해야 한다.

[0164] An Adaptive-Sync-capable DP protocol converter shall indicate Adaptive-Sync SDP support by setting the ADAPTIVE_SYNC_SDP_SUPPORTED bit in the DPRX_FEATURE_ENUMERATION_LIST_CONT_1 register (DPCD 02214h[0] = 1) in addition to setting the MSA_TIMING_PAR_IGNORED bit in the DOWN_STREAM_PORT_COUNT register(s) (DPCD 00007h[6] = 1 and DPCD 02207h[6] = 1). An Adaptive-Sync-capable DP protocol converter shall support SDP splitting in SST and MST modes, and indicates its splitting capability by setting the SST_SPLIT_SDP_CAP bit in the DPRX_FEATURE_ENUMERATION_LIST register (DPCD 02210h[1] = 1). An Adaptive-Sync-capable DP Source device may enable an Adaptive-Sync video transmission to a plugged DP protocol converter only after verifying the following:

[0165] (1) Plugged DP protocol converter has DPCD 00007h[6] = 1 and DPCD 02214h[0] = 1

[0166] (2) Stream sink plugged to the DP protocol converter indicates support for the Adaptive-Sync refresh rate range in the DisplayID or legacy EDID As is always the case with Adaptive-Sync video transmission, an Adaptive-Sync-capable DP Source device shall use an AUX write transaction to write 1 to the MSA_TIMING_PAR_IGNORE_EN bit in the DOWNSPREAD_CTRL register (DPCD 00107h[7] = 1) prior to enabling an Adaptive-Sync video transmission. When the plugged DP device has DPCD 02214h[0] = 1, a DP Source device shall transmit an Adaptive-Sync SDP before enabling an Adaptive-Sync video transmission.

[0167] When transmitting an Adaptive-Sync SDP, a DP Source device shall do the following:

[0168] (3) Transmit an Adaptive-Sync SDP on every video frame. For multi-field video modes such as Interlaced and 3D, the Adaptive-Sync SDP shall be transmitted on every video field.

[0169] (4) Ensure that the start and end of the Adaptive-Sync SDP transmission occur within the 1st half of the line (marked by BS symbol sequences) that corresponds to the start of the VSync pulse.

[0170] (5) Transmit valid HTotal[15:0], HStart[15:0], HSyncPolarity[0] (HSP), HSyncWidth[14:0]

[0171] (HSW), VStart[15:0], VSyncPolarity[0] (VSP), and VSyncWidth[14:0] (VSW) while transmitting an Adaptive-Sync SDP, as well as valid HWidth[15:0] and VHeight[15:0]. That is, an Adaptive-Sync-capable DP protocol converter shall ignore only VTotal[15:0] while receiving an Adaptive-Sync SDP.

[0172] 표 5은 Table 2-126: Adaptive-Sync SDP Header Bytes를 나타낸다.

[0173] Byte # Bit # Content HB0 7:0 Secondary-data Packet IDSpecific to stream (usually 00h) HB1 7:0 Secondary-data Packet Type22h = Adaptive-Sync HB2 4:0 Version Number01h = Version 1. No payload data bytes (same as DP v2.0, as released in June 2019).02h = Version 2. VESA AdaptiveSync shall support both the DisplayID Adaptive-Sync data block and Adaptive-Sync SDP data structure version 2.All other values are RESERVED for future versions. 7:5 RESERVEDRead all 0s HB3 5:0 Number of Valid Data BytesVersion 100h = No payload data bytes.Version 209h = Nine payload data bytes.The Adaptive-Sync SDP has 32 payload data bytes. Unused data bytes shall be zero-padded. 7:6 RESERVEDRead all 0s.

[0174] Table 6 shows Table 2-127: Adaptive-Sync SDP Version 2 Payload Data Bytes.

[0175] Byte # Bit # Content DB0 Timing Options 01 VARIABLE_FRAME_RATE_DISABLEAdaptive Sync Operation ModeWhen a Source device sets the MSA_TIMING_PAR_IGNORE_EN and FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE bits in the DOWNSPREAD_CTRL register (DPCD 00107h [7,6] = 11b, respectively):00b = AVT mode, and video frame duration is bound to change from frame-to-frame.01b = AVT mode; however, video frame duration is currently fixed.10b = FAVT mode, and TRR is yet to be reached.11b = FAVT mode, and TRR is reached.When a Source device programs DPCD 00107h[7,6] = 01b (see Section 2.18 for details):01b = Adaptive-Sync operation is disabled and the VTotal line count is fixed.00b, 10b, and 11b = RESERVED. 2 Adaptive Sync SDP Transmission Disable in PR Active StateCleared to 0 when the Sink device does not support PR.0 = Source-to-Sink device timing sync using the Adaptive-Sync SDP is enabled.1 = Source-to-Sink device timing sync using the Adaptive-Sync SDP is disabled. 3 Remote Frame Buffer (RFB) Update in PR Active StateValid only during a PR Active state. Shall be driven to 0 in PR_State 0_0 (Disabled) -or-PR_State 0_1 (Inactive). Cleared to 0 when the Sink device does not support PR.0 = No RFB update in the current active video image time interval.1 = Update the RFB - Capture the incoming video frame / Sus to the RFB. 7:4 RESERVEDRead all 0s. DB1 7:0 Minimum Vertical Total7:0Minimum Vertical Total15:8Source device shall program DB2:DB1 to the VTotal value that corresponds to the enabled base timing. The value is statically programmed and is valid in both FAVT mode and AVT mode. DB2 7:0 DB3 7:0 Target Refresh Rate7:0Target Refresh Rate9:8AVT modeSource device shall clear DB4[1:0] = 00b and DB3 = 00h.FAVT modeSource device shall program DB4[1:0] and DB3 and DV4[5] to match the average video frame rate. DB4 1:0 4:2 RESERVEDRead all 0s. 5 Target Refresh Rate DividerValid only in FAVT mode. Sink device ignores the bit in AVT mode.0 = 1.000.1 = 1.001. 6 Successive Frame Duration Increase ConfigurationIf the Source device engages in a bounded transition for low-flicker performance by using information in the DisplayID Adaptive-Sync data block and setting this bit to 1, the Source device shall:(1) Use the CVT v2.0 RB Timing v3 -or- detailed timing descriptor with 350-ppm offset exposed in the DisplayID, and(2) Constrain the duration increase to the value reported in the DisplayID Adaptive-Sync data block for a guarantee of low-flicker performance0 = Video frame duration increase transitions are unbounded.1 = Video frame duration increase transitions are bounded by the time specified in DB5. 7 Successive Frame Duration Decrease ConfigurationIf the Source device engages in a bounded transition for low-flicker performance by using the information in the DisplayID Adaptive-Sync data block and setting this bit to 1, the Source device shall:(1) Use the CVT v2.0 RB Timing v3 -or- detailed timing descriptor with 350-ppm offset exposed in the DisplayID, and(2) Constrain the duration decrease to the value reported in the DisplayID Adaptive-Sync data block for a guarantee of low-flicker performance0 = Video frame duration decrease transitions are unbounded.1 = Video frame duration decrease transitions are bounded by the time specified in DB6. DB5 7:0 Duration Increase Constraint Value in ms Unit6.2 format (six integer bits and two fractional bits) that results in a value range of 0.00 to 63.75 ms, inclusive.When the Source device clears DB4[6] = 0, the Source device shall clear DB5 = 00h.When the Source device sets DV4[6] = 1, the Source device shall program DB5 to the value that the Source device is using for the maximum duration increase. The value does not indicate the instantaneous video frame-to-frame duration delta.A 0.00 value indicates that the Source device may invoke a maximum-to-minimum refresh rate transition across a single video frame boundary.To attain optimum flicker performance without jitter impact, the Source device shall keep the DB5 value less than or equal to the limit value reported by the Sink device in the Max Single Frame Duration Increase Allowed for Attaining the Low Flicker Performance byte (Byte 1) of the DisplayID Adaptive-Sync data block's Operation Mode and Range descriptor. DB6 7:0 Duration Decrease Constraint Value in ms Unit6.2 format (six integer bits and two fractional bits) that results in a value range of 0.00 to 63.75 ms, inclusive.When the Source device clears DB4[7] = 0, the Source device shall clear DB6 = 00h.When the Source device sets DB4[7] = 1, the Source device shall program DB6 to the value that the Source device is using for the maximum duration decrease. The value does not indicate the instantaneous video frame-to-frame duration delta.A 0.00 value indicates that the Source device may invoke a maximum-to-minimum refresh rate transition across a single video frame boundary.To attain optimum flicker performance without jitter impact, the Source device shall keep the DB6 value less than or equal to the limit value reported by the Sink device in the Max Single Frame Duration Decrease Allowed for Attaining the Low Flicker Performance byte (Byte 5) of the DisplayID Adaptive-Sync data block's Operation Mode and Range descriptor. DB7 7:0 Coasting VTotal7:0 in PR Active StateShall be programmed to the Coasting Vtotal LSB value that the Sink device shall use to maintain the refresh rate when the DPTX has suspended transmission of the Adaptive-Sync SDP in a PR Active state.DB7 = 00h when the Sink device does not support PR. DB8 7:0 Coasting VTotall15:8 in PR Active StateShall be programmed to the Coasting VTotal MSB value that the Sink device shall use to maintain the refresh rate when the DPTX has suspended transmission of the Adpative-Sync SDP in a PR Active state.DB8 = 00h when the Sink device does not support PR. DB9throughDB31 191:0 RESERVEDRead all 0s.

[0176] Problems with conventional technology

[0177] Figure 5 is a diagram illustrating an example of brightness change according to the frame when both the Maximum Single Frame Duration Increase function and the Minimum Frame number function are not applied.

[0178] Figure 6 is a diagram illustrating an example of brightness change according to the frame when the Maximum Single Frame Duration Increase function is applied and the Minimum Frame number function is not applied.

[0179] Figure 7 is a diagram illustrating an example of brightness change according to the frame when both the Maximum Single Frame Duration Increase function and the Minimum Frame number function are applied.

[0180] The Successive Frame Duration Increase / Decrease Tolerance parameter, located in the Adaptive-Sync Data block of DisplayID, can control the amount of refresh rate change based on the Max Single Frame Duration. However, since this method operates only on each individual frame, the slope of the brightness change can be abrupt.

[0181] However, if adaptive-sync operation is performed through a minimum frame operation setting based on the minimum adaptive-sync frame number proposed in various embodiments of the present invention, the slope of the brightness change according to the frame can be made gentler compared to existing functions, as shown in the embodiment of Figure 7 of Example 1, thereby allowing the user to perceive less change in brightness when switching frame rates. The minimum frame operation setting based on the minimum adaptive-sync frame number proposed in various embodiments of the present invention can be used in conjunction with successive frame duration increase / decrease, as well as exert technical effects independently.

[0182] The minimum frame operation setting based on the minimum adaptive-sync frame number proposed in various embodiments of the present invention can be used in conjunction with successive frame duration increase / decrease or can be used alone.

[0183] Example 1) Case where it changes from 240Hz to 60Hz

[0184] - Maximum Single Frame Duration Increase = 8ms

[0185] - Minimum Multi Frame number = 3 Frame rate

[0186] Figure 5 shows the case where neither the Maximum Single Frame Duration Increase function nor the Minimum Frame Number function is applied. In this case, the brightness changes abruptly when switching frame rates. This demonstrates that when the frame rate changes from 240Hz to 60Hz, the user can clearly perceive a change in brightness.

[0187] Figure 6 shows the case where the Maximum Single Frame Duration Increase function is applied. In this case, the single frame duration is increased, making the slope of the brightness change somewhat gentler. However, since there is no minimum frame count setting, the overall brightness change is still not smooth.

[0188] Figure 7 shows the case where both the Maximum Single Frame Duration Increase function and the Minimum Frame Number function are applied. In this case, the minimum frame number setting is additionally applied during the frame rate switching process, making the slope of the brightness change gentler. Through this, the user perceives the brightness change caused by the frame rate change less.

[0189] The examples in FIGS. 5, 6, and 7 show that the impact of brightness changes on the user experience during frame rate switching can be improved as the proposed functions are applied. In particular, the method in FIG. 7 maximizes technical effects by using an increase in continuous frame duration and a minimum frame count setting together.

[0190] Composition and Function of the Invention

[0191] Various embodiments of the present disclosure aim to reduce abrupt changes in Luminance when changing the Frame rate by maintaining the minimum number of Frames indicated in the Sink Information Block whenever the Frame rate is changed during Adaptive-sync operation.

[0192] The Sink specifies the minimum number of frames that must be executed whenever the refresh rate changes in the Block for communication between Sources (e.g., EDID, DisplayID, and DPCD Block, etc.). The Source must refer to this information when the frame rate changes to perform video rendering.

[0193] Due to the characteristics of the display, differences in luminance occur depending on changes in frame rate; however, by using the invented function, gradual changes in brightness can be achieved even with rapid changes in frame rate, thereby reducing eye strain for the user and providing a better experience.

[0194] The Sink specifies the parameter for the minimum number of frames that must be maintained when the refresh rate changes (applicable to both increases and decreases) in the Blocks for communication between Sources (e.g., EDID, DisplayID, and DPCD blocks). The parameter for the minimum number of frames can be specified in any way through the Video Capability block. The Source must read the Sink's information Blocks and perform video rendering operations by referring to this information.

[0195] Table 7 shows, for example, cases where parameters for the minimum number of frames are indicated for EDID, DisplayID, and CTA Block.

[0196] Byte # Name Definition X Byte Minimum Adaptive-Sync Frame number The minimum number of frames to remain at when changing the refresh rate

[0197] Table 8 shows, for example, a case where the parameter for the minimum number of frames for a DPCD Block is indicated.

[0198] DPCD RegisterAddress Name Descriptor 0xxxxh[X] Minimum Adaptive-Sync Frame number The minimum number of frames to remain at when changing the refresh rate

[0199] The process of the Source device performing Adaptive-Sync operation

[0200] FIG. 8 is a diagram illustrating an example of the process of determining the Frame Range when the Source device performs an Adaptive-Sync operation.

[0201] Figure 8 shows the flow of the process for determining the Frame Range when the Source device performs an Adaptive-Sync operation.

[0202] The Source device receives a Hot Plug Detect (HPD) signal from the Sink device. The connection with the Sink device is confirmed through the reception of the HPD signal.

[0203] The Source device reads the EDID, DisplayID, or DPCD data of the Sink device. The EDID, DisplayID, or DPCD data may contain information related to Adaptive-Sync operation.

[0204] The Source device checks whether the EDID, DisplayID, or DPCD data contains blocks related to Adaptive-Sync operation.

[0205] If the EDID, DisplayID, or DPCD data contains a block related to Adaptive-Sync operation, the Source device operates in Frequency Variable Mode. Frequency Variable Mode is used to reduce power consumption and optimize display performance through variable frame rates.

[0206] If there is no information related to Adaptive-Sync in the EDID, DisplayID, or DPCD data, the Source device operates in Frequency Fixed Mode. Frequency Fixed Mode ensures stable screen output while maintaining a fixed frame rate.

[0207] FIG. 9 is a diagram illustrating an example of a process for determining a Frame Range when a Source device performs an Adaptive-Sync operation according to various embodiments of the present disclosure.

[0208] Figure 9 illustrates in more detail the process of determining the Frame Range when the Source device performs an Adaptive-Sync operation.

[0209] The Source device receives a Hot Plug Detect (HPD) signal from the Sink device. The connection with the Sink device is confirmed through the reception of the HPD signal.

[0210] The Source device reads the EDID, DisplayID, or DPCD data of the Sink device. The EDID, DisplayID, or DPCD data may contain information related to Adaptive-Sync operation.

[0211] The Source device checks whether the EDID, DisplayID, or DPCD data contains blocks related to Adaptive-Sync operation.

[0212] If there is no block related to Adaptive-Sync operation in the EDID, DisplayID, or DPCD data, the Source device operates in Frequency Fixed Mode. Frequency Fixed Mode provides stable screen output while maintaining a fixed frame rate.

[0213] If the EDID, DisplayID, or DPCD data contains an Adaptive-Sync related block, the Source device further checks whether the EDID, DisplayID, or DPCD data contains a block indicating the minimum number of frames when changing the respective refresh rate.

[0214] If the EDID, DisplayID, or DPCD data does not contain a block indicating the minimum number of frames when changing the respective refresh rate, the Source device operates in Frequency Variable Mode. Frequency Variable Mode is used to reduce power consumption and optimize display performance through variable frame rates.

[0215] If the EDID, DisplayID, or DPCD data includes a block indicating the minimum number of frames when changing the respective refresh rate, the Source device operates in variable frequency mode while maintaining the minimum number of frames when changing the respective refresh rate. In other words, the Source device operates in variable frequency mode and maintains the minimum number of frames when changing the refresh rate. This makes the user experience smoother with frame changes.

[0216] Figure 9 is an improvement over Figure 8 in that it processes the conditions of Adaptive-Sync operation in more detail. In particular, through additional conditions that maintain a minimum number of frames, unnatural brightness changes or frame loss that may occur during screen transitions can be reduced more effectively. This contributes to significantly improving the user experience.

[0217] Flow chart for exchanging data between Source and Sink devices

[0218] FIG. 10 is a diagram illustrating an example of a signal flow diagram between a Source device and a Sink device according to various embodiments of the present disclosure.

[0219] The Source device checks the connection with the Sink device through the HPD (Hot Plug Detect) signal. The HPD signal recognizes the connection status and acts as a trigger to start the next step of the process.

[0220] The Source device reads the EDID, DisplayID, or DPCD data of the Sink device. The EDID, DisplayID, or DPCD data contains information related to display settings (resolution, frequency, etc.) and plays an important role in coordinating display operation.

[0221] The Source device checks the Adaptive-Sync related block information within the EDID, DisplayID, or DPCD data. The Adaptive-Sync related block contains information on whether the Sink device supports Adaptive-Sync and what conditions to follow when switching frame rates.

[0222] If there is a block related to Adaptive-Sync in the EDID, DisplayID, or DPCD data, check the information on the minimum number of frames that must be maintained when changing each refresh rate in the EDID, DisplayID, or DPCD data. This is an important factor in ensuring smooth rendering during screen transitions.

[0223] The Source device renders and outputs video data by referencing information blocks within the Sink device's EDID, DisplayID, or DPCD data. This process focuses on optimizing display performance and improving the user experience.

[0224] FIG. 11 is a diagram illustrating an example of a signal flow diagram between a Source device and a Sink device according to various embodiments of the present disclosure.

[0225] Figure 11 illustrates the signal flow between the Source device and the Sink device, and specifically details the frame processing and data transmission and reception processes based on Adaptive-Sync operation. This flowchart shows the specific processes related to screen switching and frame rate maintenance.

[0226] The Source device checks the connection with the Sink device through the HPD (Hot Plug Detect) signal. The HPD signal recognizes the connection status and acts as a trigger to start the next step of the process.

[0227] The Source device checks the Adaptive-Sync related block information within the EDID, DisplayID, or DPCD data. The Adaptive-Sync related block contains information on whether the Sink device supports Adaptive-Sync and what conditions to follow when switching frame rates.

[0228] If there is a block related to Adaptive-Sync in the EDID, DisplayID, or DPCD data, check the information on the minimum number of frames that must be maintained when changing each refresh rate in the EDID, DisplayID, or DPCD data. This is an important factor in ensuring smooth rendering during screen transitions.

[0229] The Source device performs video rendering by referencing information blocks within the Sink device's EDID, DisplayID, or DPCD data, and sends the information regarding the minimum frame rate to be maintained in the Secondary Data Packet (SDP) to the Sink device along with the video data. The minimum frame rate information included in the SDP plays a crucial role in conveying the frame maintenance standard to the Sink device during refresh rate changes in Adaptive-Sync operation. This information provides the reference data necessary for the Sink device to maintain screen quality and synchronization performance, ensuring a smooth and consistent screen output experience for the user. By transmitting the minimum frame rate information along with the video data, the Source device enables the Sink device to output video according to the Adaptive-Sync settings. This is a critical step in optimizing the user experience by enabling smooth transitions in frame rates.

[0230] [Explanation regarding Source device claim]

[0231] The embodiments described above will be explained in detail below with reference to FIG. 12 regarding the operation of the terminal. The methods described below are distinguished only for the convenience of explanation, and it is obvious that as long as they are not mutually excluded, a part of one method may be substituted with a part of another method or combined with one another and applied.

[0232] FIG. 12 is a drawing illustrating an example of the operation process of a Source device according to various embodiments of the present disclosure.

[0233] According to various embodiments of the present disclosure, a method performed by a Source device is provided.

[0234] The Source device includes a processor; memory; and a transceiver. The memory stores instructions for performing operations based on execution by the processor.

[0235] In step S1201, the source device receives a hot plug detection (HPD) signal from the sink device.

[0236] In step S1202, the source device receives first information related to EDID (Extended Display Identification) or DPID (DisplayID) from the sink device.

[0237] In step S1203, the source device identifies the minimum number of frames related to the adaptive-sync operation based on the first information of the sink device.

[0238] In step S1204, the source device performs rendering for video information in which the refresh rate changes from a first refresh rate to a second refresh rate, such that it maintains a number of frames greater than or equal to the minimum number information at a third refresh rate corresponding to the interval between the first refresh rate and the second refresh rate.

[0239] In step S1205, the source device transmits the video information on which the rendering has been performed to the sink device.

[0240] According to various embodiments of the present disclosure, a secondary data packet (SDP) may be transmitted to the sink device along with the rendered video information. The SDP may include information on the third refresh rate that must be maintained for the number of frames corresponding to the minimum number of information by the rendering.

[0241] According to various embodiments of the present disclosure, the minimum number information may be equal to or greater than 3 or 5.

[0242] According to various embodiments of the present disclosure, the first scan rate may correspond to a first luminance, the second scan rate may correspond to a second luminance, and the third scan rate may correspond to a third luminance. The third luminance may correspond to an area between the first luminance and the second luminance.

[0243] According to various embodiments of the present disclosure, the first information may be related to support for the adaptive synchronization operation of the sink device.

[0244] According to various embodiments of the present disclosure, when the first information is not related to support for the adaptive synchronization operation, the video information may be rendered with the refresh rate fixed.

[0245] According to various embodiments of the present disclosure, if the first information is not related to the minimum number information, the video information may be rendered with the refresh rate fixed.

[0246] According to various embodiments of the present disclosure, a Source device is provided. The Source device comprises a processor; a memory; and a transceiver, and the processor may be configured to perform the method of operation of the Source device according to FIG. 7.

[0247] According to various embodiments of the present disclosure, a device for controlling a Source device is provided. The device comprises at least one processor and at least one memory operably connected to the at least one processor. The at least one memory may be configured to store instructions for performing a method of operating the Source device according to FIG. 7 based on execution by the at least one processor.

[0248] According to various embodiments of the present disclosure, one or more non-transitory computer-readable media (CRMs) storing one or more instructions are provided. The one or more instructions perform operations based on execution by one or more processors, and the operations may include a method of operation of a Source device according to FIG. 7.

[0249] The claims described in various embodiments of the present disclosure may be combined in various ways. For example, the technical features of the method claims of various embodiments of the present disclosure may be combined to be implemented as a device, and the technical features of the device claims of various embodiments of the present disclosure may be combined to be implemented as a method. Furthermore, the technical features of the method claims and the technical features of the device claims of various embodiments of the present disclosure may be combined to be implemented as a device, and the technical features of the method claims and the technical features of the device claims of various embodiments of the present disclosure may be combined to be implemented as a method.

Claims

Claim 1 A method for operating a source device, comprising: receiving a hot plug detection (HPD) signal from a sink device; receiving first information related to an Extended Display Identification (EDID) or Display ID (DPID) from the sink device; identifying information on the minimum number of frames related to an Adaptive-Sync operation based on the first information from the sink device; performing rendering for video information in which the refresh rate changes from a first refresh rate to a second refresh rate, such that the number of frames is greater than or equal to the minimum number of frames at a third refresh rate between the first refresh rate and the second refresh rate; and transmitting the rendered video information to the sink device. Claim 2 A method according to claim 1, wherein a secondary data packet (SDP) is transmitted to the sink device along with the rendered video information, and the SDP includes information of the third refresh rate that must be maintained for as many frames as the minimum number of information by the rendering. Claim 3 In claim 1, the minimum number information is equal to or greater than 3 or 5. Claim 4 A method according to claim 1, wherein the first scan rate corresponds to a first luminance, the second scan rate corresponds to a second luminance, the third scan rate corresponds to a third luminance, and the third luminance corresponds to a luminance between the first luminance and the second luminance. Claim 5 In claim 1, the method, wherein the first information relates to support for the adaptive synchronization operation of the sink device. Claim 6 In claim 1, a method in which, if the first information is not related to support for the adaptive synchronization operation, the video information is rendered with the refresh rate fixed. Claim 7 In claim 1, a method in which, when the first information is not related to the minimum number information, the video information is rendered with the refresh rate fixed. Claim 8 A source device comprises: a processor; a memory; and a transceiver, wherein the memory stores instructions for performing operations based on execution by the processor, the operations comprising: receiving a hot plug detection (HPD) signal from a sink device; receiving first information related to an Extended Display Identification (EDID) or Display ID (DPID) from the sink device; identifying information on the minimum number of frames related to an Adaptive-Sync operation based on the first information from the sink device; performing rendering for video information in which the refresh rate changes from a first refresh rate to a second refresh rate, such that the number of frames is greater than or equal to the minimum number information at a third refresh rate between the first refresh rate and the second refresh rate; and transmitting the rendered video information to the sink device. Claim 9 In claim 8, a source device wherein an SDP (secondary data packet) is transmitted to the sink device along with the rendered video information, and the SDP includes information of the third refresh rate that must be maintained for as many frames as the minimum number of information by the rendering. Claim 10 In claim 8, the source device, wherein the minimum number information is equal to or greater than 3 or 5. Claim 11 A source device according to claim 8, wherein the first scan rate corresponds to the first luminance, the second scan rate corresponds to the second luminance, the third scan rate corresponds to the third luminance, and the third luminance corresponds to the area between the first luminance and the second luminance. Claim 12 In claim 8, the source device, wherein the first information relates to the support for the adaptive synchronization operation of the sink device. Claim 13 In claim 8, where the first information is not related to support for the adaptive synchronization operation, the video information is rendered in a source device with the refresh rate fixed. Claim 14 In claim 8, where the first information is not related to the minimum number information, the video information is rendered in a source device with the refresh rate fixed. Claim 15 A computer-readable medium comprising one or more non-transitory instructions storing one or more instructions, wherein the one or more instructions perform operations based on execution by one or more processors, and the operations include: receiving a hot plug detection (HPD) signal from a sink device; receiving first information related to an Extended Display Identification (EDID) or Display ID (DPID) from the sink device; identifying information on a minimum number of frames related to an Adaptive-Sync operation based on the first information from the sink device; performing rendering for video information in which the refresh rate changes from a first refresh rate to a second refresh rate, such that the number of frames is greater than or equal to the minimum number information at a third refresh rate between the first refresh rate and the second refresh rate; and transmitting the rendered video information to the sink device.

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