System for Creating and Managing a Digital Twin of a Semiconductor PCB Area and Method for Creating and Managing a Digital Twin of a Semiconductor PCB Area Using the Same

Abstract

A digital twin system for a semiconductor PCB area to achieve the objective of the present invention comprises a system for generating a digital twin of a semiconductor PCB area and optimizing the same, the system comprising: a data collection unit that collects data related to manufacturing and testing processes of the semiconductor PCB area in real time; a modeling data optimization processing unit that receives 3D model data of the semiconductor PCB area from the data collected by the data collection unit and generates a digital twin model of the semiconductor PCB area; a lightweight modeling texture baking extraction unit that converts high-resolution surface information into a low-capacity texture based on the data collected by the data collection unit and the digital twin model generated through the modeling data optimization processing unit, thereby reducing data capacity while maintaining the accuracy of the digital twin model; a metadata combining unit that combines metadata to perform real-time analysis and prediction of the semiconductor PCB area by linking information collected by the data collection unit with the lightweight model generated through the modeling texture baking extraction unit; and an analysis unit that checks the current state of the semiconductor PCB area and predicts performance changes by utilizing the data combined through the metadata combining unit.

Description

Technology Field

[0001] The present invention relates to a digital twin generation and management system for a semiconductor PCB area and a method for generating and managing a digital twin for a semiconductor PCB area using the same. More specifically, in order to easily identify internal conditions of a PCB manufacturing process in a closed environment where interaction with the outside is limited, lightweight 3D assets that can be visualized within a virtual environment are generated based on structural foundations such as the shape, key control points, and operating range of semiconductor manufacturing equipment, configured in an optimized form within the digital twin environment, and configured to reflect key data such as power consumption, temperature, and vibration of semiconductor manufacturing equipment, thereby enabling optimal management. The invention also relates to a digital twin system for a semiconductor PCB area and a method for generating and managing a digital twin for a semiconductor PCB area using the same. Background Technology

[0002] Digital twin technology is a technique that accurately replicates physical objects or processes in a digital environment to collect and analyze data generated in the actual production environment in real time. Through this, it enables real-time monitoring of system operations, problem prediction, and plays a crucial role in improving and optimizing the performance of physical systems. Thanks to these characteristics, digital twin technology has established itself as a key tool across various industries for efficiently managing complex processes and for enhancing productivity and quality.

[0003] The semiconductor PCB manufacturing process is highly sophisticated and precise, and minute variations occurring at each stage significantly impact the quality of the final product. However, because the process takes place in a specialized environment, it is difficult to monitor detailed manufacturing information visually. Consequently, the introduction of digital twin technology is required to track detailed manufacturing information in real time and predict errors.

[0004] However, existing digital twin models used in other industries do not reflect the specific characteristics of the semiconductor PCB manufacturing process, making it difficult to apply them directly. Since each manufacturing process possesses unique characteristics and environments, using digital twin systems from other industries for semiconductor manufacturing results in a failure to adequately reflect the precision of the process.

[0005] In particular, if 3D assets lack information specialized for semiconductor PCB manufacturing, they fail to accurately represent the structural characteristics of equipment or substrates or unique process conditions, which leads to discrepancies between the digital twin model and the actual manufacturing environment and reduces the accuracy of process optimization or quality prediction.

[0006] In addition, when the 3D models constituting the digital twin environment are large, they place a significant burden on rendering and processing, causing performance degradation and consuming more resources in storage space and processing power. This results in longer loading times, slowing down system response speeds and potentially making it difficult to receive feedback. These issues hinder the efficient operation of the semiconductor PCB manufacturing process. Prior art literature

[0007] KR 10-2724949 (Notice dated 2024.11.01) The problem to be solved

[0008] The present invention aims to solve conventional problems by providing a digital twin system for a semiconductor PCB area and a method for creating and managing a digital twin of a semiconductor PCB area using the same, which enables optimal management by generating lightweight 3D assets visualizable within a virtual environment based on structural foundations such as the shape, key control points, and operating range of semiconductor manufacturing equipment, in order to easily identify internal conditions of a PCB manufacturing process in a closed environment where interaction with the outside is limited, configuring them in an optimized form within a digital twin environment, and reflecting key data such as power consumption, temperature, and vibration of the semiconductor manufacturing equipment.

[0009] The objectives of the present invention are not limited thereto, and other unmentioned objectives will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0010] A digital twin system for a semiconductor PCB area to achieve the above-mentioned objectives of the present invention comprises: a data collection unit that collects data related to manufacturing and testing processes of the semiconductor PCB area in real time; a modeling data optimization processing unit that receives 3D model data of the semiconductor PCB area from the data collected by the data collection unit and generates a digital twin model of the semiconductor PCB area; a lightweight modeling texture baking extraction unit that converts high-resolution surface information into a low-capacity texture based on the data collected by the data collection unit and the digital twin model generated through the modeling data optimization processing unit, thereby reducing data capacity while maintaining the accuracy of the digital twin model; a metadata combining unit that combines metadata to perform real-time analysis and prediction of the semiconductor PCB area by linking information collected by the data collection unit with the lightweight model generated through the modeling texture baking extraction unit; and an analysis unit that checks the current state of the semiconductor PCB area and predicts performance changes by utilizing the data combined through the metadata combining unit.

[0011] At this time, the modeling data optimization processing unit may include a high-capacity modeling unit that generates a high-capacity digital twin model of a PCB area based on data collected by the data collection unit, and a lightweighting unit that reduces the capacity of the high-capacity digital twin model to a low capacity.

[0012] In addition, the data collected by the data collection unit may include at least one of field equipment data, temperature, current, voltage, vibration, and signal integrity in the semiconductor PCB area.

[0013] In addition, it may further include a visualization unit that visualizes the digital twin model in real time and executes and displays the analysis information of the analysis unit.

[0014] In another category, a method for creating and managing a digital twin of a semiconductor PCB area comprises: a data collection step for collecting data in real time from physical structures and characteristics related to semiconductor PCB manufacturing and semiconductor PCB manufacturing and testing processes; a high-capacity modeling step for creating a high-capacity 3D model of the semiconductor PCB area based on the data collected in the data collection step; a 3D asset lightweighting step for creating a low-capacity optimized model by applying mesh simplification and algorithm optimization to the 3D model created in the high-capacity modeling step to enable real-time rendering; a texture baking step for extracting and optimizing texture information using the high-capacity 3D model; a lightweighting modeling step for creating a lightweight model by combining the low-capacity optimized model created in the 3D asset lightweighting step and the texture information extracted in the texture baking step; a metadata combining step for combining metadata including semiconductor PCB design information, environment information, and operation information with the lightweight model; and a digital twin management step for visualizing or analyzing the lightweight model combined with metadata in real time.

[0015] At this time, the data collection step can perform a process of digitizing the shape and structure of the semiconductor PCB area by utilizing laser scans, CT scans, or drawing data.

[0016] In addition, the high-capacity modeling step may include a step of aligning modeling data among the data collected in the data collection step, a step of creating a 2D reference drawing by drawing based on the aligned modeling data, a step of creating a 3D mesh drawing based on the 2D reference drawing, a step of creating a basic model based on the 3D mesh drawing, and a step of creating a high-capacity 3D model by adding detailed shape and high-resolution information based on the basic model data.

[0017] In addition, the method may further include a step of generating a point cloud before or after the process of aligning the above modeling data.

[0018] In addition, based on the above 2D reference drawing, point cloud data can be divided into sections based on at least one of the structural features, functional elements, manufacturing or design criteria of the semiconductor PCB area.

[0019] In addition, the 3D mesh drawing generation step and the basic model production step may further include a process of extracting section-specific modeling data for each of the separated sections.

[0020] Additionally, the 3D asset lightweighting step may include the step of extracting high-capacity 3D modeling data generated in the high-capacity modeling step, the step of generating a low-capacity optimized model by lightweighting the high-capacity 3D modeling data, and the step of performing UV unwrapping on the low-capacity optimized model.

[0021] Additionally, the texture baking step may include a step of extracting a texture from a high-capacity 3D model generated in the high-capacity modeling step, a step of generating optimized texture data by performing baking based on the extracted texture, and a step of generating a color and texture to be applied to the lightweight model generated in the lightweight modeling step while maintaining the surface characteristics of the high-capacity 3D model using the baked texture data.

[0022] Additionally, the lightweight modeling step may include the step of creating a material based on generated color and texture data and assigning it to the low-capacity optimization model, and the step of creating a lightweight model based on the low-capacity optimization model to which the material is assigned.

[0023] In addition, the above metadata combination step can be performed in an encrypted form to prevent external leakage and to maintain integrity and consistency without changing the format structure of the lightweight model. Effects of the invention

[0024] The digital twin system of a semiconductor PCB area according to the present invention and the method for generating and managing a digital twin of a semiconductor PCB area using the same have the following effects.

[0025] First, by lightweighting the 3D digital twin model of the semiconductor PCB area, which requires precise design and has a large number of components, it is possible to maintain detailed component information while enabling smooth maintenance of the semiconductor PCB area in a closed environment.

[0026] Second, by effectively optimizing the high-capacity model of the semiconductor PCB area in the digital twin through lightweighting, the burden of real-time simulation and rendering processing is minimized, which is expected to maximize performance.

[0027] Third, lightweighting minimizes resources consumed in storage space and processing power, thereby reducing loading times and improving system response speed to facilitate feedback, which in turn maximizes the operational efficiency of the semiconductor PCB manufacturing process.

[0028] Fourth, in addition to lightweight modeling, texture baking allows for the efficient processing of texture information, thereby maximizing real-time rendering performance while maintaining the details of the original model, which has the effect of reducing cloud and server costs.

[0029] Fifth, in the semiconductor PCB manufacturing sector where various data such as process equipment, sensors, and auditing equipment are generated, linking information metadata specialized for semiconductor PCB manufacturing—such as electrical characteristics of PCB components, process history, and wiring accuracy—with a digital twin has the effect of maximizing process optimization and quality prediction accuracy.

[0030] Sixth, specialized metadata analysis in the semiconductor PCB area enhances the prediction of defect possibilities and early response capabilities, thereby maximizing management efficiency.

[0031] Seventh, by visualizing and displaying process history and performance data layer by layer—such as wiring, components, power, and signal integrity of the semiconductor PCB—through pop-ups, managers can easily search for desired information and intuitively understand circuit operations.

[0032] Eighth, by implementing a digital twin of the semiconductor PCB area that includes not only technical engineering data, managers can directly analyze and correct problems within the digital twin, check circuit data in real time using AR glasses, or review the wiring paths of PCB circuits in a virtual space using VR. This has the effect of overcoming the disadvantages of the closed environment of the semiconductor PCB area by enabling various workers, researchers, and managers to share data and perform tasks through the virtual environment of the digital twin.

[0033] Ninth, digital twins have the effect of digitizing the entire process of semiconductor PCB manufacturing, inspection, and maintenance.

[0034] Tenth, combining metadata and AI analysis has the effect of improving defect prediction and quality control in semiconductor PCB manufacturing.

[0035] Eleventh, AR or VR-based visualization allows technicians to perform tasks more intuitively, thereby maximizing worker efficiency.

[0036] The effects of the present invention are not limited to those mentioned above, and other unmentioned effects will be clearly understood by those skilled in the art from the description in the claims. Brief explanation of the drawing

[0037] The following drawings attached to this specification illustrate preferred embodiments of the present invention and serve to further enhance understanding of the technical concept of the present invention together with the detailed description of the invention; therefore, the present invention should not be interpreted as being limited only to the matters described in such drawings. FIG. 1 is a block diagram showing the schematic configuration of a digital twin system of a semiconductor PCB area according to the present invention; FIG. 2 is a schematic block diagram showing the process of creating a digital twin system of a semiconductor PCB area according to the present invention; FIG. 3 is a block diagram showing the process flow of a modeling data optimization processing unit according to the present invention; FIG. 4 is a block diagram showing the process flow of a lightweight modeling texture baking extraction unit according to the present invention; and FIG. 5 is a block diagram illustrating the metadata combination related content according to the present invention. Specific details for implementing the invention

[0038] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the present invention, and the present invention is defined only by the scope of the claims.

[0039] The terms used in this specification are for describing embodiments and are not intended to limit the invention. In this specification, the singular form includes the plural form unless specifically stated otherwise in the text. The terms "comprises" and / or "comprising" used in this specification do not exclude the presence or addition of one or more other components in addition to the components mentioned. Throughout the specification, the same reference numerals refer to the same components, and "and / or" includes each of the mentioned components and all combinations of one or more. Although terms such as "first," "second," etc., are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish them from a single component. Therefore, the first component mentioned below may be the second component within the technical scope of the invention.

[0040] Unless otherwise defined, all terms used herein (including technical and scientific terms) may be used in a meaning commonly understood by those skilled in the art to which the present invention pertains. Furthermore, terms defined in commonly used dictionaries are not to be interpreted ideally or excessively unless explicitly and specifically defined otherwise.

[0042] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings.

[0044] Configuration of a digital twin system in the semiconductor PCB area

[0046] The digital twin system of a semiconductor PCB area according to the present invention is intended for smoother management through interaction with the outside of a semiconductor PCB manufacturing area operated in a closed environment, and is a system for creating and managing such a digital twin of a semiconductor PCB manufacturing area.

[0047] The present invention is intended for the creation and management of a digital twin of such a semiconductor PCB area, and configurations not described in detail in the present invention may be understood to include configurations identical or similar to those of a general digital twin system.

[0048] FIG. 1 is a block diagram showing the schematic configuration of a digital twin system for a semiconductor PCB area according to the present invention. As shown in FIG. 1, the digital twin system for a semiconductor PCB area according to the present invention includes a data collection unit (100), a modeling data optimization processing unit (200), a lightweight modeling texture baking extraction unit (300), a metadata combining unit (400), an analysis unit (500), and a visualization unit (600).

[0049] The data collection unit (100) is a device that collects manufacturing and process-related data of the semiconductor PCB area for the creation and management of a digital twin model. This data collection unit (100) may be composed of any device or combination of devices capable of smoothly creating and managing the digital twin of the semiconductor PCB manufacturing area, such as collecting structural information such as various information about the semiconductor PCB manufacturing equipment or the environment within the semiconductor PCB area, the shape of the manufacturing equipment, major control points, and operating ranges, or collecting information input from the outside. In one embodiment, the data collection unit (100) may include a plurality of sensor units provided inside the semiconductor PCB area, and depending on the mode of use, it may also include an external input unit such as a user PC or terminal for inputting manufacturing information by a manager. That is, the data collection unit (100) may be composed of any device capable of collecting various modeling data and texture data that can create semiconductor PCB manufacturing equipment and an environment that are as identical as possible to the actual one within the digital twin, transmitting them to the modeling data optimization processing unit (200), and collecting various information that can smoothly manage the semiconductor PCB manufacturing equipment and the environment within the area in real time. In other words, any device capable of collecting at least one of the field equipment data, temperature, current, voltage, vibration, and signal integrity in the semiconductor PCB area, and in particular, information specialized for semiconductor PCB manufacturing—namely, structural characteristics of semiconductor equipment or substrates, unique process conditions, etc.—that can maximize the correlation rate with the actual manufacturing environment may be used.

[0050] The modeling data optimization processing unit (200) generates a digital twin model of the semiconductor PCB area using data collected by the data collection unit (100), and optimizes performance by reducing the capacity of the generated digital twin model for smooth management. This modeling data optimization unit generates a high-capacity digital twin model that is as identical as possible to a physical object using data collected by the data collection unit (100), particularly field equipment data and manufacturing equipment data of the semiconductor PCB area. The generation of such a high-capacity digital twin model can be performed as a software function of the modeling data optimization processing unit (200) or through a separate high-capacity modeling unit (210). However, since the present invention is intended for management purposes such as verifying process status or equipment information through the semiconductor PCB area rather than simply representing the equipment shape, managing based on a high-capacity digital twin model can cause a significant burden on rendering and processing due to the large capacity, leading to performance degradation. Furthermore, it may result in reduced system response speed and reduced management efficiency, such as increased loading times due to the consumption of more resources for storage space and processing power.

[0051] Accordingly, the modeling data optimization processing unit (200) can perform lightweighting to reduce the capacity of the high-capacity digital twin model in various ways. This lightweighting of the high-capacity digital twin model to a low-capacity capacity can be performed by a software function of the modeling data optimization processing unit (200) or through a separate lightweighting unit (220). In one embodiment, the high-capacity digital twin model can be converted into a low-capacity model through a decimation technique, etc., via the software function of the modeling data optimization processing unit (200) or the lightweighting unit (220), and a UV unwrapping operation can be performed on the low-capacity model for a subsequent process.

[0052] As described above, the modeling data optimization processing unit (200) generates high-capacity digital twin data that is as closely matched as possible to the equipment and manufacturing environment of the actual semiconductor PCB area, and any device or system can be used as long as it can be reduced to an optimal capacity for managing the semiconductor PCB area.

[0053] The lightweight modeling texture baking extraction unit (300) is a device that optimizes and lightweights the textures of a lightweight digital twin model based on the data collected from the data collection unit (100) and the lightweight digital twin model generated through the modeling data optimization processing unit (200). This lightweight modeling texture baking extraction unit (300) extracts texture information from high-capacity modeling and converts high-resolution information, such as color and texture, into a form applicable to the lightweight digital twin model through texture baking. This function can be performed through software already input into the lightweight modeling texture baking extraction unit (300), or by including a texture baking unit (310) in the lightweight modeling texture baking extraction unit (300). Additionally, the lightweight modeling texture baking extraction unit (300) creates color and texture expressions based on the extracted textures and sets a separate material. The material created in this way performs the function of being assigned and applied to the final lightweight model. This function can also be performed through software already input into the lightweight modeling texture baking extraction unit (300), or by including a lightweight modeling extraction unit (320) in the lightweight modeling texture baking extraction unit (300).

[0054] The metadata combining unit (400) is a device that combines metadata to perform real-time analysis and prediction of the semiconductor PCB area by linking information collected from the data collection unit (100) to the digital twin model that has been finally lightweighted through the modeling data optimization processing unit (200) and the lightweight modeling texture baking extraction unit (300). This metadata combining unit (400) reflects real-time data collected from the data collection unit (100) to expand the produced lightweight digital twin model from a simple visual 3D model object into data that can interact with meaningful information, and enables it to be utilized for analysis and simulation. At this time, the metadata combining unit (400) can combine static data, environmental data, and dynamic data.

[0055] Here, static data is basic attribute information that does not change and may include the name, ID, production date, manufacturer, machine part information, circuit board layer information, parts list, etc. of the semiconductor PCB manufacturing equipment.

[0056] In addition, environmental data may include information regarding environmental changes, such as environmental sensor data like temperature, humidity, and atmospheric pressure in the semiconductor PCB area, and location information within the building of the semiconductor PCB area, which is the environment in which the model is located.

[0057] Additionally, dynamic data may include real-time changing data, such as data collected in real time from a data collection unit (100) like IoT sensor data, real-time maintenance data, animation and simulation data, etc.

[0058] The analysis unit (500) is a device that checks the current status of the semiconductor PCB area and predicts performance changes by utilizing data combined through the metadata combination unit (400). That is, the analysis unit (500) is a device that performs maintenance and optimization work on the semiconductor PCB digital twin by combining in real time not only sensor data such as temperature, voltage, current, and frequency changes collected from the data collection unit (100), electromagnetic field analysis data, and quality data recorded during the manufacturing and testing stages, but also existing PCB design data such as circuit diagrams, component placement, trace paths, VIAs, and layer information, as well as metadata such as production information of each component, component lifespan, and test results. Based on the analysis content of this analysis unit (500), it can perform functions such as predicting performance degradation, defect possibilities, and lifespan of the PCB manufacturing equipment.

[0059] The metadata combined by this metadata combining unit (400) can maintain integrity and consistency without changing the format structure of the lightweight digital twin model, and is in an encrypted form to correspond to PCB characteristics sensitive to external leakage, and the encrypted metadata is combined with the lightweight digital twin model according to a classification system of static, dynamic, and environment to create a 3D model suitable for the actual environment.

[0060] The visualization unit (600) is a device that visually displays information derived from the analysis unit (500) so that the user can intuitively understand it. Any device capable of visually displaying the current state of the semiconductor PCB area, performance change trends, and predicted maintenance information so that the user can easily understand it may be used for this visualization unit (600). However, it is preferable that it be connected via wired or wireless connection to a user terminal or user PC, etc., so that the user can quickly check the information they want.

[0061] Depending on the usage pattern, a separate feedback unit may be configured to input user feedback, or a user terminal, user PC, or visualization unit (600) used in the data collection unit (100) may be utilized as the feedback unit.

[0063] Method for creating and managing a digital twin of a semiconductor PCB area

[0065] The method for generating and managing a digital twin of a semiconductor PCB area according to the present invention is a technology for generating a digital twin model that can easily identify the internal state of a semiconductor PCB manufacturing process having a closed environment and easily maintain and manage the semiconductor PCB manufacturing process, and thereby managing the manufacturing process of the semiconductor PCB area.

[0066] Although the method for generating and managing a digital twin in such a semiconductor PCB area can utilize various system configurations, the explanation will focus on utilizing the aforementioned configuration as an example.

[0067] FIG. 2 is a schematic block diagram illustrating the process of creating a digital twin system of a semiconductor PCB area according to the present invention. The process of creating a digital twin system of a semiconductor PCB area according to the present invention is largely as illustrated in FIG. 2, and is described in more detail as follows.

[0068] First, data for creating a digital twin model of a semiconductor PCB area is collected through a data collection unit (100). The data collection unit includes all devices and functions for collecting data for creating a digital twin model as well as data for managing it, but in this step, data is collected primarily for creating a digital twin model. At this time, the collected data refers to all data constituting the semiconductor PCB area, and in one embodiment, may include shape data, process data, electrical characteristic data, environmental data, quality inspection data, maintenance data, etc.

[0069] Here, shape data may be the most basic essential data for constructing a digital twin model of a semiconductor PCB area. As an example, it may include CAD drawings or design data including 2D and 3D drawings of a manufacturing device, wiring and layer structure information, component information, etc., 3D shape information using an optical scanner, CT scanner, etc., 3D scanning data such as shape deformation analysis data of a manufactured PCB and substrate, high-resolution point cloud data through laser scanning, 3D mesh model data, etc.

[0070] Process data refers to data for constructing a digital twin that reflects the characteristics of the manufacturing process, and may include real-time data for each PCB manufacturing process, such as circuit pattern formation (etching), drilling, lamination, solder mask printing, process temperature, humidity, pressure, and chemical treatment information; sensor data measuring the temperature, humidity, vibration, and pressure of process equipment; manufacturing equipment data, such as equipment usage time, performance logs, and operating rate data; soldering and assembly data; and inspection and quality control data.

[0071] Electrical characteristic data is important data that determines the performance of a PCB and may include circuit design data, electrical circuit information including electrical signal path and connectivity verification information, signal integrity data including electrical signal delay time, noise, crosstalk, and EMI (Electromagnetic Interference) data, and power integrity data such as power supply chain analysis, voltage drop, and current flow analysis.

[0072] Environmental data refers to data collected to reflect the semiconductor PCB manufacturing environment and usage environment in a digital twin model. This may include manufacturing environment data such as factory internal temperature, humidity, fine dust concentration, occurrence of static electricity, and manufacturing room cleanroom grade information; usage environment data such as temperature changes, humidity, and vibration levels in the environment where the PCB will be used; data reflecting PCB manufacturing and the heat generation characteristics of the PCB; and thermal analysis data including thermal distribution cooling structure and airflow data.

[0073] Quality inspection data refers to data collected to ensure the quality of manufactured semiconductor PCBs, and may include optical inspection data for verifying pattern alignment on the PCB surface, circuit defects, and foreign substance detection; X-ray inspection data for verifying internal wiring defects and component connection status; electrical performance test results; and electrical test result data of individual components and soldered circuits.

[0074] Maintenance data is necessary for predictive maintenance and lifespan forecasting utilizing digital twins. This data includes PCB usage history data, such as operating time and usage conditions of PCBs used in specific products; failure data, including past failure history and failure cause analysis data; and lifespan forecast data, including reliability test results and prediction model data.

[0075] In other words, the data collection step for generating a digital twin model of the semiconductor PCB area must collect not only simple shape information but also a wide range of data as described above. In addition to the aforementioned data, it may include various information related to the semiconductor PCB area directly input by the administrator, as well as sensor and measurement devices equipped in the semiconductor PCB area for manufacturing process optimization, quality improvement, and maintenance prediction. At this time, the information directly input by the administrator may be input through various input devices connected to the system, such as an administrator terminal, an administrator PC, or AR or VR devices.

[0076] FIG. 3 is a block diagram showing the process flow of a modeling data optimization processing unit according to the present invention, and FIG. 4 is a block diagram showing the process flow of a lightweight modeling texture baking extraction unit according to the present invention.

[0077] Next, as illustrated in FIGS. 3 and 4, a digital twin model is created based on the data collected during the data collection stage through the modeling data optimization processing unit (200) and the lightweight modeling texture baking extraction unit (300). This process is described in more detail as follows.

[0078] First, a high-capacity 3D model of the semiconductor PCB area is generated based on the data collected during the data collection phase. The process of generating this high-capacity model is explained in more detail as follows.

[0079] Among the data collected during the data collection phase, modeling data for generating a digital twin is aligned. This data alignment is a critical initial step for constructing a digital twin of the semiconductor PCB area; it involves performing preprocessing tasks such as accurately aligning the data collected during the data collection phase within a consistent reference coordinate system. In other words, it is a process that ensures the reliability of digital twin model generation by integrating data of different formats, correcting shape errors between data, and aligning data for accurate basic modeling.

[0080] A step for generating a point cloud may be included before or after this modeling data alignment process. A point cloud refers to the process of creating a three-dimensional data set composed of numerous points by collecting the surfaces of objects or environments through 3D scanning. In this process, each point contains 3D coordinate values, and sometimes information such as color (RGB) and reflectance (intensity) may also be stored. Although the generated point cloud exists simply as point data, it is one of the important data utilized in subsequent processes, as it can be processed to convert into a mesh model or used as data to distinguish sections.

[0081] In one embodiment, after performing scan data alignment, a point cloud generation step can be performed to align the coordinate system of the original data and then generate a point cloud.

[0082] In another embodiment, a point cloud may be generated first by scanning with a 3D scanner, and then the point cloud information may be aligned with other data.

[0083] Next, 2D reference drawings, such as cross-sectional views or plan views, can be generated by creating drawings based on the aligned modeling data. At this time, based on the generated 2D drawings, sections can be separated according to the structural features, functional features, or manufacturing and design standards of the semiconductor PCB area. Here, structural features are based on component placement, layer separation, shape changes, etc., functional features are based on electrical partitioning, wiring density, thermal distribution analysis, etc., and manufacturing and design standards are based on processing units, design blocks, etc. This section separation is performed to improve the ease and reliability of subsequent processes for digital twin generation and to enhance the management and convenience of maintenance.

[0084] In this way, separating the sections reduces memory and computational load, allowing for efficient management of high-capacity models, and optimizing the model at the separated section level facilitates lightweight modeling for subsequent processes. Additionally, separating the sections improves accuracy based on point cloud data for each section and facilitates misalignment correction.

[0085] Furthermore, it is advisable to perform this section separation because it offers various benefits, such as the ability to modify or update only specific sections during maintenance using the finalized lightweight model, making maintenance easier, and allowing optimization methods to be applied individually to each section.

[0086] Next, a 3D mesh drawing can be generated based on a 2D reference drawing, and a basic model can be produced based on this 3D mesh drawing.

[0087] At this time, the 3D mesh drawing and basic model can generate or extract section-specific modeling data for each separated section.

[0088] Based on the basic model data produced in this way, a high-capacity 3D model of the semiconductor PCB area is created by adding detailed geometry and high-resolution information. Since the generated high-capacity model is large in size, and especially in the case of complex structures such as the semiconductor PCB area, the capacity is considerably large, it places a significant burden on rendering and information processing, causing a degradation in maintenance performance and consuming more resources in storage space and processing power to perform these tasks; therefore, such a high-capacity 3D model must be lightweighted.

[0089] Accordingly, the generated high-capacity 3D model is lightweighted to enable real-time rendering by applying mesh simplification and algorithm optimization, thereby creating a low-capacity optimized model. This process involves extracting modeling data from the high-capacity 3D model generated through the aforementioned steps, and performing lightweight processing on the extracted data to create a low-capacity optimized model.

[0090] At this stage, the lightweighting process can be achieved through Decimation techniques, such as polygon reduction, mesh simplification, and polygon reduction transformations that reduce polygons. Additionally, models of various resolutions can be generated by applying the Level of Detail (LOD) method simultaneously with the lightweighting process.

[0091] Next, a low-capacity optimized model capable of texture application is generated through UV unwrapping.

[0092] Next, a texture baking step is performed to extract and optimize texture information using a high-capacity 3D model.

[0093] This texture baking step extracts textures from a high-capacity 3D model created through a high-capacity modeling step, and performs baking based on the extracted textures to generate optimized texture data.

[0094] Then, using baked texture data, colors and textures are generated to be applied to the final lightweight model while maintaining the surface characteristics of the high-capacity 3D model.

[0095] Next, a lightweight model is generated by combining the low-capacity optimization model with texture information, such as color and texture, extracted during the texture baking step. To explain this in more detail, a material is created based on the color and texture data generated during the texture baking step, and this material is assigned to the low-capacity optimization model. Based on the resulting low-capacity optimization model, a final lightweight model is generated.

[0096] FIG. 5 is a block diagram illustrating the metadata combination related content according to the present invention.

[0097] Next, a metadata combination step is performed to combine metadata including semiconductor PCB design information, environment information, and operation information with the lightweight model. Since the semiconductor PCB design information, environment information, operation information, etc. mentioned here are identical to those described in the aforementioned metadata combination unit (400), a detailed explanation is omitted. In this way, the lightweight model is combined with data collected in real time from the data collection unit (100) to enable it to perform the role of a digital twin.

[0098] However, the present invention is intended for semiconductor PCB areas, and it is preferable that it be in an encrypted form to maintain integrity and consistency without changing the format structure of the lightweight model and to prevent external leakage. The metadata encrypted in this way is combined with the lightweight model according to a classification system of static data, dynamic data, and environmental data to create a 3D model of a digital twin corresponding to the actual environment.

[0099] Through the aforementioned process, the lightweight model combined with metadata can be visualized in real time through the visualization unit (600), or the semiconductor PCB area can be easily managed through real-time analysis based on the collected data from the data collection unit (100) provided in real time by the analysis unit (500).

[0100] At this time, real-time visualization of digital twin data including the lightweight model generated through the aforementioned process can be performed by utilizing rendering engines such as WebGL, Unity, and Unreal Engine to render 3D models in real time on the web or in applications. Through this real-time rendering, if an administrator selects a specific model, specific section, or specific location within the digital twin data of the semiconductor PCB area, it is visually displayed so that metadata regarding that area can be viewed. In addition, an AI-based analysis engine can be used to monitor the operational status within the semiconductor PCB area in real time, detect abnormal signs, and visually display them in real time.

[0101] In this way, through the aforementioned process, a digital twin of the semiconductor PCB area that includes engineering data rather than just a simple 3D model is implemented, allowing managers to directly analyze and correct problems within the digital twin, check circuit data in real time using AR glasses, or review the wiring paths of PCB circuits in a virtual space using VR. Furthermore, the disadvantages of the closed environment of the semiconductor PCB area can be overcome through the virtual environment of the digital twin, enabling various workers, researchers, and managers to share data and perform tasks.

[0103] As explained above, those skilled in the art to which the present invention pertains will understand that the present invention may be implemented in other specific forms without altering its technical concept or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. The scope of the present invention is defined by the claims set forth below rather than by the detailed description, and all modifications or variations derived from the meaning and scope of the claims and equivalent concepts should be interpreted as being included within the scope of the present invention. Explanation of the symbols

[0104] 100: Data Collection Unit 200: Modeling Data Optimization Processing Unit 210: High-capacity modeling unit 220: Lightweight Unit 300: Lightweight Modeling Texture Baking Extraction Unit 310: Texture Baking Unit 320: Lightweight Modeling Extraction Unit 400; Metadata combination part 500: Analysis Department 600: Visualization section

Claims

Claim 1 A system for generating a digital twin of a semiconductor PCB area and optimizing the same comprises: a data collection unit that collects data related to manufacturing and testing processes of the semiconductor PCB area in real time; a modeling data optimization processing unit that receives 3D model data of the semiconductor PCB area from the data collected by the data collection unit and generates a digital twin model of the semiconductor PCB area; a lightweight modeling texture baking extraction unit that converts high-resolution surface information into a low-capacity texture based on the data collected by the data collection unit and the digital twin model generated through the modeling data optimization processing unit, thereby reducing data capacity while maintaining the accuracy of the digital twin model; a metadata combining unit that combines metadata for performing real-time analysis and prediction of the semiconductor PCB area by linking information collected by the data collection unit with the lightweight model generated through the modeling texture baking extraction unit; and an analysis unit that checks the current state of the semiconductor PCB area and predicts performance changes using the data combined through the metadata combining unit; wherein the modeling data optimization processing unit comprises a high-capacity modeling unit that generates a high-capacity digital twin model of the PCB area based on the data collected by the data collection unit. A digital twin system for a semiconductor PCB area comprising: a lightweighting unit that reduces the capacity of the high-capacity digital twin model to a low-capacity capacity. Claim 2 delete Claim 3 In claim 1, the data collected by the data collection unit comprises at least one of field equipment data, temperature, current, voltage, vibration, and signal integrity of the semiconductor PCB area, in a digital twin system of the semiconductor PCB area. Claim 4 A digital twin system for a semiconductor PCB area according to claim 1, further comprising a visualization unit that visualizes the digital twin model in real time and executes and displays analysis information from the analysis unit. Claim 5 A method for generating and managing a digital twin of a semiconductor PCB area comprises: a data collection step for collecting data in real time regarding physical structures and characteristics related to semiconductor PCB manufacturing, and semiconductor PCB manufacturing and testing processes; a high-capacity modeling step for generating a high-capacity 3D model of the semiconductor PCB area based on the data collected in the data collection step; a 3D asset lightweighting step for generating a low-capacity optimized model by applying mesh simplification and algorithm optimization to the 3D model generated in the high-capacity modeling step to lightweight it so that real-time rendering is possible; a texture baking step for extracting and optimizing texture information using the high-capacity 3D model; a lightweighting modeling step for generating a lightweight model by combining the low-capacity optimized model generated in the 3D asset lightweighting step and the texture information extracted in the texture baking step; and a metadata combining step for combining metadata including semiconductor PCB design information, environment information, and operation information with the lightweight model. A method for generating and managing a digital twin of a semiconductor PCB area, comprising: a digital twin management step for visualizing or analyzing the lightweight model combined with metadata in real time; wherein the 3D asset lightweighting step comprises: a step of extracting high-capacity 3D modeling data generated in the high-capacity modeling step; a step of generating a low-capacity optimized model by lightweight processing the high-capacity 3D modeling data; and a step of performing UV unwrapping on the low-capacity optimized model. Claim 6 In claim 5, the above data collection step is a method for creating and managing a digital twin of a semiconductor PCB area, which performs a process of digitizing the shape and structure of the semiconductor PCB area using laser scan, CT scan, or drawing data. Claim 7 In claim 5, the high-capacity modeling step comprises: a step of aligning modeling data among the data collected in the data collection step; a step of creating a 2D reference drawing by drawing based on the aligned modeling data; a step of creating a 3D mesh drawing based on the 2D reference drawing; a step of producing a basic model based on the 3D mesh drawing; and a step of creating a high-capacity 3D model by adding detailed shape and high-resolution information based on the basic model data; a method for creating and managing a digital twin of a semiconductor PCB area. Claim 8 A method for generating and managing a digital twin of a semiconductor PCB area according to claim 7, further comprising the step of generating a point cloud before or after the process of aligning the modeling data. Claim 9 A method for generating and managing a digital twin of a semiconductor PCB area according to claim 8, wherein point cloud data is divided into sections based on at least one of structural features, functional elements, manufacturing or design criteria of the semiconductor PCB area based on the above 2D reference drawing. Claim 10 A method for generating and managing a digital twin of a semiconductor PCB area according to claim 9, wherein the 3D mesh drawing generation step and the basic model production step further include a process of extracting section-specific modeling data for each of the separated sections. Claim 11 delete Claim 12 A method for generating and managing a digital twin of a semiconductor PCB area according to claim 5, wherein the texture baking step comprises: a step of extracting a texture from a high-capacity 3D model generated in the high-capacity modeling step; a step of generating optimized texture data by performing baking based on the extracted texture; and a step of generating a color and texture to be applied to the lightweight model generated in the lightweight modeling step while maintaining the surface characteristics of the high-capacity 3D model using the baked texture data. Claim 13 A method for generating and managing a digital twin of a semiconductor PCB area, wherein the lightweight modeling step comprises: a step of creating a material based on generated color and texture data and assigning it to the low-capacity optimization model; and a step of generating a lightweight model based on the low-capacity optimization model to which the material is assigned. Claim 14 A method for generating and managing a digital twin of a semiconductor PCB area according to claim 5, wherein the metadata combining step is performed in an encrypted form to prevent external leakage and to maintain integrity and consistency without changing the format structure of the lightweight model.

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