Method for manufacturing a semiconductor device and a laminate

Abstract

A method for manufacturing a semiconductor device is provided in which cracks or defects do not easily occur in the chips during the manufacturing process, even when the distance between adjacent chips after reorganization is small. The method for manufacturing a semiconductor device having a planar shape that is rectangular is provided by attaching an adhesive sheet along the short side direction of a plurality of rectangular reorganization planned regions arranged in a matrix on the surface of a wafer, and grinding the back surface of the wafer on which the adhesive sheet is attached, while dividing the chips along a division planned line that defines the reorganization planned regions.

Description

Technology Field

[0001] The present invention relates to a method for manufacturing a semiconductor device and a laminate used in the method for manufacturing a semiconductor device. Background Technology

[0002] A method called DBG (Dicing Before Grinding) is known as a manufacturing process for semiconductor devices, such as semiconductor chips, in which semiconductor circuits are formed on a silicon substrate. DBG is a method of dividing a wafer into individual semiconductor chips by forming grooves of a depth corresponding to the finishing thickness on the wafer's surface and grinding the back side of the wafer to expose the previously formed grooves from the back side of the wafer.

[0003] A method called SDBG (Stealth Dicing Before Grinding) has also been proposed for the purpose of increasing the number of chips obtained from a single wafer. SDBG is a processing method in which a laser focusing point with a wavelength that is permeable to the wafer is positioned inside the wafer, and the laser is irradiated onto the wafer along a line to be divided to form a modified layer by multiphoton absorption inside the wafer, and then the back side of the wafer is ground to thin the wafer, and the wafer is divided into individual semiconductor chips using the modified layer as the division point.

[0004] When using a processing method such as SDBG, where the gap between chips in a divided wafer becomes very small, defects or cracks may occur in the divided semiconductor chips. For this reason, for example, Patent Document 1 proposes forming a defect prevention layer made of a metal film or the like at each intersection of the planned division lines on the wafer surface. Prior art literature

[0005] Japanese Patent Publication No. 2018-6653 The problem to be solved

[0006] However, the demand for miniaturization of chip size is increasing, and along with the miniaturization of semiconductor chips, the problem of cracks or defects in semiconductor chips has become significant. According to the inventors' investigation, it has been found that when using methods such as minimizing the gap formed by dicing in DBG or using methods such as SDBG where the gap between adjacent chips is substantially zero at the time of wafer division, the problem of cracks or defects caused by contact between adjacent chips becomes more significant as the chip size is miniaturized. Therefore, there is a need for a novel and useful method for manufacturing a semiconductor device that can more effectively prevent chip defects or cracks.

[0007] The present invention aims to provide a method for manufacturing a semiconductor device in which cracks or defects do not easily occur in the chips during the manufacturing process, even when the distance between adjacent chips after reorganization is small, in consideration of the above problem, and a laminate suitable therefor. means of solving the problem

[0008] The inventors, after conducting repeated examinations to solve the above problem, discovered that the problem can be solved by appropriately setting the attachment direction of an adhesive sheet attached to the circuit layer forming surface of a wafer based on the planned area of ​​the wafer to be reorganized, and thus completed the present invention.

[0009] That is, the present invention provides the following [1] to [6].

[0010] [1] A method for manufacturing a semiconductor device having a rectangular planar shape,

[0011] An adhesive sheet is attached along the short side direction of a plurality of rectangular areas scheduled for reorganization arranged in a matrix on the surface of a wafer, and

[0012] A method for manufacturing a semiconductor device, comprising grinding the back surface of a wafer to which the adhesive sheet is attached, and dividing the wafer along a planned division line that defines the area to be reorganized.

[0013] [2] After attaching the adhesive sheet to the surface of the wafer, a modified portion that serves as the starting point for division is formed inside the wafer at a planar position corresponding to the planned division line, and

[0014] A method for manufacturing a semiconductor device as described in [1], which involves grinding the back side of the wafer to which the adhesive sheet is attached and dividing the wafer along the planned dividing line.

[0015] [3] A method for manufacturing a semiconductor device as described in [1] or [2], wherein the aspect ratio, expressed as the length of the long side of the area to be reorganized / the length of the short side, is 1.05 or greater.

[0016] [4] The above-mentioned reorganization area has a length in the long direction of 5 to 50 mm and a length in the short direction of 2 to 20 mm, and is a method for manufacturing a semiconductor device as described in any one of [1] to [3].

[0017] [5] A transfer sheet is attached to the back side of the wafer after grinding, and

[0018] A method for manufacturing a semiconductor device described in any one of [1] to [4], wherein the adhesive sheet is separated from the wafer after the transfer sheet is attached.

[0019] [6] A wafer containing multiple rectangular areas scheduled for reorganization listed in a matrix, and

[0020] A laminate having an adhesive sheet attached to the surface of the wafer while tension is applied along the short side direction of the area scheduled for reorganization. Effects of the invention

[0021] According to the present invention, even when the distance between adjacent chips after reorganization is small, a method for manufacturing a semiconductor device in which cracks or defects do not easily occur in the chips during the manufacturing process, and a laminate suitable therefor can be provided. Brief explanation of the drawing

[0022] FIG. 1 is a schematic cross-sectional view of a semiconductor chip as a semiconductor device obtained by processing the wafer using a wafer having a circuit layer formed thereon, a laminate having an adhesive sheet attached to the circuit layer of the wafer, and the wafer using the laminate. FIG. 2 is an explanatory diagram showing the relationship between the attachment direction of the adhesive sheet to the wafer and the area scheduled for reorganization on the wafer. Figure 3 is a schematic cross-sectional view illustrating the manufacturing process of a laminate. Figure 4 is a schematic cross-sectional view illustrating the manufacturing process of a semiconductor device. Figure 5 is a schematic cross-sectional view illustrating the manufacturing process of a semiconductor device. FIG. 6 is a schematic plan view showing a comparison between a wafer used in a method for manufacturing a semiconductor device related to an embodiment of the present invention and a wafer used in a method for manufacturing a semiconductor device related to a comparative example. Specific details for implementing the invention

[0023] Hereinafter, embodiments of the present invention (hereinafter referred to as “the present embodiments”) will be described.

[0024] [Wafer, stack, and semiconductor device]

[0025] The semiconductor device manufactured by the method of manufacturing a semiconductor device according to the present embodiment comprises a wafer portion and a circuit portion formed on the surface thereof, and has a planar shape that is rectangular. In this specification, the term "semiconductor device" refers to any device capable of functioning by utilizing semiconductor characteristics, such as a processor, memory, or sensor. Specifically, examples include a wafer having an integrated circuit, a thinned wafer having an integrated circuit, a chip having an integrated circuit, a thinned chip having an integrated circuit, an electronic component including these chips, and electronic devices having said electronic component. Chips prior to packaging are also included.

[0026] A semiconductor device is obtained by reorganizing a wafer on which a circuit layer is formed on the surface.

[0027] In addition, in a process of processing a wafer having a circuit layer formed thereon into a semiconductor device, a laminate having an adhesive sheet attached to the circuit layer forming surface of the wafer is used.

[0028] Hereinafter, a wafer, a stack, and a semiconductor device related to embodiments of the present invention will be described using the drawings.

[0029] FIG. 1 is a schematic cross-sectional view of a semiconductor chip as a semiconductor device obtained by processing a wafer having a circuit layer formed thereon, a laminate having an adhesive sheet attached to the surface of the wafer having a circuit layer formed thereon.

[0030] As shown in FIG. 1(A), first, a wafer (W) having a circuit layer (C) formed on its surface is prepared by a semiconductor formation process including photolithography.

[0031] Next, as shown in FIG. 1(B), an adhesive sheet (1) is attached to the surface of the wafer (W) where the circuit layer (C) is formed, thereby obtaining a laminate (10).

[0032] In addition, as shown in FIG. 1(C), the back surface of the wafer (W) is ground as necessary, and the wafer (W) is divided along a planned division line that defines the area to be reorganized, thereby becoming the wafer (WI) after reorganization. In this way, the wafer (W) having the circuit layer (C) is reorganized into multiple wafers to obtain a semiconductor chip (CP) as a semiconductor device. The area to be reorganized will be explained in detail later.

[0033] <Wafer>

[0034] A wafer (W) is a disc-shaped piece of high-purity single-crystal silicon. The diameter of the wafer (W) is not limited to, but is, for example, 12 inches.

[0035] The circuit layer (C) is a layer containing a semiconductor circuit formed on the surface of a wafer (W) by a semiconductor manufacturing process.

[0036] The semiconductor process includes a process of forming a thin film of silicon oxide or aluminum, which serves as a circuit material, on a silicon wafer by sputtering, electroplating, CVD, etc., and then forming a semiconductor circuit by photolithography.

[0037] The photolithography method comprises a process of coating the thin film formed on a silicon wafer with a resist film, a process of irradiating the resist film with UV light through a mask having a circuit pattern formed thereon, a process of selectively removing an uncured portion of the resist film by developing it, a process of removing the thin film exposed by developing it by etching it, a process of imparting semiconductor properties to the silicon substrate exposed by etching it with impurities such as phosphorus or boron, a process of activating impurity ions by heat treatment using a flash lamp or laser irradiation, and a process of peeling off the resist film.

[0038] <Semiconductor Device>

[0039] A wafer (W) is divided, for example, into multiple semiconductor chips, each approximately 12 mm × 6 mm in size when viewed from a flat surface. When divided into this size, approximately 1,000 semiconductor chips are obtained from a 12-inch diameter wafer.

[0040] A semiconductor chip, which is a semiconductor device, has a wafer portion derived from a wafer (W) and a circuit portion derived from a circuit layer (C) formed on its surface, as described above.

[0041] The semiconductor chip obtained by the method for manufacturing a semiconductor device of the present embodiment has a rectangular planar shape. Because of this, various functions can be imparted to the semiconductor chip, or the top and bottom of the semiconductor chip can be easily identified.

[0042] <Laminated>

[0043] The laminate (10) is formed by attaching an adhesive sheet (1) to the surface of a wafer (W) on which a circuit layer (C) is formed.

[0044] (Adhesive sheet)

[0045] The adhesive sheet (1) is a laminate comprising a substrate layer and an adhesive layer laminated on the substrate layer, and typically comprises a substrate layer, a buffer layer formed on at least one side of the substrate layer, and an adhesive layer formed on the other side of the substrate layer. The adhesive sheet (1) may include other constituent layers other than these, for example, a primer layer may be formed on the surface of the substrate on the adhesive layer side, and a release sheet for protecting the adhesive layer until use may be laminated on the surface of the adhesive layer. Also, the substrate may be a single layer or a multi-layer. The buffer layer and the adhesive layer are also the same. By making the adhesive layer of the adhesive sheet (1) contact the circuit layer (C) of the wafer (W) so that the adhesive sheet (1) is attached to the wafer (W), the adhesive sheet (1) acts as a protective film that protects the circuit layer (C) of the wafer (W).

[0046] (Recording layer)

[0047] The material of the substrate layer is not particularly limited, but it is preferable to be a resin film because it is desirable for processing electronic components as it generates less dust compared to paper or nonwoven fabric, and it is easy to obtain. By having a substrate layer, the shape stability of the adhesive sheet can be improved or elasticity can be imparted to the adhesive sheet. Also, even when the irregularities of the circuit layer (C) of the wafer (W) are large, the side opposite to the adhesive sheet is easily maintained smooth.

[0048] The substrate layer may be a substrate layer consisting of a single layer film made of one resin film, or a substrate layer consisting of a multilayer film in which a plurality of resin films are laminated.

[0049] The thickness of the substrate layer is preferably 5 to 250 μm, more preferably 10 to 200 μm, and even more preferably 25 to 150 μm, from the perspective of providing appropriate elasticity to the adhesive sheet and handling ability when the adhesive sheet is rolled up.

[0050] Examples of resin films that can be used in the substrate layer include, for instance, polyolefin-based films, vinyl halogenated polymer-based films, acrylic resin-based films, rubber-based films, cellulose-based films, polyester-based films, polycarbonate-based films, polystyrene-based films, polyphenylene sulfide-based films, cycloolefin polymer-based films, and films composed of cured products of an energy beam curable composition containing urethane resin.

[0051] The polyester film used in the substrate layer may be a film composed of a copolymer of polyester, or a resin-mixed film composed of a mixture of the polyester and a relatively small amount of another resin. Among these polyester films, a polyethylene terephthalate film is preferred from the perspective of being easy to obtain and having high thickness precision.

[0052] (Adhesive layer)

[0053] The adhesive layer formed on the substrate layer or intermediate layer protects the circuit layer (C) by securely fixing the adhesive sheet to the circuit layer (C) of the wafer (W).

[0054] The adhesive layer contains an adhesive. Examples of adhesives include acrylic adhesives, rubber adhesives, urethane adhesives, silicone adhesives, polyvinyl ether adhesives, olefin adhesives, etc. One or more of these adhesives may be used in combination.

[0055] The thickness of the adhesive layer can be appropriately adjusted according to the size of the irregularities of the circuit layer to be protected, but is preferably 5 to 200 μm, more preferably 7 to 150 μm, and even more preferably 10 to 100 μm.

[0056] (Middle layer)

[0057] The intermediate layer is not particularly limited, but is preferably formed of a resin composition containing urethane (meth)acrylate and a thiol group-containing compound in order to obtain good unevenness absorption.

[0058] The thickness of the intermediate layer can be appropriately adjusted according to the size of the irregularities on the surface of the semiconductor to be protected, but in terms of enabling absorption of relatively large irregularities, it is preferably 50 to 400 μm, more preferably 70 to 300 μm, and even more preferably 80 to 250 μm.

[0059] (Application direction of the adhesive sheet)

[0060] FIG. 2 is an explanatory diagram showing the relationship between the attachment direction of the adhesive sheet (1) to the wafer (W) and the reorganization planned area (R) on the wafer (W).

[0061] As shown in FIG. 2(A), on the surface of the wafer (W), a semiconductor circuit is formed within an individual reorganization planned area (R) defined by a V-notch (Wv) indicating a reference direction for processing or machining of the wafer (W) and a planned division line (E). The semiconductor circuit is formed based on the direction indicated by the V-notch (Wv). In addition, the lamination of the adhesive sheet described later is also carried out based on the direction indicated by the V-notch (Wv).

[0062] Here, the area scheduled for reorganization (R) is rectangular when viewed from a planar perspective. The planned division line (E) defining the area scheduled for reorganization (R) is virtual, and individual circuits are formed so as not to cross the planned division line (E), and there is no need to physically form the planned division line (E) defining the area scheduled for reorganization (R) on the surface of the wafer (W) or the circuit layer (C). However, in order to make the area scheduled for reorganization (R) easier to recognize or to ensure that the division of the wafer (W) proceeds smoothly, a processing groove or the like that becomes the planned division line (E) may be formed in advance by photolithography.

[0063] By making the area (R) scheduled for reorganization into a square shape, the shape of the semiconductor chip obtained finally becomes a square.

[0064] In the example shown in FIG. 2(A), each circuit of the circuit layer (C) is formed such that the short side direction (d2) of each reorganization planned area (R) coincides with the direction (d3) indicated by the V-notch (Wv) (hereinafter also referred to as the longitudinal direction). Thus, the long side direction (d1) of the reorganization planned area coincides with the direction orthogonal to the direction (d3) indicated by the V-notch (Wv) (hereinafter also referred to as the transverse direction).

[0065] The length of the long side of the area (R) scheduled for reorganization is preferably 5 to 50 mm, more preferably 7 to 40 mm, and even more preferably 10 to 30 mm, from the perspective of making it easier to suppress defects or cracks in the semiconductor chip during the manufacturing process and to make it easier to impart various functions to the semiconductor chip.

[0066] The length of the short side direction of the area (R) scheduled for reorganization is preferably 2 to 20 mm, more preferably 3 to 18 mm, and even more preferably 4 to 15 mm, from the perspective of increasing ease of handling or making it easier to impart the minimum necessary functions to the semiconductor chip.

[0067] The aspect ratio, expressed as the ratio of the length in the long direction to the length in the short direction of the area (R) scheduled for reorganization (length in the long direction / length in the short direction), is preferably 1.05 or higher, more preferably 1.10 or higher, and even more preferably 1.15 or higher, in order to appropriately maintain a balance between the ability to suppress defects or cracks in the semiconductor chip during the manufacturing process and the ability to impart functionality to the semiconductor chip; furthermore, it is preferably 10 or lower, more preferably 7.0 or lower, and even more preferably 5.0 or lower.

[0068] In addition, in this embodiment, as described below, when manufacturing a semiconductor device, the wafer (W) is divided by the SDBG, so the distance between adjacent chips is substantially zero. Because of this, the longitudinal and transverse lengths of the reorganization planned area (R) match the longitudinal and transverse lengths of the semiconductor chip.

[0069] In addition, semiconductor circuits may not be formed outside the area scheduled for reorganization (R), and unused semiconductor circuits outside the area scheduled for reorganization may be formed as dummy circuits.

[0070] As shown in FIG. 2(B), the adhesive sheet (1) has a length and width that can cover the entire surface of the wafer (W). When using a wafer (W) with a diameter of 12 inches, for example, a long adhesive sheet (1) with a width of 400 mm can be used. Also, in FIG. 2(B), the wafer (W) covered by the adhesive sheet (1) and the area (R) scheduled for reorganization are shown as thin lines to facilitate understanding. If the adhesive sheet (1) is light-transmitting, the shape and alignment direction of the area (R) scheduled for reorganization can be confirmed through the adhesive sheet (1).

[0071] When attaching the adhesive sheet (1), the wafer (W) is set in the bonding device based on the direction (d3) indicated by the V-notch (Wv). At this time, the wafer (W) is set so that the attachment direction (d4) of the adhesive sheet (1) by the bonding device follows the direction (d3) indicated by the V-notch (Wv). Thus, in this embodiment, the short side direction (d2) of the area (R) to be reorganized follows the direction (d3) indicated by the V-notch (Wv).

[0072] After the adhesive sheet (1) is attached to the circuit layer (C) of the wafer (W), the adhesive sheet (1) protruding from the wafer (W) is cut and removed as needed. As described below, if the adhesive sheet (1) is attached by a method such as attaching it while applying tension to eliminate bending of the adhesive sheet (1), the adhesive sheet (1) is attached to the circuit layer (C) with tension applied along the attachment direction (d4) of the adhesive sheet (1). Thus, a laminate (10) is formed with tension applied along the short side direction (d2) of the area (R) scheduled for reorganization.

[0073] Here, the attachment direction (d4) of the adhesive sheet is set to follow the direction (d3) indicated by the V-notch (Wv) (in short, in this example, the short side direction (d2) of the area (R) to be reorganized), but as shown in FIG. 2(B), the attachment direction (d4) of the adhesive sheet (1) can be set to be within a certain angle (θ) with respect to the direction (d3) indicated by the V-notch (Wv). Here, θ is preferably within the range of ± 45°, more preferably ± 40°, and even more preferably ± 35° with respect to the direction (d3) indicated by the V-notch (Wv).

[0074] [Method for manufacturing a laminate]

[0075] FIG. 3 is a schematic cross-sectional view illustrating the manufacturing process of a laminate. FIG. 3(A) is a drawing showing a wafer (W) having a circuit layer (C) formed thereon placed on a support (100), FIG. 3(B) is a drawing showing an adhesive sheet (1) attached to the circuit layer (C) of the wafer (W), and FIG. 3(C) is a drawing showing the adhesive sheet (1) attached to the circuit layer (C) of the wafer (W).

[0076] As shown in FIG. 3(A), the wafer (W) is placed on the support (100) so that the back surface of the wafer (W) on which the circuit layer (C) is formed contacts the support (100), and then, as shown in FIG. 3(B), an adhesive sheet (1) is attached to the circuit layer (C) of the wafer (W). In this example, one end of the adhesive sheet (1) is wound with a winding member or held with a gripping member to be held in a state lifted from the wafer (W), and the adhesive sheet (1) is sequentially pressed from the other end by a pressure member (101) while the adhesive sheet (1) is attached to the surface on which the circuit layer (C) of the wafer (W) is formed.

[0077] At this time, in order to eliminate as much sagging of the adhesive sheet (1) as possible, a constant tension is applied in the longitudinal direction of the adhesive sheet (1) (in other words, the attachment direction of the adhesive sheet (1)), or a pressing force by a pressurizing body is applied in the longitudinal direction of the adhesive sheet (1), so that the adhesive sheet (1) is attached to the wafer (W) with tension applied in the attachment direction (d4). The adhesive sheet (1) is attached to the circuit layer (C) of the wafer (W) with almost no tension applied in the width direction of the adhesive sheet (1).

[0078] After the adhesive sheet (1) is attached to the circuit layer (C), the adhesive sheet (1) protruding from the wafer (W) is cut and removed as needed. In this way, a laminate (10) with the adhesive sheet (1) attached to the circuit layer (C) of the wafer (W) is manufactured as shown in FIG. 3(C).

[0079] In addition, there are no particular restrictions on the material constituting the support (100), and for example, metal materials such as stainless steel are used.

[0080] [Method for manufacturing a semiconductor device]

[0081] An example of a method for manufacturing a semiconductor device according to the present embodiment includes a process of processing a laminate having an adhesive sheet attached to a circuit layer of a wafer, dividing the wafer and grinding the back side of the wafer, attaching a transfer sheet to a surface opposite to the circuit layer forming surface of the divided wafer (in other words, the back side of the wafer), removing the adhesive sheet, and then dividing and reorganizing the wafer together with the transfer sheet. Each process will be described sequentially below. In addition, a transfer sheet is a sheet that is attached to the back side of a wafer so that, after the wafer is separated from the adhesive sheet, the wafer is transferred to its surface to hold the wafer.

[0082] Figures 4 and 5 are schematic cross-sectional views illustrating the manufacturing process of a semiconductor device.

[0083] FIG. 4(A) is a drawing showing a state in which a laminate (10) is placed on a support (200) separate from the support (100). As shown in FIG. 4(A), the laminate (10) is placed on the support (200) so that the adhesive sheet (1) comes into contact with the support (200). Additionally, for the support (200), for example, a porous table made of the same material as the support (100) or a ceramic material may be used.

[0084] FIG. 4(B) is a diagram showing a laser being irradiated onto a wafer (W) from the back side. As shown in FIG. 4(B), a condenser (102) is used to position the laser (103) so that the point of concentration of the laser (103), which has a wavelength that is permeable to the wafer (W), becomes the interior of the wafer (W). Then, the laser (103) and the wafer (W) are moved relative to each other along a planned division line (E) that defines a planned division area (R), and the laser (103) is irradiated onto the wafer (W) from the back side. As a result, a modified portion (M) is formed inside the wafer (W) at a planar position corresponding to the planned division line (E). The modified portion (M) is a part of the wafer (W) that has been modified by the laser irradiation and serves as the starting point for the wafer (W) to be divided.

[0085] FIG. 4(C) is a drawing showing the back side of a wafer (W) being ground. As shown in FIG. 4(C), the back side of the wafer (W) is ground using a grinder (104) until it reaches a desired thickness. Through this process, the wafer (W) becomes thinner and lighter. At the same time, the wafer (W) is divided along a planned division line (E) that defines a planned area (R) starting from the modified part (M). Also, the modified part (M) formed within the wafer (W) is removed by grinding.

[0086] In SDBG, when the wafer is split during grinding, only cracks caused by stealth dicing (referenced P in Fig. 4(C)) exist between adjacent chips, and the distance between chips is practically zero. Because of this, chips are easily shifted by slight stress or impact, causing contact, pressure, friction, or collision between chips, resulting in a situation where cracks are likely to occur. In addition, when an adhesive sheet, such as a protective sheet for back grinding, is attached, tension is applied in the direction of attachment, so stress is likely to remain in the laminate after the adhesive sheet is attached. Because of this, as the back side of the wafer is ground, the wafer (W) is split into individual chips starting from the modified part (M), and at the same time, the stress within the laminate is released, making it easy for the chips to move in the direction of attachment of the adhesive sheet, and consequently, it is presumed that the chips contact, pressure, friction, or collision between chips causes cracks.

[0087] In the method for manufacturing a semiconductor device according to the present embodiment, the reason why defects or cracks in the chip are suppressed is not limited to this, but one reason is the following. In short, by making the longitudinal length and transverse length of the chip different and attaching an adhesive sheet along the short side direction of the chip, the number of cutting lines between chips in the direction of attachment of the adhesive sheet increases compared to the case where the adhesive sheet is attached along the long side direction of the chip. As a result, the amount of movement of the chip in the direction of attachment is distributed among more chips, and contact, pressure, friction, collision, etc. between chips are reduced, which is presumed to lead to the suppression of cracks or defects.

[0088] In addition, in the present embodiment, the modified portion is removed by grinding, but for example, in applications where wafer thinning is not required or where the wafer is originally thick, at least a portion of the modified portion may remain on the wafer even after grinding.

[0089] FIG. 5(A) shows a process of separating a laminate (11) in which a wafer (W) is ground and divided from a support (200). FIG. 5(B) shows a process of attaching a laminate (11) in which a wafer (W) is ground and divided to a transfer sheet held in a ring frame (300). FIG. 5(C) shows a process of separating an adhesive sheet (1) from a laminate (11) attached to a transfer sheet (303). FIG. 5(D) is an expand process of separating individual chips together with a transfer sheet (303).

[0090] As shown in FIG. 5(A), a laminate (11) in which a wafer (W) is ground and divided and separated from a support (200) is attached to a film adhesive (301) of a transfer sheet (303) comprising a film adhesive (301) and a support sheet (302), which is maintained by a ring frame (300) as shown in FIG. 5(B). Then, as shown in FIG. 5(C), the adhesive sheet (1) is separated from the laminate (11) in which the wafer (W) is ground and divided, and as shown in FIG. 5(D), the film adhesive (301) is also cut to fit the chip by pulling the support sheet (302) (the film adhesive after cutting is indicated by reference numeral 301a), and the chips are separated into individual chips with a gap (G) between them.

[0091] Additionally, as for the transfer sheet (303), for example, a film-like adhesive (301) having curability can be formed by interposing an adhesive layer as needed on a support sheet (302) that includes a substrate made of the same material as the substrate layer of the adhesive sheet (1) described above.

[0092] According to the above manufacturing method, it is possible to manufacture semiconductor devices with a high yield rate while suppressing the occurrence of chip defects or cracks during the manufacturing process.

[0093] In addition, in this embodiment, the wafer is divided using SDBG, but it is not limited to this, and for example, the wafer may be divided using DBG. When using DBG, if the distance between chips formed by dicing is small, the effect of preventing chip defects or cracks is easily achieved. When using DBG, the wafer is half-cut from the surface of the wafer on which the circuit layer is formed, an adhesive sheet is attached to the circuit-forming surface of the wafer, and then the back surface of the wafer is ground.

[0094] Examples

[0095] Next, specific embodiments of the present invention will be described, but the present invention is not limited in any way by these examples.

[0096] [Examples and Comparative Examples]

[0097] The chips of Examples 1 to 3 and Comparative Examples 1 to 4 were manufactured in the following order. In addition, for Examples 1 to 3 and Comparative Examples 1 to 4, mirror wafers without any circuit layers were used to match the experimental conditions as much as possible and to facilitate the experiment.

[0098] <Example 1>

[0099] A mirror wafer of single-crystal silicon with a diameter of 12 inches was prepared, and based on the V-notch formed in the mirror wafer, an adhesive sheet was attached to one side of the wafer (hereinafter referred to as the first surface) along the direction indicated by the apex of the V-notch (hereinafter referred to as the longitudinal direction). As the adhesive sheet, the back grind tape "E-3135KN" manufactured by Lintec Co., Ltd. was used. The attachment of the adhesive sheet was carried out using an attachment device ("RAD-3510F / 12" manufactured by Lintec Co., Ltd.) under conditions of an indentation depth of 15 μm, an outdentation depth of 150 μm, an attachment speed of 5 mm / s, an attachment stress of 0.35 MPa, and an attachment temperature of 23 ℃.

[0100] Next, SDBG was performed such that the longitudinal length was 6 mm and the length in the direction orthogonal to the longitudinal direction (hereinafter referred to as the transverse direction) was 12 mm. Specifically, using the stealth dicing laser "DFL7361" manufactured by DISCO Co., Ltd., laser irradiation was performed from the side of the surface opposite to the first surface of the wafer (hereinafter referred to as the second surface) to form a modified layer inside the wafer such that a modified area of ​​6 mm in height × 12 mm in width was formed by arranging 980 areas in a matrix.

[0101] In addition, by using a backside grinding device ("DPG8760" manufactured by DISCO Co., Ltd.) to grind the other side of the wafer (hereinafter referred to as the second surface) until the thickness of the wafer becomes 30 μm, the modified layer inside the wafer is removed, and the wafer is divided along a planned division line that defines each planned area for reorganization.

[0102] Next, the dicing tape ("D-175" manufactured by Lintec Co., Ltd.) installed on the tape mounter "RAD-2700" manufactured by Lintec Co., Ltd. was attached to the second surface of the reorganized wafer, and the adhesive sheet was removed. Then, using an IR camera installed on the stealth dicing laser, the presence or absence of cracks was observed from the first surface side, and the number of chips with cracks was counted.

[0103] One out of 980 chips had a crack, and the crack rate was 0.10%.

[0104] <Example 2>

[0105] A wafer having an adhesive sheet attached to the first surface along the longitudinal direction in the same order as in Example 1 was processed by SDBG under the same conditions as in Example 1, except that the longitudinal length was 4 mm and the transverse length was 12 mm, and the wafer was reorganized into 1471 chips.

[0106] As a result of observing in the same manner as in Example 1, the number of chips that developed a crack was 1 out of 1,471, and the crack occurrence rate was 0.07%.

[0107] <Example 3>

[0108] A wafer having an adhesive sheet attached to the first surface along the longitudinal direction in the same order as in Example 1 was processed by SDBG under the same conditions as in Example 1, except that the longitudinal length was 8 mm and the transverse length was 12 mm, and the wafer was reorganized into 735 chips.

[0109] As a result of observing in the same manner as in Example 1, the number of chips with cracks was 1 out of 735, and the crack occurrence rate was 0.13%.

[0110] <Comparative Example 1>

[0111] A wafer having an adhesive sheet attached to the first surface along the longitudinal direction in the same order as in Example 1 was processed by SDBG under the same conditions as in Example 1, except that the longitudinal length was 12 mm and the transverse length was 6 mm, and the wafer was reorganized into 980 chips.

[0112] FIG. 6 is a schematic plan view showing an embodiment of the present invention and a comparative example. As shown in FIG. 6(A), in the wafer (W1) of Examples 1 and 2, the attachment direction (d4) of the adhesive sheet (1) and the short side direction (d2) of the area (R) to be reorganized are aligned with the direction (d3) indicated by the V-notch (Wv). Meanwhile, as shown in FIG. 6(B), in the wafer (W2) of Comparative Example 1, the attachment direction (d4) of the adhesive sheet and the long side direction (d1) of the area (R) to be reorganized are aligned with the direction (d3) indicated by the V-notch.

[0113] As a result of observing in the same manner as in Example 1, 11 out of 980 chips were found to have cracks, and the crack occurrence rate was 1.12%.

[0114] <Comparative Example 2>

[0115] A wafer with an adhesive sheet attached to its first surface in the same manner as in Example 1 was processed by SDBG under the same conditions as in Example 1, except that the longitudinal length was 12 mm and the transverse length was 4 mm, and the wafer was reorganized into 1471 chips.

[0116] As a result of observing in the same manner as in Example 1, the number of chips with cracks was 14 out of 1471, and the crack occurrence rate was 0.95%.

[0117] <Comparative Example 3>

[0118] SDBG processing was performed on a wafer having an adhesive sheet attached to the first surface in the same manner as in Example 1, except that the longitudinal length was 12 mm and the transverse length was 12 mm, and the wafer was reorganized into 490 chips.

[0119] As a result of observing in the same manner as in Example 1, the number of chips that developed cracks was 6 out of 490, and the crack occurrence rate was 1.22%.

[0120] <Comparative Example 4>

[0121] A wafer with an adhesive sheet attached to its first surface in the same manner as in Example 1 was processed by SDBG under the same conditions as in Example 1, except that the longitudinal length was 12 mm and the transverse length was 8 mm, and the wafer was reorganized into 735 chips.

[0122] As a result of observing in the same manner as in Example 1, 9 out of 735 chips were found to have cracks, and the crack occurrence rate was 1.22%.

[0123] The results of Examples 1 to 3 and Comparative Examples 1 to 4 are shown in Table 1.

[0124]

[0125] As is evident from the results in Table 1, in Examples 1 to 3, where the attachment direction of the adhesive sheet and the short side direction of the chip are aligned, it can be seen that the number of chips that caused cracks is small and the crack occurrence rate is also very small.

[0126] In contrast, in Comparative Examples 1, 2, and 4, where the attachment direction of the adhesive sheet and the long side direction of the chip are aligned, the number of chips with cracks increases. In particular, it can be seen that the crack occurrence rate values ​​in Comparative Examples 1 and 2 have increased by more than 10 times compared to Examples 1 and 2, respectively, and that Comparative Example 4 has increased by nearly 10 times compared to Example 3.

[0127] In addition, in Comparative Example 3, in which the shape of the chip is square and the length of one side is equal to the length of the long side of the chip in Examples 1 to 3, it can be seen that the number of chips that caused cracks increases, and the value of the crack occurrence rate increases by more than 10 times compared to Examples 1 and 2, and increases by nearly 10 times compared to Example 3.

[0128] Industrial applicability

[0129] The method for manufacturing a semiconductor device according to the present invention does not easily cause chip defects or cracks even when using processing methods such as SDBG that divide a wafer so that the distance between chips becomes very small, and can be preferably applied to the manufacture of semiconductor chips used in processors, memory, sensors, etc. In addition, the laminate of the present invention can be preferably used in the method for manufacturing a semiconductor device. Explanation of the symbols

[0130] 1 : Adhesive sheet 10 : Laminate 11: A laminate in which the wafer portion is ground and divided 100, 200 : Support 101 : Pressure body 102 : Concentrator 103 : Laser 104 : Grinder 300 : Ring frame 301: Film adhesive 301a: Cut film adhesive 302: Support sheet 303: Transfer Sheet C: Circuit layer CP: Semiconductor chip (semiconductor device) d1 : Long side direction d2 : Short side direction d3 : Direction indicated by the V-notch d4 : Attachment direction (tension direction) E: Planned division line G : Gap M : Modification part P: Crack R : Area scheduled for reorganization Wv : V notch W : Wafer WI: Reorganized Wafer

Claims

Claim 1 A method for manufacturing a semiconductor device having a planar shape that is rectangular, wherein an adhesive sheet is attached along the short side direction of a plurality of rectangular areas scheduled for reorganization arranged in a matrix on the surface of a wafer, and the back surface of the wafer on which the adhesive sheet is attached is ground, and the wafer is divided along a planned division line defining the areas scheduled for reorganization, and the aspect ratio, expressed as the length in the long side direction of the areas scheduled for reorganization and the length in the short side direction, is 1.05 or more and 7.0 or less. Claim 2 A method for manufacturing a semiconductor device according to claim 1, wherein, after attaching the adhesive sheet to the surface of the wafer, a modified portion serving as a starting point for division is formed inside the wafer at a planar position corresponding to the planned division line, and the wafer is divided along the planned division line while grinding the back surface of the wafer to which the adhesive sheet is attached. Claim 3 delete Claim 4 A method for manufacturing a semiconductor device according to claim 1 or 2, wherein the area scheduled for reorganization has a length in the long side direction of 5 to 50 mm and a length in the short side direction of 2 to 20 mm. Claim 5 A method for manufacturing a semiconductor device according to claim 1 or 2, wherein a transfer sheet is attached to the back side of the wafer after grinding, and after the transfer sheet is attached, the adhesive sheet is separated from the wafer. Claim 6 A laminate comprising a disc-shaped wafer including a plurality of rectangular areas scheduled for reorganization arranged in a matrix, and an adhesive sheet attached to the surface of the wafer while tension is applied along the short side direction of the areas scheduled for reorganization, wherein the aspect ratio, expressed as the length in the long side direction of the areas scheduled for reorganization and the length in the short side direction, is 1.05 or greater and 7.0 or less.

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