Epitaxial growth substrate and method for manufacturing the same, and semiconductor substrate and method for manufacturing the same

Abstract

The purpose is to obtain a substrate for epitaxial and non-epitaxial growth of group III nitrides such as AlN, AlxGa1-xN (0 < X ​​< 1), and GaN, which have few crystal defects, are of high quality, and are inexpensive. The substrate for epitaxial growth comprises a support substrate, a planarization layer of 0.5 to 3 μm installed on the upper surface of the support substrate, and a seed crystal layer installed on the upper surface of the planarization layer. The support substrate includes a core of polycrystalline ceramics of group III nitrides and an encapsulation layer of 0.05 to 1.5 μm that encapsulates the core. The seed crystal layer is installed by thin-film transfer of a surface layer of 0.1 to 1.5 μm of Si <111> single crystal having an oxidation-induced stacking fault (OSF) of 10 or fewer / cm2.

Description

Technology Field

[0001] The present invention relates to aluminum nitride (AlN) and aluminum gallium nitride (Al x Ga1 － x The present invention relates to a seed substrate for epitaxial and flawless epitaxial growth of high-performance Group III nitrides, such as N (where 0 < x < 1) and gallium nitride (GaN), and a method for manufacturing the same. More specifically, it relates to AlN, Al₂O₃, which are high-quality and low-cost materials with very few crystal defects, warping, or voids. x Ga1 － x The present invention relates to a substrate for epitaxial and non-epitaxial growth of group III nitrides such as N(0<X<1) and GaN-based, and a method for manufacturing the same. Background Technology

[0002] Crystal substrates of Group III nitrides, such as AlN and GaN, possess a wide band gap and exhibit excellent high-frequency characteristics, including short-wavelength luminescence and high voltage resistance. For this reason, Group III nitride substrates are expected to be applied to devices such as light-emitting diodes (LEDs), lasers, Schottky diodes, power devices, and high-frequency devices. For example, AlN-based crystal substrates are particularly being used for the purpose of eliminating bacteria and viruses, sparked by recent outbreaks such as the coronavirus, specifically AlN and / or Al x Ga1 － x The demand for substrates for light-emitting diodes in the deep ultraviolet region (UVC; 200–280 nm) using single crystals of N (0.5 < X < 1) is increasing. However, the current situation is that these AlN and / or Al x Ga1 － xSingle-crystal substrates with N (0.5 < X < 1) have many defects, low quality, and high cost, so even when various devices are manufactured, the expected characteristics cannot be obtained, which limits the widespread adoption and expansion of applications for these substrates. Meanwhile, with the launch of 5G communication and the progress of EVs, there is a demand for GaN-based crystal substrates for higher high-frequency characteristics and greater withstand voltage performance. As a result, there is a desire for epitaxial and non-defective substrates for GaN-based crystal substrates that have very few crystal defects and are also low cost. However, in the current situation, just like AlN-based substrates, GaN-based crystal substrates also have many crystal defects and are of low quality, yet their price is high, hindering their widespread adoption in the aforementioned devices, and further improvements are required.

[0003] For example, regarding AlN single-crystal substrates, as described in Non-Patent Literature 1 and Non-Patent Literature 2, since AlN does not have a melting point, it is difficult to manufacture them using general melting methods such as silicon (Si) single crystals. Instead, they are typically produced by sublimation (modified Rayleigh method) using silicon carbide (SiC) or AlN as seed crystals at 1700–2250°C under an N2 atmosphere, or, as disclosed in Patent Literature 1 and Non-Patent Literature 3, by hydride vapor phase growth (HVPE) on a sapphire substrate or an AlN substrate obtained by sublimation. Since AlN single crystals produced by the sublimation method require high temperatures for crystal growth, the current situation is limited to small-diameter substrates with a diameter of only φ2 to φ4 inches due to equipment constraints, and they are very expensive. The dislocation density of the obtained AlN single crystal is <10 5 cm －2Although the amount is relatively small, on the other hand, it has the drawback of low resistivity and low ultraviolet transmittance because the crystal becomes colored due to contamination by carbon or metal impurities originating from carbon materials such as crucibles or insulating materials. Meanwhile, AlN single crystals produced by the hydride vapor phase growth (HVPE) method on a sapphire substrate are relatively inexpensive and have little coloration, but due to the difference in lattice constants between AlN and sapphire, the dislocation density of the AlN crystal is high and it also has low resistivity. Furthermore, AlN crystals obtained by HVPE deposition on an AlN substrate by the sublimation method have a relatively low dislocation density, but they are opaque to deep ultraviolet light and have low resistivity due to contamination by colorants from the AlN of the base substrate. In addition, conventionally, expensive sublimation method AlN crystals are used as base substrates that also serve as seed crystals, which has the drawback of being very expensive.

[0004] Regarding GaN substrates, bulk GaN substrates in which GaN crystals are grown in a liquid such as liquid ammonia or Na flux have relatively few defects and are of high quality, but they are very expensive because they require high-temperature and high-pressure equipment. In addition, just like the AlN substrates of the sublimation method mentioned above, they are used as base substrates that also serve as seed crystals, which results in very high costs. On the other hand, if heteroepitaxial growth is performed on sapphire substrates using the MOCVD method or hydride vapor phase growth method (HVPE method, THVPE method) to grow crystals in the vapor phase, it is theoretically possible to increase the quality and size of the crystals, but in reality, because the lattice constants and coefficients of thermal expansion between the generated GaN crystal and the sapphire base substrate differ significantly, many crystal defects or cracks occur during manufacturing, and high-quality crystals are not obtained.

[0005] As one of the solutions to these problems, Patent Document 2 discloses a so-called QST (trade name) substrate having an AlN ceramic core and a sealing layer that encapsulates the AlN ceramic core with a multilayer film of SiO2 / PSi / SiO2 / Si3N4, a planarization layer such as SiO2 on the upper surface of the support substrate, and a seed crystal layer having a thin film of Si <111> transferred as a seed crystal on the upper surface of the planarization layer.

[0006] However, this method is prone to causing differences in thermal expansion rates between each multilayer film encapsulating the core, or between the encapsulation layer, planarization layer, and seed crystal layer. Furthermore, thermal stress based on these differences in thermal expansion rates causes cracks, chipping, or deformation between the encapsulation layer, planarization layer, or seed crystal layer, or between layers formed during subsequent epitaxial film deposition processes. As a result, it was found that contamination and various deformations caused by the diffusion of impurities in the AlN ceramic core are induced in the seed crystal, which also has an adverse effect on subsequent epitaxial growth, resulting in a low-performance epitaxial growth film with many crystal defects.

[0007] For this reason, AlN and / or Al for substrates for light-emitting diodes used in the deep ultraviolet region (UVC; 200–280 nm) of microwaves, for example, where high characteristics and particularly low crystal defects are required. x Ga 1－x It was difficult to obtain GaN crystal substrates suitable for N(0<X<1), or for high frequency and high voltage resistance associated with 5G communication or EV conversion of vehicles, with fewer crystal defects, high quality, and low cost, so a new solution was desired.

[0008] Therefore, the inventors arrived at the present invention as a result of various considerations to solve the above-mentioned problem. That is, one of the key components of the present invention is to minimize the difference in thermal expansion coefficients between each multilayer film encapsulating the core, or between the encapsulation layer, the planarization layer, and the seed crystal layer, and to optimize the film thicknesses between the encapsulation layer, the planarization layer, and the seed crystal layer in a balanced manner, specifically to optimize the composition and thickness of the encapsulation layer, and / or to add a stress adjustment layer as necessary, thereby minimizing thermal stress and making it more stress-free.

[0009] Meanwhile, although the role of the seed crystal has been understood so far, its nature has not been deeply examined. In particular, the causal relationship between the nature of the Si <111> seed crystal and the subsequent epitaxial film formation has not been sufficiently studied. Therefore, the inventors of the present invention have thoroughly eliminated factors such as deformation caused by thermal stress differences between the layers and contamination from the core by optimizing the composition of each layer and minimizing thermal stress between layers, and have investigated the effect of the nature of the Si <111> seed crystal on the epitaxial film formation.

[0010] As a result, AlN, Al x Ga1 － x In order to obtain high performance and low cost by sintering a substrate for epitaxial growth of group III nitrides such as N (0 < X ​​< 1) and GaN, it was discovered that, in addition to the above deformation or contamination, the oxidation-induced stacking fault (OSF) described in Patent Document 3 among the nature of the Si <111> seed crystal has a significant influence. That is, it was found that the less OSF there is in the Si <111> seed crystal, the fewer defects there are during epitaxial film formation, and the better the subsequent device characteristics.

[0011] Conventionally, because many crystal defects existed in epitaxial films, it was generally believed that the amount of oxidation-induced stacking faults (OSF) in Si <111> seed crystals had little effect on defects in epitaxial films. However, the inventors re-examined the defects in epitaxial films under conditions that made them more visible, and as a result, discovered that there is a significant causal relationship between the nature of Si <111> seed crystals and defects in epitaxial films, and completed the present invention by making this another important component of the present invention. Prior art literature

[0012] Japanese Patent No. 6042545, Japanese Patent No. 6626607, Japanese Patent No. 2936916

[0013] Japanese Journal of Applied Physics; Vol.46, No.17, 2007, pp.L389-L391 SEI Technical Review; No.177, pp.88-91 Fujikura Kibo; No.119, 2010 Vol.2, pp.33-38 LEDs Magazine Japan; December 2016, pp.30-31 The problem to be solved

[0014] The present invention has been made in consideration of the above circumstances, and is based on AlN, Al, which has few crystal defects, is of high quality, and is inexpensive. x Ga1 － x The purpose is to obtain a substrate for epitaxial and non-epistential growth of Group III nitrides such as N (0 < X ​​< 1) and GaN. To achieve this objective, the epitaxial growth substrate of the present invention minimizes the difference in thermal expansion coefficients and reduces stress by optimizing the composition or thickness of each film between the multilayer films encapsulating the core serving as the base substrate, or between the encapsulation layer, the planarization layer, and the Si <111> seed crystal layer, and the upper surface of the planarization layer has 10 oxide-induced stacking faults (OSF) / cm² 2A thin film of 0.1 to 1.5 μm of a Si <111> single crystal was transferred to form a seed crystal layer. In addition, the number of oxidation-induced stacking faults (OSF) of the present invention (pieces / cm²) 2 ) was measured using the evaluation method of Patent Document 3. Although it becomes difficult to measure the defect density when the thickness of the seed crystal layer decreases, it is believed that the defect density does not change due to thin film transfer.

[0015] In the present invention, it is important to minimize the difference in thermal expansion coefficients between each multilayer film, or between the encapsulation layer, planarization layer, and seed crystal layer; to achieve this, it is indispensable to optimize the composition and film thickness of the encapsulation layer, planarization layer, and seed crystal layer in good balance. In particular, optimizing the composition and thickness of the encapsulation layer, and / or adding a stress adjustment layer as necessary to reduce stress, and reducing the oxidation-inducing stacking faults (OSF) on the upper surface of the planarization layer to 10 / cm² 2 By transferring a thin film of 0.1 to 1.5 μm of Si <111> single crystal to form a seed crystal layer, it is possible to achieve low crystal defects, high performance, and low cost. means of solving the problem

[0016] To achieve the above objective, the present invention provides an epitaxial growth substrate according to an embodiment of the present invention, comprising a support substrate, a planarization layer of 0.5 to 3 μm installed on the upper surface of the support substrate, and a seed crystal layer installed on the upper surface of the planarization layer. The support substrate comprises a core of polycrystalline ceramics of Group III nitride and an encapsulation layer of 0.05 to 1.5 μm encapsulating the core. The seed crystal layer has 10 oxidation-induced stacking faults (OSF) per cm² 2 It is installed by transferring a thin film of the surface layer of a Si <111> single crystal with a thickness of 0.1 to 1.5 μm.

[0017] In the present invention, it is preferable that the polycrystalline ceramic of group III nitride forming the core be an AlN ceramic.

[0018] In the present invention, it is preferable that the encapsulation layer includes at least a layer of Si3N4.

[0019] In the present invention, the planarization layer is made of SiO2 and / or silicon oxynitride (Si x O y N z It is good if it consists of ) or AlAs.

[0020] In the present invention, it is preferable that the electrical resistivity (at room temperature) of Si <111> forming the seed crystal layer be 1 kΩ·cm or higher.

[0021] In the present invention, it is preferable to further provide a stress adjusting layer on the lower surface of the support substrate.

[0022] In the present invention, the encapsulation layer may be formed using the LPCVD method.

[0023] In the present invention, the planarization layer is formed on one side or the entire upper surface of a support substrate using SiO2 and / or silicon oxynitride (Si x O y N z ) or it is preferable that AlAs be deposited by any of the plasma CVD method, LPCVD method, or low-pressure MOCVD method.

[0024] In the present invention, the seed crystal layer has 10 OSF particles / cm² 2 It is preferable to install it by implanting hydrogen and / or He into a Si <111> single crystal having an electrical resistivity (at room temperature) of 1 kΩ·cm or higher, and then transferring a thin film of 0.1 to 1.5 μm by means of physical means at 450°C or lower.

[0025] In the present invention, the stress adjustment layer can be selected from SiO2, Si3N4, amorphous Si, polycrystalline Si, etc., alone or in combination thereof, having a coefficient of thermal expansion capable of correcting warping after providing a planarization layer. Here, when considering the correspondence with the electrostatic chuck of the process device in the device manufacturing process, it is suitable to select at least polycrystalline Si produced by a method selected from sputtering, plasma CVD, or LPCVD for the bottom layer of the support substrate. In addition, to improve the affinity between the encapsulation layer and the stress adjustment layer, SiO2 and / or silicon oxynitride (Si x O y N z It is suitable to interpose a polycrystalline Si layer between the polycrystalline Si layer and the support substrate. When using a polycrystalline Si film that serves as both a stress regulating film and a chucking film for an electrostatic chuck, the polycrystalline Si may be deposited directly, or amorphous Si may be polycrystalline after deposition by heating or laser irradiation as described above. The reason for placing the polycrystalline Si film at the bottom layer is that, when considering the interaction with the electrostatic chuck of the process device, the smaller the distance between the electrostatic chuck surface and the chuck-matching film, and the lower the resistivity of the chuck-matching film, the stronger the electrostatic adsorption force becomes.

[0026] In addition, the semiconductor substrate according to an embodiment of the present invention is characterized by having a III-V semiconductor thin film formed on the upper surface of the above epitaxial growth substrate. The III-V semiconductor thin film may be a nitride semiconductor thin film containing Ga and / or Al.

[0027] In addition, a method for manufacturing a substrate for epitaxial growth according to an embodiment of the present invention comprises the steps of: preparing a core made of a core of polycrystalline ceramics of group III nitride; forming a support substrate by depositing an encapsulation layer with a thickness of 0.05 μm or more and 1.5 μm or less to surround the core; forming a planarization layer with a thickness of 0.5 μm or more and 3.0 μm or less on the upper surface of the support substrate; and forming an oxidation-induced stacking fault (OSF) of 10 / cm² on the upper surface of the planarization layer. 2 The method comprises a step of installing a seed crystal layer by transferring a thin film of the surface layer of a Si <111> single crystal of 0.1 to 1.5 μm.

[0028] In the present invention, the encapsulation layer may be formed using the LPCVD method.

[0029] In the present invention, the planarization layer is formed on one side or the entire upper surface of a support substrate using SiO2 and / or silicon oxynitride (Si x O y N z ) or it is preferable that AlAs be deposited by any of the plasma CVD method, LPCVD method, or low-pressure MOCVD method.

[0030] In the present invention, OSF is 10 pieces / cm 2 It is preferable to install a seed crystal layer by implanting hydrogen and / or He into a Si <111> single crystal having an electrical resistivity (at room temperature) of 1 kΩ·cm or higher, and then transferring a thin film of 0.1 to 1.5 μm by means of physical means at 450°C or lower.

[0031] In the present invention, it is preferable to further provide a step of installing a stress adjustment layer on the bottom surface of a support substrate. This stress adjustment layer has a thermal expansion coefficient that enables further correction of warping after providing a planarization layer, and is preferably made of polycrystalline Si produced by a method selected from at least the sputtering method and the LPCVD method.

[0032] In addition, a method for manufacturing a semiconductor substrate according to an embodiment of the present invention comprises a step of manufacturing a substrate for epitaxial growth by the method for manufacturing a substrate for epitaxial growth above, and a step of forming a III-V semiconductor thin film on the upper surface of the substrate for epitaxial growth. Effects of the invention

[0033] According to the present invention, AlN and / or Al, etc., for a substrate for a light-emitting diode used in the deep ultraviolet region (UVC; 200~280 nm), x Ga1 － x N(0<X<1), or a GaN crystal substrate suitable for high frequency and high voltage resistance associated with 5G communication or EV conversion of vehicles, can be sintered to provide a substrate for epitaxial and non-epitaxial growth of group III nitrides, and can be provided at a high quality and low cost. Brief explanation of the drawing

[0034] Figure 1 is a diagram showing the cross-sectional structure of the terminal plate (1). Figure 2 is a diagram showing the sequence of manufacturing the terminal plate (1). Specific details for implementing the invention

[0035] Embodiments of the present invention will be described in detail below, but the present invention is not limited thereto.

[0036] Figure 1 shows the cross-sectional structure of a terminal substrate (hereinafter referred to simply as "terminal substrate") (1) for epitaxial growth of a group III nitride according to the present embodiment. The terminal substrate (1) shown in Figure 1 has a structure in which a flattening layer (4) and a Si <111> terminal crystal layer (2) are laminated on a support substrate (3). Additionally, if necessary, a stress adjustment layer (5) is installed on a surface (bottom) opposite to the surface where the flattening layer (4) of the support substrate (3) is laminated.

[0037] The support substrate (3) is provided with a core (31) that serves as the core material of the support substrate (3) and a sealing layer (32) that covers the core (31).

[0038] The core (31) is formed by polycrystalline ceramics of group III nitrides. Specifically, AlN, Si3N4, GaN, or mixtures thereof can be used, but polycrystalline AlN ceramics are suitable because they have lattice constants and thermal expansion coefficients close to those of the target group III nitride crystals, high thermal conductivity, and are inexpensive. In terms of device processing, it is preferable to select a mirror-finish wafer with a thickness of 200 to 1000 μm that is used in semiconductor lines. There are various methods for manufacturing AlN ceramics, but the so-called sheet forming / atmospheric pressure sintering method is common due to its productivity. In the sheet forming / atmospheric pressure sintering method, AlN powder, a sintering aid, an organic binder, a solvent, etc. are mixed to form a wafer-shaped green sheet, which is then degreased, sintered under an N2 atmosphere, and polished to produce a product. As a sintering aid, Y2O3, Al2O3, CaO, etc. are selected, but Y2O3 is typically suitable as it exhibits the highest thermal conductivity in the substrate after sintering.

[0039] If AlN ceramic is used as a core (31) as is, metal impurities in the raw material AlN or Y2O3 powder, carbon, oxygen, and other impurities from the insulating material, furnace material, container, etc. during sintering become contaminants, causing adverse effects such as crystal defects or discoloration on the target single crystal.

[0040] For this reason, a sealing layer (32) is installed to enclose and enclose the core (31) of the polycrystalline ceramic. Specifically, when enclosing the core (31) with the sealing layer (32), consideration must be given to the composition and film thickness of each layer constituting the sealing layer (32) so that thermal stress is as small as possible and thermal conductivity is as large as possible. In the present invention, in terms of manufacturing cost, it is desirable to optimize the total film thickness of the sealing layer (32) within the range of 0.05 to 1.5 μm.

[0041] The composition of the sealing layer (32) can be appropriately selected considering the thermal expansion rate and thermal conductivity, but in order to further increase the ability to prevent the diffusion of impurities, it is preferable to seal the entire layer by covering it with a film made of at least silicon nitride (Si3N4).

[0042] In this sealing layer (32), if necessary, for example, if an electrostatic chuck is to be used, p-Si may be installed as a layer for the electrostatic chuck. This p-Si layer may be formed between the AlN ceramics and the Si3N4 layer, or, depending on the case, may be installed together with the stress adjustment layer (5) described later, or on the lower layer. In that case, if the adhesion between p-Si, the AlN core, and Si3N4 is insufficient, SiO2 or silicon oxynitride (Si2), which have high adhesion performance, may be used in consideration of the affinity between the layers and the rate of thermal expansion. x O y N z It is good to interpose a membrane such as ).

[0043] In the case of a substrate for epitaxial growth of group III nitrides such as GaN for high frequency, particularly ultra-high frequency such as gigawave or milliwave, it is preferable that the electrical resistivity (at room temperature) of the above Si <111> seed crystal layer (2) be 1 kΩ·cm or higher in order to avoid high frequency loss in a device fabricated using an epitaxial layer grown using said substrate. This is because in the case of a Si <111> seed crystal layer (2) with an electrical resistivity (at room temperature) of 1 kΩ·cm or less, high frequency loss due to gigawave or milliwave increases, causing the device to heat up, consume a large amount of power, and fail to produce characteristics.

[0044] When installing a p-Si film for an electrostatic chuck, it is preferable to use a p-Si with a higher resistance within the range where the required adsorption force is obtained. The location should be as far as possible from the seed crystal layer (2) where the epitaxial film is stacked, or the lower layer of the core (31) or the lower layer of the stress adjustment layer (5), or it may be formed as a multilayer film simultaneously with the stress adjustment layer (5). High-resistance p-Si has low high-frequency loss, and when placed below the support substrate (3), it is close to the electrostatic chuck, so sufficient electrostatic force is generated even at high resistance. For this reason, sufficient substrate adsorption is possible without doping. To reduce additional high-frequency loss, it is more preferable to remove the p-Si layer by back grinding the substrate at the end of device fabrication. When installing the stress adjustment layer (5), it is preferable to maintain the resistance of the p-Si as high as possible, but the minimum amount of doping, such as boron (B) or phosphorus (P), required to generate the required electrostatic force is not limited.

[0045] In the encapsulation layer (32), if the thickness of each layer becomes too thick, the stress between the layers due to the difference in thermal expansion rates increases, causing delamination between the layers. Therefore, even if a film of various compositions is selected and combined, it is not desirable for the thickness of the encapsulation layer (32) to be 1.5 μm or more. On the other hand, from the perspective of the function of encapsulating impurities, a thickness of 0.05 μm or less is insufficient for preventing the diffusion of impurities. From the above, it is desirable for the thickness of the encapsulation layer (32) to be in the range of 0.05 to 1.5 μm. In addition, the film formation method of the encapsulation layer can be selected from conventional film formation methods such as MOCVD, atmospheric pressure CVD, LPCVD, and sputtering, but it is particularly desirable to use the LPCVD method due to the film quality, film coverage, and ability to prevent the diffusion of impurities.

[0046] A flattening layer (4) of 0.5 to 3 μm is laminated on the encapsulation layer (32) on at least the upper surface of the support substrate (3). This flattening layer (4) is made of SiO2, Al2O3, Si3N4, SiC, or silicon oxynitride (Si x O y N z It is selected from Si, GaAs, AlAs, etc., which are commonly used as film materials for conventional ceramics such as ), or as sacrificial layers for etching, but SiO2 and / or silicon oxynitride (Si₂) which facilitates grinding or polishing during planarization and also facilitates separation when obtaining a bare substrate, etc. x O y N z It is desirable to select from ) or AlAs.

[0047] Additionally, the flattening layer (4) is usually laminated on only one side of the encapsulation layer (32) for cost reasons, but in cases of large warping, it may be formed to cover the entire encapsulation layer (32). The thickness of the flattening layer (4) must be such that it can fill voids or irregularities in the core (31), encapsulation layer (32), etc., and also obtain sufficient smoothness to transfer seed crystals. However, a flattening layer (4) that is too thick is undesirable as it causes warping or cracking of the substrate (1). Therefore, it is suitable to install it with a thickness of at least 0.5 to 3 μm on the upper surface. This is because if it is less than 0.5 μm, it cannot fill most of the voids or irregularities in the core (31) or encapsulation layer (32) of the AlN ceramics, and if it is more than 3 μm, warping caused by the flattening layer (4) is likely to occur.

[0048] The method for forming the flattening layer (4) is suitable in terms of the required film quality and film formation efficiency, such as plasma CVD, LPCVD, or low-pressure MOCVD. Stacked SiO2 and / or silicon oxynitride (Si x O y N z ) or AlAs, depending on the condition of the film, heat treatment for the purpose of sintering or CMP polishing for smoothness is performed to prepare for the thin film transfer of the seed crystal layer (2) described later.

[0049] The seed crystal is AlN, Al targeted by the present invention. x Ga1 － x A substrate with a crystal structure similar to Group III nitrides such as N (0 < X ​​< 1) and GaN is selected. Accordingly, Si <111>, SiC, SCAM, AlN, AlGaN, and sapphire are considered, but Si <111> is suitable due to its ease of scaling to large diameters, availability of commercial products, and low cost. Among these, among Si <111> crystals, the oxidation-induced stacking fault (OSF) is 10 / cm² 2 The Si <111> single crystal below is particularly suitable as described above.

[0050] This is 10 OSF / cm³ of Si <111> seed crystals that serve as seeds for the epitaxial film deposition in the next process. 2 If it is below this level, the epitaxially deposited crystals follow the seed crystal, resulting in fewer defects; furthermore, devices using them exhibit high characteristics and good yield, leading to low costs, whereas OSF is 10 crystals / cm 2 This is because if it exceeds, defects in the epitaxially formed crystal also increase rapidly, the device characteristics deteriorate, and the yield inevitably worsens, resulting in high costs.

[0051] In addition, when using the epitaxial and non-epitrous substrate obtained by epitaxially depositing a film on the substrate (1) for a high-frequency device, particularly for high-frequency devices after 5G, it is preferable to select a Si <111> seed crystal with an electrical resistivity (at room temperature) of 1 kΩ·cm or more. This is because if the electrical resistivity (at room temperature) of the Si <111> seed crystal is less than 1 kΩ·cm, high-frequency loss occurs due to the resistance, power consumption increases, or heat is generated, causing the characteristics of the device to deteriorate.

[0052] After performing ion implantation limited to hydrogen and / or helium (He) ion species, which have little effect on the electrical resistance of the single crystal substrate, the ion implantation surface of the Si <111> seed crystal is bonded to the upper surface of the planarization layer (4), and a thin film of 0.1 to 1.5 μm is peeled and transferred to the planarization layer (4) using physical means such as fingernails at 450°C or lower to form the seed crystal layer (2). Unlike heavy elements such as boron (B), light elements such as hydrogen or He are suitable for ion implantation into the seed crystal in that they cause little damage to the seed crystal due to ion implantation and do not lower the electrical resistance. In addition, by performing peeling and transfer at a low temperature of 450°C or lower, thermal damage to the Si <111> seed crystal, which is unavoidable in thermal peeling and transfer at high temperatures of 700°C or higher in the conventional smart cut method, can be prevented.

[0053] The transfer thickness of the seed crystal layer (2) should be 0.1 to 1.5 μm. In ion implantation, the damaged layer alone has a thickness of approximately 0.1 μm, so if it is less than 0.1 μm, a good seed crystal is not obtained. Also, if the transfer thickness is 1.5 μm or more, the ion implanter requires high-output ion energy, so the ion implanter becomes huge, requiring massive investment and is not economical. In addition, if the thickness of the seed crystal layer (2) is thin (for example, 1.0 μm or less), there is a possibility that direct measurement of the defect density will be difficult; however, since it is thought that the defect density does not change due to thin film transfer, the defect density of OSF in the seed crystal layer (2) is 10 defects / cm², which is the same as that of the Si <111> seed crystal. 2 It is estimated to be as follows.

[0054] To describe a more specific implementation method, hydrogen and / or He is ion-implanted into the seed crystal at a depth of 0.2 to 3.5 μm, and then the upper surface of the planarization layer (4) and the ion-implanted surface of the seed crystal are bonded. After that, the seed crystal may be peeled off at a temperature of 450°C or lower using a physical method such as gas pressure or fingernails. This is because at high temperatures exceeding 450°C, stress or thermal damage caused by impurity diffusion or thermal stress is likely to occur in the seed crystal of the transferred thin film.

[0055] After that, the upper surface of the transferred thin film is lightly etched with CMP polishing and / or a chemical solution to remove the inevitable ion implantation damage layer, and a terminal crystal thin film (terminal crystal layer (2)) with a thickness of 0.1 to 1.5 μm is obtained. In addition, if higher uniformity is required for ion implantation, it is preferable to deposit SiO2 or the like on the ion implantation surface of the substrate as needed before performing ion implantation.

[0056] In the present invention, a stress adjustment layer (5) may also be added to the bottom surface of the support substrate (3) as needed. For the stress adjustment layer (5), a film material and thickness having a thermal expansion coefficient capable of correcting the warping of the substrate (1) caused by forming the planarization layer (4) are selected. For example, the stress adjustment layer (5) can be selected from SiO2, Si3N4, amorphous Si, polycrystalline Si, etc., either alone or in combination thereof. Here, when considering the correspondence with the electrostatic chuck of the process device in the device manufacturing process, it is suitable to select at least polycrystalline Si produced by a method selected from the sputtering method, plasma CVD, or LPCVD method for the bottom layer of the support substrate. Typically, it is suitable to deposit polycrystalline Si (p-Si) as the stress adjustment layer (5) to also correspond to the electrostatic chuck. Furthermore, from the perspective of correcting warping and affinity with the encapsulation layer (32), SiO2 and / or silicon oxynitride (Si2) between the polycrystalline Si and the encapsulation layer x O y N z...etc. may be included. When using a polycrystalline Si film that also serves as a chucking film for the electrostatic chuck as the stress adjustment layer (5), the polycrystalline Si may be deposited directly, or amorphous Si may be polycrystalline after deposition by heating or laser irradiation. By installing the polycrystalline Si film at the bottom layer, the distance between the electrostatic chuck surface and the chuck-corresponding film can be shortened, and the resistivity of the film can be lowered to increase the electrostatic adsorption force.

[0057] Next, with reference to FIG. 2, the sequence of the method for manufacturing a Group III nitride-based epitaxial growth substrate (1) according to the present embodiment will be explained. In addition, if the method suitable for forming each layer has already been explained along with the configuration of each part of the substrate (1), the redundant explanation here will be omitted.

[0058] First, a core (31) made of nitride ceramics is prepared (S01 in FIG. 2). Next, a sealing layer (32) with a thickness of 0.05 μm to 1.5 μm is formed to surround the core (31) to form a support substrate (3) (S02 in FIG. 2). At this time, the sealing layer (32) may be formed using the LPCVD method. Next, a flattening layer (4) with a thickness of 0.5 μm or more and 3.0 μm or less is formed on the upper surface of the support substrate (3) (S03 in FIG. 2). Additionally, if necessary, a stress adjustment layer (5) is formed on the lower surface of the support substrate (3) (S04 in FIG. 2). Furthermore, the flattening layer (4) and the stress adjustment layer (5) may be formed simultaneously.

[0059] In addition, separately from S01 to S04, a Si <111> single crystal substrate (20) which is a seed crystal for peeling and transferring the seed crystal layer (2) is prepared (S11 in FIG. 2). Then, ion implantation is performed from one side (ion implantation surface) of the single crystal substrate (20) to form a peeling location (brittle layer) (21) within the single crystal substrate (20) (S12 in FIG. 2).

[0060] Next, the ion implantation surface of the single crystal substrate (20) is bonded to the planarization layer (4) formed on the support substrate (3) to form a bonded substrate (S21 in FIG. 2). Then, the single crystal substrate (20) is separated at the peeling position (21) of the single crystal substrate (20) in the bonded substrate (S22 in FIG. 2). By doing so, a single crystal film of Si <111> is transferred as a thin film on the carbonization layer (4) on the support substrate (3) as a seed crystal layer (2). Meanwhile, the remaining part of the separated Si <111> single crystal substrate (20) can be repeatedly used to transfer a thin film of the seed crystal layer when fabricating another group III nitride-based composite substrate by polishing its surface again to form an ion implantation surface.

[0061] The above describes the composition and manufacturing method of the epitaxial growth substrate (1). The present invention has two essential components that exhibit a synergistic effect: 1) minimization of thermal stress by optimizing the composition and film thickness of the encapsulation layer between each layer, particularly the encapsulation layer, and 2) growth of a superior epitaxial film crystal by a superior seed crystal. Additionally, 3) further reduction of stress in the stress adjustment layer as needed, and 4) ion implantation limited to light elements such as hydrogen and / or He, and thin film transfer by physical means such as fingernails at 450°C or lower are effective. By the present invention, an epitaxial substrate or a flawless substrate with very little warping, voids, crystal defects, etc., and very little high-frequency loss of the device can be economically obtained.

[0062] The substrate of the present invention significantly improves the characteristics of devices, such as light-emitting diodes used in the deep ultraviolet region (UVC; 200 to 280 nm), high-frequency devices for 5G communication or EV vehicles, or high-voltage devices, and also significantly improves the manufacturing yield of the devices.

[0063] Examples

[0064] The present invention will be explained more specifically below with reference to examples and comparative examples, but the present invention is not limited to these examples.

[0065] [Example 1]

[0066] (Preparation of support substrate)

[0067] A support substrate (3) with a structure in which a core (31) of polycrystalline ceramics is covered with an encapsulation layer (32) was prepared. A commercially available AlN substrate was used for the core (31) of the polycrystalline ceramics. This AlN substrate was prepared by mixing 100 parts by weight of AlN powder and 35 parts by weight of Y2O3 as a sintering aid with an organic binder, solvent, etc. to form a green sheet, degreasing it, and sintering it at 1900°C under an N2 atmosphere. A double-sided polished φ8 inch × t725 μm substrate was used. The encapsulation layer (32) was formed by covering the entire core (31) of the AlN ceramics with a silicon oxynitride layer 0.1 μm thick by the LPCVD method, and then encapsulating the entire core with a Si3N4 layer 0.4 μm thick using another LPCVD device. The total thickness of the encapsulation layer (32) was set to 0.5 μm. On this Si3N4 layer, for the purpose of planarization, a 6㎛ thick SiO2 layer was deposited only on one side of the upper layer using a plasma CVD method (ICP-CVD apparatus). After that, the layer was sintered at 1000°C, and then the SiO2 layer was planarized to a thickness of 2㎛ (Ra=0.2nm) by CMP polishing to prepare for thin film transfer of the seed crystal.

[0068] (Preparation of seed crystals)

[0069] In the evaluation of Patent Document 3, the oxidation-induced stacking fault (OSF) was 8 / cm² 2 A φ8-inch, 725 μm thick Si <111> single-crystal substrate with an electrical resistivity (at room temperature) of 1.5 kΩ·cm was prepared as a seed crystal substrate. On this Si substrate, hydrogen was introduced at 100 keV to a depth of 0.6 μm with a dose of 8 × 10⁻⁶ 17 cm －2 Ion implantation was performed under the conditions of.

[0070] First, a thin film of the surface layer of the ion-implanted Si <111> single crystal, with a thickness of 0.6 μm, was transferred onto the flattening layer (4) (thickness 2 μm) of the prepared support substrate (3). The damaged portion of the Si <111> single crystal during ion implantation and transfer was lightly polished with CMP to make the thickness of the Si <111> single crystal layer 0.4 μm and form the seed crystal layer (2). The obtained substrate (1) was free of cracks, film peeling, or warping as a result of balancing the film thickness between each layer of the encapsulation layer (32) and between the encapsulation layer (32), the flattening layer (4), and the seed crystal layer (2) against each thermal stress.

[0071] In addition, the remaining Si <111> single-crystal substrate after thin film transfer could be repeatedly used as a number of seed crystals by repeating ion implantation several times, making it very economical.

[0072] In this embodiment, a substrate (1) was obtained having a support substrate (3) having a structure of an AlN ceramic core (31) and an encapsulation layer (32), a planarization layer (4) with a thickness of 2 μm, and a seed crystal layer (2) of a Si <111> single crystal with a thickness of 0.4 μm. The following simple evaluation was performed on the characteristics of this substrate (1) as a substrate for epitaxial growth of GaN.

[0073] The above substrate (1) was placed in the reactor of the MOCVD apparatus and epitaxial growth was performed. At this time, the epitaxial layer was formed by sequentially depositing AlN and AlGaN from the side of the substrate (1) toward the growth direction, and then epitaxially growing GaN. The structure of the epitaxial layer is not limited to this; for example, AlGaN may not be deposited, or AlN may be deposited after AlGaN deposition. In this evaluation, an AlN layer of 100 nm and an AlGaN layer of 150 nm were formed. Also, the total film thickness of the epitaxial layer was set to 5 μm. During epitaxial growth, TMAl (trimethylaluminum) may be used as the Al source, TMGa (trimethylgallium) as the Ga source, and NH3 as the N source, but are not limited to these. In addition, the carrier gas can be N2 and H2 or any of them, and it is preferable to set the process temperature to about 900 to 1200°C.

[0074] Afterwards, to evaluate the dislocation density, etch pits were generated by molten alkali (KOH) etching, and the etch pit density (hereinafter EPD) was measured. In addition, X-ray rocking curve (XRC) measurements were performed to evaluate crystallinity.

[0075] As a result, EPD is 0.2×10 4 cm －2 It exhibited a very low dislocation density. In addition, the full width at half maximum (FWHM) in the XRC measurement of the GaN (0002) plane of the substrate (hereinafter referred to simply as "FWHM of 0002 XRC") was 135 arcsec, and a high-quality GaN single crystal was obtained. From these results, it can be seen that the substrate (1) according to the present embodiment has excellent properties as a substrate for epitaxial growth. When an epitaxial substrate with an epitaxial layer installed on this substrate (1) was used for a 30 GHz / 20 Gbps high-frequency device, the surface temperature of the device was 43°C, and no temperature rise due to high-frequency loss was observed to the extent that it would be a particular problem.

[0076] [Comparative Example 1]

[0077] 16 Oxidation-Inducing Stacking Faults (OSF) / cm² 2 A φ8-inch single-crystal Si <111> substrate with an electrical resistivity (at room temperature) of 0.2 kΩ·cm was used as the seed crystal substrate, and a seed crystal layer (2) with a thickness of 1.3 μm was transferred as a thin film; otherwise, a seed substrate (1) was fabricated under the same conditions as in Example 1. A 5 μm thick GaN film was deposited on this seed substrate (1) by the MOCVD method, just as in Example 1. As a result, the EPD was 15×10 4 cm －2 It exhibited a very large dislocation density. Also, the FWHM of the 0002 XRC was 930 arcsec, and it became a GaN single crystal with poor crystallinity compared to Example 1. In addition, when this epitaxial substrate was used for a 30 GHz / 20 Gbps high-frequency device, the surface temperature of the device became high at 125°C due to high-frequency loss, making long-term use impossible.

[0078] [Example 2]

[0079] (Preparation of support substrate)

[0080] A support substrate (3) having a structure in which a polycrystalline ceramic core (31) is covered with an encapsulation layer (32) was prepared. For the polycrystalline ceramic core (31), a commercially available AlN substrate identical to that of Example 1 was used. The encapsulation layer (32) was first formed by wrapping the entire AlN ceramic core (31) with a 0.3 μm thick SiO2 layer using the LPCVD method, and then encapsulating the entire structure with a 0.8 μm thick Si3N4 layer using another LPCVD device. The total thickness of the encapsulation layer (32) was set to 1.1 μm. On this Si3N4 layer, silicon oxynitride was deposited with a thickness of 5 μm only on the upper layer of the encapsulation layer (32) using the LPCVD method for the purpose of planarization. Subsequently, the silicon oxynitride layer was reduced to a thickness of 2.5 μm by CMP polishing. At this stage, the entire substrate was significantly warped to about 30 μm. To correct this warping, silicon oxide was formed on the bottom surface to a thickness of 5 μm as a stress adjustment layer (5), and non-doped polycrystalline Si, which also serves as an electrostatic chuck adsorption layer, was formed to a thickness of 0.2 μm using plasma CVD. As a result, the warping was eliminated, and sufficient adsorption and desorption could be performed on the electrostatic chuck.

[0081] (Preparation of seed crystals)

[0082] Evaluation of Patent Document 3 shows that the oxidation-induced stacking fault (OSF) is 0 / cm² 2 A φ8-inch, 725 μm thick single-crystal Si <111> substrate with an electrical resistivity (at room temperature) of 2.3 kΩ·cm was prepared as a seed crystal substrate. On this Si substrate, hydrogen was applied at 130 keV to a depth of 1.4 μm with a dose of 9.5 × 10⁻⁶ 17 cm －2 Ion implantation was performed under the conditions of.

[0083] First, a thin film of the surface layer (1.4 μm) of the ion-implanted Si <111> single crystal was transferred onto the flattening layer (32) (thickness 2.5 μm) of the prepared support substrate (3). The damaged portion of the Si <111> single crystal during ion implantation and transfer was lightly polished with CMP to make the thickness of the Si <111> single crystal layer 1 μm and form the seed crystal layer (2). The obtained seed substrate (1) was free of cracks, film peeling, or warping as a result of balancing the film thickness between each layer of the encapsulation layer (32) and between the encapsulation layer (32), the flattening layer (4), and the seed crystal layer (2).

[0084] In addition, the remaining Si <111> single crystal substrate after thin film transfer could be repeatedly used as a number of seed crystals by repeating ion implantation several times, just like in Example 1, making it very economical.

[0085] In this embodiment, a substrate (1) was obtained having a support substrate (3) having a structure of an AlN ceramic core (31) and an encapsulation layer (32), a planarization layer (4) with a thickness of 2.5 μm, and a seed crystal layer (2) of a Si <111> single crystal with a thickness of 1 μm. The following simple evaluation was performed on the characteristics of this substrate (1) as a substrate for epitaxial growth of AlN.

[0086] On this substrate (1), a 600 μm thick AlN single crystal was deposited using the THVPE method with AlCl3 and NH3 as raw materials. The deposited AlN single crystal was cut with a wire saw and polished to produce a smooth φ8-inch substrate. In addition, this cut AlN single crystal substrate had no coloration, and the transmittance of light with a wavelength of 220 nm was approximately 80% when converted to a film thickness of 100 μm. Next, this substrate was used as a substrate for the epitaxial growth of AlN, and the following simple evaluation was performed.

[0087] A 2 μm thick AlN film was deposited on the above AlN substrate by the MOCVD method, and, as in the evaluation in Example 1, etch pits were generated by the molten alkali (KOH) etching method to evaluate the dislocation density and EPD measurements were performed. In addition, X-ray rocking curve (XRC) measurements were performed to evaluate crystallinity.

[0088] As a result, EPD is 0.5×10 4 cm －2 It exhibited a very low dislocation density. In addition, the FWHM of the 0002 XRC was 110 arcsec, and a high-quality AlN single crystal was obtained. This AlN single crystal was an excellent substrate for LED substrates for the deep ultraviolet region, having very few defects, high device characteristics, and a low cost.

[0089] [Example 3]

[0090] A substrate (1) for epitaxial growth was obtained under the same conditions as in Example 1, except that the flattening layer (4) of Example 1 was a flattening layer (4) of a two-layer structure of SiO2 / AlAs with a total thickness of 2.5 μm, in which the lower layer is composed of AlAs with a thickness of 2 μm and the upper layer is composed of SiO2 with a thickness of 0.5 μm.

[0091] In addition, the remaining Si <111> single-crystal substrate after thin film transfer could be repeatedly used as a number of seed crystals by repeating ion implantation several times, making it very economical.

[0092] In this embodiment, a substrate (1) was obtained having a support substrate (3) having a structure of an AlN ceramic core (31) and an encapsulation layer (32), a composite planarization layer (4) of SiO2 / AlAs with a total thickness of 2.5 μm, and a seed crystal layer (2) of a Si <111> single crystal with a thickness of 0.4 μm on top thereof. This substrate (1) was used as a substrate for epitaxial growth of GaN to epitaxially grow a thick film of GaN.

[0093] After depositing a 30㎛ thick GaN film on the above substrate (1) by MOCVD, the planarization layer (4) of SiO2 / AlAs was dissolved with an aqueous HF solution to obtain a GaN substrate with a thickness of about 30㎛.

[0094] To evaluate the dislocation density of this GaN bare substrate, etch pits were generated by molten alkali (KOH) etching as in the evaluation in Example 1, and EPD measurements were performed. In addition, X-ray rocking curve (XRC) measurements were performed as an evaluation of crystallinity.

[0095] As a result, EPD is 0.05×10 4 cm －2 It exhibited a very low dislocation density. In addition, the FWHM of the 0002 XRC was 101 arcsec, and a high-quality GaN single crystal was obtained. From these figures, it can be seen that the substrate (1) of this embodiment is excellent as an epitaxial growth substrate for obtaining a non-glossy substrate. When a non-glossy GaN substrate obtained by epitaxial growth using this substrate (1) was used for a 30GHz / 20Gbps high-frequency device, the surface temperature of the device was 38℃, and it was an excellent substrate with low heat generation due to high-frequency loss. Explanation of the symbols

[0096] 1 terminal board 2 seed crystal layers 3 Support substrate 4 leveling layer 5 Stress adjustment layer 20 Single crystal substrate of a seed crystal 21 Excision location

Claims

Claim 1 An epitaxial growth substrate comprising a support substrate, a planarization layer of 0.5 to 3 μm installed on the upper surface of the support substrate, and a seed crystal layer installed on the upper surface of the planarization layer, wherein the support substrate comprises a core of polycrystalline ceramics of group II nitride and an encapsulation layer of 0.05 to 1.5 μm encapsulating the core, and the seed crystal layer has 10 oxidation-inducing stacking defects / cm² 2 A substrate for epitaxial growth characterized by being formed by thin film transfer of a surface layer of 0.1 to 1.5 μm of Si <111> single crystal, wherein the stress adjustment layer is provided on the lowest surface of the support substrate, and the stress adjustment layer has a thermal expansion coefficient that enables further correction of warping after the planarization layer is provided, and is made of polycrystalline Si produced by at least a method selected from the sputtering method, plasma CVD method, and LPCVD method. Claim 2 An epitaxial growth substrate comprising a support substrate, a planarization layer of 0.5 to 3 μm installed on the upper surface of the support substrate, and a seed crystal layer installed on the upper surface of the planarization layer, wherein the support substrate comprises a core of polycrystalline ceramics of group III nitride and an encapsulation layer of 0.05 to 1.5 μm encapsulating the core, and the seed crystal layer has 10 oxidation-inducing stacking defects / cm² 2 A substrate for epitaxial growth characterized by having a thickness of 0.1 to 1.5 μm and having a stress adjusting layer on the bottom surface of the support substrate, wherein the stress adjusting layer has a thermal expansion coefficient that enables further correction of warping after having the planarization layer, and is made of polycrystalline Si produced by at least a method selected from the sputtering method, plasma CVD method, and LPCVD method. Claim 3 A substrate for epitaxial growth according to claim 1 or 2, characterized in that the polycrystalline ceramic of a group III nitride forming the core is an AlN ceramic. Claim 4 A substrate for epitaxial growth according to claim 1 or 2, characterized in that the encapsulation layer comprises at least a layer of Si3N4. Claim 5 In claim 1 or 2, the planarization layer is SiO2 and / or silicon oxynitride (Si x O y N z A substrate for epitaxial growth characterized by being composed of ) or AlAs. Claim 6 A substrate for epitaxial growth according to claim 1 or 2, characterized in that the electrical resistivity (at room temperature) of Si <111> forming the seed crystal layer is 1 kΩ·cm or higher. Claim 7 delete Claim 8 delete Claim 9 In claim 1 or 2, the stress adjusting layer is located directly below the lower surface of the support substrate and is composed of SiO2 and / or silicon oxynitride (Si x O y N z A substrate for epitaxial growth characterized by being installed as polycrystalline Si via ) Claim 10 An epitaxial growth substrate according to claim 1 or 2, characterized in that the encapsulation layer is formed by the LPCVD method. Claim 11 In claim 1 or 2, the planarization layer is formed on one side or the entire upper surface of the support substrate, with SiO2 and / or silicon oxynitride (Si x O y N z A substrate for epitaxial growth characterized by forming a film on ) or AlAs by any one of the plasma CVD method, LPCVD method, or low-pressure MOCVD method. Claim 12 In claim 1 or 2, the seed crystal layer has 10 oxidation-inducing stacking defects / cm² 2 An epitaxial growth substrate characterized by being installed by ion-implanting hydrogen and / or He into a Si <111> single crystal having an electrical resistivity (at room temperature) of 1 kΩ·cm or less, and then transferring a thin film of 0.1 to 1.5 μm by physical means at 450°C or less. Claim 13 A semiconductor substrate characterized by having a III-V semiconductor thin film formed on the upper surface of an epitaxial growth substrate described in claim 12. Claim 14 A semiconductor substrate according to claim 13, characterized in that the above-mentioned III-V semiconductor thin film is a nitride semiconductor thin film containing Ga and / or Al. Claim 15 A step of preparing a core comprising a core made of polycrystalline ceramics of group III nitride; a step of forming a support substrate by depositing an encapsulation layer with a thickness of 0.05 μm or more and 1.5 μm or less to surround the core; a step of depositing a planarization layer with a thickness of 0.5 μm or more and 3.0 μm or less on the upper surface of the support substrate; and a step having 10 oxidation-inducing stacking defects / cm² on the upper surface of the planarization layer 2 A method for manufacturing a seed substrate for epitaxial growth, comprising the step of installing a seed crystal layer by thin-film transferring a surface layer of 0.1 to 1.5 μm of a Si <111> single crystal or less, and the step of further installing a stress adjustment layer on the bottom surface of the support substrate, wherein the stress adjustment layer has a thermal expansion coefficient that enables further correction of warping after the planarization layer, and is made of polycrystalline Si produced by at least a method selected from the sputtering method, plasma CVD method, and LPCVD method. Claim 16 A method for manufacturing a substrate for epitaxial growth according to claim 15, characterized in that the above-mentioned encapsulation layer is formed by the LPCVD method. Claim 17 In claim 15, the planarization layer is formed on one side or the entire upper surface of the support substrate as SiO2 and / or silicon oxynitride (Si x O y N z A method for manufacturing a substrate for epitaxial growth, characterized in that ) or AlAs is formed by any one of the plasma CVD method, LPCVD method, or low-pressure MOCVD method. Claim 18 In any one of claims 15 to 17, in the step of installing the seed crystal layer, the oxidation-causing stacking defect is 10 / cm² 2 A method for manufacturing a seed substrate for epitaxial growth, characterized by implanting hydrogen and / or He into a Si <111> single crystal having an electrical resistivity (at room temperature) of 1 kΩ·cm or less, and then transferring a thin film of 0.1 to 1.5 μm by means of physical means at 450°C or less to install the seed crystal layer. Claim 19 delete Claim 20 delete Claim 21 A method for manufacturing a semiconductor substrate comprising the step of manufacturing an epitaxial growth substrate by the method for manufacturing an epitaxial growth substrate described in any one of claims 15 to 17, and the step of forming a III-V semiconductor thin film on the upper surface of the epitaxial growth substrate.

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