Method and system for output power limiting via mode transfer in grid-forming inverter for overcurrent protection

Abstract

An overcurrent protection method for an inverter operating in a grid forming control mode may include the steps of measuring the output current of the inverter, comparing whether the magnitude of the measured output current exceeds a preset protection threshold (I_limit), switching the operating mode of the inverter from a voltage control-based grid forming mode to a current control-based grid following mode when the output current exceeds the protection threshold, and controlling and limiting the current reference value within a preset limit in the switched grid following mode to supply a fault current to the power grid.

Description

Technology Field

[0001] The present invention relates to the field of power and renewable energy grid connection control technology.

[0002] More specifically, the present invention relates to an output limiting method and system that switches the operating mode in real time from a voltage-controlled type to a current-controlled type grid-following (GFL) mode in order to prevent hardware damage caused by overcurrent in the event of a grid fault and to continuously supply a fault current that satisfies the grid code in an inverter operating in a grid-forming (GFM) control mode having voltage source characteristics. Background Technology

[0004] With the recent increase in the proportion of renewable energy generation, Inverter-Based Resources (IBRs) are replacing traditional rotating machine-based generators and becoming the mainstream of power systems. In particular, the introduction of Grid Forming (GFM) control technology, in which inverters autonomously generate voltage and frequency, is accelerating to maintain frequency and voltage stability in environments with insufficient grid inertia.

[0005] However, GFM inverters have a structural feature designed to have very low output impedance to achieve ideal voltage source characteristics. Due to this, there is a limitation in that when an accident such as a short circuit occurs on the grid side and the voltage drops rapidly, a massive inrush current, amounting to tens of times the rated current, flows in due to the difference between the inverter's internal voltage and the grid voltage.

[0006] Conventional protection methods have used to immediately trip the inverter's PWM switching when an overcurrent occurs, or to forcibly limit the current command value within the voltage control loop. While the immediate trip method can protect the hardware, it has the problem of hindering protection coordination by cutting off the supply of fault current necessary for the grid. The simple current limit method, on the other hand, has limitations in that it causes a wind-up phenomenon where integral errors of the external voltage controller accumulate, leading to severe overshoot and control instability during fault recovery. The problem to be solved

[0008] The present invention aims to protect the hardware and fundamentally block the occurrence of physical overcurrent without stopping the inverter by detecting the overcurrent of the GFM inverter when a grid fault occurs and immediately changing the control structure to a current control-based GFL mode.

[0009] In addition, the present invention aims to support system voltage recovery and assist in the detection of faults by protective relays through vector control logic that preferentially supplies reactive current and limits active current in proportion to the magnitude of the system voltage drop during a fault section.

[0010] The present invention aims to achieve seamless switching without phase jump or transient inrush current due to changes in control modes by mutually hand-over current command values ​​and frequency information between controllers and initializing integrator state values ​​during mode switching. means of solving the problem

[0012] An overcurrent protection method for an inverter operating in a grid forming control mode may include the steps of measuring the output current of the inverter, comparing whether the magnitude of the measured output current exceeds a preset protection threshold (I_limit), switching the operating mode of the inverter from a voltage control-based grid forming mode to a current control-based grid following mode when the output current exceeds the protection threshold, and controlling the current reference value within a preset limit in the switched grid following mode to supply a fault current to the power grid. Effects of the invention

[0014] The mode-switching type output limiting method and system of a grid-forming inverter for overcurrent protection and fault current supply according to the present invention has the effect of preventing damage to the inverter by solving the overcurrent problem, which is a structural weakness of voltage source control, through mode switching to current source control.

[0015] The present invention can improve transient response characteristics during accident recovery by fundamentally eliminating the controller wind-up problem that occurs in a simple limiter method.

[0016] The present invention can enable smooth operation mode changes by minimizing the switching shock between heterogeneous control modes through state value transfer technology.

[0017] The present invention applies hysteresis logic using timers and voltage conditions during accident recovery, thereby preventing chattering caused by frequent mode switching in unstable system conditions. Brief explanation of the drawing

[0019] FIG. 1 is a block diagram showing the configuration of a mode-switching output limiting system of a grid-forming inverter for overcurrent protection and fault current supply according to one embodiment. FIG. 2a illustrates the normal operating state and circuit characteristics of a grid forming (GFM) inverter according to one embodiment. FIG. 2b illustrates the principle of overcurrent generation in a grid forming inverter when a system fault occurs according to one embodiment. FIG. 2c illustrates conventional overcurrent protection methods and their limitations according to one embodiment. FIG. 3a illustrates a circuit model and waveforms to explain the principle of overcurrent generation in a grid forming (GFM) inverter according to one embodiment. FIG. 3b illustrates the integrator wind-up phenomenon and the resulting problems that occur when applying a conventional simple current limiter method according to one embodiment. FIG. 3c illustrates a comparison of the operating characteristics of the grid forming (GFM) mode and the grid following (GFL) mode during a grid fault according to one embodiment. Figure 4 illustrates a comparison of the current response characteristics in the event of a fault of an inverter to which the prior art according to one embodiment and the technology of the present invention are applied. FIG. 5a illustrates an overall control block diagram for seamless mode switching between a grid forming (GFM) inverter and a grid following (GFL) inverter according to one embodiment. FIG. 5b illustrates in detail the configuration of a voltage controller in grid forming (GFM) mode according to one embodiment. FIG. 5c illustrates in detail the power control loop configuration of a grid following (GFL) mode according to one embodiment. FIG. 5d illustrates the connection relationship between a current controller and a pulse width modulation (PWM) generator according to one embodiment. FIG. 6a shows the simulation waveform of a conventional grid forming inverter to which mode switching logic according to one embodiment is not applied. FIG. 6b illustrates a simulation waveform when the mode switching and stabilization control technique of the present invention according to one embodiment is applied. Specific details for implementing the invention

[0020] FIG. 1 is a block diagram showing the configuration of a mode-switching output limiting system of a grid-forming inverter for overcurrent protection and fault current supply according to one embodiment.

[0021] A system (100) according to one embodiment may include a processor (120) and memory (130), and some of the illustrated components may be omitted or substituted. In a modern computing environment, various input / output interfaces, network modules, security chips, power management units, etc., may be added in addition to these basic components, but for the sake of brevity in the drawings, only the core components are shown. A system (100) according to one embodiment may be a server or a terminal, and if implemented as a server, it may be equipped with high-performance enterprise-grade hardware and deployed in a cloud environment or an on-premises data center. If implemented as a terminal, it may be realized in various forms such as a smartphone, tablet, IoT device, or wearable device, and may have a hardware configuration optimized for each form.

[0022] According to one embodiment, the processor (120) is configured to perform operations or data processing regarding the control and / or communication of each component of the system (100) and may be composed of one or more processors. In modern systems, heterogeneous computing structures are widely adopted in which various types of processors, such as a central processing unit (CPU), a graphics processing unit (GPU), a neural network processing unit (NPU), and a digital signal processing unit (DSP), are used together and optimized for different workloads. The CPU is based on architectures such as x86-64, ARM, and RISC-V, and various configurations are possible from a single core to 64 cores or more. The memory (130) may store information related to the method described above or store a program in which the method described above is implemented. Memory (130) may be volatile or non-volatile memory; volatile memory mainly uses DRAM and SRAM, while non-volatile memory may utilize various next-generation memory technologies such as NAND flash (SSD), eMMC, UFS, NOR flash, PRAM, MRAM, and ReRAM. In modern systems, L1 / L2 / L3 caches, main memory, and swap space are organically linked through a memory hierarchy to optimize the balance between performance and capacity. Memory (130) can store various file data, and the stored file data can be updated according to the operation of the processor (120). Modern storage technology can improve data integrity and performance through file system-level transaction support, journaling, data deduplication, real-time compression, and snapshot functions.

[0023] According to one embodiment, the processor (120) can execute a program and control the device (100). The code of the program executed by the processor (120) can be stored in memory (130), and such code can be stored and executed in various forms, such as machine language, bytecode, or interpreter language. Modern processors optimize execution performance through advanced techniques such as instruction pipelining, branch prediction, speculative execution, and instruction-level parallelism. The operations of the processor (120) can be performed by loading instructions stored in memory (130), and in this process, steps such as instruction fetch, decode, execute, memory access, and write-back are performed. The system (100) can be connected to an external device (e.g., a personal computer or a network) through an input / output device (not shown in the drawing) and exchange data. Input / output devices may include various wired and wireless interfaces such as USB, Thunderbolt, HDMI, DisplayPort, PCIe, Ethernet, Wi-Fi, Bluetooth, NFC, 5G, and infrared communication, which enable interaction with other devices.

[0024] According to one embodiment, the processor (120) may have a form capable of executing software to control various components of an electronic device, namely hardware or software, and performing various data processing and operations. At the operating system level, various hardware is managed through a consistent interface via a Hardware Abstraction Layer (HAL), and the functions of specific hardware can be utilized through device drivers. For example, the processor may have a form capable of storing commands or data received from a sensor module or a communication module in volatile memory, processing them, and storing the resulting data in non-volatile memory. When processing sensor data, it is processed into meaningful information through processes such as noise filtering, calibration, feature extraction, and pattern recognition. Such a processor may include a main processor and an auxiliary processor, and the auxiliary processor may have a form capable of consuming less power than the main processor or being optimized for specific functions. The low-power auxiliary processor can efficiently perform background tasks such as motion detection, voice recognition, and location tracking while minimizing battery consumption in standby mode. The auxiliary processor may have a form capable of operating on behalf of the main processor when it is inactive, or operating together with it when it is active to control functions related to the display module, sensor module, or communication module. This asymmetric multiprocessing structure is effective for optimizing the balance between power efficiency and performance.

[0026] FIG. 2a illustrates the normal operating state and circuit characteristics of a grid forming (GFM) inverter according to one embodiment.

[0027] FIG. 2a illustrates a state in which a grid forming (GFM) inverter according to one embodiment is connected to a power grid or load and operates normally. The GFM inverter can perform a voltage / frequency reference forming method that forms a reference for voltage and frequency on its own, without relying on the voltage or frequency of an external grid.

[0028] According to one embodiment, the GFM inverter may be designed to have a low output impedance lower than a specified level to realize ideal voltage source characteristics. Output impedance refers to the resistance component between the inverter's internal voltage source and the output terminal; the lower this value, the less voltage fluctuation occurs due to load variations, thereby enabling voltage maintenance performance. During normal operation, the inverter supplies a normal load current determined by the formed voltage and the load impedance, thereby maintaining stable power balance.

[0030] FIG. 2b illustrates the principle of overcurrent generation in a grid forming inverter when a system fault occurs according to one embodiment.

[0031] Figure 2b illustrates a voltage dip situation in which a fault (e.g., short circuit) occurs on the power system side, causing the system voltage to drop rapidly beyond a specified level within a specified time. The graph on the right side of the figure exemplarily shows the voltage magnitude dropping from a normal level (e.g., 1.0 pu) to a bottom level (e.g., 0.1 pu) relative to the fault point (t_fault).

[0032] According to one embodiment, the low output impedance characteristics of the GFM inverter during such an accident can cause a massive overcurrent. According to Ohm's law, the current can be determined by dividing the difference between the inverter's internal voltage and the grid voltage by the output impedance. Since the inverter attempts to maintain a constant internal voltage due to GFM control characteristics while the grid voltage drops close to zero, the difference between the two voltages can be maximized. At this time, because the impedance corresponding to the denominator is very small, a physical inrush current amounting to tens of times the rated current can flow from the inverter toward the grid. Such a massive overcurrent can act as a risk factor capable of thermally destroying power semiconductor devices (e.g., IGBT, MOSFET) inside the inverter within a few milliseconds (ms).

[0034] FIG. 2c illustrates conventional overcurrent protection methods and their limitations according to one embodiment.

[0035] FIG. 2c may show the limitations of conventional protection methods 1 and 2 that were used to solve the aforementioned overcurrent problem.

[0036] According to one embodiment, Method 1 (=Immediate Trip) may refer to a method of cutting off the gate signal of the inverter and opening the circuit as soon as an overcurrent is detected. The open switch shape in the drawing may indicate that the connection between the inverter and the grid is severed. While this method can reliably protect the inverter hardware, it may cause a problem of loss of fault current support from the grid's perspective. A power grid's protection relay can detect the fault location and operate the circuit breaker only when a fault current exceeding a certain level flows; however, if the inverter stops, the protection relay does not operate, which can expand the scope of the fault's propagation.

[0037] According to one embodiment, Method 2 (=Simple Current Limiter) may refer to a method of forcibly cutting (saturating) the current command value within the inverter control loop so that it does not exceed a specific value. The waveform distortion graph in the drawing may indicate that the current, which should be in the form of a sine wave, is deformed into a shape close to a square wave as the top and bottom are cut off by the limiter. Such waveform distortion not only increases harmonic components and degrades power quality, but also, from the perspective of the controller, can cause non-linear control problems where the input and output are not proportional. In particular, although the voltage controller continuously increases the control signal to meet the target voltage, the actual current does not increase because it is blocked by the limiter; consequently, a wind-up phenomenon occurs in which the integral value inside the controller accumulates infinitely, which can lead to an uncontrollable state.

[0038] As such, the limitations of the prior art illustrated in FIGS. 2a to 2c may serve as the technical background for proposing a mode-switching overcurrent protection method according to an embodiment of the present invention. Examples of the inverter structure, types of faults, and protection methods described in the drawings are merely examples to aid in understanding the present invention and are not limited thereto, and may vary depending on the configuration of the system or grid environment settings.

[0040] FIG. 3a illustrates a circuit model and waveforms to explain the principle of overcurrent generation in a grid forming (GFM) inverter according to one embodiment.

[0041] FIG. 3a may illustrate the structural vulnerability experienced by a system (100) operating in grid forming (GFM) mode during a grid fault situation. The circuit diagram (310) on the left side of the drawing may represent the system (100) modeled as a Thevenin equivalent circuit. Here, the system (100) may be represented in a form where an internal voltage source (E_inv) and an output impedance (Z_out) are connected in series. Grid forming control may have a voltage source (Stiff Voltage Source) characteristic that attempts to maintain the internal induced electromotive force (E_inv) constant regardless of changes in the grid voltage (V_g). Additionally, it may be common for the system (100) to be designed with a very small output impedance (Z_out) for ideal voltage source operation.

[0042] According to one embodiment, the waveform (320) on the right side of the drawing may represent a voltage dip situation in which the voltage (V_grid) of the connection point (PCC) drops rapidly due to a system fault. According to Ohm's law, the output current (I_out) of the system (100) can be determined as '(E_inv - V_g) / (Z_out)'. When V_g drops close to zero in the event of a fault, the voltage difference (E_inv - V_g), which is the numerator, increases, while the impedance (Z_out), which is the denominator, is very small, so the output current (I_out) can mathematically increase rapidly.

[0043] According to one embodiment, due to this principle, the system (100) inevitably generates a massive overcurrent that far exceeds the rated current (I_rated) and may enter an overcurrent zone as shown in the shaded area of ​​the drawing. This is a phenomenon that occurs by physical laws without separate control changes and can be a risk factor that can damage the power semiconductor of the inverter. The behavior of voltage and current shown in the drawing is merely an example and is not limited thereto, and may vary depending on the system impedance or the type of fault.

[0045] FIG. 3b illustrates the integrator wind-up phenomenon and the resulting problems that occur when applying a conventional simple current limiter method according to one embodiment.

[0046] FIG. 3b illustrates the side effects that occur when a simple current limiter is applied inside the voltage control loop of the system (100) to prevent overcurrent in a time series. The first graph (330) of FIG. 3b may show a situation where the system voltage (V_g) drops sharply at the time of the fault (t_fault) and then recovers at the time of the fault clearance (t_clear).

[0047] According to one embodiment, the second graph (340) may represent a change in the integrator value within the controller. The outer voltage controller of the system (100) may perform an integrator operation to compensate for the error (V_err) when the measured voltage (V_meas) is lower than the reference voltage (V_ref). During the fault period (t_fault ~ t_clear), the actual output current is limited by the current limiter (third graph), but since the voltage is still low, the voltage controller may continue to increase the command value to meet the target voltage and accumulate the error. This signifies an integrator wind-up phenomenon, which can be represented in the figure as the integrator value increasing linearly over time.

[0048] According to one embodiment, the third graph (350) may represent the inverter current (I_out) waveform immediately after the fault clearing (t_clear). Even though the grid voltage has returned to normal, the system (100) may momentarily fall into an uncontrollable state due to the already excessively accumulated integral value and cause a severe overshoot. This overshoot may cause a secondary trip of the system (100) or increase grid instability. Therefore, the simple current limiter method may have limitations in that it is difficult to guarantee linearity and stability of control.

[0050] FIG. 3c illustrates a comparison of the operating characteristics of the grid forming (GFM) mode and the grid following (GFL) mode during a grid fault according to one embodiment.

[0051] FIG. 3c illustrates the operation of the grid forming (GFM) mode and the grid following (GFL) mode in the event of an accident to explain a solution according to one embodiment of the present invention.

[0052] (a) on the left side of the diagram represents the operation of the GFM mode described earlier, which may show a phenomenon where a massive overcurrent occurs while trying to maintain the voltage due to the voltage source characteristics.

[0053] (b) on the right side of the drawing may indicate the operation when the system (100) detects a fault and switches to Grid Following (GFL) mode. GFL mode may refer to a control method in which the inverter operates as a current source. When the system (100) switches to GFL mode, the system (100) no longer attempts to directly form the grid voltage and may have a constant current source characteristic of following the phase of the grid voltage and outputting only the commanded current.

[0054] According to one embodiment, the system (100) limits the current command value in GFL mode to within the rated range (e.g., 1.2 pu), thereby preventing physical overcurrent from occurring even if the grid voltage drops sharply. The system (100) fundamentally blocks entry into an overcurrent region such as (a) and can continuously supply fault current within a safe range such as (b). Through this, the system (100) can perform stable operation that satisfies the grid code while protecting the hardware. The shape of the graph or the current limit range shown in the drawing is merely an example for convenience of explanation and is not limited thereto, and may vary depending on the settings of the system (100).

[0056] Figure 4 illustrates a comparison of the current response characteristics in the event of a fault of an inverter to which the prior art according to one embodiment and the technology of the present invention are applied.

[0057] Figure 410 in Fig. 4 illustrates the overcurrent phenomenon that a conventional grid forming (GFM) inverter may experience during a grid fault. For example, a fault may occur in the inverter at time t=1.5s where the grid voltage (V_grid) drops sharply from 1.0 pu to a lower voltage. At this time, due to the inverter's tendency to maintain voltage source characteristics, the output current (I_out) may significantly exceed a preset limit (e.g., 1.2 pu), causing a severe overcurrent that spikes to 2.5 pu or higher. Additionally, due to control instability, the conventional inverter may exhibit divergence, where the current waveform fails to converge and oscillates severely; this can be a direct cause of hardware failure. The magnitude of the preset limit is merely an example and is not a limiting factor, but may vary depending on the settings.

[0058] Figure 420 of FIG. 4 may illustrate a current limiting operation performed by a system (100) according to one embodiment of the present invention in the same fault situation. The system (100) may switch the operating mode from a voltage control mode to a current control mode (GFL) immediately upon detecting a grid voltage drop at time t=1.5s (Mode Switch to GFL). The mentioned time is merely an example and is not limited thereto, and may vary depending on the situation.

[0059] According to one embodiment, the system (100) can independently control the dq-axis current component after mode switching. Referring to the graph of the central dq-axis current component in Figure 420, the system (100) can rapidly decrease the d-axis current (I_de) corresponding to active power and increase the q-axis current (I_qe) corresponding to reactive power to help restore voltage. The system (100) can form such a waveform through vector priority control that secures reactive current preferentially within the total current capacity and limits active current within the remaining capacity.

[0060] According to one embodiment, the system (100) can stably limit the total output current magnitude (|I_out|) so that it does not exceed a preset limit (Limit, 1.2 pu). Referring to the bottom graph of Figure 420, the system (100) can immediately clamp the current magnitude to 1.2 pu or less and maintain it constant even if a momentary transient response occurs immediately after a fault. Through this, the system (100) can protect the inverter element while continuously and stably supplying the fault current required for the grid protection relay to detect the fault. The values ​​of time (t), voltage, and current unit (pu) indicated in the graph are merely examples and are not limited thereto, and may vary depending on the system capacity or settings.

[0062] FIG. 5a illustrates an overall control block diagram for seamless mode switching between a grid forming (GFM) inverter and a grid following (GFL) inverter according to one embodiment.

[0063] FIG. 5a illustrates an integrated control structure for changing control modes in the event of a grid fault and during recovery in a system (100) according to one embodiment. The system (100) may include an excitation control loop (510) and a grid synchronization controller (512). Excitation may refer to the process of generating a magnetic field by supplying a direct current (DC) to a generator rotor. The phase-locked loop (PLL) block at the top of the figure may play a role in tracking the phase and frequency (w_PLL) by controlling the grid voltage (vq) to zero in grid-following (GFL) mode. On the other hand, the active power controller may generate an internal frequency and phase based on a swing equation including virtual inertia (1 / J) and damping (D) in grid-forming (GFM) mode.

[0064] According to one embodiment, the system (100) can exchange frequency information between two controllers through a mode switch. For example, when switching to GFL mode, the system (100) can prevent phase jumps by inputting the frequency of GFM as the initial value of the PLL. Conversely, when returning to GFM mode, the system (100) can suppress synchronization inrush current by inputting the frequency of the PLL as the initial value of the integrator of the active power controller.

[0065] According to one embodiment, the system (100) can calculate the output power of the inverter in real time through a power calculation unit (514). The system (100) can calculate the current power using the measured dq-axis voltages (vd, vq) and currents (id, iq) through formulas such as active power Pm = 1.5 * (v_d * i_d + v_q * i_q) and reactive power Qm = 1.5 * (-v_d * i_q + v_q * i_d). The calculated power values ​​can be used as feedback signals for each controller.

[0067] FIG. 5b illustrates in detail the configuration of a voltage controller in grid forming (GFM) mode according to one embodiment.

[0068] FIG. 5b may show the internal configuration of a voltage controller (520) for maintaining a constant voltage in grid forming (GFM) mode. The voltage controller (9520) receives the error between the d-axis and q-axis voltage command values ​​(Vd_ref, Vq_ref) and the actual measured voltage (v_d, v_q) and performs proportional-integral (PI) control to output current command values ​​(id_GFM, iq_GFM). At this time, the cross-coupled term (w_b * C_f) may represent decoupling control that compensates for interference components between the d and q axes. The system (100) can prevent voltage overshoot that may occur at the moment the voltage controller is activated by setting the current command value generated in GFL mode as the initial value of the integrator (K_iv / s) within the voltage controller during fault recovery.

[0069] According to one embodiment, a voltage controller (520) can perform the role of maintaining the output voltage of the inverter constant in grid forming mode. The voltage controller can receive the error between the d-axis voltage command value (Vd_ref) and the q-axis voltage command value (Vq_ref) and the actual measured voltage (v_d, v_q). The voltage controller can generate a d-axis current command value (id_GFM) and a q-axis current command value (iq_GFM) by compensating for the voltage error through a proportional-integral (PI) controller (K_pv + K_iv / s).

[0070] According to one embodiment, the voltage controller (520) may include decoupling control logic to eliminate mutual interference between the d-axis and the q-axis. The cross-coupled term (w_b * C_f) may refer to a term that compensates for interference caused by the capacitance (C_f) component of the output filter. The system (100) can precisely control the d-axis and q-axis voltages independently by multiplying the measured voltage by the compensation term and cross-adding or subtracting. Additionally, the system (100) can prevent voltage overshoot that may occur at the moment the voltage controller (520) is activated by setting the current command value generated in GFL mode during fault recovery as the initial value of the integrator (K_iv / s) within the voltage controller.

[0072] FIG. 5c illustrates in detail the power control loop configuration of a grid following (GFL) mode according to one embodiment.

[0073] FIG. 5c may show a power control loop (530) for following active power (P*) and reactive power (Q*) commands in grid following (GFL) mode. The system (100) can perform an operation to convert the power command into a current command (id_GFL, iq_GFL) based on the measured d-axis voltage (vd). In this process, the system (100) can generate a current command value by applying vector priority control to preferentially supply reactive power (Q) and reduce active power (P) within a limited current capacity when the grid voltage drops.

[0074] According to one embodiment, the power control loop (530) can perform the role of converting the active power command (P_ref) and reactive power command (Q_ref) required by the upper controller in grid following mode into current command values. The system (100) can generate a current command by performing a mathematical operation based on the measured d-axis voltage (vd). As illustrated in the drawing, the system (100) can perform an operation of multiplying the active power command (P_ref) by 2 and dividing it by (3 * vd) to generate a d-axis current command (id_GFL).

[0075] According to one embodiment, this operation structure may have the characteristic that when the grid voltage (vd) decreases, the current command (id_GFL) increases inversely proportionally to maintain the same power. When the current command value calculated in this process attempts to exceed a preset protection threshold, the system (100) may limit the current command through the limiter described above. Additionally, the cross term (v_q * i_q / v_d) illustrated in the drawing is a term for compensating for interference between the dq axes, through which the system (100) can ensure linearity of power control even during voltage fluctuations.

[0077] FIG. 5d illustrates the connection relationship between a current controller and a pulse width modulation (PWM) generator according to one embodiment.

[0078] FIG. 5d illustrates the process in which a current command value selected via a mode switching switch is input to a current controller (540). In the event of a fault, the system (100) can select and transmit a GFL current command (id_GFL, iq_GFL) instead of a GFM current command (id_GFM, iq_GFM) to the current controller. The current controller can generate a voltage command (vt_d, vt_q) by proportional-integral (PI) control of the error between the input current command and the actual current (i_d, i_q). Finally, the PWM generation unit can generate an inverter switching signal based on this voltage command. The system (100) can ensure the continuity of control by sampling the last current command value output by the GFM controller at the time of mode switching (t_fault) and maintaining it as the input to the current controller in the initial GFL mode.

[0079] According to one embodiment, the system (100) may include a mode switching switch to select a current command value based on the operating mode. The system (100) may select the GFM current command (id_GFM, iq_GFM) generated in FIG. 5b during normal grid forming operation, and select the GFL current command (id_GFL, iq_GFL) generated in FIG. 5c during a grid fault and transmit it to a current controller (540).

[0080] According to one embodiment, a current controller (540) can generate a voltage command (vt_d, vt_q) that the inverter must output by proportional-integral (PI) control (K_pi + K_ii / s) the error between the input current command value and the actual measured current (i_d, i_q). The current controller (540) may include a decoupling term (w_b * L_f) to compensate for cross-coupled due to inductance (Lf). A PWM generation unit (PWM Generation) (550) can convert the dq-axis voltage command into a three-phase voltage command (abc) using a phase angle and generate a PWM signal to drive the power semiconductor switch of the inverter based on the converted value. The system (100) can perform a handover operation by sampling the last current command value that the GFM controller output at the time of mode switching (t_fault) and maintaining it as the input of the current controller at the beginning of entering the GFL mode.

[0082] FIG. 6a shows the simulation waveform of a conventional grid forming inverter to which mode switching logic according to one embodiment is not applied.

[0083] FIG. 6a shows graphs of power (P_Power) (602), voltage (Grid_Voltage) (604), and current (GFM_Current) (606) in a state where the system operates only in grid forming (GFM) mode without separate mode switching logic. The mode state graph (GFM&GFL_MODE) (608) can show that the system (100) maintains the GFM mode (= value 1.0) throughout the entire simulation period.

[0084] According to one embodiment, a fault may occur on the grid side at time 2.0 seconds, causing a low-voltage situation in which the grid voltage (Grid_Voltage) (604) drops rapidly to about 50% of the normal state. At this time, if one examines the output current (GFM_Current) waveform (606) of the system (100), it can be seen that a massive inrush current, equivalent to tens of times the rated current, occurs at 2.0 seconds, the time at which the fault occurs. The mentioned times and figures regarding the voltage drop are merely examples and are not limited thereto, and may vary depending on the situation.

[0085] According to one embodiment, such overcurrent generation may be attributed to the structural characteristics of grid forming control in which the system (100) operates as a voltage source. The system (100) may operate as an equivalent circuit having an internal voltage source (E_inv) and a very low output impedance (Z_out). According to Ohm's law, the output current (I_out) may be determined by dividing the difference between the internal voltage source and the grid voltage (V_grid) by the output impedance. Since the system (100) has a property (Stiff Voltage) of maintaining the internal voltage constant even if the grid voltage drops close to zero due to a fault, the voltage difference may increase rapidly, and an overcurrent that is physically uncontrollable may be introduced.

[0086] According to one embodiment, a situation may be shown where the fault is cleared at time 2.5 seconds and the system voltage returns to a normal range. However, it can be observed that the current waveform of the system (100) does not stabilize and continues to be in an uncontrollable state, such as oscillating or diverging severely. This may be because an integrator wind-up phenomenon occurred during the period when the fault persists (2.0 seconds to 2.5 seconds), as the voltage controller inside the system (100) continues to integrate the error to match the target voltage. The accumulated excessive integration value may cause a severe overshoot at the moment the voltage is restored, making self-recovery of the system (100) impossible.

[0088] FIG. 6b illustrates a simulation waveform when the mode switching and stabilization control technique of the present invention according to one embodiment is applied.

[0089] Referring to FIG. 6b, the system (100) may indicate a protection sequence to be executed when a grid fault (e.g., a 50% voltage drop) occurs at the 2.0-second mark while operating normally (1.2 seconds to 2.0 seconds) in grid forming (GFM) mode. Referring to the mode state graph in FIG. 618, it can be seen that the system (100) switches to grid following mode by changing the mode flag (GFM_MODE) from 1 (GFM) to 0 (GFL) immediately upon detecting the fault. The mentioned times and values ​​for voltage drops are merely examples and are not limited thereto, and may vary depending on the situation.

[0090] According to one embodiment, the system (100) operates in GFL mode during a fault duration of 2.0 to 2.5 seconds and can effectively control the current. Looking at the current graph (GFM_Current) (616), unlike FIG. 6a, it can be seen that no massive overcurrent occurs, and the output current is stably clamped within the limit set by the system (100). This may be because the system (100) corrects the power command based on the voltage measured in real-time in GFL mode and directly controls the current, thereby preventing the occurrence of overcurrent at the source. In addition, the system (100) can smoothly change the control mode without current transients even at the moment of mode switching through the hand-over logic.

[0091] According to one embodiment, even if the system voltage returns to the normal range (Voltage Recovery) at the time of 2.5 seconds in Figure 614, the system (100) may not immediately return to GFM mode but may maintain a stabilization standby state for a certain period of time (2.5 seconds to 2.75 seconds). This may be the result of the operation of a timer latch and voltage condition logic set within the system (100). To prevent transient phenomena or hunting that may occur during the voltage recovery process, the system (100) may forcibly maintain GFL mode (Hysteresis) until the system is completely stabilized.

[0092] According to one embodiment, when stabilization conditions (e.g., timer expiration and voltage normal verification) are met at time 2.75 seconds, the system (100) can perform a seamless return from GFL mode to GFM mode. At this time, the system (100) can inject the final current state and phase information of the GFL mode into the GFM controller through reverse hand-over. As a result, as can be seen in the waveform after 2.75 seconds in the drawing, the system (100) can return to the voltage source control mode without voltage overshoot or inrush current and resume normal power supply (250kW).

[0093] According to one embodiment, the system (100) can perform a protection sequence that switches from a grid forming (GFM) mode to a grid following (GFL) mode when a grid fault occurs. At the point in time (t_fault) when the system detects a grid fault and switches to GFL mode, the system (100) can perform an initialization operation to prevent conflicts between control modes.

[0094] According to one embodiment, the system (100) can sample the d-axis and q-axis current command values ​​(i_d_GFM, i_q_GFM) that the voltage controller of the GFM control loop last output. The system (100) can perform a current controller command value handover in which these sampled values ​​are injected as the initial values ​​of the current controller integrator of the first sampling cycle immediately after entering the GFL mode. Expressed as a mathematical relationship (i_dq_GFL_ref <- i_dq_GFM), this means that the initial current command of the GFL mode is set to be the same as the last current command of the GFM mode. Through this handover process, the system (100) can suppress transient responses by ensuring the continuity of the current command even if the control mode changes abruptly from voltage control to current control.

[0095] Additionally, the system (100) can perform phase synchronization of the phase-locked circuit (PLL) in the event of a fault. The system (100) can input the internal angular frequency (w_GFM) generated during GFM operation as the initial value of the integrator of the PLL within the GFL control loop. That is, the system (100) can forcibly assign the initial frequency value (w_PLL_Integrator) of the PLL integrator to the final frequency value (w_GFM) of the GFM mode. Through this, the system (100) can prevent the phase jump phenomenon caused by the mismatch between the inverter's internal phase and the grid phase at the moment of mode switching, and enable smooth mode switching.

[0096] According to one embodiment, the system (100) can perform reverse compensation according to the fault recovery sequence even at the point in time (t_recovery) when the grid voltage returns to a normal range and returns to GFM mode. The system (100) can perform voltage controller anti-windup initialization. The system (100) can set the actual current command values ​​(i_d_GFL, i_q_GFL) controlled in GFL mode as the initial values ​​of the PI controller integral term within the voltage controller in GFM mode. This may be to prevent the integral value from starting from '0' or from an excessive accumulated value prior to the fault when the deactivated voltage controller is reactivated. By using the currently flowing stable current state as the starting point of the voltage controller, the system (100) can effectively suppress voltage overshoot that may occur at the time of recovery and stably resume voltage source control. These initialization and handover methods are merely examples and are not limited thereto; they can be modified and applied in various ways depending on the type of controller (e.g., PR controller, hysteresis controller) or system configuration.

[0098] According to one embodiment, an overcurrent protection method for an inverter operating in a grid-forming control mode can measure the output current of the inverter and compare whether the magnitude of the measured output current exceeds a preset protection threshold (I_limit). Here, the grid-forming control mode may refer to a state in which the inverter operates as a voltage source by forming its own voltage and frequency independently of the grid voltage. The inverter can detect the three-phase output current in real time through a current sensor and convert it into a dq-axis coordinate system to calculate the magnitude of the current vector. The preset protection threshold may refer to a hardware limit or a software limit that considers a safety margin, which the power semiconductor device (e.g., IGBT) inside the inverter can withstand without being damaged.

[0099] According to one embodiment, when the output current exceeds a protection threshold, the operating mode of the inverter can be switched from a voltage-controlled grid-forming mode to a current-controlled grid-following mode. This may mean changing the control structure of the inverter from a characteristic of maintaining a constant voltage (Stiff Voltage Source) to a current source having a characteristic of following a current command. In the grid-forming mode, a structural vulnerability may occur in which excessive current flows to maintain the voltage when the grid voltage drops sharply. Therefore, the system (100) can prevent the occurrence of a physical overcurrent by switching the control loop immediately upon detection of an overcurrent, thereby cutting off the output of the voltage controller and activating the current controller. This mode switching can have the effect of ensuring grid continuity by allowing the inverter to continue operation without tripping.

[0100] According to one embodiment, the step of switching to a current control-based grid following mode may include an integrator state initialization process that suppresses transient response during control mode switching by hand-overing the current reference value output by the voltage controller of the grid forming mode to the initial setting value of the current controller of the grid following mode, and setting the internal frequency value of the grid forming mode to the initial value of the integrator in the phase-locked loop (PLL) of the grid following mode. At the moment the control structure changes, the inverter can ensure the continuity of control and suppress transient inrush current caused by a phase jump by forcibly injecting the last output value of the previous mode into the integrator in the controller that was deactivated.

[0101] According to one embodiment, a fault current can be supplied to the power grid by limiting the current reference value in the switched grid following mode. The inverter may further include the step of preferentially allocating a reactive current reference value in proportion to the voltage dip of the grid voltage and determining an active current reference value within a range where the magnitude of the total output current vector does not exceed the protection threshold. This may be intended to preferentially supply reactive power that helps restore voltage in compliance with the Grid Connection Regulation (FRT). The inverter can calculate the maximum allowable margin of the active current by calculating the square root of the value obtained by subtracting the square of the reactive current reference value from the square of the protection threshold, and prevent overcurrent tripping by operating a limiter to output the active current only within this range.

[0102] According to one embodiment, the inverter measures the grid's d-axis voltage (V_de) in real time and can calculate an active current reference value based on the measured d-axis voltage rather than a fixed rated voltage. In the event of an accident where the grid voltage drops sharply, the inverter can control the target active power output to be lowered in proportion to the magnitude of the lowered voltage. This is intended to suppress the phenomenon where excessive current is generated when attempting to forcibly output the rated output in a low voltage state and to maintain power balance.

[0103] According to one embodiment, the inverter can perform sequence control to operate a timer for a preset minimum holding time from the point at which it switches to the grid-following mode. During the period in which the timer is operated, the inverter can block a return to the grid-forming mode and forcibly maintain the grid-following mode even if the output current decreases below a protection threshold or the grid voltage recovers. This is intended to prevent chattering caused by frequent mode switching due to unstable fault conditions and to allow a return to the mode only after the grid has been reliably stabilized.

[0104] According to one embodiment, upon grid fault recovery following the step of supplying fault current, the inverter can return from grid following mode to grid forming mode. When the timer expires and the grid voltage is restored, the inverter can perform reverse state value transfer by setting the current reference value of the grid following mode as the initial value of the integrator within the voltage controller of the grid forming mode. Additionally, the inverter can synchronize the virtual inertia frequency with the grid frequency by setting the output frequency of the phase-locked loop (PLL) as the initial value of the integral term of the swing equation within the active power controller of the grid forming mode. Through this bidirectional state value initialization and synchronization process, the inverter can prevent voltage overshoot and inrush current caused by phase difference at the time of return, and re-enter the voltage source control mode.

[0106] According to one embodiment, an overcurrent protection method for an inverter operating in a grid forming control mode can measure the output current of the inverter and compare whether the magnitude of the measured output current exceeds a preset protection threshold (I_limit). If the output current exceeds the protection threshold, the operating mode of the inverter can be switched from a voltage control-based grid forming mode to a current control-based grid following mode, and a fault current can be supplied to the power grid by limiting the current reference value in the switched grid following mode.

[0107] According to one embodiment, an overcurrent protection method for an inverter operating in a grid forming control mode can measure the output current of the inverter and compare whether the magnitude of the measured output current exceeds a preset protection threshold (I_limit). Here, the grid forming control mode may refer to a state in which the inverter operates as a voltage source by forming its own voltage and frequency independently of the grid voltage. The inverter can detect the output current in real time through a current sensor and calculate the magnitude of the current vector by performing a coordinate transformation.

[0108] According to one embodiment, when the output current exceeds a protection threshold, the operating mode of the inverter can be switched from a voltage-controlled grid-forming mode to a current-controlled grid-following mode.

[0109] According to one embodiment, a fault current can be supplied to the power system by limiting the current reference value in the switched grid following mode. Limiting the current reference value may mean a process of forcibly clamping the magnitude of the target current that the inverter intends to output to within the protection threshold value. The system can perform the function of helping the system's protection relay detect the fault location by continuously injecting current into the system within an allowable maximum limit, rather than cutting off the current even in a fault situation.

[0110] According to one embodiment, the step of switching to a current control-based grid following mode may include a process of handing over a current reference value output by a voltage controller in a grid forming mode to an initial setting value of a current controller in a grid following mode. The system can ensure the continuity of current control by sampling the output value last calculated by the voltage controller and setting it as the initial value of the integrator of the newly activated current controller.

[0111] According to one embodiment, a system (e.g., the system (100) of FIG. 1) can perform an integrator state value initialization process that suppresses transient response during control mode switching by setting the internal frequency value of the grid forming mode as the initial value of the integrator in the phase-locked circuit (pll) of the grid following mode. By injecting angular frequency information generated in the grid forming mode into the integrator of the phase-locked circuit, the system can prevent a phase jump from occurring at the time of mode switching and implement a seamless mode transfer.

[0112] According to one embodiment, the step of supplying fault current may further include an operation of generating a reactive current reference value in proportion to the drop in grid voltage, while preferentially attenuating the active current reference value so that the magnitude of the total output current vector does not exceed a protection threshold. To comply with grid connection regulations (frt), the system may preferentially supply reactive power that helps voltage recovery and reduce active power components of relatively low importance to control the system so that the magnitude of the total current vector does not exceed a hardware limit.

[0113] According to one embodiment, the system can calculate the maximum margin that the active current can have using a protection threshold (I_limit) and a reactive current reference value (I_q_ref) generated according to the grid voltage drop. The maximum margin can be calculated as the square root of the value obtained by subtracting the square of the reactive current command from the square of the total allowable current. The system can operate a limiter to output the active current reference value (I_d_ref) only within the calculated maximum margin range.

[0114] According to one embodiment, the system measures the d-axis voltage (V_de) of the system in real time and can calculate an active current reference value based on the measured d-axis voltage rather than a fixed rated voltage. By controlling the active power output to naturally attenuate in proportion to the voltage magnitude during a voltage drop, the system can suppress the phenomenon of overcurrent occurring due to the operation to maintain the rated output.

[0115] According to one embodiment, the system may operate a timer for a preset minimum holding time from the point at which it switches to grid following mode. During the period in which the timer operates, even if the output current decreases below a protection threshold or the grid voltage recovers, the system may block a return to grid forming mode and forcibly maintain the grid following mode. To prevent hunting or chattering caused by frequent mode switching due to unstable fault conditions, the system may fix the control mode until the system is sufficiently stabilized.

[0116] According to one embodiment, the method may further include a step of returning from a grid-following mode to a grid-forming mode upon grid fault recovery after the step of supplying fault current. The step of returning to a grid-forming mode may include a process of checking whether a preset stabilization time has elapsed after the overcurrent or undervoltage condition is resolved, and simultaneously checking whether the grid voltage has recovered to a preset normal range. The system may minimize the possibility of a recurrence of the fault by returning to a normal operation mode only when both temporal conditions (e.g., a timer) and physical conditions (e.g., voltage) are satisfied.

[0117] According to one embodiment, when the timer expires and the grid voltage is restored, the system can set the current reference value of the grid following mode as the initial value of the integrator in the voltage controller of the grid forming mode. By reflecting the stable current state currently flowing as the initial state of the voltage controller, the system can suppress voltage overshoot that may occur at the moment control is transferred.

[0118] According to one embodiment, the inverter can form voltage and frequency using an active power controller that includes a swing equation based on virtual inertia in grid forming mode. During the process of returning to the mode, the system can set the output frequency of the phase locking circuit (pll) as the initial value for the integral term of the swing equation within the active power controller. By forcibly synchronizing the frequency of the virtual rotor internally generated by the inverter with the actual frequency of the current grid, the system can prevent inrush current caused by the phase difference at the time of return.

[0120] According to one embodiment, the step of switching to a current-controlled grid-following mode may include an integrator state initialization process that suppresses transient response during control mode switching by hand-overing a current reference value output by a voltage controller in the grid-forming mode to an initial setting value of a current controller in the grid-following mode, and setting an internal frequency value of the grid-forming mode to an initial value of an integrator in the phase-locked loop (PLL) of the grid-following mode.

[0121] According to one embodiment, the step of switching to a current control-based grid following mode may include an integrator state initialization process that suppresses transient response during control mode switching by hand-overing the current reference value output by the voltage controller of the grid forming mode to the initial setting value of the current controller of the grid following mode, and setting the internal frequency value of the grid forming mode to the initial value of the integrator within the phase locking loop (PLL) of the grid following mode. The inverter may sample and store the d-axis and q-axis current command values ​​at the last point in time that the external voltage control loop generated to compensate for voltage errors while operating in the grid forming mode. At the moment the mode is switched, the inverter may perform a hand-over operation to forcibly inject the sampled current command values ​​as initial values ​​into the integrator within the current controller of the grid following mode, which was previously deactivated. By transferring these state values, the inverter can prevent current spikes or excessive overshoot caused by control discontinuity by allowing the current controller to start control from the previous valid current command value, rather than '0', even if the control structure changes abruptly from voltage control to current control.

[0122] In addition, the inverter can set the internal angular frequency (w_GFM) information, which it generates and maintains internally in grid forming mode, as the initial value of the frequency integrator within the phase-locked loop (PLL) in grid following mode. Generally, while grid forming mode forms the phase using an internal oscillator, grid following mode operates based on a phase-locked loop that tracks the grid voltage; therefore, a phase mismatch between the two modes may occur at the time of switching. The inverter can input the frequency information of the grid forming mode into the integrator of the phase-locked loop to match the initial phase at the start of grid following mode with the final phase of the grid forming mode. Through this synchronization of frequency and phase information, the inverter can suppress the occurrence of a phase jump at the moment of mode switching.

[0123] According to one embodiment, the step of supplying fault current may further include generating a reactive current reference value in proportion to the voltage dip of the system voltage, and attenuating the active current reference value first so that the magnitude of the total output current vector does not exceed the protection threshold value (I_limit).

[0124] According to one embodiment, the step of supplying fault current may further include an operation of generating a reactive current reference value in proportion to the voltage dip of the grid voltage, while preferentially attenuating the active current reference value so that the magnitude of the total output current vector does not exceed the protection threshold (I_limit). To perform the Low Voltage Ride Through (LVRT) function required by the Grid Code, the inverter may inject reactive current into the power grid to assist in voltage recovery when a voltage dip fault occurs, in which the magnitude of the grid voltage drops below the normal range. The inverter may perform proportional control to inject more reactive current as the voltage dip increases, and to this end, it may calculate a reactive current reference value (I_q_ref) by multiplying the voltage fluctuation by a proportionality constant (K-factor).

[0125] In addition, the inverter can actively limit the active current reference value (I_d_ref) to prevent the total output current from exceeding the hardware protection threshold due to reactive current injection. The inverter can execute Vector Priority logic that prioritizes the allocation of reactive current resources with Voltage Support as the primary objective while the total allowable current capacity is limited, and controls the output of active power only within the remaining current margin. Specifically, the inverter can calculate the maximum allowable limit for the active current in real time by calculating the square root of the difference between the square of the reactive current reference value (I_q_ref) and the square of the protection threshold (I_limit). If the original active current command value exceeds this maximum allowable limit, the inverter performs a clamping operation to cut the active current command value to the size of the maximum allowable limit, thereby safely controlling the system so that the magnitude of the total current vector does not exceed the protection threshold, which is a physical limit, while fulfilling the obligation to supply reactive power.

[0126] According to one embodiment, the process of preferentially attenuating the active current reference value can be controlled such that the magnitude of the total current vector does not exceed the protection threshold while ensuring the highest priority for reactive power injection by operating a limiter to output the active current reference value (I_d_ref) only within the calculated maximum margin range, using a protection threshold (I_limit) and a reactive current reference value (I_q_ref) generated according to the system voltage drop. At this time, the maximum margin that the active current can have can be calculated through the square root of '{(I_limit)^2 - (I_q_ref)^2}'.

[0127] According to one embodiment, the process of preferentially attenuating the active current reference value may include the step of the inverter calculating the maximum margin that the active current can have using the protection threshold (I_limit) and the reactive current reference value (I_q_ref) generated according to the grid voltage drop, and operating a limiter to output the active current reference value (I_d_ref) only within the calculated maximum margin range. The inverter may set reactive power injection as the top priority goal to support voltage recovery in the event of a grid fault. By utilizing the fact that the total output current consists of the vector sum of the active current component and the reactive current component, the inverter may first allocate the reactive current component within the protection threshold, which is a physical current limit, and calculate the remaining capacity as the available range of the active current.

[0128] Specifically, the inverter can calculate the maximum margin that the active current can have in real time through a formula that takes the square root of the value obtained by subtracting the square of the reactive current reference value from the square of the protection threshold. If the active current command value required by the upper controller exceeds the calculated maximum margin, the inverter can forcibly clamp the active current command value down to that maximum margin value. This control operation can have the effect of preventing overcurrent tripping of the inverter by mathematically and precisely limiting the magnitude of the total current vector so that it does not exceed the hardware protection threshold while faithfully fulfilling the obligation to inject reactive power.

[0130] According to one embodiment, the method may further include a step of returning from grid following mode to grid forming mode upon grid fault recovery after the step of supplying fault current. The step of returning to grid forming mode may include checking whether a preset stabilization time has elapsed after the overcurrent or undervoltage condition is resolved, and simultaneously checking whether the grid voltage has recovered to a preset normal range; and if the timer expires and the grid voltage is recovered, setting the current reference value of the grid following mode to the initial value of the integrator in the voltage controller of the grid forming mode, and setting the output frequency of the phase locking circuit (PLL) to the initial value of the frequency integrator in the active power controller of the grid forming mode to return the operating mode.

[0131] According to one embodiment, the inverter can return the operating mode from the grid following mode to the grid forming mode when the grid fault is removed and the voltage is restored after the step of supplying the fault current. As a prerequisite for performing the mode return, the inverter can simultaneously check whether the timer that has been operating since the overcurrent detection point has expired and whether the grid voltage has recovered to a preset normal range (e.g., 85% or more of the rated voltage). To prevent hunting phenomena that may occur if the mode is immediately restored in unstable situations where the voltage temporarily recovers and then drops again, or in intermittent fault situations, the inverter may forcibly maintain the grid following mode for a preset timer period and then return to the grid forming mode only when safety is ensured.

[0132] According to one embodiment, when the timer expires and the grid voltage is restored, the inverter can perform a reverse handover operation in which the current reference value output in grid-following mode is set as the initial value of the integrator in the voltage controller of grid-forming mode. When the deactivated voltage controller resumes operation, the inverter can start control by initializing the integrator value to the current state value currently flowing in the grid, rather than starting it as '0' or an uninitialized value. Through this initialization, the inverter can suppress sudden fluctuations in the control output or voltage overshoot that may occur the moment the voltage controller is activated, thereby enabling a stable soft landing in the voltage source control mode.

[0133] According to one embodiment, the inverter can return to the operating mode by setting the output frequency of the phase-locked loop (PLL) as the initial value of the frequency integrator within the active power controller of the grid-forming mode. If the grid-forming control algorithm used by the inverter includes a swing equation for implementing virtual inertia, the frequency integrator may represent the integral term of the swing equation. During the grid-following mode, the inverter can synchronize by injecting the actual frequency information of the grid, which the PLL was tracking in real time, into the initial value of the virtual rotor frequency of the grid-forming controller. Through such frequency and phase synchronization, the inverter can prevent the occurrence of inrush current caused by the phase difference by minimizing the difference between the inverter's internal voltage phase and the grid voltage phase at the time of returning to the GFM mode.

[0134] According to one embodiment, the inverter can form voltage and frequency using an active power controller that includes a swing equation based on virtual inertia in grid forming mode. In the process of returning to the mode, the output frequency of the phase locking loop (PLL) is set as the initial value for the integral term of the swing equation within the active power controller, thereby synchronizing the frequency inside the inverter with the grid frequency and preventing inrush current caused by the phase difference at the time of return.

[0135] According to one embodiment, the inverter can form voltage and frequency using an active power controller that includes a swing equation based on virtual inertia in grid forming mode. Here, virtual inertia refers to a technology that controls a power electronics-based inverter, which lacks a physical rotating body, to behave as if it possesses mechanical inertia similar to that of a synchronous generator. The active power controller can calculate the internal frequency and phase angle that the inverter must output by calculating the swing equation based on the error between the target active power and the actual output active power. Through this virtual inertia control, the inverter provides damping characteristics that resist frequency fluctuations in the grid and can operate as a voltage source that forms a reference for grid voltage and frequency.

[0136] According to one embodiment, the process of an inverter returning from a grid-following mode to a grid-forming mode upon fault recovery may include a step of setting the output frequency of a phase-locked loop (PLL) as an initial value for the integral term of the swing equation within the active power controller. Since the inverter tracks the frequency and phase of the grid voltage in real time through the phase-locked loop during the grid-following mode, the output value of the phase-locked loop may contain the most accurate grid frequency information at the time of return. By injecting this grid frequency value as an initial value into the frequency integrator of the swing equation, which was previously static or calculated with a different value, the inverter can immediately match the speed of the virtual rotor inside the inverter with the actual grid frequency.

[0137] According to one embodiment, the inverter can prevent inrush current caused by a phase difference at the time of return by synchronizing the internal frequency of the inverter with the grid frequency through frequency synchronization. If the mode is returned without such synchronization process, a sudden difference (Phase Jump) may occur between the voltage phase inside the inverter and the phase of the restored grid voltage, which may cause a massive synchronization inrush current at the inverter output terminal, thereby posing a risk of causing an overcurrent trip again. The inverter can smoothly align the phases of the inverter output voltage vector and the grid voltage vector at the moment of return to voltage source control through logic that initializes the integral term of the swing equation to the grid frequency.

[0139] According to one embodiment, the step of supplying fault current can suppress the occurrence of overcurrent by measuring the d-axis voltage (V_de) of the system in real time and calculating an active current reference value based on the measured d-axis voltage rather than a fixed rated voltage, thereby controlling the active power output to naturally attenuate in proportion to the voltage magnitude when the system voltage drops.

[0140] According to one embodiment, the step of supplying fault current can suppress the occurrence of overcurrent by measuring the d-axis voltage (V_de) of the grid in real time and calculating an active current reference value based on the measured d-axis voltage rather than a fixed rated voltage, thereby controlling the active power output to naturally attenuate in proportion to the voltage magnitude when the grid voltage drops. The inverter can monitor the effective magnitude of the grid voltage in real time by extracting the d-axis voltage component on a rotating coordinate system synchronized with the phase of the grid voltage. Generally, if the inverter attempts to follow a fixed active power command, a control characteristic may appear in which the current is rapidly increased to output the same power when the grid voltage drops. To prevent such overcurrent phenomena, the inverter can directly reflect the magnitude of the d-axis voltage measured in real time into the calculation of the current reference value instead of maintaining the fixed power command during a fault section where the voltage drops sharply. An inverter can induce a power equilibrium state in which output power naturally decreases as voltage decreases, by lowering the target active power output by the ratio of the measured voltage to the rated voltage reduction, or by limiting the magnitude of the current itself regardless of voltage fluctuations.

[0141] According to one embodiment, after the step of switching to a current control-based grid following mode, a timer is operated for a preset minimum holding time from the time of switching to the grid following mode, and during the period in which the timer is operated, even if the output current decreases below the protection threshold (I_limit) or the grid voltage recovers, the return to the grid forming mode is blocked and the grid following mode is forcibly maintained to prevent chattering caused by frequent mode switching.

[0142] According to one embodiment, the inverter can perform sequence control to operate an internal timer for a preset minimum dwell time from the point at which it is switched to a current control-based grid following mode. Here, the minimum dwell time may refer to the minimum physical time (e.g., hundreds of milliseconds to several seconds) required for the grid to be physically stabilized after a grid fault is detected and the mode is switched. During the time window in which the timer is operating, the inverter may ignore a request to return to the grid following mode and forcibly maintain the grid following mode, even if the measured output current decreases below a protection threshold or the grid voltage temporarily recovers to a normal range (e.g., 0.9 pu or higher).

[0143] This forced mode-holding behavior may be intended to account for "unstable recovery" situations that may occur in actual power grid environments. For example, in situations such as intermittent earth faults where grid faults are not completely eliminated or excessive oscillations occur during voltage recovery, if the inverter reverts to a mode based solely on voltage magnitude without a timer, a chattering phenomenon may occur, where the grid forming mode and grid following mode are repeated every few milliseconds. Such frequent mode switching not only increases the computational burden on the controller but can also cause rapid thermal stress on power semiconductor devices, thereby shortening their lifespan. Therefore, the inverter can set a hysteresis interval via a timer to allow mode reversion only after the transient state has completely dissipated and the grid has been reliably stabilized.

[0145] The embodiments described above may be implemented as hardware components, software components, and / or a combination of hardware components and software components. For example, the devices, methods, and components described in the embodiments may be implemented using one or more general-purpose or special-purpose computers, such as, for example, a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a programmable logic unit (PLU), a microprocessor, or any other device capable of executing and responding to instructions.

[0146] Software may include computer programs, code, instructions, or a combination of one or more of these, and may configure a processing unit to operate as desired or command the processing unit independently or collectively. Software and / or data may be permanently or temporarily embodied in any type of machine, component, physical device, virtual equipment, computer storage medium or device, or transmitted signal wave in order to be interpreted by the processing unit or to provide instructions or data to the processing unit.

[0147] Although the embodiments have been described above with reference to the limited drawings, those skilled in the art can apply various technical modifications and variations based on the above. For example, suitable results may be achieved even if the described techniques are performed in a different order than described, and / or if the components of the described system, structure, device, circuit, etc. are combined or assembled in a form different from described, or replaced or substituted by other components or equivalents.

Claims

Claim 1 An overcurrent protection method for an inverter operating in a grid forming control mode, comprising: a step of measuring the output current of the inverter; a step of comparing whether the magnitude of the measured output current exceeds a preset protection threshold (I_limit); a step of switching the operating mode of the inverter from a voltage control-based grid forming mode to a current control-based grid following mode when the output current exceeds the protection threshold; and a step of controlling the current reference value within a preset limit in the switched grid following mode to supply a fault current to the power grid. Claim 2 A method for limiting the output of an inverter according to claim 1, wherein the step of switching to a current control-based grid following mode further includes an integrator state initialization step of suppressing a transient response during control mode switching by hand-overing a current reference value output by a voltage controller of the grid forming mode to an initial setting value of a current controller of the grid following mode, and setting an internal frequency value of the grid forming mode to an initial value of an integrator within a phase-locked loop (PLL) of the grid following mode. Claim 3 A method for limiting the output of an inverter according to claim 1, wherein the step of supplying the fault current further comprises the step of preferentially allocating a reactive current reference value in proportion to the voltage dip of the system voltage and determining an active current reference value within a range in which the magnitude of the total output current vector does not exceed the protection threshold value. Claim 4 In claim 3, the operation of determining the active current reference value further comprises the step of calculating the maximum margin that the active current can have using the protection threshold value (I_limit) and the reactive current reference value (I_q_ref) generated according to the grid voltage drop, and the step of operating a limiter to output the active current reference value (I_d_ref) only within the calculated maximum margin range, thereby controlling the magnitude of the total current vector so as not to exceed the protection threshold value while ensuring reactive power injection, wherein the maximum margin that the active current can have is calculated through the square root of {(I_limit)^2 - (I_q_ref)^2}. Claim 5 A method for limiting the output of an inverter according to claim 1, further comprising, after the step of supplying the fault current, a step of returning from the grid following mode to the grid forming mode upon grid fault recovery, wherein the step of returning to the grid forming mode further comprises: a step of checking whether a preset stabilization time has elapsed after the overcurrent state or undervoltage state is resolved, and simultaneously checking whether the grid voltage has recovered to a preset normal range; and, if the preset stabilization time has elapsed and the grid voltage has recovered, a step of setting the current reference value of the grid following mode to the initial value of an integrator in the voltage controller of the grid forming mode, and setting the output frequency of the phase synchronous circuit (PLL) to the initial value of a frequency integrator in the active power controller of the grid forming mode to return to the operating mode. Claim 6 delete Claim 7 A method for limiting the output of an inverter according to claim 1, wherein the step of supplying the fault current further comprises the step of measuring the d-axis voltage (V_de) of the system in real time and the step of calculating an effective current reference value based on the measured d-axis voltage rather than a fixed rated voltage, thereby suppressing the occurrence of overcurrent by controlling the effective power output to naturally attenuate in proportion to the voltage magnitude when the system voltage drops.

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