Ferroelectric memory device and operating method thereof

Abstract

A memory device according to an embodiment of the present invention may include: a memory cell array comprising a plurality of memory cells; a peripheral circuit that performs a normal operation of applying a driving voltage for reading or writing data stored in the memory cells and a recovery operation of applying a recovery voltage to increase the residual polarization of the memory cells; and a control logic that controls the peripheral circuit to perform the normal operation after performing the recovery operation upon power-up.

Description

Technology Field

[0001] This patent document relates to semiconductor design technology, specifically to a method for performing a recovery operation of applying a wake-up pulse to a ferroelectric memory device. Background Technology

[0003] Ferroelectric Random Access Memory (FeRAM) is attracting attention as a next-generation memory device due to its non-volatile characteristics, which preserve data even when the power is off and offer data processing speeds comparable to DRAM. FeRAM has a structure nearly identical to DRAM, and by using a ferroelectric material with high residual polarization for the cell capacitor, it is possible to achieve the characteristic where data is not erased even when the electric field is removed.

[0004] Meanwhile, ferroelectrics can experience fatigue due to normal operations, such as read or write operations performed on memory cells. A ferroelectric in a fatigued state may reduce the capabilities of the memory cell, which may render the memory cell inoperable. Therefore, a method has been proposed to recover a ferroelectric memory device in a fatigued state by applying a wake-up pulse to increase the polarization characteristics of the ferroelectric. The problem to be solved

[0006] Embodiments of the present invention can provide a ferroelectric memory device capable of performing a recovery operation that increases the residual polarization of the ferroelectric by applying a unipolar wake-up pulse of a driving voltage level to the ferroelectric memory cells upon power-up. means of solving the problem

[0008] According to an embodiment of the present invention, a memory device may include: a memory cell array comprising a plurality of memory cells; a peripheral circuit that performs a normal operation of applying a driving voltage for reading or writing data stored in the memory cells and a recovery operation of applying a recovery voltage to increase the residual polarization of the memory cells; and a control logic that controls the peripheral circuit to perform the normal operation after performing the recovery operation upon power-up.

[0009] According to an embodiment of the present invention, a method of operating a memory device may include: a step of performing a recovery operation to increase the residual polarization of a plurality of memory cells upon power-up; and a step of performing a normal operation to apply a driving voltage to read or write data stored in the memory cells after the recovery operation. Effects of the invention

[0011] The ferroelectric memory device according to the proposed embodiment has the effect of ensuring the reliability of the memory device's operation by performing a recovery operation during initial operation and then performing a normal operation in a state where target characteristics can be secured.

[0012] The ferroelectric memory device according to the proposed embodiment has the effect of minimizing power consumption by performing a recovery operation using a unipolar wake-up pulse having a magnitude substantially equal to or lower than the magnitude of the driving voltage. In addition, since there is no need to generate a voltage greater than the magnitude of the driving voltage, a separate voltage generation circuit is not required, so an improvement in the integration density of the memory device can also be expected.

[0013] The ferroelectric memory device according to the proposed embodiment can utilize more charge as the up-state polarization available within the driving voltage range increases, thereby reducing failures caused by capacitor defects during wafer testing, improving yield, and increasing the durability and data retention time of the device.

[0014] In addition, the ferroelectric memory device according to the proposed embodiment can reduce the burden on the process and further ensure mass producibility by securing the desired capacitor capacity even in a ferroelectric memory device having a thinner dielectric film. Brief explanation of the drawing

[0016] Figures 1a and 1b are hysteresis loop characteristic diagrams of a ferroelectric material. FIG. 2 is a block diagram of a memory device according to an embodiment of the present invention. FIGS. 3a to 3d are drawings for explaining the configuration of the memory cell of FIG. 2. FIG. 4 is a flowchart for explaining the operation of a memory device according to an embodiment of the present invention. FIGS. 5A and 5B are hysteresis loop characteristic diagrams of a ferroelectric material according to an embodiment of the present invention. FIGS. 6a to 6d are waveform diagrams for explaining the recovery operation and normal operation of FIG. 4. FIG. 7 is an IV graph showing the polarization characteristics of a ferroelectric material by performing a recovery operation according to an embodiment of the present invention. FIGS. 8 and 9 are flowcharts for explaining the recovery operation of a memory device according to an embodiment of the present invention. FIG. 10 is a circuit diagram of a sensing amplifier circuit for performing a recovery operation according to a first embodiment of the present invention. FIGS. 11a to 11c are waveform diagrams for explaining the recovery operation using the sensing amplifier circuit of FIG. 10. FIG. 12 is a circuit diagram of a sensing amplifier circuit for performing a recovery operation according to a second embodiment of the present invention. FIGS. 13a to 13c are waveform diagrams for explaining the recovery operation using the sensing amplifier circuit of FIG. 12. FIGS. 14 and FIGS. 15 are flowcharts for explaining a recovery operation according to a third embodiment of the present invention. FIG. 16 is a block diagram of an information processing system to which a ferroelectric memory device according to an embodiment of the present invention is applied. Specific details for implementing the invention

[0017] Hereinafter, in order to provide a detailed explanation so that a person skilled in the art to which the present invention pertains can easily implement the technical concept of the present invention, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings.

[0019] FIG. 1a is a hysteresis loop characteristic of a ferroelectric in an initial state, and FIG. 1b is a hysteresis loop characteristic of a ferroelectric in a fatigue state. FIG. 1a and FIG. 1b show the amount of charge (Q) stored in a ferroelectric capacitor according to voltage (V).

[0020] Referring to Fig. 1a, the charge (Q) is proportional to the polarization of the ferroelectric material, and it can be seen that the polarization induced by the electric field is not extinguished even after the electric field is removed, but maintains a certain amount (states A and C) due to the presence of residual polarization or spontaneous polarization. Below, an example will be given where state A corresponds to a logic high level and state C corresponds to a logic low level.

[0021] A (+) voltage (V1) can be applied to the ferroelectric capacitor to charge it until it reaches state B. As the (+) voltage (V1) is removed, state B follows path (10) until it reaches state C, which corresponds to a logic low level. Likewise, a (-) voltage (V2) can be applied to the ferroelectric capacitor to charge it until it reaches state D. As the (-) voltage (V2) is removed, state D follows path (20) until it reaches state A, which corresponds to a logic high level. The charge states (states A and C) may also be referred to as residual polarization values, that is, the polarization (or charge) remaining when the external bias (e.g., voltage) is removed.

[0022] Meanwhile, residual polarization may decrease depending on the number of access operations (read or write operations, hereinafter referred to as normal operations) or operations applied to the ferroelectric memory cell, and accordingly, the ferroelectric material may enter a fatigue state.

[0023] Referring to Fig. 1b, the hysteresis loop of a ferroelectric in a fatigued state (solid line) is shown relative to the hysteresis loop of a ferroelectric in an initial state (dashed line). The hysteresis loop of a ferroelectric in a fatigued state has a lower remanent polarization (indicated as the charged state (A-1, C-1 state)) compared to the remanent polarization of the hysteresis loop of a ferroelectric in an initial state (i.e., indicated as the charged state (A, C state)).

[0024] That is, as normal operation is performed, that is, as fatigue accumulates in the ferroelectric memory cell, the two charge states (A-1 and C-1 states) of the ferroelectric hysteresis loop may continue to decrease in size. As a result, the difference between the two charge states (A-1 and C-1 states) decreases, and an error may occur in the sensing operation that detects the logic level of the data stored in the ferroelectric memory cell.

[0025] Therefore, a recovery operation to improve / restore residual polarization and increase stored charge can be performed on a ferroelectric in a fatigued state. For example, a wake-up pulse of a specific voltage level can be applied to a ferroelectric in a fatigued state to increase the residual polarization from a charged state (A-1, C-1 state) to a charged state (A, C state), respectively. That is, the hysteresis loop of the fatigued state can be restored to the hysteresis loop of the initial state.

[0026] On the other hand, when a bipolar pulse is used as a wake-up pulse, it is performed by applying a voltage greater than the conventional driving voltage range, resulting in high power consumption and degradation of the reliability of the cell capacitor's dielectric due to the application of high voltage. Furthermore, the increase in residual polarization through a ± 1V bipolar pulse is limited to about 50%, so it does not show a significant effect. In addition, when the goal is low-power operation, driving the pulse at a high voltage requires high power consumption, which significantly undermines the advantage of saving power by utilizing non-volatile memory devices.

[0027] Furthermore, hafnium oxide or zirconium oxide-based dielectric materials exhibit their strongest ferroelectric properties at the level of approximately 10 nm; at thicknesses below this, the ferroelectric properties weaken, leading to increased anti-dielectricity or pinched hysteresis, which is an intermediate state between ferroelectric and anti-dielectric. As the minimum feature size of memory continues to decrease, the thickness of integrable dielectric films is also becoming thinner. Consequently, it is becoming increasingly difficult to secure ferroelectric properties using hafnium oxide or zirconium oxide-based materials.

[0029] Hereinafter, with reference to the drawings, a method for performing a recovery operation in which a unipolar wake-up pulse of a driving voltage level is applied to ferroelectric memory cells upon power-up is described according to an embodiment of the proposed invention.

[0030] FIG. 2 is a block diagram of a memory device (100) according to an embodiment of the present invention.

[0031] Referring to FIG. 2, the memory device (100) may include a memory cell array (110), peripheral circuits (120), and control logic (130).

[0032] A memory cell array (110) may include a plurality of memory cells (MC). According to an embodiment, the plurality of memory cells may be non-volatile memory cells. In particular, the plurality of memory cells (MC) may be composed of ferroelectric memory cells. Since ferroelectric memory cells have a naturally occurring electric polarization, they may have a non-zero polarization even after the electric field is removed. The plurality of memory cells (MC) may be arranged in a matrix form between a plurality of rows (i.e., word lines (WL)) and a plurality of columns (i.e., bit lines (BL)). According to an embodiment, the plurality of rows may each consist of one word line and one plate line or source line.

[0033] The peripheral circuit (120) can drive the memory cell array (110) under the control of the control logic (130). For example, the peripheral circuit (120) can select specific memory cells of the memory cell array (110) by applying various voltages to the word lines (WL) and bit lines (BL) under the control of the control logic (130), and can perform normal operations such as read or write operations on the selected memory cells. That is, the normal operation may include an access operation that accesses the selected memory cells according to the driving voltage applied to the memory cells through the word lines (WL) and bit lines (BL) during the read or write operation.

[0034] Meanwhile, as described in FIGS. 1a and 1b, the polarization of a ferroelectric memory cell may decrease and the stored charge may decrease due to fatigue resulting from normal operations such as read or write operations. Accordingly, the peripheral circuit (120) may perform a recovery operation to increase the residual polarization of the ferroelectric memory cells by applying a recovery voltage to the memory cells (MC) through the word lines (WL) and / or bit lines (BL) of the memory cell array (110). In particular, in an embodiment of the present invention, the peripheral circuit (120) may perform a recovery operation before performing a normal operation upon power-up under the control of the control logic (130), and the amplitude of the recovery voltage used during the recovery operation may be substantially the same as or lower than the amplitude of the driving voltage applied to the memory cells (MC) during normal operations.

[0035] Meanwhile, before performing a recovery operation, the peripheral circuit (120) may perform a backup operation to write data previously stored in the memory cells (MC) of the memory cell array (110) to spare cells of another memory cell array under the control of the control logic (130). Additionally, after performing a recovery operation, the peripheral circuit (120) may perform a write-back operation to write the original data backed up to the spare cells of another memory cell array back to the memory cells (MC) of the memory cell array (110) under the control of the control logic (130).

[0036] More specifically, the peripheral circuit (120) may include a row control circuit (121), a sensing amplifier circuit (123), a column control circuit (125), and a data input / output circuit (127).

[0037] The row control circuit (121) can be connected to the memory cells (MC) of the memory cell array (110) through word lines (WL). The row control circuit (121) can operate in response to the control of the control logic (130). The row control circuit (121) can receive a row address (RADD), an active command (ACT), and a precharge command (PCG) from the control logic (130). The row control circuit (121) can decode the row address (RADD) to select one of the word lines (WL). The row control circuit (121) can activate the selected word line according to the active command (ACT) and deactivate the activated word line according to the precharge command (PCG). For example, the row control circuit (121) may apply a high voltage (VPP) higher than the power supply voltage (VDD) level to the selected word line to activate the word line. According to an embodiment, the row control circuit (121) may include an address buffer, a row decoder, a voltage generation circuit, etc. Meanwhile, the row control circuit (121) may additionally drive the source line or plate line of the memory cell array (110) under the control of the control logic (130).

[0038] The sensing amplifier circuit (123) can be connected to the memory cells (MC) of the memory cell array (110) via bit lines (BL). The sensing amplifier circuit (123) can operate in response to the control of the control logic (130). The sensing amplifier circuit (123) can receive a sensing control signal (SAEN) and a wake-up signal (WU_EN) from the control logic (130). The sensing amplifier circuit (123) may include a plurality of bit line sense amplifiers, each connected to a pair of bit lines (BL, BLB). Each bit line sense amplifier can detect and amplify the voltage difference between the corresponding main bit line (BL) and the subbit line (BLB) in response to the sensing control signal (SAEN). In particular, in an embodiment of the present invention, bit line sense amplifiers can each apply a recovery voltage to at least one bit line among the main bit line (BL) and the subbit line (BLB) in response to a wake-up signal (WU_EN).

[0039] The column control circuit (125) can operate in response to the control of the control logic (130). The column control circuit (125) can receive a column address (CADD) from the control logic (130). The column control circuit (125) can decode the column address (CADD) to select some bit lines among a plurality of bit lines (BL) and transfer data between the selected bit lines and the data input / output circuit (127). The column control circuit (125) can exchange data with the data input / output circuit (127) through data lines (DL). For example, the column control circuit (125) can transfer data read from the bit lines (BL) to the data input / output circuit (127) through the data lines (DL), or transfer data provided from the data input / output circuit (127) through the data lines (DL) to the bit lines (BL). According to an embodiment, the column control circuit (122) may include a column decoder.

[0040] The data input / output circuit (127) can exchange data with an external device (e.g., a memory controller or a test device) through a data pad (DQ). The data input / output circuit (127) can operate in response to the control of the control logic (130). The data input / output circuit (127) can receive a read command (RD) or a write command (WT) from the control logic (130). During a read operation, the data input / output circuit (127) can output data transmitted through the data lines (DL) to the data pad (DQ) in response to the read command (RD). During a write operation, the data input / output circuit (127) can receive data provided from an external device through the data pad (DQ) in response to the write command (WT).

[0041] The control logic (130) is configured to control the overall operation of the memory device (100). The control logic (130) can receive a command (CMD) and an address (ADDR) from an external device. Based on the command (CMD) and the address (ADDR), the control logic (130) can control the peripheral circuit (120) by generating a row address (RADD), a column address (CADD), an active command (ACT), a precharge command (PCG), a read command (RD), a write command (WT), a sensing control signal (SAEN), and a wake-up signal (WU_EN). The control logic (130) can buffer and decode the address (ADDR) and output it as a row address (RADD) and a column address (CADD). The control logic (130) can decode a command (CMD) to generate an active command (ACT), a precharge command (PCG), a read command (RD), a write command (WT), a sensing control signal (SAEN), and a wake-up signal (WU_EN). The control logic (130) can generate a sensing control signal (SAEN) that is activated in response to the active command (ACT) and deactivated in response to the precharge command (PCG). According to an embodiment of the present invention, the control logic (130) can generate a sensing control signal (SAEN) and a wake-up signal (WU_EN) that are activated for a predetermined period before normal operation upon power-up. According to an embodiment, the control logic (130) can control the wake-up signal (WU_EN) to pulse at least once.

[0043] FIGS. 3a to 3d are drawings for explaining the configuration of any one of the memory cells (MC) of FIG. 2.

[0044] Referring to FIG. 3a, the memory cell (MC) may be composed of one access transistor (T1) and one ferroelectric capacitor (C1). That is, each memory cell (MC) has a 1T / 1C configuration in which a cell storing 1 bit is composed of one transistor and one capacitor. The first electrode of the ferroelectric capacitor (C1) may be connected to a common plate. The access transistor (T1) may be connected between the second electrode of the ferroelectric capacitor (C1) and the bit line (BL), and its gate may be connected to the word line (WL).

[0045] A ferroelectric memory cell (MC) can store a logic state (i.e., data '1' or data '0') based on the electrical polarization of a ferroelectric capacitor (C1). Between the two electrodes of the ferroelectric capacitor (C1), a ferroelectric material based on silicon, hafnium oxide, zirconium oxide, and hafnium-zirconium oxide may be formed. Alternatively, between the two electrodes of the ferroelectric capacitor (C1), a ferroelectric material based on a perovskite-based piezoelectric material (e.g., BaTiO3, SrTiO3, PbZrTiO, etc.) may be formed. When a voltage is applied to the electrodes of the ferroelectric capacitor (C1) (e.g., a second electrode), the ferroelectric material is polarized in the direction of the electric field. The switching threshold for changing the polarization state of the ferroelectric capacitor (C1) is called the coercive voltage. The ferroelectric capacitor (C1) exhibits the hysteresis characteristics described in FIGS. 1a and 1b, and a current corresponding to the polarization state flows through the capacitor. If the voltage applied to the ferroelectric capacitor (C1) is greater than the coercive voltage, the ferroelectric capacitor (C1) changes its polarization states according to the polarity of the applied voltage. The polarization state of the ferroelectric capacitor (C1) remains unchanged even after the power supply is removed. Due to these polarization characteristics, the ferroelectric memory device exhibits characteristics as a non-volatile memory.

[0046] Referring to FIG. 3b, a memory cell (MC) may be composed of one access transistor (T2) and one ferroelectric capacitor (C2). As in FIG. 3a, each memory cell (MC) has a 1T / 1C configuration. The ferroelectric capacitor (C2) may have the same configuration as the ferroelectric capacitor (C1) in FIG. 3a. The access transistor (T2) may be connected between the second electrode of the ferroelectric capacitor (C2) and the bit line (BL), so that its gate may be connected to the word line (WL). The first electrode of the ferroelectric capacitor (C2) may be connected to the plate line (PL). In this case, the row control circuit (121) can control a row line composed of the word line (WL) and the plate line (PL) per memory cell. The memory cells (MC) illustrated in FIG. 3b may have an array form in which they have independent plates but are connected through plate lines (PL).

[0047] Referring to FIG. 3c, the memory cell (MC) may be configured as a single transistor (T3) connected between the source line (SL) and the bit line (BL), with the gate connected to the word line (WL). In this case, a ferroelectric material may be used as the dielectric material of the gate of the memory cell (MC). The ferroelectric material may have the same configuration as the ferroelectric material of the ferroelectric capacitor (C1) of FIG. 3a.

[0048] Referring to FIG. 3d, the memory cell (MC) may be configured as a single transistor (T4) connected between the source line (SL) and the bit line (BL), with the gate connected to the word line (WL). At this time, the gate of the transistor (T4) may include a floating gate electrode (Gf), a dielectric material (Ff), and a control gate electrode (Gc), and a ferroelectric material may be used as the dielectric material. The dielectric material (Ff) may have the same configuration as the ferroelectric material of the ferroelectric capacitor (C1) of FIG. 3a.

[0050] FIG. 4 is a flowchart for explaining the operation of a memory device (100) according to an embodiment of the present invention.

[0051] Referring to FIG. 4, the memory device (100) can be initialized upon power-up (S410). Since the memory device (100) has a non-volatile characteristic in which data is preserved even when the power is off, the memory device (100) may be in a fatigued state upon power-up.

[0052] After this, the memory device (100) can perform a recovery operation by applying a recovery voltage to increase the residual polarization of the ferroelectric memory cells (S420).

[0053] The memory device (100) can perform a recovery operation using a recovery voltage having a magnitude substantially equal to or lower than the magnitude of the driving voltage applied to the memory cells (MC) during a read or write operation. For example, the recovery voltage is a voltage applied to the ferroelectrics of the memory cells and may include a voltage (or potential difference) applied between the two electrodes of the ferroelectric capacitors (C1, C2) of FIG. 3a and 3b, a voltage applied to the gate of the single transistor (T3) of FIG. 3c, and a voltage applied to the floating gate (Gf) of the single transistor (T4) of FIG. 3d. That is, in an embodiment of the present invention, the recovery voltage may be applied to the ferroelectrics of the memory cells through a bit line. Preferably, the recovery voltage may include a unipolar wake-up pulse. According to an embodiment, the recovery voltage may be composed of a one-time unipolar wake-up pulse. That is, the recovery voltage can pulse once at a constant voltage during the recovery operation period with a unipolar wake-up pulse. At this time, the pulse width of the recovery voltage can be wider than the pulse width of the driving voltage during normal operation.

[0054] After this, the memory device (100) can perform normal operations such as read operations or write operations (S430).

[0055] During a read operation, the memory device (100) can select one of a plurality of word lines (WL) according to a row address (RADD) and activate the selected word line. Afterward, the bit line sense amplifiers of the memory device (100) can detect and amplify the voltage difference between the memory cells connected to the activated word line and the bit line pairs (BL, BLB) connected thereto in response to a sensing control signal (SAEN). The memory device (100) can output data transmitted from the bit lines selected according to a column address (CADD) to an external device through a data pad (DQ) according to a read command (RD).

[0056] When a write operation is performed, the memory device (100) can select one of a plurality of word lines (WL) according to a row address (RADD) and activate the selected word line. The memory device (100) can receive data provided from an external device through a data pad (DQ) in response to a write command (WT) and transmit it to bit lines selected according to a column address (CADD). Bit line sense amplifiers can detect and amplify data applied to bit line pairs (BL, BLB) in response to a sensing control signal (SAEN) and write it to memory cells connected to the activated word line.

[0057] During a read or write operation, the memory device (100) may apply a high voltage (VPP) to the word line to activate the word line, and apply a ground voltage (VSS) or a low voltage (VBB) to the word line to deactivate the word line. Additionally, the memory device (100) may provide a bit line precharge voltage (VBLP), a core voltage (VCORE), and a ground voltage (VSS) as operating voltages to the bit line sense amplifiers. According to an embodiment, the memory device (100) may provide a power supply voltage (VDD) instead of a core voltage (VCORE) having a voltage level lower than that of the power supply voltage (VDD). As described above, during a read or write operation, the memory device (100) may apply driving voltages such as a high voltage (VPP), a power supply voltage (VDD), a core voltage (VCORE), a bit line precharge voltage (VBLP), a ground voltage (VSS), and a low voltage (VBB) to the memory cells.

[0059] FIGS. 5A and 5B are hysteresis loop characteristic diagrams of a ferroelectric material according to an embodiment of the present invention.

[0060] Referring to Fig. 5a, the hysteresis loop characteristics of the ferroelectric material after performing a recovery operation (S420) are illustrated. As shown in Fig. 5a, the hysteresis loop of the ferroelectric material after performing a recovery operation (solid line) is illustrated in contrast to the hysteresis loop of the ferroelectric material in the initial state (dashed line). The hysteresis loop of the ferroelectric material after performing a recovery operation has a higher residual polarization (indicated as the charge state (A-2, C-2 state)) compared to the residual polarization of the ferroelectric material's hysteresis loop in the initial state (i.e., indicated as the charge state (A, C state)).

[0061] Referring to FIG. 5b, the hysteresis loop characteristics of the ferroelectric material after normal operation (S430) are illustrated. As shown in FIG. 5b, fatigue accumulates in the ferroelectric memory cell as normal operation is performed. Accordingly, the two charge states (A-2, C-2 states) of the ferroelectric hysteresis loop can continue to decrease in size.

[0062] However, according to an embodiment of the proposed invention, residual polarization can be increased in advance by performing a recovery operation before normal operation. In this state, even if the residual polarization decreases as normal operation is performed, the margin of the sensing operation is secured due to the previously increased residual polarization, thereby improving operational reliability.

[0064] FIGS. 6a to 6d are waveform diagrams for explaining the recovery operation and normal operation of FIG. 4. FIGS. 6a to 6d illustrate the potential difference between the two electrodes of the ferroelectric material of the memory cell during the recovery operation and normal operation.

[0065] Referring to FIGS. 6a and 6b, during a recovery operation (S420-1), a one-time unipolar wake-up pulse may be applied to the memory cell as a recovery voltage. In this case, a (+) or (-) potential difference may be generated between the two electrodes of the ferroelectric material of the memory cell. The wake-up pulse may consist of a time taken to reach a target voltage level (or potential difference) (T1, i.e., Rising Time), a time maintained at the target voltage level (or potential difference) (T2, i.e., Pulse Width), and a time taken to reach a ground voltage level from the target voltage level (or potential difference) (T3, i.e., Falling Time). The pulse maintained time (T2) may be determined by considering the characteristics of the ferroelectric material. For example, considering the pinched hysteresis characteristics of a 5 nm hafnium zirconium oxide-based ferroelectric, the pulse width can be configured to be at least 10 us.

[0066] Afterwards, during normal operation (S430-1), read or write operations can be performed using driving voltages such as high voltage (VPP), power supply voltage (VDD), core voltage (VCORE), bit line precharge voltage (VBLP), ground voltage (VSS), and low voltage (VBB). Accordingly, a (+) or (-) potential difference may be generated between the two electrodes of the ferroelectric material of the memory cell. As shown in FIGS. 6a and 6b, the pulse size of the wake-up pulse applied during recovery operation may be equal to or smaller than the pulse size of the driving voltage applied during normal operation. Additionally, the pulse width of the wake-up pulse (i.e., the pulse holding period (T2)) may have a wider width than the pulse width of the driving voltage applied during normal operation.

[0067] Referring to FIGS. 6c and 6d, during the recovery operation (S420-2), multiple-time unipolar wake-up pulses may be applied to the memory cell as a recovery voltage. In this case, a (+) or (-) potential difference may occur between the two electrodes of the ferroelectric material of the memory cell. The number of pulsings of the wake-up pulses may be determined according to the pulse width (i.e., pulse holding period (T2)) of the one-time unipolar wake-up pulses of FIGS. 6a and 6b.

[0068] Afterwards, during normal operation (S430-2), read or write operations can be performed using driving voltages such as high voltage (VPP), power supply voltage (VDD), core voltage (VCORE), bit line precharge voltage (VBLP), ground voltage (VSS), and low voltage (VBB). Accordingly, a (+) or (-) potential difference may be generated between the two electrodes of the ferroelectric material of the memory cell. As shown in FIGS. 6c and 6d, the pulse size of the wake-up pulse applied during recovery operation may be equal to or smaller than the pulse size of the driving voltage applied during normal operation.

[0069] As described above, in an embodiment of the proposed invention, the magnitude of the potential difference between the two electrodes of the ferroelectric material during recovery operation may be substantially the same as or lower than the magnitude of the potential difference between the two electrodes of the ferroelectric material during normal operation. Therefore, power consumption due to recovery operation can be minimized, and since a separate voltage generation circuit to generate a voltage greater than the driving voltage is not required, an improvement in the integration density of the memory device can also be expected.

[0071] FIG. 7 is an IV graph showing the polarization characteristics of a ferroelectric material according to the performance of a recovery operation according to an embodiment of the present invention.

[0072] Referring to Fig. 7, it can be seen that when a single unipolar wake-up pulse is applied during recovery operation, the peak current associated with the up-state shifts to the left, increasing the responsive polarization from 0 to VDD / 2. In particular, it can be seen that the non-switching current decreases as the current going from the up-state to the non-polar state (0) mostly occurs only in negative bias. As described above, the polarization can increase by more than twofold as the two phenomena interact in combination.

[0073] Accordingly, the ferroelectric memory device according to an embodiment of the present invention can utilize more charge as the up-state polarization available within the driving voltage range increases, thereby increasing the durability and data retention time of the device. In addition, by securing the desired capacitor capacity even in a ferroelectric memory device with a thinner dielectric film, the burden on the process can be reduced and mass producibility can be further secured.

[0075] Hereinafter, the recovery operation according to an embodiment of the present invention will be described in detail.

[0076] FIGS. 8 and FIGS. 9 are flowcharts for explaining the recovery operation of a memory device (100) according to an embodiment of the present invention.

[0077] Referring to FIG. 8, the memory device (100) can perform a backup operation (S710) of writing data previously stored in memory cells (MC) of a memory cell array (110) to spare cells of another memory cell array. The backup operation can be performed to back up the data previously stored in memory cells (MC) because the data is destroyed during a subsequent recovery voltage application operation (S720). During the backup operation, the data previously stored in memory cells (MC) can be read out through a read operation, and the read-out data can be written to spare cells of another memory cell array through a write operation.

[0078] When the backup operation is completed, the memory device (100) can perform a recovery voltage application operation to apply a recovery voltage to the ferroelectric of the memory cells (MC) through the bit line (S720).

[0079] More specifically, referring to FIG. 9, the control logic (130) may provide a row address (RADD) along with an active command (ACT) to the row control circuit (121). The row control circuit (121) may select a specific word line (e.g., a first word line) according to the row address (RADD) and activate the selected word line according to the active command (ACT) (S721). The row control circuit (121) may apply a high voltage (VPP) higher than the power supply voltage (VDD) level to the word line to activate the selected word line.

[0080] During a recovery operation, the control logic (130) can provide a sensing control signal (SAEN) and a wake-up signal (WU_EN) to the sensing amplifier circuit (123). Each bit line sense amplifier of the sensing amplifier circuit (123) can detect and amplify the voltage difference between the bit line pairs (BL, BLB) of memory cells connected to the activated word line in response to the sensing control signal (SAEN). In particular, in an embodiment of the present invention, each bit line sense amplifier can apply a recovery voltage to memory cells connected to the activated word line through at least one bit line among the main line (BL) and the sub-bit line (BLB) of the bit line pair (BL, BLB) in response to the wake-up signal (WU_EN) (S722). At this time, the column control circuit (125) can sequentially increase the column address (CADD) until it becomes an all-high bit and provide it to the column control circuit (125). Accordingly, each bit line sense amplifier can apply a recovery voltage to all memory cells connected to the active word line. According to an embodiment, the recovery voltage may be applied only to selected memory cells without applying a recovery voltage to all memory cells connected to the active word line.

[0081] After the above operation (S722) is performed on all memory cells connected to the activated word line, the control logic (130) can select the next word line by providing the row address (RADD) along with the active command (ACT) to the row control circuit (121) (S724). Likewise, the row control circuit (121) can select the next word line (e.g., a second word line) according to the row address (RADD) and activate the selected word line according to the active command (ACT) (S721). Each bit line sense amplifier can apply a recovery voltage to the memory cells connected to the activated word line through at least one bit line among the main bit line (BL) and the subbit line (BLB) of the bit line pair (BL, BLB) in response to the wake-up signal (WU_EN) (S722).

[0082] Until the activated word line reaches the last word line (NO of S723), the peripheral circuit (120) repeats the above operations (S721–723) so that a recovery voltage can be applied to the ferroelectrics of the memory cells through the bit line.

[0083] Referring again to FIG. 8, the memory device (100) can perform a write-back operation to write original data backed up in spare cells of another memory cell array back to the memory cells (MC) of the memory cell array (110) (S730). During the write-back operation, data previously stored in spare cells of another memory cell array can be read out through a read operation, and the read-out data can be written to the memory cells (MC) through a write operation.

[0084] Accordingly, the recovery operation of the memory device (100) can be completed.

[0086] Hereinafter, the configuration of a specific sensing amplifier circuit (123) for performing a recovery operation according to an embodiment of the present invention will be discussed. In the following embodiments, the case in which bit line sense amplifiers are provided with a power supply voltage (VDD) and a ground voltage (VSS) as operating voltages will be described as an example.

[0087] FIG. 10 is a circuit diagram of the sensing amplifier circuit (123) of FIG. 2 for performing a recovery operation according to the first embodiment of the present invention. FIG. 10 shows the configuration of the sensing amplifier circuit (123) and the column control circuit (125) connected to one bit line pair (BL, BLB).

[0088] Referring to FIG. 10, the sensing amplifier circuit (123) may include a sensing control circuit (210), a bit line sense amplifier (220), a voltage supply circuit (230), a precharge circuit (240), and a recovery bias circuit (250).

[0089] The sensing control circuit (210) can generate a pull-up control signal (SAP), a pull-down control signal (SAN), and an equalization signal (BLEQ) in response to a sensing control signal (SAEN). The sensing control circuit (210) can activate the pull-up control signal (SAP) and the pull-down control signal (SAN) according to the activation of the sensing control signal (SAEN), and can deactivate the pull-up control signal (SAP) and the pull-down control signal (SAN) according to the deactivation of the sensing control signal (SAEN). Additionally, the sensing control circuit (210) can deactivate the equalization signal (BLEQ) according to the activation of the sensing control signal (SAEN), and can activate the equalization signal (BLEQ) according to the deactivation of the sensing control signal (SAEN).

[0090] The bit line sense amplifier (220) can detect and amplify data of bit line pairs (BL, BLB) using a pull-up driving voltage supplied to a pull-up power line (RTO) and a pull-down driving voltage supplied to a pull-down power line (SB). When a word line (WL) is activated, data stored in a memory cell (MC) connected to the activated word line is transmitted to the junction line (BL), and the bit line sense amplifier (220) can detect and amplify the data of the memory cell (MC) transmitted through the junction line (BL). The bit line sense amplifier (220) may be configured as an amplification circuit comprising a cross-coupled latch including a plurality of PMOS transistors (e.g., a pair of PMOS transistors) and a plurality of NMOS transistors (e.g., a pair of NMOS transistors). The bit line sense amplifier (220) can detect and amplify the voltage of the bit line pair (BL, BLB) connected to the differential input terminal using the pull-up driving voltage supplied to the pull-up power line (RTO) and the pull-down driving voltage supplied to the pull-down power line (SB).

[0091] The voltage supply circuit (230) can supply the power supply voltage (VDD) as a pull-up driving voltage to the pull-up power line (RTO) in response to the pull-up control signal (SAP), and supply the ground voltage (VSS) as a pull-down driving voltage to the pull-down power line (SB) in response to the pull-down control signal (SAN). For example, the voltage supply circuit (230) may include a first transistor (M1) connected between the power supply voltage (VDD) terminal and the pull-up power line (RTO) and receiving the pull-up control signal (SAP) as a gate, and a second transistor (M2) connected between the ground voltage (VSS) terminal and the pull-down power line (SB) and receiving the pull-down control signal (SAN) as a gate.

[0092] The precharge circuit (240) can precharge the rect line (BL) and the subbit line (BLB) to a bit line precharge voltage (VBLP) in response to an equalization signal (BLEQ). Preferably, the bit line precharge voltage (VBLP) can be half the level (VDD / 2) of the power supply voltage (VDD). For example, the precharge circuit (240) may be composed of a third transistor (M3) connected between the rect line (BL) and the subbit line (BLB), a fourth transistor (M4) connected between the bit line precharge voltage (VBLP) terminal and the rect line (BL), and a fifth transistor (M5) connected between the bit line precharge voltage (VBLP) terminal and the subbit line (BLB), and the third to fifth transistors (M3 to M5) may receive the equalization signal (BLEQ) as input to their gates.

[0093] The recovery bias circuit (250) can apply a recovery voltage (VWU) to the fixed line (BL) according to the wake-up signal (WU_EN). For example, the recovery bias circuit (250) may include a sixth transistor (M6) connected between the fixed line (BL) and the recovery voltage (VWU) terminal, which receives the wake-up signal (WU_EN) as input to its gate. Preferably, the recovery voltage (VWU) may have a level that is a predetermined level greater or smaller than the bit line precharge voltage (VBLP). In this case, the predetermined level may correspond to the minimum voltage difference between the bit line pair (BL, BLB) to which the bit line sense amplifier (220) can detect and amplify data.

[0094] The column control circuit (125) may include a column decoder (not shown) that decodes a column address (CADD) to generate a column selection signal (Yi). Additionally, the column control circuit (125) may further include an eighth transistor (M8) connected between a positive bit line (BL) and a positive data line (DL) and receiving a column selection signal (Yi) as a gate, and a ninth transistor (M9) connected between a negative bit line (BLB) and a negative data line (DLB) and receiving a column selection signal (Yi) as a gate.

[0095] Meanwhile, in the case of the sensing amplifier circuit (123) of FIG. 10, the memory cells (MC) of the memory cell array (110) may share a common plate. That is, each memory cell (MC) may include an access transistor (T1) connected between a ferroelectric capacitor (C1) whose first electrode shares a common plate and a second electrode (BL) corresponding to the ferroelectric capacitor (C1), as shown in FIG. 3a, and to which a word line corresponding to the gate is connected.

[0097] FIGS. 11a to 11c are waveform diagrams for explaining a recovery operation using the sensing amplifier circuit (123) of FIG. 9.

[0098] Referring to Fig. 11a, a typical bit line sensing operation is illustrated.

[0099] Before the bit line sensing operation, the equalization signal (BLEQ) is activated to a logic high level, and accordingly, the main line (BL) and the sub-bit line (BLB) are precharged to the bit line precharge voltage (VBLP). During the initial period of the bit line sensing operation, the word line (WL) is activated as a high voltage (VPP) is applied. Charge sharing occurs between the main line (BL) and the sub-bit line (BLB), resulting in a minute voltage difference. Subsequently, as the power supply voltage (VDD) and the ground voltage (VSS) are applied to the pull-up power line (RTO) and the pull-down power line (SB), respectively, the bit line sense amplifier (220) can detect and amplify the voltage difference between the main line (BL) and the sub-bit line (BLB). As a result, the main line (BL) reaches the power supply voltage (VDD) level and the sub-bit line (BLB) becomes the ground voltage (VSS) level, allowing logic high level data to be written to the memory cell (MC).

[0100] Referring to Fig. 11b, a case is illustrated in which a recovery voltage (VWU) greater than half the level (VDD / 2) of the power supply voltage (VDD) is applied, which is the bit line precharge voltage (VBLP).

[0101] Before the recovery operation, the equalization signal (BLEQ) is activated to a logic high level, and accordingly, the rect line (BL) and the subbit line (BLB) are precharged to the bit line precharge voltage (VBLP). During the recovery operation, as the wake-up signal (WU_EN) is activated, the recovery bias circuit (250) can apply a recovery voltage (VWU) having a voltage level greater than the bit line precharge voltage (VBLP) to the rect line (BL). Subsequently, the word line (WL) is activated as the high voltage (VPP) is applied. Charge sharing occurs between the rect line (BL) and the subbit line (BLB), resulting in a minute voltage difference. Subsequently, as the power supply voltage (VDD) and ground voltage (VSS) are applied to the pull-up power line (RTO) and pull-down power line (SB), respectively, the bit line sense amplifier (220) can detect and amplify the voltage difference between the main line (BL) and the sub-bit line (BLB).

[0102] That is, regardless of whether the data stored in the memory cell (MC) is at a logic high level or a low level, when the recovery voltage (VWU) is greater than the bit line precharge voltage (VBLP), the recovery voltage (VWU) is applied to the fixed line (BL), and the logic high level data can be written to the memory cell (MC). FIG. 11b illustrates a case where the wake-up signal (WU_EN) pulses once, but the proposed invention is not limited thereto. As the wake-up signal (WU_EN) pulses a predetermined number of times, the recovery voltage (VWU) can be repeatedly applied to the memory cell (MC) through the fixed line (BL). For reference, when a recovery voltage (VWU) greater than the bit line precharge voltage (VBLP) is applied, as shown in FIG. 6a and FIG. 6c, a (+) potential difference may occur between the two electrodes of the ferroelectric material of the memory cell during the recovery operation.

[0103] Referring to Fig. 11c, a case is illustrated in which a bit line precharge voltage (VBLP), that is, a recovery voltage (VWU) smaller than half the level (VDD / 2) of the power supply voltage (VDD), is applied.

[0104] Before the recovery operation, the equalization signal (BLEQ) is activated to a logic high level, and accordingly, the rect line (BL) and the subbit line (BLB) are precharged to the bit line precharge voltage (VBLP). During the recovery operation, as the wake-up signal (WU_EN) is activated, the recovery bias circuit (250) can apply a recovery voltage (VWU) having a voltage level lower than the bit line precharge voltage (VBLP) to the rect line (BL). Subsequently, the word line (WL) is activated as the high voltage (VPP) is applied. Charge sharing occurs between the rect line (BL) and the subbit line (BLB), resulting in a minute voltage difference. Subsequently, as the power supply voltage (VDD) and ground voltage (VSS) are applied to the pull-up power line (RTO) and pull-down power line (SB), respectively, the bit line sense amplifier (220) can detect and amplify the voltage difference between the main line (BL) and the sub-bit line (BLB).

[0105] That is, regardless of whether the data stored in the memory cell (MC) is at a logic high level or a low level, if the recovery voltage (VWU) is smaller than the bit line precharge voltage (VBLP), the recovery voltage (VWU) is applied to the fixed line (BL), and the logic low level data can be written to the memory cell (MC). FIG. 11c illustrates a case where the wake-up signal (WU_EN) pulses once, but the proposed invention is not limited thereto. As the wake-up signal (WU_EN) pulses a predetermined number of times, the recovery voltage (VWU) can be repeatedly applied to the memory cell (MC) through the fixed line (BL). For reference, when a recovery voltage (VWU) smaller than the bit line precharge voltage (VBLP) is applied, as shown in FIG. 6b and FIG. 6d, a (-) potential difference may occur between the two electrodes of the ferroelectric material of the memory cell during the recovery operation.

[0107] FIG. 12 is a circuit diagram of a sensing amplifier circuit (123) for performing a recovery operation according to a second embodiment of the present invention. FIG. 12 shows the configuration of a sensing amplifier circuit (123) and a column control circuit (125) connected to one bit line pair (BL, BLB).

[0108] Referring to FIG. 12, the sensing amplifier circuit (123) may include a sensing control circuit (310), a bit line sense amplifier (320), a voltage supply circuit (330), a precharge circuit (340), and a recovery bias circuit (350). Since the sensing control circuit (310), bit line sense amplifier (320), voltage supply circuit (330), and precharge circuit (340) of FIG. 12 are substantially the same as the configurations of FIG. 10, a detailed description is omitted.

[0109] The sensing amplifier circuit (123) of FIG. 12 can be applied to a scheme that performs bit line sensing operations by utilizing a reference voltage (VREF) having a voltage level between the bit line precharge voltage (VBLP) and the ground voltage (VSS). The recovery bias circuit (350) can receive a first control signal (ENL) for charging the main bit line (BL) to the reference voltage (VREF) and a second control signal (ENR) for charging the subbit line (BLB) to the reference voltage (VREF). For example, the first control signal (ENL) and the second control signal (ENR) can be provided separately from the control logic (130) of FIG. 2.

[0110] The recovery bias circuit (350) may include 10 to 13 transistors (M10 to M13). The 10th transistor (M10) is connected between the rect line (BL) and the reference voltage (VREF) terminal to receive a first control signal (ENL) as input to its gate. The 11th transistor (M11) is connected between the boobit line (BLB) and the reference voltage (VREF) terminal to receive a second control signal (ENR) as input to its gate. The 12th transistor (M12) is connected between the rect line (BL) and the ground voltage (VSS) terminal to receive a second control signal (ENR) as input to its gate. The 13th transistor (M13) is connected between the boobit line (BLB) and the ground voltage (VSS) terminal to receive a first control signal (ENL) as input to its gate.

[0111] With the above configuration, during normal operation, the recovery bias circuit (350) can charge the rect line (BL) to a reference voltage (VREF) and discharge the rect line (BLB) to a ground voltage (VSS) in response to a first control signal (ENL). Additionally, the recovery bias circuit (350) can charge the rect line (BLB) to a reference voltage (VREF) and discharge the rect line (BL) to a ground voltage (VSS) in response to a second control signal (ENR). During normal operation, the reference voltage (VREF) may have a voltage level between the bit line precharge voltage (VBLP) and the ground voltage (VSS).

[0112] Meanwhile, in the second embodiment of the proposed invention, during a recovery operation, the recovery bias circuit (350) may receive a wake-up signal (WU_EN) as a second control signal (ENR). When the wake-up signal (WU_EN) is activated during a recovery operation, the 11th transistor (M11) may turn on to apply a reference voltage (VREF) to the boobit line (BLB), and the 12th transistor (M12) may turn on to apply a ground voltage (VSS) to the rect line (BL). At this time, the reference voltage (VREF) and the ground voltage (VSS) may be used as recovery voltages. That is, the recovery bias circuit (350) may apply a reference voltage (VREF) to the boobit line (BLB) and apply a ground voltage (VSS) to the rect line (BL) according to the wake-up signal (WU_EN). During recovery operation, the reference voltage (VREF) can have a power supply voltage (VDD) level or a ground voltage (VSS) level.

[0113] Meanwhile, in the case of the sensing amplifier circuit (123) of FIG. 12, the memory cells (MC) of the memory cell array (110) may have independent plates and may have an array form connected through plate lines (PL). That is, each memory cell (MC) may include a ferroelectric capacitor (C2) in which a first electrode shares an individual plate line (PL), as shown in FIG. 3b, and an access transistor (T2) in which a word line corresponding to a gate is connected between a bit line (BL) corresponding to a second electrode of the ferroelectric capacitor (C2).

[0115] FIGS. 13a to 13c are waveform diagrams for explaining a recovery operation using the detection amplification circuit (123) of FIG. 12.

[0116] Referring to Fig. 13a, a typical bit line sensing operation is illustrated.

[0117] Before the bit line sensing operation, the equalization signal (BLEQ) is activated to a logic high level, and accordingly, the main bit line (BL) and the secondary bit line (BLB) are precharged to the bit line precharge voltage (VBLP). During the initial period of the bit line sensing operation, if the second control signal (ENR) is activated before the word line (WL) is activated, the eleventh transistor (M11) is turned on to apply a reference voltage (VREF) to the secondary bit line (BLB), and the twelfth transistor (M12) is turned on to apply a ground voltage (VSS) to the main bit line (BL). At this time, the reference voltage (VREF) may have a voltage level between the bit line precharge voltage (VBLP) and the ground voltage (VSS).

[0118] Afterward, when the word line (WL) is activated as high voltage (VPP) is applied, the charge in the memory cell (MC) is transferred through the rect line (BL), and the voltage of the rect line (BL) becomes a level higher than the voltage of the subbit line (BLB). Accordingly, charge sharing occurs between the rect line (BL) and the subbit line (BLB), resulting in a minute voltage difference. As the power supply voltage (VDD) and the ground voltage (VSS) are applied to the pull-up power line (RTO) and the pull-down power line (SB), respectively, the bit line sense amplifier (320) can detect and amplify the voltage difference between the rect line (BL) and the subbit line (BLB). Consequently, the rect line (BL) reaches the power supply voltage (VDD) level, and the subbit line (BLB) becomes the ground voltage (VSS) level, allowing logic high level data to be written to the memory cell (MC).

[0119] Referring to Fig. 13b, the reference voltage (VREF) is set to the ground voltage (VSS) level, and during recovery operation, the maintenance line (BL) is always sensed only at the power voltage (VDD) level.

[0120] Before the recovery operation, the equalization signal (BLEQ) is activated to a logic high level, and accordingly, the main bit line (BL) and the subbit line (BLB) are precharged to the bit line precharge voltage (VBLP).

[0121] When a recovery operation is performed, as the second control signal (ENR) is activated, the recovery bias circuit (350) can apply a ground voltage (VSS) to the rect line (BL) and apply a reference voltage (VREF) at the ground voltage (VSS) level to the subbit line (BLB). Subsequently, when the word line (WL) is activated as a high voltage (VPP) is applied, the charge in the memory cell (MC) is transferred through the rect line (BL), and the voltage of the rect line (BL) becomes a level higher than the voltage of the subbit line (BLB). Accordingly, charge sharing occurs between the rect line (BL) and the subbit line (BLB), resulting in a minute voltage difference. Subsequently, as the power supply voltage (VDD) and ground voltage (VSS) are applied to the pull-up power line (RTO) and pull-down power line (SB), respectively, the bit line sense amplifier (320) can detect and amplify the voltage difference between the main bit line (BL) and the subbit line (BLB).

[0122] That is, as the reference voltage (VREF) at the ground voltage (VSS) level is applied to the subbit line (BLB), logic high level data can be written to the memory cell (MC). FIG. 13a illustrates a case where the second control signal (ENR) pulses once, but the proposed invention is not limited thereto. As the second control signal (ENR) pulses a predetermined number of times, logic high level data can be repeatedly written to the memory cell (MC).

[0123] Referring to Fig. 13c, the reference voltage (VREF) is set to the power voltage (VDD) level, and during recovery operation, the maintenance line (BL) is always sensed only at the ground voltage (VSS) level.

[0124] Before the recovery operation, the equalization signal (BLEQ) is activated to a logic high level, and accordingly, the main bit line (BL) and the subbit line (BLB) are precharged to the bit line precharge voltage (VBLP).

[0125] When the recovery operation is performed, as the second control signal (ENR) is activated, the recovery bias circuit (350) can apply a ground voltage (VSS) to the rect line (BL) and apply a reference voltage (VREF) at the power supply voltage (VDD) level to the boobit line (BLB). Accordingly, the rect line (BL) is lowered to the ground voltage (VSS) level, and the boobit line (BLB) is raised to the power supply voltage (VDD) level. Subsequently, when the word line (WL) is activated as the high voltage (VPP) is applied, the rect line (BL) has a lower voltage level than the boobit line (BLB), even if the charge in the memory cell (MC) is transferred through the rect line (BL). Subsequently, as the power supply voltage (VDD) and ground voltage (VSS) are applied to the pull-up power line (RTO) and pull-down power line (SB), respectively, the bit line sense amplifier (320) can detect and amplify the voltage difference between the main bit line (BL) and the subbit line (BLB).

[0126] That is, as the reference voltage (VREF) of the power supply voltage (VDD) level is applied to the subbit line (BLB), logic low level data can be written to the memory cell (MC). FIG. 13b illustrates a case where the second control signal (ENR) pulses once, but the proposed invention is not limited thereto. As the second control signal (ENR) pulses a predetermined number of times, logic low level data can be repeatedly written to the memory cell (MC).

[0128] Meanwhile, in the first and second embodiments, a method using a sensing amplifier circuit (123) to apply a recovery voltage to a memory cell through a bit line was described as an example. Below, a recovery operation using a test pattern input from an external test device during a burn-in test operation will be described.

[0129] Problems of performance degradation may occur due to various factors, such as variations in the process of the semiconductor memory device or variations in signals provided to various circuits for operating the semiconductor memory device. Therefore, the semiconductor memory device can test for manufacturing defects or discrepancies between design and function through a wafer burn-in test. When entering the wafer burn-in test mode, the memory device (100) can simultaneously turn on the cell transistors of the memory cells, write a test pattern provided from an external test device to all memory cells, and then read them out again to verify within a short period of time whether they are operating normally.

[0130] FIGS. 14 and FIGS. 15 are flowcharts for explaining a recovery operation according to a third embodiment of the present invention.

[0131] Referring to FIG. 14, the memory device (100) can enter a burn-in test mode (S1310). To enter the burn-in test mode, a test mode signal may be provided from an external test device to the control logic (130) of the memory device (100), or a test mode signal may be generated in the internal control logic (130).

[0132] When entering burn-in test mode, the control logic (130) may provide a row address (RADD) and an active command (ACT) for selecting memory cells (MC) to the row control circuit (121), provide a sensing control signal (SAEN) to the sensing amplifier circuit (123), and provide a column address (CADD) to the column control circuit (125). Additionally, the control logic (130) may provide a write command (WT) for receiving a test pattern provided from an external test device to the data input / output circuit (127). Additionally, when entering burn-in test mode, the control logic (130) may control the row control circuit (121) so that a plate voltage different from normal operation is applied to the plate line or common plate, or a source voltage different from normal operation is applied to the source line.

[0133] The memory device (100) can perform a recovery voltage application operation to apply a recovery voltage to the ferroelectric material of the memory cells (MC) through the bit lines (BL) (S1320). When the recovery voltage application operation is performed, the control logic (130) can control the peripheral circuit (120) so that a test pattern input through the wafer burn-in device is written to the memory cells (MC). For example, the row control circuit (121) selects and activates the word lines (WL) according to the row address (RADD) and active command (ACT), the column control circuit (125) connects the bit lines (BL) to the data line (DL) according to the column address (CADD), and the sensing amplifier circuit (123) can write the test pattern transmitted through the bit lines (BL) to the memory cells (MC) according to the sensing control signal (SAEN). Preferably, a recovery operation can be performed by applying a unipolar wake-up pulse to memory cells (MC) by writing a test pattern of all-high data or all-low data.

[0134] After all recovery operations have been performed, the memory device (100) can terminate the recovery operations by exiting the burn-in test mode (S1330).

[0135] Meanwhile, according to an embodiment, in a burn-in test mode, the memory device (100) can divide a plurality of word lines (WL) into even word lines and odd word lines, write a test pattern to memory cells (MC) connected to the even word lines, and then write a test pattern to memory cells (MC) connected to the odd word lines.

[0136] Referring to FIG. 15, the low control circuit (121) can select and activate the even word lines by applying a high voltage (VPP) level to the even word lines (S1321). The sensing amplifier circuit (123) can write logic high level or logic low level data to all memory cells (MC) connected to the even word lines by transmitting a test pattern transmitted through the data line (DL) to the bit lines (BL) (S1322). Accordingly, a recovery operation can be performed by applying a unipolar wake-up pulse to the memory cells (MC) connected to the even word lines. For example, during the recovery operation, the bit line precharge voltage (VBLP) is set to a level lower than half the level (VDD / 2) of the power supply voltage (VDD), and the plate voltage or source voltage can be set to the power supply voltage (VDD) level. In this situation, if all-high data or all-low data is applied to bit lines after high voltage (VPP) is applied to even word lines, stress greater than normal operation may be applied to half of the memory cells (MC).

[0137] Afterward, the low control circuit (121) selects and activates the odd word lines (S1323), and the sensing amplifier circuit (123) transmits the test pattern transmitted through the data line (DL) to the bit lines (BL) to write logic high level or logic low level data to all memory cells (MC) connected to the odd word lines (S1324). Accordingly, a recovery operation can be performed to apply a unipolar wake-up pulse to the memory cells (MC) connected to the odd word lines. For example, during the recovery operation, the bit line precharge voltage (VBLP) is set to a level lower than half the level (VDD / 2) of the power supply voltage (VDD), and the plate voltage or source voltage can be set to the power supply voltage (VDD) level. In this situation, if all-high data or all-low data is applied to the bit lines after high voltage (VPP) is applied to the odd word lines, stress greater than normal operation may be applied to the remaining half of the memory cells (MC).

[0138] As described above, in the third embodiment of the proposed invention, the reliability of the operation of the memory device can be secured by performing a normal operation in a state where target characteristics can be secured by performing a recovery operation in advance before the normal operation is performed.

[0140] FIG. 16 is a block diagram of an information processing system (400) to which a ferroelectric memory device according to an embodiment of the present invention is applied.

[0141] Referring to FIG. 16, a memory device (100) according to embodiments of the present invention or a memory system (410) including the same may be mounted on an information processing system (400), such as a mobile device or a desktop computer. The information processing system (400) may be equipped with a memory system (410), a modem (420), a central processing unit (450), RAM (440), and a user interface (430) that are electrically connected to a system bus (460). Additionally, the memory system (410) may be a non-volatile memory system including non-volatile memory, and as an example, the memory system (410) may include a memory device (100) and a memory controller (412). The memory device (100) of FIG. 16 may perform the same configuration and operation as the ferroelectric memory device (100) described in FIG. 2 to FIG. 15.

[0142] The memory system (410) may store data processed by the central processing unit (450) or data input from an external source. Although not shown in FIG. 16, the information processing system (400) may further be provided with an application chipset, a camera image processor (CIS), input / output devices, etc.

[0144] Although the technical concept of the present invention has been specifically described according to the preferred embodiments above, it should be noted that the above-described embodiments are for illustrative purposes only and are not intended to be limiting. Furthermore, a person skilled in the art will understand that various embodiments are possible within the scope of the technical concept of the present invention.

[0145] For example, the logic gates and transistors exemplified in the above-described embodiment must be implemented with different positions and types depending on the polarity of the input signal.

Claims

Claim 1 A memory device comprising: a memory cell array including a plurality of memory cells; a peripheral circuit that performs a normal operation of applying a driving voltage for reading or writing data stored in the memory cells and a recovery operation of applying a recovery voltage to increase the residual polarization of the memory cells; and a control logic that controls the peripheral circuit so that the normal operation is performed after the recovery operation is performed upon power-up, wherein the peripheral circuit includes: a sense amplifier that detects and amplifies the voltage difference between a rect line and a boobit line; and a recovery bias circuit that applies the recovery voltage to at least one bit line among the rect line and the boobit line according to a wake-up signal provided from the control logic. Claim 2 In claim 1, the recovery voltage is a memory device having a magnitude substantially equal to or lower than the amplitude of the driving voltage. Claim 3 In claim 1, the recovery voltage is a memory device comprising a unipolar wake-up pulse. Claim 4 In claim 1, the recovery voltage comprises a single unipolar wake-up pulse that maintains a constant voltage level, and the wake-up pulse has a width wider than the pulse width of the driving voltage. Claim 5 delete Claim 6 In claim 1, the recovery bias circuit comprises a memory device including a transistor connected between the rectified line and the recovery voltage terminal, and receiving the wake-up signal as a gate. Claim 7 In claim 1, the recovery voltage is a memory device having a voltage level lower than the bit line precharge voltage or a voltage level higher than the bit line precharge voltage. Claim 8 A memory device according to claim 1, wherein each memory cell comprises: a ferroelectric capacitor in which a first electrode shares a common plate; and an access transistor connected between a second electrode of the ferroelectric capacitor and a corresponding bit line, and to which a word line corresponding to a gate is connected. Claim 9 A memory device according to claim 1, wherein the recovery bias circuit comprises: a first transistor connected between the rect line and the first recovery voltage terminal and receiving the wake-up signal as a gate; and a second transistor connected between the boobit line and the second recovery voltage terminal and receiving the wake-up signal as a gate. Claim 10 In claim 9, the first recovery voltage has a voltage level corresponding to the ground voltage, and the second recovery voltage has a voltage level corresponding to the ground voltage or the power supply voltage. Claim 11 A memory device according to claim 1, wherein each memory cell comprises: a ferroelectric capacitor having a first electrode connected to an individual plate line; and an access transistor connected between a second electrode of the ferroelectric capacitor and a corresponding bit line, with a word line connected to a gate. Claim 12 delete Claim 13 delete Claim 14 In claim 1, the memory cells are a memory device comprising ferroelectric memory cells. Claim 15 delete Claim 16 delete Claim 17 delete Claim 18 delete Claim 19 delete Claim 20 delete Claim 21 delete Claim 22 delete Claim 23 delete

Images