Integrate circuit device inclduing gate contact

Abstract

An integrated circuit element comprises: a substrate including a device region and a field region; active regions extending in a first direction in the device region; a first gate structure extending in a second direction intersecting the first direction in the device region and the field region; a second gate structure spaced apart from the first gate structure in the first direction; a first gate contact connected to the first gate structure in the device region; and a second gate contact connected to the second gate structure in the field region, wherein the first gate contact and the second gate contact are located at a level lower than the top of the first gate structure, and the first minimum width of the first gate contact and the second minimum width of the second gate contact are different from each other.

Description

Technology Field

[0001] The present disclosure relates to an integrated circuit device comprising a gate contact. Background Technology

[0002] With the miniaturization of devices, the high integration of integrated circuit devices is progressing rapidly, and the need to reduce the area of ​​integrated circuit devices is also increasing. Accordingly, there is a need for the development of technology that can reduce the area occupied by contacts, vias, and wiring within a relatively small area while ensuring insulation distances between contacts, vias, and wirings, and also improve the reliability of integrated circuit devices. The problem to be solved

[0003] The objective according to the embodiments of the present disclosure is to provide an integrated circuit device that can improve reliability while having a relatively reduced area. means of solving the problem

[0004] An integrated circuit device according to one embodiment of the present disclosure comprises: a substrate including a device region and a field region; active regions extending in a first direction in the device region; a first gate structure extending in a second direction intersecting the first direction in the device region and the field region; a second gate structure spaced apart from the first gate structure in the first direction; a first gate contact connected to the first gate structure in the device region; and a second gate contact connected to the second gate structure in the field region, wherein the first gate contact and the second gate contact are located at a level lower than the top of the first gate structure, and the first minimum width of the first gate contact and the second minimum width of the second gate contact may be different from each other.

[0005] An integrated circuit device according to one embodiment of the present disclosure comprises: a substrate including a device region and a field region; active regions extending in a first direction in the device region; a first gate electrode extending in a second direction intersecting the first direction in the device region and the field region; a first gate capping layer on the first gate electrode; a second gate electrode spaced apart from the first gate electrode in the first direction; a second gate capping layer on the second gate electrode; a first gate contact connected to the first gate electrode by penetrating the first gate capping layer in the device region; and a second gate contact connected to the second gate electrode by penetrating the second gate capping layer in the field region, wherein the first minimum width of the first gate contact and the second minimum width of the second gate contact may be different from each other.

[0006] An integrated circuit device according to one embodiment of the present disclosure comprises: a substrate including a device region and a field region; active regions extending in a first direction in the device region; a first gate electrode extending in a second direction intersecting the first direction in the device region and the field region; a first gate capping layer on the first gate electrode; a second gate electrode spaced apart from the first gate electrode in the first direction; a second gate capping layer on the second gate electrode; a first gate contact connected to the first gate electrode by penetrating the first gate capping layer in the device region; a second gate contact connected to the second gate electrode by penetrating the second gate capping layer in the field region; a source / drain region disposed on the active region; and a source / drain contact disposed on the source / drain region, wherein the first minimum width of the first gate contact may be greater than the second minimum width of the second gate contact. Effects of the invention

[0007] According to an embodiment of the present disclosure, by placing the gate contact in the device region as well as the field region, the overall area of ​​the integrated circuit device can be reduced, while the reliability of the integrated circuit device can be improved by securing an insulation distance between the gate contact and the source / drain contact pattern and reducing the resistance of the gate contact. Brief explanation of the drawing

[0008] FIG. 1 is a planar layout for illustrating an integrated circuit element according to one embodiment of the present disclosure. FIG. 2a is a drawing showing the cross-section along I-I' and II-II' of FIG. 1. FIG. 2b is a drawing showing the cross-section along III-III' and the cross-section along VI-VI' of FIG. 1. FIG. 3 is a drawing showing a cross-section along I-I' and a cross-section along II-II' of FIG. 1 according to one embodiment of the present disclosure. FIGS. 4a to 14b are cross-sectional views illustrated in the order of process to explain a method for manufacturing an integrated circuit element according to one embodiment of the present disclosure. FIG. 15a is a drawing showing a cross-section along I-I' and II-II' of FIG. 1 according to one embodiment of the present disclosure, and FIG. 15b is a drawing showing a cross-section along III-III' and VI-VI' of FIG. 1 according to the above embodiment. Specific details for implementing the invention

[0009] FIG. 1 is a planar layout for illustrating an integrated circuit element according to one embodiment of the present disclosure. FIG. 2a is a cross-sectional view along I-I' and II-II' of FIG. 1. FIG. 2b is a cross-sectional view along III-III' and VI-VI' of FIG. 1.

[0010] Referring to FIGS. 1, 2a, and 2b, the integrated circuit element (100) may comprise a logic cell including transistors. For example, the transistor may be a FinFET (fin field effect transistor). The integrated circuit element (100) may include a logic cell (LC) formed on a substrate (101).

[0011] An integrated circuit element (100) includes a substrate (101). The substrate (101) may include a plate shape extending in a first direction (X direction) and a second direction (Y direction), and may include a portion protruding in a third direction (Z direction). The first direction (X direction) and the second direction (Y direction) may be orthogonal to each other on the same plane. The third direction (Z direction) may be orthogonal to the first direction (X direction) and the second direction (Y direction). The substrate (101) may include a semiconductor such as Si or Ge, or a compound semiconductor such as SiGe, SiC, GaAs, InAs, or InP. The substrate (101) may include a conductive region, for example, the conductive region may include an impurity-doped well or an impurity-doped structure.

[0012] A logic cell (LC) may include a first element region (RX1) and a second element region (RX2). The first element region (RX1) and the second element region (RX2) may be spaced apart in a second direction (Y direction) with a field region (FD) in between. Active regions (105) may be formed in the first element region (RX1) and the second element region (RX2). The active regions (105) may be pin-shaped active regions protruding from the substrate (101). The active regions (105) extend along a first direction (X direction) and may be spaced apart from each other in a second direction (Y direction).

[0013] The first device isolation layer (107) may cover the lower portion of the active regions (105). The active regions (105) may protrude above the upper surface of the first device isolation layer (107). The second device isolation layer (109) may be disposed within a field region (FD) on the substrate (101). A deep trench (DT) defined by the substrate (101) and the first device isolation layer (107) may be formed in the field region (FD), and the second device isolation layer (109) may fill the deep trench (DT). The second device isolation layer (109) may distinguish between the first device region (RX1) and the second device region (RX2). The first device isolation layer (107) and the second device isolation layer (109) may each include an oxide.

[0014] Gate structures (GS) may extend in a second direction (Y direction) intersecting with active regions (105). Gate structures (GS) may be formed across each of the first device region (RX1), the field region (FD), and the second device region (RX2). Gate structures (GS) are placed on the first device isolation layer (107) and the second device isolation layer (109) and may cover a portion of the upper part of the active region (105) protruding over the first device isolation layer (107). Gate structures (GS) have the same width in the first direction (X direction) and may be arranged at a constant pitch along the first direction (X direction).

[0015] Transistors may be formed along gate structures (GS) in each of the first device region (RX1) and the second device region (RX2). The transistors may each be MOS transistors of a three-dimensional structure in which a channel is formed on top of the fin-shaped active regions (105). In one embodiment, the first device region (RX1) may be an NMOS transistor region and the second device region (RX2) may be a PMOS transistor region.

[0016] Each gate structure (GS) may include a gate electrode (123), gate spacers (SP), a gate insulating layer (121), and a gate capping layer (125). The gate electrode (123) may have a structure in which a metal nitride layer, a metal layer, a conductive capping layer, and a gap-fill metal layer are stacked in sequence. For example, the metal nitride layer and the metal layer may include at least one of Ti, Ta, W, Ru, Nb, Mo, and Hf. For example, the gap-fill metal layer may include W or Al. The gate electrode (123) may include a work function metal-containing layer. The work function metal-containing layer may include at least one of Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, and Pd.

[0017] Gate spacers (SPs) may be disposed on both sidewalls of the gate electrode (123). The gate spacers (SPs) may include SiN, SiOCN, SiCN, or a combination thereof, but are not limited thereto. Each gate spacer (SP) may be made of multiple films.

[0018] A gate insulating layer (121) may be interposed between the gate electrode (123) and the gate spacer (SP), between the gate electrode (123) and the active regions (105), between the gate electrode (123) and the first device isolation layer (107), and between the gate electrode (123) and the second device isolation layer (109). The gate insulating layer (121) may extend along the profile of the active region (105) protruding over the first device isolation layer (107). The gate insulating layer (121) may comprise silicon oxide, a high dielectric material, or a combination thereof. The high dielectric material may comprise at least one of a metal oxide or a metal oxynitride.

[0019] In one embodiment, transistors formed along gate structures (GS) in each of the first device region (RX1) and the second device region (RX2) may include negative capacitance (NC) FETs using a negative capacitor. In this case, for example, the gate insulating layer (121) may include a ferroelectric material film having ferroelectric properties and a paraelectric material film having paraelectric properties.

[0020] Ferroelectric film materials can have negative capacitance, while paraelectric film materials can have positive capacitance. For example, if two or more capacitors are connected in series and each capacitor has a positive capacitance, the total capacitance will be smaller than the capacitance of each individual capacitor. Conversely, if at least one of the capacitances of the two or more capacitors connected in series has a negative value, the total capacitance will have a positive value and may be greater than the absolute value of each individual capacitance.

[0021] When a ferroelectric material film with negative capacitance and a paraelectric material film with positive capacitance are connected in series, the total capacitance value of the series-connected ferroelectric material film and paraelectric material film can increase. By utilizing the increase in the total capacitance value, a transistor containing a ferroelectric material film can have a subthreshold swing (SS) of less than 60 mV / decade at room temperature.

[0022] Ferroelectric material films may have ferroelectric properties. Ferroelectric material films may include, for example, at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanium oxide. Here, as an example, hafnium zirconium oxide may be a material in which zirconium (Zr) is doped into hafnium oxide. As another example, hafnium zirconium oxide may be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

[0023] The ferroelectric material film may further include a doped dopant. For example, the dopant may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin (Sn). Depending on which ferroelectric material the ferroelectric material film contains, the type of dopant included in the ferroelectric material film may vary.

[0024] When the ferroelectric material film contains hafnium oxide, the dopant included in the ferroelectric material film may include, for example, at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and yttrium (Y). When the dopant is aluminum (Al), the ferroelectric material film may contain 3 at% to 8 at% (atomic %) of aluminum. Here, the ratio of the dopant may be the ratio of aluminum to the sum of hafnium and aluminum. When the dopant is silicon (Si), the ferroelectric material film may contain 2 at% to 10 at% of silicon. When the dopant is yttrium (Y), the ferroelectric material film may contain 2 at% to 10 at% of yttrium. When the dopant is gadolinium (Gd), the ferroelectric material film may contain 1 at% to 7 at% of gadolinium. When the dopant is zirconium (Zr), the ferroelectric material film may contain 50 at% to 80 at% of zirconium.

[0025] The paraelectric material film may have paraelectric properties. The paraelectric material film may include, for example, at least one of silicon oxide and a metal oxide having a high dielectric constant. The metal oxide included in the paraelectric material film may include, for example, at least one of hafnium oxide, zirconium oxide, and aluminum oxide, but is not limited thereto.

[0026] Ferroelectric and paraelectric film layers may contain the same material. Ferroelectric film layers possess ferroelectric properties, whereas paraelectric film layers may not. For example, if both ferroelectric and paraelectric film layers contain hafnium oxide, the crystal structure of the hafnium oxide contained in the ferroelectric film layer is different from the crystal structure of the hafnium oxide contained in the paraelectric film layer.

[0027] The ferroelectric material film may have a thickness that exhibits ferroelectric properties. The thickness of the ferroelectric material film may be, for example, 0.5 nm to 10 nm, but is not limited thereto. Since the critical thickness at which ferroelectric properties are exhibited may vary for each ferroelectric material, the thickness of the ferroelectric material film may vary depending on the ferroelectric material.

[0028] For example, the gate insulating layer may include a single ferroelectric material film. For another example, the gate insulating layer may include a plurality of ferroelectric material films spaced apart from each other. The gate insulating layer may have a stacked film structure in which a plurality of ferroelectric material films and a plurality of paraelectric material films are alternately stacked.

[0029] The gate capping layer (125) may be disposed on the gate electrode (123), the gate insulating layer (121), and the gate spacers (SP). For example, the gate capping layer (125) may comprise silicon nitride.

[0030] In one embodiment, the gate capping layer (125) may have a different height along a second direction (Y direction). The gate capping layer (125) may have a different height in the first and second device regions (RX1, RX2) and in the field region (FD). The gate capping layer (125) may have a first height (Ta) in the first and second device regions (RX1, RX2) and a second height (Tb) greater than the first height (Ta) in the field region (FD). Here, the first height (Ta) may be the maximum height of the gate capping layer (125) in the first and second device regions (RX1, RX2), and the second height (Tb) may be the maximum height of the gate capping layer (125) in the field region (FD). Additionally, the level of the uppermost (E1, E2) of the gate capping layer (125) with respect to the upper surface of the substrate (101) may differ in the first and second device regions (RX1, RX2) and in the field region (FD). The level (LVa) of the uppermost (E1) of the gate capping layer (125) in the first and second device regions (RX1, RX2) may be lower than the level (LVb) of the uppermost (E2) of the gate capping layer (125) in the field region (FD). The level of the lowermost of the gate capping layer (125) may be constant along the second direction (Y direction). The height of the gate structures (GS) may change according to the height change of the gate capping layer (125) in the second direction (Y direction), and accordingly, the height of the gate structures (GS) may be greater in the field region (FD) than in the first and second device regions (RX1, RX2).

[0031] In the active region (105), a recessed region may be formed in which the upper portion of the active region (105) protruding over the first device isolation layer (107) is partially removed. The recessed region may be formed between the gate structures (GS). A source / drain region (S / D) may be disposed in the recessed region between the gate structures (GS). The source / drain region (S / D) may include an epitaxially grown semiconductor layer. For example, the source / drain region (S / D) may include at least one of an epitaxially grown Si layer, an epitaxially grown SiC layer, and an epitaxially grown SiGe layer.

[0032] Source / drain contact patterns (CA) may be disposed on source / drain regions (S / D). The source / drain regions (S / D) may be electrically connected to an upper wiring layer (not shown in the drawing) through the source / drain contact patterns (CA). Each source / drain contact pattern (CA) may include a barrier layer (145) and a plug layer (147). The barrier layer (145) may cover the side walls and bottom surface of the plug layer (147). For example, the barrier layer (145) may include Ti, Ta, TiN, TaN, or a combination thereof, and the plug layer (147) may include W, Co, Cu, Ru, Mn, or a combination thereof.

[0033] Silicide films (141) may be formed between source / drain regions (S / D) and source / drain contact patterns (CA). For example, the silicide films (141) may include titanium silicide. Contact spacers (143) may be formed on the sidewalls of the source / drain contact patterns (CA). For example, the contact spacers (143) may include SiN, SiCN, SiCON, or a combination thereof, but are not limited thereto.

[0034] Source / drain contact patterns (CA) may have different heights depending on the location. Source / drain contact patterns (CA) may include a first part (P1) and a second part (P2) that are integrally connected to each other and have different heights along a second direction (Y direction). On the active region (105), the first part (P1) of the source / drain contact pattern (CA) may have a first height, and the second part (P2) may have a second height greater than the first height. In one embodiment, with respect to the upper surface of the substrate (101), the upper level of the first part (P1) may be lower than the level of the upper surface of the gate electrode (123), and the upper level of the second part (P2) may be higher than the level of the upper surface of the gate electrode (123). However, the present invention is not limited thereto, and the upper level of each of the first part (P1) and the second part (P2) may be higher than the level of the upper surface of the gate electrode (123).

[0035] Gate contacts (CB) can be connected to gate electrodes (123) by penetrating the gate capping layers (125) in a third direction (Z direction). The gate contacts (CB) can be located at a level lower than the top level (LVb) of the gate structure (GS) with respect to the upper surface of the substrate (101). That is, the gate contacts (CB) can be located at a level lower than the top level (E2) of the gate capping layer (125).

[0036] In one embodiment, the gate structures (GS) may include a first gate structure (GS1) and a second gate structure (GS2) that are spaced apart from each other in a first direction (X direction), and the gate contacts (CB) may include a first gate contact (CB1) connected to the first gate structure (GS1) and a second gate contact (CB2) connected to the second gate structure (GS2). The first gate contact (CB1) may be connected to the first gate structure (GS1) in a first device region (RX1), and the second gate contact (CB2) may be connected to the second gate structure (GS2) in a field region (FD).

[0037] The first gate contact (CB1) can be connected to the first gate electrode (123) by penetrating the first gate capping layer (125) of the first gate structure (GS1). The first gate contact (CB1) may have a first minimum width (Wa). The first minimum width (Wa) is the width of the first direction (X direction) of the first gate contact (CB1) and may be the minimum horizontal distance between the bottom of one side wall of the first gate contact (CB1) and the bottom of the other side wall facing it. The first gate contact (CB1) may have a first height (Ha). The first height (Ha) may be the vertical distance from the bottom to the top of the first gate contact (CB1).

[0038] The second gate contact (CB2) can be connected to the second gate electrode (123) by penetrating the second gate capping layer (125) of the second gate structure (GS2). The second gate contact (CB2) may have a second minimum width (Wb) different from the first minimum width (Wa). The second minimum width (Wb) is the width of the second direction (Y direction) of the second gate contact (CB2) and may be the minimum horizontal distance between the bottom of one sidewall of the second gate contact (CB2) and the bottom of the other sidewall facing it. For example, the second minimum width (Wb) may be smaller than the first minimum width (Wa). The second gate contact (CB2) may have a second height (Hb). The second height (Hb) may be the vertical distance from the bottom to the top of the second gate contact (CB2). The second height (Hb) may be greater than the first height (Ha). The first gate contact (CB1) is located in the first device region (RX1), thereby reducing the area required by the field region (FD) and contributing to reducing the size of the logic cell (LC). Additionally, by having a relatively wider width and shorter length compared to the second gate contact (CB2), the resistance value can be lowered.

[0039] In one embodiment, the first maximum width of the first gate contact (CB1) may be greater than the second maximum width of the second gate contact (CB2). The first maximum width is the width in the first direction (X) of the first gate contact (CB1) and may be the width of the upper surface of the first gate contact (CB1). The second maximum width is the width in the first direction (X direction) of the second gate contact (CB2) and may be the width of the upper surface of the second gate contact (CB2). Consequently, the first gate contact (CB1) has a relatively larger width than the second gate contact (CB2) at both the top and bottom, thereby having a relatively lower resistance value compared to the second gate contact (CB2).

[0040] In one embodiment, source / drain contact patterns (CA) located adjacent to both sides of the first gate contact (CB1) may each have a second portion (P2) included therein that does not overlap with the first gate contact (CB1) in the first direction (X direction). By having first portions (P1) with relatively low height located on both sides of the first gate contact (CB1), the distance between the first gate contact (CB1) and the source / drain contact patterns (CA) can be secured to prevent the occurrence of parasitic capacitance.

[0041] Buried insulating layers (150) may be disposed on source / drain contact patterns (CA). The buried insulating layers (150) are disposed on a first portion (P1) of the source / drain contact pattern (CA) and may be in contact with a portion of the side of a second portion (P2). The buried insulating layers (150) may cover a portion of the gate capping layers (125). The buried insulating layers (150) may include silicon oxide, SiOC, SiOCN, SiON, SiCN, SiN, or a combination thereof, but are not limited thereto.

[0042] A first interlayer insulating layer (110) may be disposed on the first device isolation layer (107) and the second device isolation layer (109). The first interlayer insulating layer (110) may be disposed between the gate structures (GS) in the field region (FD). The first interlayer insulating layer (110) may cover the source / drain regions (S / D), contact spacers (143), and the buried insulating layer (150). A second interlayer insulating layer (170) may be disposed on the first interlayer insulating layer (110). The second interlayer insulating layer (170) may cover the upper surface of the gate capping layer (125) and the upper surface of the buried insulating layer (150) in the first and second device regions (RX1, RX2). The second interlayer insulating layer (170) can cover the upper surface of the gate capping layer (125) and the upper surface of the first interlayer insulating layer (110) in the field region (FD).

[0043] The first interlayer insulating layer (110) and the second interlayer insulating layer (170) may each comprise an oxide, a nitride, an ultra-low-k (ULK) material having an ultra-low dielectric constant K of about 2.2 to 2.4, or a combination thereof. For example, the first interlayer insulating layer (110) and the second interlayer insulating layer (170) may each comprise TEOS (tetraethylorthosilicate), HDP (high density plasma), BPSG (boro-phospho-silicate glass), FCVD (flowable chemical vapor deposition) oxide, SiON, SiN, SiOC, SiCOH, or a combination thereof.

[0044] First vias (VA1) may be placed on source / drain contact patterns (CA). The first via (VA1) may penetrate the second interlayer insulating layer (170) and come into contact with the upper surface of the second portion (P2) of the source / drain contact pattern (CA). Second vias (VA2) may be placed on gate contacts (CB). The second vias (VA2) may penetrate the second interlayer insulating layer (170) and come into contact with the upper surface of the gate contacts (CB).

[0045] The first vias (VA1) and the second vias (VA2) may each include a barrier layer and a buried metal layer. For example, the barrier layer may include Ti, Ta, TiN, TaN, or a combination thereof, and the buried metal layer may include Co, Cu, W, Ru, Mn, or a combination thereof.

[0046] In a logic cell (LC), a power line (VDD) may be connected to an active region (105) in a first device region (RX1) through some of the source / drain contact patterns (CA), and a ground line (VSS) may be connected to an active region (105) in a second device region (RX2) through other of the source / drain contact patterns (CA). The power line (VDD) and the ground line (VSS) may be located at a higher level than the upper surface of the source / drain contact patterns (CA). The power line (VDD) and the ground line (VSS) may each include a barrier layer and a conductive layer for wiring, the barrier layer may include Ti, Ta, TiN, TaN, or a combination thereof, and the conductive layer for wiring may include Co, Cu, W, an alloy thereof, or a combination thereof.

[0047] FIG. 3 is a drawing showing a cross-section along I-I' and a cross-section along II-II' of FIG. 1 according to one embodiment of the present disclosure.

[0048] Referring to FIG. 3, the first minimum width (Wa') of the first gate contact (CB1) may be smaller than the second minimum width (Wb') of the second gate contact (CB2). By having a relatively small width, the first gate contact (CB1) can secure a distance from the second part (P2) of the adjacent source / drain contact pattern (CA), thereby reducing parasitic capacitance. Additionally, a process margin is secured with respect to the second part (P2) of the source / drain contact pattern (CA), preventing a short circuit between the first gate contact (CB1) and the second part (P2). The second gate contact (CB2) can have a relatively large width, thereby lowering the resistance value.

[0049] In one embodiment, the first gate contact (CB1) may have a minimum width smaller than the second gate contact (CB2), and may also have a maximum width smaller. Here, the maximum width may be the width of the first direction (X) of the upper surface of the gate contact.

[0050] FIGS. 4a to 14b are cross-sectional views illustrated in the order of process to explain a method for manufacturing an integrated circuit element according to one embodiment of the present disclosure. FIGS. 4a, 5a, 6a, 7a, 8a, 9a, 10a, 11a, 12a, 13a, and 14a are cross-sectional views of I-I' and II-II' of FIG. 1 illustrated in the order of process. FIGS. 4b, 5b, 6b, 7b, 8b, 9b, 10b, 11b, 12b, 13b, and 14b are cross-sectional views of III-III' and IV-IV' of FIG. 1 illustrated in the order of process.

[0051] Referring to FIG. 1, FIG. 4a and FIG. 4b, a substrate (101) can be partially etched to form active regions (105) that protrude upward (i.e., in the Z direction) from the upper surface of the substrate (101) and extend in a first direction (X direction). The active regions (105) may be fin-shaped active regions having a fin shape. The active regions (105) may be formed in a first device region (RX1) and a second device region (RX2), respectively.

[0052] A first device isolation layer (107) can be formed covering the lower sidewalls of the active regions (105). The active regions (105) may protrude above the upper surface of the first device isolation layer (107). A deep trench (DT) separating the first device region (RX1) and the second device region (RX2) can be formed by etching a portion of the first device isolation layer (107) and a portion of the substrate (101), and a second device isolation layer (109) filling the deep trench (DT) can be formed. The second device isolation layer (109) can be formed in a field region (FD) between the first device region (RX1) and the second device region (RX2). The field region (FD) may correspond to the area where the deep trench (DT) and the second device isolation layer (109) are formed.

[0053] Referring to FIGS. 5a and 5b, dummy gate structures (DGs) can be formed extending in a second direction (Y direction) intersecting active regions (105) on the first device isolation layer (107) and the second device isolation layer (109). Each dummy gate structure (DG) may include a dummy gate line (DL) and a dummy gate capping layer (DC). For example, the dummy gate line (DL) may include silicon oxide and / or polysilicon, and the dummy gate capping layer (DC) may include silicon nitride.

[0054] Gate spacers (SP) can be formed on both side walls of each of the dummy gate structures (DG), and recessed regions can be formed by partially etching the active regions (105) exposed on both sides of the dummy gate structures (DG). Source / drain regions (S / D) can be formed in each of the recessed regions. A first interlayer insulating layer (110) covering the first device isolation layer (107), the second device isolation layer (109), the source / drain regions (S / D), and the gate spacers (SP) can be formed between the dummy gate structures (DG).

[0055] Referring to FIGS. 6a and 6b, dummy gate structures (DG) can be removed from the results of FIGS. 5a and 5b, and a gate space can be formed between gate spacers (SP). A gate insulating layer (121), a gate electrode (123), and a gate capping layer (125) can be formed within the gate space. First, a gate insulating layer (121) and a gate electrode (123) that fill the gate space can be formed. Subsequently, a portion of the upper part of the gate insulating layer (121) and the gate electrode (123) can be removed by etch-back. During the etch-back process, a portion of the upper part of the gate spacer (SP) can also be removed. Subsequently, a gate capping layer (125) covering the upper surface of each of the gate insulating layer (121), the gate electrode (123), and the gate spacer (SP) can be formed.

[0056] In one embodiment, before forming the gate insulating layer (121), an interface layer (not shown in the drawing) covering the surface of the active regions (105) exposed through the gate space may be formed. The interface layer may be formed by partially oxidizing the active regions (105).

[0057] Referring to FIGS. 7a and 7b, a first upper insulating layer (130) can be formed covering the upper surface of the gate capping layer (125) and the upper surface of the first interlayer insulating layer (110). Subsequently, source / drain contact holes (CH) can be formed to expose source / drain regions (S / D) by penetrating the first upper insulating layer (130) and the first interlayer insulating layer (110). During the process of forming the source / drain contact holes (CH), the source / drain regions (S / D) may be partially etched. Subsequently, a contact spacer (143) covering the inner wall of the source / drain contact hole (CH) can be formed. The contact spacer (143) can be formed by forming an insulating film that conformally covers the inner wall of the source / drain contact hole (CH), and then partially etching the insulating film through anisotropic etching. Through the above anisotropic etching, the insulating film may be partially removed to expose the source / drain region (S / D), and the source / drain region (S / D) may be partially removed.

[0058] A silicide film (141) covering a source / drain region (S / D) inside a source / drain contact hole (CH) can be formed, and a source / drain contact (CP) filling the source / drain contact hole (CH) can be formed on the silicide film (141). The source / drain contact (CP) may include a barrier layer (145) and a plug layer (147).

[0059] Referring to FIGS. 8a and 8b, an etch stop layer (ST) can be formed covering the upper surface of each of the source / drain contacts (CP) and the first upper insulating layer (130), and mask patterns (MP) can be formed on the etch stop layer (ST). The mask patterns (MP) can be formed to overlap perpendicularly with parts of the source / drain contacts (CP). For example, the mask patterns (MP) can be formed to be positioned at a location corresponding to the first via (VA1) shown in FIG. 1.

[0060] The etching stop layer (ST) may include, for example, SiOC, SiN, or a combination thereof. The mask patterns (MP) may include, for example, silicon oxide, SOH (spin-on hardmask), a photoresist film, or a combination thereof.

[0061] Referring to FIGS. 9a and 9b, the etching stop layer (ST) can be etched through an etching process using mask patterns (MP) as etching masks, and subsequently, the exposed source / drain contacts (CP) can be partially etched in a first etching atmosphere. In the first etching atmosphere, the exposed portions of the source / drain contacts (CP) are partially etched, thereby forming source / drain contact patterns (CA) having different heights depending on the location. The source / drain contact patterns (CA) can be formed to include a first portion (P1) and a second portion (P2) that are integrally connected to each other and have different heights along a second direction (Y direction).

[0062] The first etching atmosphere may be an etching atmosphere for etching a metal-containing film constituting source / drain contacts (CPs). The first etching atmosphere may be an etching atmosphere in which the amount of etching of the metal-containing film constituting the source / drain contacts (CPs) is greater than the amount of etching of the insulating films constituting each of the gate capping layer (125) and the first upper insulating layer (130), and the amount of etching of the insulating films constituting each of the gate capping layer (125) and the first upper insulating layer (130) is greater than 0.

[0063] In one embodiment, the amount of etching of the metal-containing film, e.g., tungsten film, constituting the source / drain contacts (CPs) in the first etching atmosphere for etching the exposed portions of the source / drain contacts (CPs) may be greater than the amount of etching of the insulating film, e.g., silicon nitride film, constituting the gate capping layer (125), and may be greater than the amount of etching of the insulating film, e.g., silicon oxide film, constituting the first upper insulating layer (130). The amount of etching of the insulating film constituting the gate capping layer (125) in the first etching atmosphere may be greater than the amount of etching of the insulating film constituting the first upper insulating layer (130). For example, the ratio of the etching amount for the metal-containing film constituting the source / drain contacts (CP) in the first etching atmosphere, the etching amount for the insulating film constituting the gate capping layer (125), and the etching amount for the insulating material constituting the first upper insulating layer (130) may be approximately 6:3:1, but the present invention is not limited thereto.

[0064] As a result, while etching exposed portions of source / drain contacts (CP) using a mask pattern (MP) as an etching mask, some of the gate capping layers (125) and at least some of the first upper insulating layer (130) that are exposed together in the first etching atmosphere may be etched. Almost all of the first upper insulating layer (130) may be removed so that the upper surface of the gate capping layer (125) is exposed, and some of the upper portion of the gate capping layer (125) may be removed so that the height is reduced.

[0065] The gate capping layers (125) may have different etching amounts in the first and second device regions (RX1, RX2) and the field region (FD) in the first etching atmosphere. That is, the gate capping layers (125) may have different etching amounts between the portions between the source / drain contacts (CP) and the portions not between the source / drain contacts (CP) in the first direction (X direction) in the first etching atmosphere. Since the source / drain contacts (CP) are etched at a faster rate than the gate capping layers (125) in the first etching atmosphere, the height of the source / drain contacts (CP) may be lower than the height of the gate capping layers (125), and at this time, the side of the gate capping layer (125) may be partially exposed. In the first etching atmosphere, the portion between the source / drain contacts (CP) of the gate capping layers (125) is exposed not only on the top surface but also on the side surface, so the exposed area increases, and thus the amount of etching for the portion of the gate capping layer (125) located on the first and second device regions (RX1, RX2) can be relatively large. On the other hand, the portions of the gate capping layers (125) located in the field region (FD) have only the top surface exposed, and the side surface is covered by the first interlayer insulating layer (110), which has a relatively slow etching rate, so the amount of etching for the portion of the gate capping layer (125) located in the field region (FD) can be relatively small. Accordingly, the height of the gate capping layers (125) in the first and second device regions (RX1, RX2) and the height in the field region (FD) may differ due to the etching process by the first etching atmosphere. That is, the height of the gate capping layers (125) may differ between the portion located between the source / drain contacts (CP) and the portion not located between them. The height (Ta) of the gate capping layers (125) in the first and second device regions (RX1, RX2) may be smaller than the height (Tb) in the field region (FD).Additionally, based on the upper surface of the substrate (101), the uppermost level (LV1) of the gate capping layers (125) in the first and second device regions (RX1, RX2) may be lower than the uppermost level (LV2) in the field region (FD). Here, the height (Ta) of the gate capping layers (125) in the first and second device regions (RX1, RX2) refers to the maximum height of the gate capping layers (125) in the first and second device regions (RX1, RX2), and the height of the gate capping layers (125) in the field region (FD) may refer to the maximum height of the gate capping layers (125) in the field region (FD).

[0066] Among the gate capping layers (125), the gate capping layer (125) positioned adjacent to the mask pattern (MP) may have a relatively smaller etching amount in the part closer to the mask pattern (MP) and a relatively larger etching amount in the part further away from the mask pattern (MP). Accordingly, when the mask pattern (MP) is formed on only one of two adjacent source / drain contacts (CP) along the first direction (X direction), the gate capping layer (125) may include an asymmetric capping layer having a variable thickness along the first direction (X direction) between the two source / drain contacts (CP). A first part (P1) of the source / drain contact pattern (CA) may be located on one side of the asymmetric capping layer, and a second part (P2) of the other source / drain contact pattern (CA) may be located on the other side corresponding to the one side.

[0067] Referring to FIGS. 10a and 10b, a buried insulating layer (150) can be formed on the result of FIGS. 9a and 9b. The buried insulating layer (150) can cover source / drain contact patterns (CA) and can cover the gate capping layer (125) and the first interlayer insulating layer (110). Additionally, the buried insulating layer (150) can cover the mask pattern (MP). Subsequently, a second upper insulating layer (155) can be formed on the buried insulating layer (150). For example, the second upper insulating layer (155) may include an oxide.

[0068] Referring to FIGS. 11a and 11b, a chemical mechanical polishing (CMP) process can be performed to remove the second upper insulating layer (155), the mask pattern (MP), and the etch stop layer (ST), and to remove a portion of the source / drain contact pattern (CA) and a portion of the buried insulating layer (150). By the CMP process, the upper surface of the second portion (P2) of the source / drain contact pattern (CA) may be exposed. By the CMP process, the upper surface (150us) of the buried insulating layer (150) in the first and second device regions (RX1, RX2) may be exposed, and the respective upper surfaces (125us, 110us) of the gate capping layer (125) and the first interlayer insulating layer (110) in the field region (FD) may be exposed. The gate capping layer (125) in the first and second device regions (RX1, RX2) may not be exposed. However, if the gate capping layer (125) includes an asymmetric capping layer, the top of the asymmetric capping layer may be exposed.

[0069] In one embodiment, the CMP process may be performed using the gate capping layer (125) and / or the first interlayer insulating layer (110) as a polishing stop layer. For example, the CMP process may be performed until the upper surface (125us) of the gate capping layer (125) is exposed. When the CMP process is performed using the gate capping layer (125) and / or the first interlayer insulating layer (110) as a polishing stop layer, the slurry used in the CMP process may have a greater selectivity ratio with respect to the insulating material forming the buried insulating layer (150) than to the insulating materials forming the gate capping layer (125) and the first interlayer insulating layer (110), respectively. As a result, the level (LV4) of the upper surface (150us) of the buried insulating layer (150) in the first and second device regions (RX1, RX2) and the level (LV3) of the upper surface (1250us, 110us) of the gate capping layer (125) and the first interlayer insulating layer (110) in the field region (FD) may differ. That is, the height of the resulting product after the CMP process is performed may differ in the first and second device regions (RX1, RX2) and in the field region (FD). For example, the level (LV4) of the upper surface (150us) of the buried insulating layer (150) in the first and second device regions (RX1, RX2) may be lower than the level (LV3) of the upper surface (125us, 110us) of the gate capping layer (125) and the first interlayer insulating layer (110) in the field region (FD).

[0070] Referring to FIGS. 12a and 12b, a third upper insulating layer (160) can be formed on the result of FIGS. 11a and 11b. The third upper insulating layer (160) can cover the upper surface of the buried insulating layer (150). For example, the third upper insulating layer (160) may include an oxide.

[0071] Subsequently, gate contact holes (CTH) that partially expose the gate electrode (123) can be formed. The gate contact holes (CTH) may include a first gate contact hole (CTH1) formed in the first and second device regions (RX1, RX2) and a second gate contact hole (CTH2) formed in the field region (FD). In the first and second device regions (RX1, RX2), the first gate contact hole (CTH1) may be formed to expose the gate electrode (123) by penetrating the third upper insulating layer (160), the buried insulating layer (150), and the gate capping layer (125). In the field region (FD), the second gate contact hole (CTH2) may be formed to expose the gate electrode (123) by penetrating the third upper insulating layer (160) and the gate capping layer (125).

[0072] The first gate contact hole (CTH1) and the second gate contact hole (CTH2) can be formed by forming a mask pattern (not shown in the drawing) that includes a first opening (not shown in the drawing) exposing the upper surface of the third upper insulating layer (160) corresponding to the area where the first gate contact hole (CTH1) is to be formed on the third upper insulating layer (160), and a second opening (not shown in the drawing) exposing the upper surface of the third upper insulating layer (160) corresponding to the area where the second gate contact hole (CTH2) is to be formed, and then using the mask pattern as an etching mask for anisotropic etching. The first gate contact hole (CTH1) and the second gate contact hole (CTH2) can be formed simultaneously through the anisotropic etching process. In one embodiment, the size of the first opening and the size of the second opening may be the same, but are not limited thereto.

[0073] In one embodiment, the first minimum width (W1) of the first gate contact hole (CTH1) and the second minimum width (W2) of the second gate contact hole (CTH2) may be different from each other. For example, the first minimum width (W1) may be larger than the second minimum width (W2). The height (Ta) of the gate capping layer (125) etched when the first gate contact hole (CTH1) is formed through the anisotropic etching process is smaller than the height (Tb) of the gate capping layer (125) etched when the second gate contact hole (CTH2) is formed. Additionally, with respect to the upper surface of the substrate (101), the uppermost level (LV4) of the gate capping layer (125) etched when the first gate contact hole (CTH1) is formed is lower than the uppermost level (LV3) of the gate capping layer (125) etched when the second gate contact hole (CTH2) is formed. Accordingly, the level at which the gate capping layer (125) begins to be etched as the first gate contact hole (CTH1) is formed and the level at which the gate capping layer (125) begins to be etched as the second gate contact hole (CTH2) is formed may be different, and the height (or amount of etching) at which the gate capping layer (125) is etched as the first gate contact hole (CTH1) is formed and the height (or amount of etching) at which the gate capping layer (125) is etched as the second gate contact hole is formed may be different. As a result, the first minimum width (W1) at the bottom of the first gate contact hole (CTH1) and the second minimum width (W2) at the bottom of the second gate contact hole (CTH2) may be formed differently from each other. In addition, the difference in the level at which the gate capping layer (125) begins to be etched and the difference in the height at which the gate capping layer (125) is etched may affect the formation of the top width of the first gate contact (see CB1 in FIG. 14a) and the top width of the second gate contact (see CB2 in FIG. 14a), which are the final results formed thereafter, differently.

[0074] Referring to FIGS. 13a and 13b, gate contacts (CB) can be formed within gate contact holes (CTH). The gate contacts (CB) may include a barrier layer (171) and a plug layer (172). A first gate contact (CB1) may be formed within a first gate contact hole (CTH1), and a second gate contact (CB2) may be formed within a second gate contact hole (CTH2). The width of the first gate contact (CB1) and the width of the second gate contact (CB2) may be determined according to the width of the first gate contact hole (CTH1) and the width of the second gate contact hole (CTH2), respectively.

[0075] Referring to FIG. 14a and FIG. 14b, the upper surface of the second portion (P2) of the source / drain contact pattern (CA) can be exposed through a CMP process. Through the CMP process, a third upper insulating layer (160), a portion of the buried insulating layer (150), a portion of the first gate contact (CB1), and a portion of the second gate contact (CB2) can be removed, and a portion of the gate capping layer (125) and a portion of the first interlayer insulating layer (110) can also be removed. As a portion of the buried insulating layer (150) is removed, the upper surface of the gate capping layer (125) can be exposed in the first and second device regions (RX1, RX2). As the third upper insulating layer (160) is removed, the upper surface of the gate capping layer (125) and the upper surface of the first interlayer insulating layer (110) can be exposed in the field region (FD). The height of the resulting product after performing the above CMP process may differ between the first and second device regions (RX1, RX2) and the field region (FD), and accordingly, the height difference of the gate capping layer (125) is maintained, and the height difference between the first gate contact (CB1) and the second gate contact (CB2) may also occur. The reason the height of the resulting product after performing the above CMP process differs between the first and second device regions (RX1, RX2) and the field region (FD) may be that the selectivity ratio of the slurry used in the CMP process is different for the insulating material forming the buried insulating layer (150) and the insulating material forming the gate capping layer (125) and / or the first interlayer insulating layer (110). For example, the above CMP process may use the gate capping layer (125) and / or the first interlayer insulating layer (110) as a polishing stop layer.

[0076] FIG. 15a is a drawing showing a cross-section along I-I' and II-II' of FIG. 1 according to one embodiment of the present disclosure, and FIG. 15b is a drawing showing a cross-section along III-III' and VI-VI' of FIG. 1 according to the above embodiment.

[0077] The integrated circuit element includes active regions (105, 201), and the active regions (105, 201) may include a pin-shaped active region (105) that protrudes from the substrate (101) and extends in a first direction (X direction), and a plurality of wire patterns (201) positioned spaced apart from the pin-shaped active region (105) in a third direction (Z direction). The wire patterns (201) may be spaced apart from each other in a third direction (Z direction). A device isolation layer (107) covering the side of the pin-shaped active region (105) may be formed on the substrate (101).

[0078] A gate structure (GS) may be disposed on a pin-shaped active region (105). The gate structure (GS) may include a gate insulating layer (121) in contact with a wire pattern (201), a gate electrode (123) surrounding the wire pattern (201), a gate spacer (SP) disposed on both side walls of the gate electrode (123), and a gate capping layer (125) on the gate electrode (123).

[0079] The gate spacer (SP) may include inner spacers (203) located at a lower level than the uppermost wire pattern (201) among the wire patterns (201), and outer spacers (205) located at a higher level than the uppermost wire pattern (201). The inner spacers (203) may be in contact with the source / drain region (S / D). In one embodiment, the inner spacers (203) may be omitted.

[0080] The integrated circuit element includes a source / drain contact pattern (CA), a buried insulating layer (150), a first gate contact (CB1), a second gate contact (CB2), a first interlayer insulating layer (110), a second interlayer insulating layer (170), a first via (VA1) and a second via (VA2), and the configurations may have the same or similar features as the same configurations described in FIG. 2a and FIG. 2b.

[0081] Although embodiments according to the technical concept of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing its technical concept or essential features. The embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0083] RX1: First element region RX2: Second element region FD: Field Area 101: Substrate 105: Active region 107: First device isolation layer 109: Second device isolation layer S / D: Source / drain region 110: First interlayer insulation layer GS: Gate structure 121: Gate insulating layer 123: Gate electrode 125: Gate Capping Layer SP: Gate Spacer 150: Buried insulation layer CB: Gate contact CA: Source / Drain Contact Pattern VA1: 1st via VA2: 2nd via

Claims

Claim 1 An integrated circuit device comprising: a substrate including a device region and a field region; active regions extending in a first direction in the device region; a first gate structure extending in a second direction intersecting the first direction in the device region and the field region; a second gate structure spaced apart from the first gate structure in the first direction; a first gate contact connected to the first gate structure in the device region; and a second gate contact connected to the second gate structure in the field region, wherein the first gate contact and the second gate contact are located at a level equal to or lower than the top of the first gate structure, and the first minimum width of the first gate contact and the second minimum width of the second gate contact are different from each other, and the first height of the first gate contact and the second height of the second gate contact are different from each other. Claim 2 An integrated circuit element according to claim 1, wherein the first minimum width is greater than the second minimum width. Claim 3 An integrated circuit element according to claim 1, wherein the first minimum width is smaller than the second minimum width. Claim 4 delete Claim 5 An integrated circuit element according to claim 1, wherein the second height is greater than the first height. Claim 6 An integrated circuit device comprising: a substrate including a device region and a field region; active regions extending in a first direction in the device region; a first gate structure extending in a second direction intersecting the first direction in the device region and the field region; a second gate structure spaced apart from the first gate structure in the first direction; a first gate contact connected to the first gate structure in the device region; and a second gate contact connected to the second gate structure in the field region, wherein the first gate contact and the second gate contact are located at a level equal to or lower than the top of the first gate structure, and the first minimum width of the first gate contact and the second minimum width of the second gate contact are different from each other, and the first gate structure has a height in the device region that is smaller than the height in the field region. Claim 7 An integrated circuit device comprising: a substrate including a device region and a field region; active regions extending in a first direction in the device region; a first gate structure extending in a second direction intersecting the first direction in the device region and the field region; a second gate structure spaced apart from the first gate structure in the first direction; a first gate contact connected to the first gate structure in the device region; and a second gate contact connected to the second gate structure in the field region, wherein the first gate contact and the second gate contact are located at a level equal to or lower than the top of the first gate structure, and the first minimum width of the first gate contact and the second minimum width of the second gate contact are different from each other, and the first gate structure comprises a gate electrode and a gate capping layer on the gate electrode, wherein the height of the gate capping layer in the device region is smaller than the height of the gate capping layer in the field region. Claim 8 An integrated circuit device according to claim 7, wherein, with respect to the upper surface of the substrate, the uppermost level of the gate capping layer within the device region is lower than the uppermost level of the gate capping layer within the field region. Claim 9 A substrate including a device region and a field region; active regions extending in a first direction in the device region; a first gate electrode extending in a second direction intersecting the first direction in the device region and the field region; a first gate capping layer on the first gate electrode; a second gate electrode spaced apart from the first gate electrode in the first direction; a second gate capping layer on the second gate electrode; a first gate contact connected to the first gate electrode by penetrating the first gate capping layer in the device region; a second gate contact connected to the second gate electrode by penetrating the second gate capping layer in the field region; and a source / drain region disposed on the active region. An integrated circuit device comprising a source / drain contact disposed on the source / drain region, wherein the first minimum width of the first gate contact is greater than the second minimum width of the second gate contact, and the source / drain contact comprises a first portion having a first height and a second portion having a second height greater than the first height, and the first height of the first gate contact and the second height of the second gate contact are different. Claim 10 delete

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