Semiconductor package including redistribution substrate and method of manufacturing the same

Abstract

The present invention provides a semiconductor package and a method for manufacturing the same. The semiconductor package comprises: a conductive structure including a lower conductive pattern and a redistribution structure electrically connected to the lower conductive pattern on the lower conductive pattern; an insulating structure covering at least one side of the lower conductive pattern and the side of the redistribution structure; and a protective layer disposed between at least one of the lower conductive pattern and the insulating structure and between the redistribution structure and the insulating structure; a semiconductor chip disposed on the redistribution substrate; and a lower connection pattern electrically connected to the lower conductive pattern on the lower side of the redistribution substrate, wherein the protective layer comprises a first protective layer in contact with at least one of the side of the lower conductive pattern and the side of the redistribution structure, and a second protective layer in contact with at least a portion of the side of the first protective layer.

Description

Technology Field

[0001] The present invention relates to a semiconductor package including a redistribution substrate and a method for manufacturing the same. Background Technology

[0003] Generally, a semiconductor package may consist of a printed circuit board and a semiconductor chip mounted on the printed circuit board. This type of semiconductor package structure presents difficulties in reliably packaging semiconductor chips that require recent multifunctionality and high performance. The problem to be solved

[0005] One of the technical problems that the technical concept of the present invention aims to solve is to provide a reliable semiconductor package.

[0006] One of the technical problems that the technical concept of the present invention aims to solve is to provide a method for manufacturing a semiconductor package. means of solving the problem

[0008] A semiconductor package according to one embodiment of the technical concept of the present invention is provided. The semiconductor package comprises: a conductive structure including a lower conductive pattern and a redistribution structure electrically connected to the lower conductive pattern on the lower conductive pattern; an insulating structure covering at least one side of the lower conductive pattern and the side of the redistribution structure; and a protective layer disposed between at least one of the lower conductive pattern and the insulating structure and between the redistribution structure and the insulating structure; a semiconductor chip disposed on the redistribution substrate; and a lower connection pattern electrically connected to the lower conductive pattern on the lower side of the redistribution substrate, wherein the protective layer comprises a first protective layer in contact with at least one of the side of the lower conductive pattern and the side of the redistribution structure, and a second protective layer in contact with at least a portion of the side of the first protective layer.

[0010] A method for manufacturing a semiconductor package according to one embodiment of the technical concept of the present invention is provided. The semiconductor package manufacturing method comprises forming a lower conductive pattern on a carrier; forming a first protective layer covering the side of the lower conductive pattern and a second protective layer covering the side of the first protective layer on the carrier, and forming a structure including an insulating structure and a redistribution structure on the first and second protective layers; mounting a semiconductor chip on the structure; and removing the carrier to expose the lower conductive pattern. Effects of the invention

[0012] According to embodiments of the technical concept of the present invention, a redistribution substrate may include a lower conductive pattern, a redistribution structure on the lower conductive pattern, an insulating structure covering the side of the lower conductive pattern and the redistribution structure, and a protective layer between the lower conductive pattern and the insulating structure. The protective layer may serve to protect the lower conductive pattern by preventing the lower conductive pattern from peeling off. Accordingly, since the protective layer can prevent defects caused by the peeling off of the lower conductive pattern, the reliability of the semiconductor package can be improved.

[0013] The various and beneficial advantages and effects of the present invention are not limited to those described above and will be more easily understood in the process of explaining specific embodiments of the present invention. Brief explanation of the drawing

[0015] FIG. 1 is a cross-sectional view showing a semiconductor package according to one embodiment of the present invention. Figure 2 is a magnified view of a portion showing an exemplary example of the part marked 'A' in Figure 1. FIG. 3 is a cross-sectional view showing a modified example of a semiconductor package according to one embodiment of the present invention. Figure 4 is a magnified view of an exemplary example of the part marked 'B' in Figure 3. FIGS. 5 to 15 are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. Specific details for implementing the invention

[0016] Hereinafter, embodiments of the present invention will be described as follows with reference to the attached drawings.

[0017] First, a semiconductor package (1) according to an embodiment of the present invention will be described with reference to FIGS. 1 and FIGS. 2. FIGS. 1 is a cross-sectional view showing a semiconductor package according to an embodiment of the present invention, and FIGS. 2 is a partial enlarged view showing an exemplary example of the part marked 'A' in FIGS. 1.

[0019] Referring to FIGS. 1 and FIGS. 2, a semiconductor package (1) according to one embodiment may include a redistribution substrate (60) and a semiconductor chip (100) on the redistribution substrate (60).

[0020] The above-mentioned rewiring substrate (60) may include a conductive structure (55), a protective layer (10a), and an insulating structure (45). The semiconductor chip (100) may be one or a plurality of. The semiconductor chip (100) may include at least one of a logic chip and a memory chip. For example, the semiconductor chip (100) may include a microprocessor such as a central processor unit (CPU), a graphics processor unit (GPU), an application processor (AP), a logic chip such as a field programmable gate array (FPGA) or an application-specific IC (ASIC), or a memory chip. The memory chip may be a volatile memory chip or a non-volatile memory chip. For example, the volatile memory chip may include a dynamic random access memory (DRAM), static RAM (SRAM), thyristor RAM (TRAM), zero capacitor RAM (ZRAM), or twin transistor RAM (TTRAM). In addition, the non-volatile memory chip may include, for example, flash memory, MRAM (magnetic RAM), STT-MRAM (spin-transfer torque MRAM), FRAM (ferroelectric RAM), PRAM (phase change RAM), RRAM (resistive RAM), nanotube RRAM, polymer RAM, nano floating gate memory, holographic memory, molecular electronics memory, or insulator resistance change memory.

[0021] The insulating structure (45) may include a first insulating layer (15), a second insulating layer (25) on the first insulating layer (15), and a third insulating layer (40) on the second insulating layer (25). Although the insulating structure (45) is illustrated with three insulating layers (15, 25, 40), the embodiment is not limited thereto and may be composed of two or four or more insulating layers.

[0022] The insulating structure (45) may include a polymer material. At least one of the first to third insulating layers (15, 25, 40) may be formed of a polymer material. For example, at least one of the first to third insulating layers (15, 25, 40) may include a photoimageable dielectric (PID). For example, the PID may include a photosensitive polyimide material or a photosensitive PBO (polybenzoxazole).

[0023] The conductive structure (55) may include a lower conductive pattern (5) and a redistribution structure (35) on the lower conductive pattern (5). The conductive structure (55) may further include an upper conductive pattern (50) on the redistribution structure (35). The lower conductive pattern (5) may be multiple. The upper conductive pattern (50) may be multiple.

[0024] The lower conductive pattern (5) may include a lower surface (5L), an upper surface (5U), and a side surface (5S). The first insulating layer (15) may surround the side surface (5S) of the lower conductive pattern (5) and cover at least a portion of the upper surface (5U) of the lower conductive pattern (5). The lower surface of the insulating structure (45), i.e., the lower surface (15L) of the first insulating layer (15), is substantially the same as the lower surface (5L) of the lower conductive pattern (5). They can be placed at the same level. For example, the lower surface (15L) of the first insulating layer (15) can be coplanar with the lower surface (5L) of the lower conductive pattern (5).

[0025] Throughout the specification, the term "level" may be used to compare relative positions when viewed with respect to the attached drawings of the cross-sectional structure. Therefore, in the following, even without a separate explanation or definition of the term "level," it may be understood in relation to the attached drawings of the cross-sectional structure.

[0026] The lower conductive pattern (5) may be formed by a seed metal layer (4a) and a metal material pattern (4b) that are stacked in sequence. The seed metal layer (4a) may include a Ti material, a Ti / Cu material, or a Ti / W / Cu material. The metal material pattern (4b) may include a Cu material.

[0027] The thickness of the seed metal layer (4a) may differ from the thickness of the metal material pattern (4b). The thickness of the seed metal layer (4a) may be smaller than the thickness of the metal material pattern (4b). The thickness of the seed metal layer (4a) may be substantially the same as the thickness of the first protective layer (9a) described later.

[0029] The protective layer (10a) may be placed between the side (5S) of the lower conductive pattern (5) and the insulating structure (45). The protective layer (10a) may be placed so as to cover only the side (5S) of the lower conductive pattern (5) and not the upper surface (5U) of the lower conductive pattern (5). The protective layer (10a) may act as an adhesive to bond the lower conductive pattern (5) and the insulating structure (45). Therefore, the protective layer (10a) may be referred to as an 'adhesive layer'.

[0030] The protective layer (10a) can serve to protect the lower conductive pattern (5) by preventing the lower conductive pattern (5) from peeling off. Therefore, since the protective layer (10a) can prevent defects caused by the peeling off of the lower conductive pattern (5), the reliability of the semiconductor package (1) can be improved.

[0031] The above protective layer (10a) may be formed as a multilayer structure. For example, the protective layer (10a) may be a structure in which a first protective layer (9a) and a second protective layer (9b) are sequentially stacked on the side (5S) of the lower conductive pattern (5).

[0032] The first protective layer (9a) may be positioned to be in direct contact with the side (5S) of the lower conductive pattern (5) and to surround the side (5S) of the lower conductive pattern (5). The first protective layer (9a) may be used as a seed metal layer to form the second protective layer (9b). The first protective layer (9a) may be formed of a conductive material. For example, the first protective layer (9a) may include a Ti material, a Ti / W material, or a Ti / W / Cu material. The material of the first protective layer (9a) is not limited to the types described above and may be replaced with other conductive materials. According to an embodiment, the first protective layer (9a) may be made of substantially the same material as the seed metal layer (4a).

[0033] The bottom (10BEA) of the first protective layer (9a) is substantially the lower surface (5L) of the lower conductive pattern (5). They can be placed at the same level. The bottom (10BEA) of the first protective layer (9a) can be in contact with the seed metal layer (4a) of the lower conductive pattern (5).

[0034] The top (10UEA) of the first protective layer (9a) is substantially the upper surface (5U) of the lower conductive pattern (5). They can be placed at the same level. The top (10UEA) of the first protective layer (9a) can come into contact with the metal material pattern (4b) of the lower conductive pattern (5).

[0035] The first protective layer (9a) may be formed to have a substantially uniform thickness (T1). The thickness (T1) of the first protective layer (9a) is approximately 10 to about 100 It can be within the range of.

[0037] The second protective layer (9b) may be positioned to be in direct contact with a portion of the side of the first protective layer (9a) and to surround the side of the first protective layer (9a). That is, a portion of the second protective layer (9b) may be in contact with the side of the first protective layer (9a), while the other portion may not be in contact with the first protective layer (9a). The second protective layer (9b) may be used as a blocking layer to prevent oxide material from penetrating into the lower conductive pattern (5) and causing the lower conductive pattern (5) to oxidize. The second protective layer (9b) may be formed of an insulating material. For example, the second protective layer (9b) may include at least one of SiO2 and SiN. The material of the second protective layer (9b) is not limited to the types described above and may be replaced with other materials having insulating properties.

[0038] The bottom (10BEB) of the second protective layer (9b) can be positioned at a higher level than the bottom surface of the insulating structure (45), that is, the bottom surface (15L) of the first insulating layer (15).

[0039] The top (10UEB) of the second protective layer (9b) can be positioned at a higher level than the top (10UEA) of the first protective layer (9a).

[0041] The second protective layer (9b) may be formed to have a substantially uniform thickness (T2). The thickness (T2) of the second protective layer (9b) may be formed to be thicker than the thickness (T1) of the first protective layer (9a). The thickness (T2) of the second protective layer (9b) is approximately 100 to about 1000 It may be within the range of. The thickness (T2) of the second protective layer (9b) is 100 In the case of less than that, the blocking rate of oxide material penetrating through the second protective layer (9b) is lowered, and the effect of preventing oxidation of the lower conductive pattern (5) may be reduced.

[0043] The above-described redistribution structure (35) may include a plurality of redistribution patterns (20, 30) arranged at different height levels. For example, the plurality of redistribution patterns (20, 30) may include a lower redistribution pattern (20) and an upper redistribution pattern (30). Although FIG. 1 illustrates two redistribution patterns arranged at different levels, embodiments of the present invention are not limited thereto and may include three or more redistribution patterns arranged at different levels. For example, one or more redistribution patterns having a structure similar to the upper redistribution pattern may be arranged between the lower redistribution pattern (20) and the upper redistribution pattern (30).

[0044] The lower redistribution pattern (20) may include a redistribution via (20v) penetrating the first insulating layer (15) and a redistribution line (20i) extending from the redistribution via (20v) and disposed on the first insulating layer (15). In the lower redistribution pattern (20), the redistribution via (20v) penetrates the first insulating layer (15) and may come into contact with the upper surface (5U) of the lower conductive pattern (5). The redistribution via (20v) may have a width smaller than the width of the conductive pattern (5).

[0045] The lower redistribution pattern (20) may be formed by a seed metal layer (18a) and a metal material pattern (18b) that are stacked in sequence. The seed metal layer (18a) may include a Ti / Cu material or a Ti / W / Cu material. The metal material pattern (18b) may include a Cu material.

[0046] The upper redistribution pattern (30) may include a redistribution via (30v) that penetrates the second insulating layer (25) and is electrically connected to the lower redistribution pattern (20), and a redistribution line (30i) that extends from the redistribution via (30v) and is disposed on the second insulating layer (25). In the upper redistribution pattern (30), the redistribution via (30v) may penetrate the second insulating layer (25) and come into contact with the lower redistribution pattern (20). The upper redistribution pattern (30) may be formed by a seed metal layer (28a) and a metal material pattern (28b) that are stacked in sequence. The seed metal layer (28a) may include a Ti / Cu material or a Ti / W / Cu material. The metal material pattern (28b) may include a Cu material. The third insulating layer (40) may cover the upper surface and the side surface of the upper redistribution pattern (30).

[0047] The upper conductive pattern (50) may include a pad portion (50b) positioned at a level higher than the upper surface of the insulating structure (45), i.e., the upper surface (40U) of the third insulating layer (40), and a via portion (50v) extending downward from at least a portion of the pad portion (50b) and electrically connected to the redistribution structure (35). The insulating structure (45) may cover the side of the via portion (50v).

[0048] In the upper conductive pattern (50), the via portion (50v) penetrates the third insulating layer (40) and can be electrically connected to the upper redistribution pattern (30). The pad portion (50b) may also be referred to as a bump portion.

[0049] The upper conductive pattern (50) may be formed by a seed metal layer (48a) and a metal material pattern (48b) that are stacked in sequence. The seed metal layer (48a) may include a Ti / Cu material or a Ti / W / Cu material. The metal material pattern (48b) may include a Cu material, a Ni material, an Au material, or a mixed material comprising at least two of these.

[0050] The semiconductor package (1) may further include a lower connection pattern (150) below the redistribution substrate (60) and an upper connection pattern (120) between the redistribution substrate (60) and the semiconductor chip (100).

[0051] The lower connection pattern (150) may be electrically connected to the lower conductive pattern (5) of the redistribution board (60). The upper connection pattern (120) may be electrically connected to the upper conductive pattern (50) of the redistribution board (60) and the pad (105) of the semiconductor chip (100). The pad (105) of the semiconductor chip (100) may also be referred to as a bump. The upper connection pattern (120) may come into contact with the upper conductive pattern (50) of the redistribution board (60) and may come into contact with the pad (105) of the semiconductor chip (100).

[0052] The upper connection pattern (120) may have a land, ball, or pin shape. The upper connection pattern (120) may be formed of a low-melting-point metal. For example, the upper connection pattern (120) may include a solder material, for example, an alloy containing tin (Sn) (e.g., Sn-Ag-Cu, etc.).

[0053] The lower connection pattern (150) may include a low-melting-point metal, for example, tin (Sn) or an alloy containing tin (Sn-Ag-Cu). The lower connection pattern (150) may be a land, a ball, or a pin. The lower connection pattern (150) may include a copper pillar or a solder ball.

[0054] The semiconductor package (1) may further include an underfill resin (130) that is disposed between the redistribution substrate (60) and the plurality of semiconductor chips (100) and surrounds the side of the upper connection pattern (150). The underfill resin (130) may include an insulating resin such as epoxy resin.

[0055] The semiconductor package (1) may further include a sealing material (140) that surrounds at least the side of the semiconductor chip (100) on the redistribution substrate (60). The sealing material (140) surrounds the side of the semiconductor chip (100) and may cover the upper surface of the semiconductor chip (100).

[0056] The above sealant (140) may include an insulating material, such as a resin like EMC (epoxy molding compound) or ABF (Ajinomoto Build-up Film).

[0057] The above underfill resin (130) may be formed in a Molded Under-fill (MUF) manner and may constitute part of the above suture material (140).

[0058] In the above-described embodiment, the redistribution substrate (60) may have a first surface (40U) and a second surface (15L) facing each other, the semiconductor chip (100) may be placed on the first surface (40U) of the redistribution substrate (60), and the lower connection pattern (150) may be placed below the second surface (15L) of the redistribution substrate (60).

[0060] Next, examples of modifications to some components of the semiconductor package (1) described above will be explained. Hereinafter, the components of the semiconductor package (1) that can be modified or replaced will be described in detail, and the remaining components will be omitted from the description or described by direct reference as components that can be modified.

[0061] A semiconductor package (2) according to a modified example will be described with reference to FIGS. 3 and FIGS. 4. FIGS. 3 is a cross-sectional view showing a modified example of a semiconductor package according to one embodiment of the present invention, and FIGS. 4 is a partial enlarged view showing an exemplary example of the part marked 'B' in FIGS. 3.

[0062] While the semiconductor package (1) described above has the protective layer (10a) formed only on the side (5S) of the lower conductive pattern (5), the semiconductor package (2) of the modified example has the difference that the protective layer (10a, 20a, 30a) is formed on the side (5S) of the lower conductive pattern (5) and on the side of the redistribution structure (35), respectively. In the case of the modified example of FIG. 3, the case where the protective layer (10a, 20a, 30a) is formed on both the side (5S) of the lower conductive pattern (5) and the side of the redistribution structure (35) was described as an example, but depending on the embodiment, the protective layer (20a, 30a) may be formed only on the side of the redistribution structure (35), and the protective layer (20a, 30a) may be formed only on some of the redistribution structures (35). That is, a protective layer (20a, 30a) may be formed on only one of the lower redistribution pattern (20) and the upper redistribution pattern (30). Below, only the protective layer (20a, 30a) formed on the side of the redistribution structure (35) will be described. Since the protective layer (20a, 30a) has the same configuration as the protective layer (10a) described earlier, a detailed description is omitted.

[0064] Referring to FIGS. 3 and 4, the protective layer (20a, 30a) may be formed on the side (20S) of the lower redistribution pattern (20) and the side (30S) of the upper redistribution pattern (30), respectively. The protective layer (20a, 30a) may be formed in a multilayer structure, similar to the protective layer (10a) described earlier. That is, the protective layer (20a) may have a structure in which a first protective layer (19a) and a second protective layer (19b) are stacked sequentially on the side (20S) of the lower redistribution pattern (20). The protective layer (30a) may have a structure in which a first protective layer (29a) and a second protective layer (29b) are stacked sequentially on the side (30S) of the upper redistribution pattern (30).

[0066] The lower portion (20BEA, 30BEA) of the first protective layer (19a, 29a) is substantially with respect to the lower surface of the lower redistribution pattern (20) and the redistribution line (20i, 30i), respectively. They can be placed at the same level. The bottom (20BEA, 30BEA) of the first protective layer (19a, 29a) can each come into contact with the seed metal layer (28a, 29a) of the lower redistribution pattern (20) and the upper redistribution pattern (30).

[0067] The upper surface (20UEA, 30UEA) of the first protective layer (19a, 29a) is substantially with respect to the upper surface of the redistribution line (20i, 30i), respectively. They can be placed at the same level. The top (20UEA, 30UEA) of the first protective layer (19a, 29a) can each come into contact with the metal material pattern (18b, 28b) of the lower conductive pattern (5).

[0068] The bottom (20BEB, 20BEB) of the second protective layer (19b, 29b) can each be positioned at a higher level than the bottom surface of the insulating structure (45), that is, the bottom surface of the second and third insulating layers (25, 40).

[0069] The bottom (20BEB, 20BEB) of the second protective layer (19b, 29b) may each be positioned at a higher level than the top (20UEA, 30UEA) of the first protective layer (19a, 29a).

[0070] The protective layer (20a, 30a) can prevent the lower redistribution pattern (20) and the upper redistribution pattern (30) from peeling off, thereby protecting the lower redistribution pattern (20) and the upper redistribution pattern (30). Therefore, since the protective layer (20a, 30a) can prevent defects caused by the peeling off of the lower redistribution pattern (20) and the upper redistribution pattern (30), the reliability of the semiconductor package (2) can be improved.

[0072] Next, with reference to FIGS. 5 to 15, an exemplary example of a method for manufacturing a semiconductor package according to one embodiment of the present invention will be described.

[0073] Referring to FIG. 5, a lower conductive pattern (5) can be formed on a carrier (1000). The lower conductive pattern (5) can be formed in the same shape as the lower conductive pattern (5) described with reference to FIG. 1 and FIG. 2. Multiple lower conductive patterns (5) can be formed. The lower conductive pattern (5) can be formed by a seed metal layer (4a) and a metal material pattern (4b) that are stacked in sequence.

[0074] A conductive material layer (9L1) and an insulating material layer (9L2) can be sequentially laminated to cover the lower conductive pattern (5). The conductive material layer (9L1) is intended to form the first protective layer (9a) in a subsequent process, and the insulating material layer (9L2) is intended to form the second protective layer (9b) in a subsequent process. The conductive material layer (9L1) and the insulating material layer (9L2) may be formed from the same material as the first protective layer (9a) and the second protective layer (9b) described with reference to FIGS. 1 and 2.

[0075] The conductive material layer (9L1) can be formed by a PVD process, and the insulating material layer (9L2) can be formed by a CVD process.

[0076] In one example, the thickness of the portion covering the upper surface of the lower conductive pattern (5) and the surface of the carrier (1000) that does not overlap with the lower conductive pattern (5) may be greater than the thickness of the portion covering the side of the lower conductive pattern (5).

[0077] In another example, the conductive material layer (9L1) and the insulating material layer (9L2) can each be formed with a substantially uniform thickness.

[0079] Referring to FIG. 6, the insulating material layer (9L2) can be dry-etched (E1) to remove the area of ​​the insulating material layer (9L2) excluding the area covering the side (9L1S) of the conductive material layer (9L1). When dry-etching is performed, the insulating material layer (9L2) is anisotropically etched in a direction perpendicular to the carrier substrate (1000), so that only the area covering the side (9L1S) of the conductive material layer (9L1) of the insulating material layer (9L2) remains, and the remaining area is removed. Thus, the upper surface of the lower conductive pattern (5) and the conductive material layer (9L1) stacked on the upper surface of the carrier substrate (1000) can be exposed. Through this, a second protective layer (9b) can be formed. Since the insulating material layer (9L2) is dry-etched while the conductive material layer (9L2) covers the lower conductive pattern (5), the lower conductive pattern (5) is exposed during the dry-etching process, thereby preventing the chamber where the dry-etching process is performed from being contaminated by the material of the lower conductive pattern (5).

[0081] Referring to FIG. 7, the conductive material layer (9L1) can be wet-etched (E2) to remove the area excluding the area covering the side of the lower conductive pattern (5). Wet-etching can be performed using a material with a high etching selectivity ratio for the conductive material layer (9L1). Thus, the conductive material layer (9L1) can be etched and removed while minimizing the etching of the second protective layer (9b) formed in the previous process. When wet-etching is performed, the conductive material layer (9L1) is isotropically etched so that the area of ​​the conductive material layer (9L1) in contact with the upper surface (5U) of the lower conductive pattern (5) and the area in contact with the carrier substrate (1000) can all be removed. Through this, only the area covered by the second protective layer (9b) remains, so that the first protective layer (9a) can be formed spaced apart from the upper surface (1000L) of the carrier substrate (1000).

[0083] Referring to FIG. 8, a first insulating layer (15) may be formed on the protective layer (10), and an opening (15o) may be formed that penetrates the first insulating layer (15) and exposes a portion of the lower conductive pattern (5). The first insulating layer (15) may be the same as the first insulating layer (15) described in FIG. 1.

[0085] Referring to FIG. 9, a lower redistribution pattern (20) can be formed, comprising a redistribution via (20v) that fills the opening (15o) and contacts the lower conductive pattern (5), and a redistribution line (20i) that extends from the redistribution via (20v) and is disposed on the first insulating layer (15). The lower redistribution pattern (20) can be formed using a plating process. For example, forming the lower redistribution pattern (20) may include forming a seed metal layer (18a), forming a metal material pattern (18b) on the seed metal layer (18a) by a plating process, and patterning the seed metal layer (18a) and the metal material pattern (18b).

[0087] Referring to FIG. 10, a conductive material layer (19L1) and an insulating material layer (19L2) can be sequentially laminated to cover the lower redistribution pattern (20) in substantially the same process as performed in FIG. 5. The conductive material layer (19L1) and the insulating material layer (19L2) can be formed in the same shape and with the same material as the conductive material layer (9L1) and the insulating material layer (9L2) described with reference to FIG. 5.

[0089] Referring to FIG. 11, a dry etching process and a wet etching process, substantially identical to those performed in FIG. 6 and FIG. 7, can be performed to form a protective layer (20a) including a first protective layer (19a) and a second protective layer (19b) on the side of the lower redistribution pattern (20).

[0091] Referring to FIG. 12, a second insulating layer (25) covering the lower redistribution pattern (20) can be formed on the first insulating layer (15), and an opening (25o) penetrating the second insulating layer (25) and exposing a part of the lower redistribution pattern (20) can be formed. The second insulating layer (25) may be the same as the first insulating layer (25) described in FIG. 1.

[0093] Referring to FIG. 13, an upper redistribution pattern (30) can be formed, comprising a redistribution via (30v) that fills the opening (25o) and contacts the lower redistribution pattern (20), and a redistribution line (30i) that extends from the redistribution via (30v) and is formed on the second insulating layer (25). The upper redistribution pattern (30) can be formed by substantially the same process as the lower redistribution pattern (20). The upper redistribution pattern (30) may include a seed metal layer (28a) and a metal material pattern (28b) stacked in sequence. Thus, a redistribution structure (35) comprising the lower redistribution pattern (20) and the upper redistribution pattern (30) as described in FIG. 1 can be formed.

[0094] A protective layer (30a) including a first protective layer (29a) and a second protective layer (29b) may be formed on the side of the upper redistribution pattern (30). The protective layer (30a) may be formed using substantially the same process as the protective layer (20a) of the upper redistribution pattern (30).

[0095] A third insulating layer (40) covering the upper redistribution pattern (30) can be formed on the second insulating layer (25). Thus, an insulating structure (45) comprising the first to third insulating layers (15, 25, 40) as described in FIG. 1 can be formed.

[0096] An upper conductive pattern (50) can be formed, comprising a via portion (50v) penetrating the third insulating layer (40) and contacting the upper redistribution pattern (30), and a pad portion (50b) extending from the via portion (50v) and formed on the third insulating layer (40). The upper conductive pattern (50) can be formed by a seed metal layer (48a) and a metal material pattern (48b) that are stacked in sequence. Thus, a conductive structure (55) can be formed, comprising the lower conductive pattern (5), the redistribution structure (35), and the upper conductive pattern (50) as described in FIG. 1.

[0098] Referring to FIG. 14, a semiconductor chip (100) can be prepared. The semiconductor chip (100) may be the same as the semiconductor chip (100) in FIG. 1.

[0099] The semiconductor chip (100) can be mounted on a structure including the insulating structure (45) and the conductive structure (55). For example, the semiconductor chip (100) may include a pad (105), and the pad (105) of the semiconductor chip (100) and the upper conductive pattern (50) may be joined using an upper connecting pattern (120). The upper connecting pattern (120) may include a solder material. For example, the upper connecting pattern (120) joined to the pad (105) of the semiconductor chip (100) and the upper conductive pattern (50) may be formed using a solder reflow process. An underfill resin (130) surrounding the side of the upper connecting pattern (120) may be formed between the insulating structure (45) and the semiconductor chip (100). A sealing material (140) covering at least the side of the semiconductor chip (100) can be formed on the insulating structure (45).

[0101] Referring to FIG. 15, the carrier (1000 in FIG. 15) can be removed to expose the lower end of the first protective layer (9a) in contact with the lower surface of the first insulating layer (15), and at the same time, the seed metal layer (4a) of the lower conductive pattern (5) can be exposed.

[0103] Again, referring to FIG. 1, a lower connecting pattern (150) can be formed in contact with the lower surface of the lower conductive pattern (5) and the bottom of the protective layer (10a). The lower connecting pattern (150) can be formed with a solder ball.

[0105] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing its technical concept or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0107] 1: Semiconductor package 5: Underlying conductive pattern 10a: Protective layer 15: First insulating layer 25: Second insulation layer 40: Third insulation layer 45: Insulating structure 20: Bottom redistribution pattern 30: Upper redistribution pattern 35: Redistribution structure 45: Insulating structure 50: Upper conductive pattern 55: Conductive structure 60: Redistribution board 100: Semiconductor chip 120: Upper connection pattern 130: Underfill resin 140: Suture material 150: Lower connection pattern

Claims

Claim 1 A redistribution substrate comprising: a conductive structure including a lower conductive pattern and a redistribution structure electrically connected to the lower conductive pattern on the lower conductive pattern; an insulating structure covering at least one side of the lower conductive pattern and the side of the redistribution structure; and a protective layer disposed between at least one of the lower conductive pattern and the insulating structure and between the redistribution structure and the insulating structure; a semiconductor chip disposed on the redistribution substrate; and a semiconductor package comprising a lower connection pattern electrically connected to the lower conductive pattern on the lower side of the redistribution substrate, wherein the protective layer comprises a first protective layer in contact with at least one of the side of the lower conductive pattern and the side of the redistribution structure, and a second protective layer in contact with at least a portion of the side of the first protective layer, wherein the bottom of the first protective layer is disposed at the same level as the bottom surface of the insulating structure, and the bottom of the second protective layer is disposed at a level higher than the bottom surface of the insulating structure. Claim 2 A semiconductor package according to claim 1, wherein the first protective layer comprises a conductive material and the second protective layer comprises an insulating material. Claim 3 In claim 1, the lower conductive pattern comprises a seed metal layer and a metal material pattern on the seed metal layer, and the seed metal layer of the lower conductive pattern is in contact with the first protective layer in a semiconductor package. Claim 4 In paragraph 3, the seed metal layer of the lower conductive pattern and the first protective layer comprise the same material in a semiconductor package. Claim 5 A semiconductor package according to paragraph 3, wherein the lower end of the first protective layer contacts the seed metal layer of the lower conductive pattern, and the upper end of the first protective layer contacts the metal material pattern of the lower conductive pattern. Claim 6 A semiconductor package according to paragraph 2, wherein the portion of the side of the second protective layer that contacts the side of the first protective layer extends beyond the top of the side of the first protective layer, and the distance between the top of the side of the second protective layer and the semiconductor chip is smaller than the distance between the top of the side of the first protective layer and the semiconductor chip. Claim 7 A semiconductor package according to claim 1, wherein the upper surface of the first protective layer is positioned at the same level as the upper surface of the lower conductive pattern, and the upper surface of the second protective layer is positioned at a higher level than the upper surface of the first protective layer. Claim 8 In claim 1, the redistribution structure comprises a redistribution line and a redistribution pattern including a redistribution via extending downward from a part of the redistribution line and contacting the lower conductive pattern, wherein the redistribution via has a width smaller than the width of the lower conductive pattern, and the semiconductor package. Claim 9 A method for manufacturing a semiconductor package comprising: forming a lower conductive pattern on a carrier; forming a first protective layer on the carrier that covers the side of the lower conductive pattern; forming a second protective layer that covers the side of the first protective layer; forming a structure including an insulating structure and a redistribution structure on the first and second protective layers; mounting a semiconductor chip on the structure; and removing the carrier to expose the lower conductive pattern, wherein the bottom of the first protective layer is positioned at the same level as the bottom surface of the insulating structure, and the bottom of the second protective layer is positioned at a higher level than the bottom surface of the insulating structure. Claim 10 A method for manufacturing a semiconductor package according to claim 9, wherein forming the first protective layer and the second protective layer comprises forming a conductive material layer on the carrier to cover the lower conductive pattern, forming an insulating material layer on the conductive material layer, dry-etching the insulating material layer to remove an area excluding the area covering the side of the conductive material layer, and wet-etching the conductive material layer to remove an area excluding the area covering the side of the lower conductive pattern.

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