Image sensor including stakced chips

Abstract

An image sensor is provided. The image sensor comprises a first lower chip; and an upper chip bonded to the first lower chip on the first lower chip. The first lower chip and the upper chip share a plurality of pixels, and each of the plurality of pixels includes a photoelectric conversion element, a floating diffusion region, a ground region, and a transmission gate disposed within the upper chip; and a plurality of lower transistors disposed within the first lower chip, wherein the first lower transistor among the plurality of lower transistors includes a plurality of first channel layers stacked vertically, and a first gate that spans the plurality of first channel layers and surrounds each of the plurality of first channel layers.

Description

Technology Field

[0001] The present invention relates to an image sensor comprising stacked chips. Background Technology

[0003] An image sensor is a semiconductor-based sensor that receives light and generates an electrical signal, and may include a pixel array having multiple pixels and a logic circuit for driving the pixel array and generating an image. Each pixel may include a photodiode and a pixel circuit that converts a charge generated by the photodiode into an electrical signal. The problem to be solved

[0005] One of the technical problems that the technical concept of the present invention aims to solve is to provide an image sensor capable of increasing integration density and improving performance by placing pixel circuits on a lower chip and an upper chip. means of solving the problem

[0007] An image sensor according to one embodiment of the technical concept of the present invention is provided. The image sensor comprises a first lower chip; and an upper chip bonded to the first lower chip on the first lower chip. The first lower chip and the upper chip share a plurality of pixels, and each of the plurality of pixels includes a photoelectric conversion element, a floating diffusion region, a ground region, and a transmission gate disposed within the upper chip; and a plurality of lower transistors disposed within the first lower chip, wherein the first lower transistor among the plurality of lower transistors includes a plurality of first channel layers stacked vertically, and a first gate that spans the plurality of first channel layers and surrounds each of the plurality of first channel layers.

[0009] An image sensor according to one embodiment of the technical concept of the present invention is provided. The image sensor comprises a first lower chip; an upper chip bonded to the first lower chip on the first lower chip; and a second lower chip bonded to the first lower chip below the first lower chip. The first lower chip and the upper chip include a pixel array comprising a plurality of pixels, and the second lower chip includes a control circuit for controlling the pixel array, and each of the plurality of pixels includes a photoelectric conversion element, a floating diffusion region, a ground region, a transmission gate, a reset transistor, a select transistor, and a driving transistor, and the upper chip includes the photoelectric conversion element, the floating diffusion region, the ground region, and the transmission gate, and the first lower chip includes at least one transistor among the reset transistor, the select transistor, and the driving transistor, and the at least one transistor of the first lower chip is a first three-dimensional transistor comprising a plurality of first channel layers stacked vertically, and a first gate that spans the plurality of first channel layers and surrounds each of the plurality of first channel layers.

[0011] An image sensor according to an embodiment of the technical concept of the present invention is provided. The image sensor comprises a first lower chip; an upper chip bonded to the first lower chip on the first lower chip; and a second lower chip bonded to the first lower chip below the first lower chip. The first lower chip and the upper chip comprise a pixel array comprising a plurality of pixels, and the second lower chip comprises a control circuit for controlling the pixel array, and each of the plurality of pixels comprises a photoelectric conversion element, a floating diffusion region, a ground region, a transmission gate, a reset transistor, a selection transistor, and a driving transistor. The upper chip comprises the photoelectric conversion element, the floating diffusion region, the ground region, and the transmission gate. The first lower chip comprises at least one transistor among the reset transistor, the selection transistor, and the driving transistor. The upper chip comprises an upper semiconductor substrate having a first surface and a second surface facing each other; color filters on the second surface of the upper semiconductor substrate; and a pixel isolation structure within the upper semiconductor substrate. The upper insulating structure below the first surface of the upper semiconductor substrate; and upper junction pads embedded within the upper insulating structure and having lower surfaces that form a co-plane with the lower surface of the upper insulating structure are further included. The photoelectric conversion element is disposed within the upper semiconductor substrate between the pixel separation structures, and the floating diffusion region and the ground region are disposed within the upper semiconductor substrate adjacent to the first surface of the upper semiconductor substrate. The first lower chip further includes a first lower semiconductor substrate; a first lower insulating structure on the first lower semiconductor substrate; first lower junction pads embedded within the first lower insulating structure and having upper surfaces that form a co-plane with the upper surface of the first lower insulating structure; and a lower protective insulating layer below the first lower semiconductor substrate.The second lower chip further comprises a second lower semiconductor substrate; and a second lower insulating structure on the second lower semiconductor substrate. The first lower junction pads and the upper junction pads are joined while in contact with each other. The at least one transistor of the first lower chip is a first three-dimensional transistor comprising a plurality of first channel layers stacked vertically, and a first gate that spans the plurality of first channel layers and surrounds each of the plurality of first channel layers. Effects of the invention

[0013] According to embodiments of the technical concept of the present invention, an image sensor comprising an upper chip and a lower chip that are vertically joined can be provided. By dividing and arranging the elements constituting the pixel circuit of the image sensor between the upper chip and the lower chip, respectively, the size of each pixel included in the pixel array area can be reduced, and more pixels can be arranged within a pixel array of the same area. Accordingly, an image sensor capable of generating high-resolution images can be provided.

[0014] In addition, some of the transistors among the elements constituting the pixel circuit can be formed as high-performance transistors with a gate-all-around-gate structure.

[0015] The various and beneficial advantages and effects of the present invention are not limited to those described above and will be more easily understood in the process of explaining specific embodiments of the present invention. Brief explanation of the drawing

[0017] FIG. 1 is a simplified block diagram of an image sensor according to one embodiment of the present invention. FIG. 2 is a schematic perspective view of an image sensor according to one embodiment of the present invention. FIG. 3a is a diagram briefly illustrating an example of a pixel circuit of an image sensor according to one embodiment of the present invention. FIG. 3b is a diagram briefly illustrating another example of a pixel circuit of an image sensor according to one embodiment of the present invention. FIG. 4 is a top view schematically showing an example of an image sensor according to one embodiment of the present invention. FIGS. 5, FIGS. 6, FIGS. 7, FIGS. 8 and FIGS. 9 are schematic drawings illustrating an example of an image sensor according to an embodiment of the present invention. FIG. 10 is a schematic perspective view showing an example of a modified image sensor according to one embodiment of the present invention. FIG. 11 is a schematic perspective view showing an example of a modified image sensor according to one embodiment of the present invention. FIG. 12 is a cross-sectional view schematically showing an example of a modified image sensor according to one embodiment of the present invention. FIGS. 13 and FIGS. 14 are schematic drawings illustrating modified examples of an image sensor according to one embodiment of the present invention. FIG. 15 is a cross-sectional view schematically showing an example of a modified image sensor according to one embodiment of the present invention. FIG. 16 is a cross-sectional view schematically showing an example of a modified image sensor according to one embodiment of the present invention. FIG. 17 is a cross-sectional view schematically showing an example of a modified image sensor according to one embodiment of the present invention. Specific details for implementing the invention

[0018] In the following, terms such as 'top', 'upper part', 'upper surface', 'lower', 'lower part', 'lower surface', 'side surface', 'top', and 'bottom' may be understood as referring to the drawings, except where otherwise indicated by drawing symbols.

[0019] Referring to FIG. 1, an image sensor according to an embodiment of the present invention will be described. FIG. 1 is a simplified block diagram of an image sensor according to an embodiment of the present invention.

[0020] Referring to FIG. 1, the image sensor (1) may include a pixel array (10) and a logic circuit (20), etc.

[0021] The pixel array (10) may include a plurality of pixels (PX) arranged in an array form along a plurality of rows and a plurality of columns. Each of the plurality of pixels (PX) may include at least one photoelectric conversion element that generates a charge in response to light, and a pixel circuit that generates a pixel signal corresponding to the charge generated by the photoelectric conversion element. The photoelectric conversion element may include a photodiode formed of a semiconductor material, and / or an organic photodiode formed of an organic material. For example, the pixel circuit may include a floating diffusion transistor, a transfer transistor, a reset transistor, a driving transistor, and a selection transistor.

[0022] The configuration of the pixels (PX) may vary depending on the embodiments. In one example, each of the pixels (PX) may include an organic photodiode containing an organic material, or may be implemented as a digital pixel. If the pixels (PX) are implemented as digital pixels, each of the pixels (PX) may include an analog-to-digital converter for outputting a digital pixel signal.

[0023] The logic circuit (20) may include circuits for controlling the pixel array (10). In one example, the logic circuit (20) may include a row driver (21), a readout circuit (22), a column driver (23), control logic (24), etc. The row driver (21) may drive the pixel array (10) in units of row lines. For example, the row driver (21) may generate a transmission control signal that controls a transmission transistor of the pixel circuit, a reset control signal that controls a reset transistor, a selection control signal that controls a selection transistor, etc., and input them to the pixel array (10) in units of row lines.

[0024] The readout circuit (22) may include a Correlated Double Sampler (CDS), an Analog-to-Digital Converter (ADC), etc. The Correlated Double Samplers may be connected to pixels (PX) and column lines. The Correlated Double Samplers may read pixel signals through column lines from pixels (PX) connected to a row line selected by a row line selection signal of the row driver (21). The Analog-to-Digital Converter may convert the pixel signal detected by the Correlated Double Sampler into a digital pixel signal and transmit it to the column driver (23).

[0025] The column driver (23) may include a latch or buffer circuit capable of temporarily storing a digital pixel signal and an amplification circuit, and may process a digital pixel signal received from the readout circuit (22).

[0026] The row driver (21), the readout circuit (22), and the column driver (23) can be controlled by the control logic (24). The control logic (24) may include a timing controller for controlling the operation timing of the row driver (21), the readout circuit (22), and the column driver (23).

[0027] Among the above pixels (PX), pixels (PX) placed at the same position in the horizontal direction may share the same column line. For example, the above pixels (PX) placed at the same position in the vertical direction may be simultaneously selected by the row driver (21) and may output pixel signals through the column lines.

[0028] In one embodiment, the readout circuit (22) can simultaneously obtain pixel signals from pixels (PX) selected by the row driver (21) through column lines. The pixel signals may include a reset voltage and a pixel voltage, and the pixel voltage may be a voltage in which the charge generated in response to light at each of the pixels (PX) is reflected in the reset voltage.

[0030] With reference to FIG. 2 and FIG. 1, an example of an image sensor (1) according to an embodiment of the present invention will be described. FIG. 2 is a schematic perspective view showing an image sensor (1) according to an embodiment of the present invention.

[0031] Referring to FIGS. 1 and 2, the image sensor (1) may include a plurality of chips stacked in sequence. For example, the plurality of chips may include an upper chip (CH_U), a first lower chip (CH_L1) below the upper chip (CH_U), and a second lower chip (CH_L2) below the first lower chip (CH_L1).

[0032] The first lower chip (CH_L1) and the upper chip (CH_U) may include the pixel array (10), and the second lower chip (CH_L2) may include the logic circuit (20).

[0033] Accordingly, the elements of each of the pixels (PX in FIG. 1) constituting the pixel array (10) may be divided and arranged in the first lower chip (CH_L1) and the upper chip (CH_U). For example, the upper chip (CH_U) may include a first pixel area (PA1), and the first lower chip (CH_L1) may include a second pixel area (PA2) that overlaps vertically with the first pixel area (PA1).

[0034] The upper chip (CH_U) may further include a pad area (PAD) disposed on at least one side of the pixel array (10).

[0036] Next, together with FIGS. 1 and 2, with reference to FIG. 3a, an example of a pixel circuit of an image sensor (1) according to an embodiment of the present invention will be described. FIG. 3a is a diagram briefly illustrating an example of a pixel circuit of an image sensor according to an embodiment of the present invention.

[0037] Referring to FIG. 3a together with FIG. 1 and FIG. 2, each of the plurality of pixels (PX in FIG. 1) may include a photoelectric conversion element (PD) and a pixel circuit, and the pixel circuit may include a transfer transistor (TX), a reset transistor (RX), a select transistor (SX), and a driving transistor (DX), etc. Additionally, the pixel circuit may further include a floating diffusion region (FD) in which charge generated from the photoelectric conversion element (PD) is accumulated.

[0038] Hereinafter, the above-mentioned photoelectric conversion element (PD) will be described by referring to it as a photodiode, which is an example of the above-mentioned photoelectric conversion element (PD).

[0039] The above photodiode (PD) can generate and accumulate charge in response to light incident from the outside. Depending on the embodiments, the above photodiode (PD) may be replaced with a phototransistor, photogate, pinned photodiode, etc.

[0040] The transfer transistor (TX) can be turned on or turned off by a transfer control signal input to the transfer gate (TG). The transfer transistor (TX) can transfer the charge generated in the photodiode (PD) to the floating diffusion region (FD). The floating diffusion region (FD) can store the charge generated in the photodiode (PD). Depending on the amount of charge accumulated in the floating diffusion region (FD), the voltage output by the driving transistor (DX) may vary.

[0041] The reset transistor (RX) can reset the voltage of the floating diffusion region (FD) by removing the charge accumulated in the floating diffusion region (FD). The drain electrode of the reset transistor (RX) is connected to the floating diffusion region (FD), and the source electrode can be connected to the power supply voltage (VDD). When the reset transistor (RX) is turned on, the power supply voltage (VDD) connected to the source electrode of the reset transistor (RX) is applied to the floating diffusion region (FD), and the charge accumulated in the floating diffusion region (FD) can be removed by the reset transistor (RX).

[0042] The driving transistor (DX) can operate as a source follower buffer amplifier. The driving transistor (DX) can amplify the voltage change of the floating diffusion region (FD) and output it to one of the column lines (COL1, COL2). The select transistor (SX) can select the pixels (PX) to be read row by row. When the select transistor (SX) is turned on, the voltage of the driving transistor (DX) can be output to one of the column lines (COL1, COL2). For example, when the select transistor (SX) is turned on, a reset voltage or a pixel voltage can be output through the column lines (COL1, COL2).

[0043] Each of the above-mentioned plurality of pixels (PX) may further include a ground region (GND) capable of receiving a ground voltage. Accordingly, each of the above-mentioned plurality of pixels (PX) may include the ground region (GND), the photodiode (PD), the transmission transistor (TX), the reset transistor (RX), the select transistor (SX), and the driving transistor (DX).

[0044] In each of the plurality of pixels (PX), the transmission transistor (TX), including the ground region (GND), the photodiode (PD), and the transmission gate (TG), may be placed within the first pixel region (PA1) of the upper chip (CH_U) in FIG. 2, and the reset transistor (RX), the select transistor (SX), and the driving transistor (DX) may be placed within the second pixel region (PA2) of the upper chip (CH_U) in FIG. 2.

[0046] Next, with reference to FIG. 3b, another example of a pixel circuit of an image sensor (1) according to one embodiment of the present invention will be described. FIG. 3b is a diagram briefly illustrating another example of a pixel circuit of an image sensor according to one embodiment of the present invention.

[0047] With reference to FIG. 3b in conjunction with FIG. 1 and 2, two or more adjacent pixels may share at least some of the transistors included in the pixel circuit. For example, four adjacent pixels may share a reset transistor (RX), driving transistors (DX1, DX2), and a select transistor (SX).

[0048] Each of the four adjacent pixels may include a photodiode (PD1-PD4), a ground region (GND), a transmission transistor (TX1-TX4) having a transmission gate (TG1-TG4), and a floating diffusion region (FD1-FD4).

[0049] In one example, a first region (PA1a) in which the first pixel of the four pixels is placed may include a ground region (GND), a first photodiode (PD1), a first floating diffusion region (FD1), and a first transmission transistor (TX1) having a first transmission gate (TG1). In the first region (PA1a), the first photodiode (PD1) may be connected to the first floating diffusion region (FD1) through the first transmission transistor (TX1). Likewise, the second to fourth photodiodes (PD2-PD4) of the second to fourth regions (PA1b-PA1d) in which the second to fourth pixels of the four pixels are placed may be connected to the second to fourth floating diffusion regions (FD2-FD4) through second to fourth transmission transistors (TX2-TX4) each having second to fourth transmission gates (TG2-TG4).

[0050] In four adjacent pixels, the first to fourth floating diffusion regions (FD1-FD4) can be connected to each other by wiring or the like to operate as a single floating diffusion region (FD), and the first to fourth transmission transistors (TX1-TX4) can be commonly connected to the single floating diffusion region (FD) formed by connecting the first to fourth floating diffusion regions (FD1-FD4).

[0051] The pixel circuit may include the reset transistor (RX), the first and second driving transistors (DX1, DX2), and the select transistor (SX). The reset transistor (RX) may be controlled by a reset control signal (RG), and the select transistor (SX) may be controlled by a select control signal (SEL). For example, each of the four pixels (PX) may include one additional transistor in addition to the transfer transistor (TX). Among the four transistors included in the four pixels, two may be connected in parallel to provide the first and second driving transistors (DX1, DX2), one of the remaining two transistors may be provided as the select transistor (SX), and the other may be configured to provide the reset transistor (RX).

[0052] The pixel circuit described above with reference to FIG. 3b is merely one embodiment and is not necessarily limited to this form. For example, one of the four transistors may be assigned as a driving transistor and one as a selection transistor. Additionally, by connecting the remaining two in series and assigning them as first and second reset transistors, an image sensor capable of controlling the conversion gain of the pixel can be implemented. Alternatively, the pixel circuit may vary depending on the number of transistors included in each of the pixels (PX).

[0054] Next, with reference to FIG. 4, together with FIG. 1, FIG. 2, and FIG. 3a, a pixel (PX) within the first pixel area (PA1) of the upper chip (CH_U) will be described. FIG. 4 is a top view schematically showing a pixel (PX) within the first pixel area (PA1) of the upper chip (CH_U).

[0055] Referring to FIG. 4 together with FIG. 1, FIG. 2, and FIG. 3a, the image sensor (1) may further include a pixel separation region (PI) surrounding one pixel (PX) in a top view. The pixel (PX) may include a floating diffusion region (FD), a ground region (GND), and a transmission gate (TG).

[0056] The image sensor (1) may further include a device isolation region (STI) between the floating diffusion region (FD) and the ground region (GND).

[0057] The image sensor (1) may further include a floating diffusion contact (FD_C) electrically connected to the floating diffusion region (FD), a ground contact (GND_C) for grounding the ground region (GND), and a transmission gate contact (TG_) electrically connected to the transmission gate (TG).

[0059] Next, together with FIGS. 1, 2, and 3b, a plurality of pixels (PX) disposed within the first pixel area (PA1) of the upper chip (CH_U) will be described with reference to FIGS. 5 and 6. FIG. 5 is a top view schematically showing a plurality of pixels (PX) disposed within the first pixel area (PA1) of the upper chip (CH_U), and FIG. 6 is a cross-sectional view showing areas taken along the lines I-I', II-II' and III-III' of FIG. 5.

[0060] Referring to FIGS. 5 and 6 together with FIGS. 1, 2, and 3b, in the image sensor (1), the upper chip (CH_U) may further include a pixel separation region (PI) surrounding each of a plurality of pixels (PX) in a top view. Each of the plurality of pixels (PX) may include the floating diffusion region (FD), the ground region (GND), and the transmission gate (TG).

[0061] The upper chip (CH_U) may further include an upper semiconductor substrate (103) having a first surface (103S1) and a second surface (103S2) facing each other. The upper semiconductor substrate (103) may be a single-crystal silicon substrate, but the embodiment is not limited thereto. For example, the upper semiconductor substrate (103) may be a semiconductor substrate comprising a compound semiconductor material.

[0062] The above photodiodes (PD) can be placed within the upper semiconductor substrate (103).

[0063] The pixel separation region (PI) may be disposed within the upper semiconductor substrate (103) and may be disposed between the photodiodes (PD). The pixel separation region (PI) may be arranged in a grid shape.

[0064] In one example, the plurality of pixels (PX) may include the first to fourth pixels (PX1-PX4) described in FIG. 3b. For example, as described in FIG. 3b, the first pixel (PX1) may include the ground region (GND), the first photodiode (PD1), the first floating diffusion region (FD1), and the first transmission gate (TG1); the second pixel (PX2) may include the ground region (GND), the second photodiode (PD2), the second floating diffusion region (FD2), and the second transmission gate (TG2); the third pixel (PX3) may include the ground region (GND), the third photodiode (PD3), the third floating diffusion region (FD3), and the third transmission gate (TG3); and the fourth pixel (PX4) may include the ground region (GND), the fourth photodiode (PD4), the fourth floating diffusion region (FD4), and the fourth transmission gate (TG4).

[0065] The upper chip (CH_U) may include the ground regions (GND), the first to fourth photodiodes (PD1-PD4), the first to fourth floating diffusion regions (FD1-FD4), and the fourth transmission gates (TG1-TG4). The ground region (GND), the fourth photodiode (PD4), and the fourth floating diffusion region (FD4) may be disposed within the upper semiconductor substrate (103). The ground regions (GND) and the floating diffusion regions (FD) may be disposed within the semiconductor substrate (103) adjacent to the first surface (103S1) of the upper semiconductor substrate (103) and located below the photodiodes (PD).

[0066] Each of the above transmission gates (TG) may include a transmission gate electrode (TGb) and a gate dielectric (TGa) between the transmission gate electrode (TGb) and the upper semiconductor substrate (103).

[0067] Each of the above transmission gates (TG) may extend from the first surface (103S1) of the upper semiconductor substrate (103) in a direction toward the second surface (103S2) from the first surface (103S1). The transmission gates (TG) may include at least a portion disposed within a recessed area in a direction toward the second surface (103S2) from the first surface (103S1) of the semiconductor substrate (103).

[0069] The upper chip (CH_U) may further include a device isolation region (STI) disposed on the first surface (103s1) of the upper semiconductor substrate (103). The device isolation region (STI) may be formed by shallow trench isolation. For example, the device isolation region (STI) may be formed of an insulating material such as silicon oxide that fills the trench.

[0070] The above-mentioned device isolation region (STI) can be arranged to surround each of the above-mentioned ground regions (GND) and the above-mentioned floating diffusion regions (FD).

[0071] The upper chip (CH_U) may further include an insulating structure (ARL) disposed on the second surface (103S2) of the upper semiconductor substrate (103), color filters (125) disposed on the insulating structure (ARL), a grid structure (120) disposed between the color filters (125) on the insulating structure (ARL), and micro lenses (130) disposed on the color filters (125).

[0072] The insulating structure (ARL) may include an anti-reflection layer capable of preventing light reflection caused by a sudden change in refractive index on the second surface (103S2) of the upper semiconductor substrate (103), which may be formed of silicon. The microlenses (130) can focus incident light into the photodiodes (PD).

[0073] The upper chip (CH_U) may further include an upper insulating structure (109) disposed below the first surface (103S1) of the upper semiconductor substrate (103).

[0074] The image sensor (1) may further include floating diffusion contacts (FD_C) electrically connected to the floating diffusion regions (FD), ground contacts (GND_C) for grounding the ground regions (GND), and transmission gate contacts (TG_C) electrically connected to the transmission gates (TG). The floating diffusion contacts (FD_C), the ground contacts (GND_C), and the transmission gate contacts (TG_C) may be disposed within the upper insulating structure (109) and may be formed of a conductive material.

[0075] The image sensor (1) may further include upper junction pads (115) embedded within the upper insulating structure (109) and having lower surfaces that form a co-surface with the lower surface of the upper insulating structure (109), and an upper wiring structure (112) disposed within the upper insulating structure (109) and electrically connecting the upper junction pads (115) and the contacts (FD_C, GND_C, TG_C). The upper junction pads (115) may include a metallic material such as copper.

[0076] The first lower chip (CH_L1) may include a first lower semiconductor substrate (203), a plurality of transistors (TR1, TR2, TR3, TR4) disposed on the first lower semiconductor substrate (203), a first lower insulating structure (250) covering the plurality of transistors (TR1, TR2, TR3, TR4) on the first lower semiconductor substrate (203), first lower junction pads (240) embedded within the first lower insulating structure (250) and having upper surfaces that form a co-surface with the upper surface of the first lower insulating structure (250), and a first lower wiring structure (220) disposed within the first lower insulating structure (250) and electrically connecting the first lower junction pads (240) and the plurality of transistors (TR1, TR2, TR3, TR4).

[0077] In one example, the plurality of transistors (TR1, TR2, TR3, TR4) may comprise the reset transistor (RX), the driving transistors (DX1, DX2), and the select transistor (SX) described in FIG. 3b. As described in FIG. 3b, the number of transistors included in each of the pixels (PX) may increase, so the number of the plurality of transistors (TR1, TR2, TR3, TR4) may increase.

[0078] In one example, at least one of the plurality of transistors (TR1, TR2, TR3, TR4) may constitute the reset transistor (RX). For example, when the first transistor (TR1) among the plurality of transistors (TR1, TR2, TR3, TR4) is the reset transistor (RX), the first transistor (TR1) may include a first source / drain (SD1), a second source / drain (SD2), and a gate (G1), and the second source / drain (SD2) may be electrically connected to the floating diffusion region (FD) through the first lower wiring structure (220), the first lower junction pad (240), the upper junction pad (115), the upper wiring structure (112), and the floating diffusion contact (FD_C). The second source / drain (SD2) can be electrically connected to the floating diffusion region (FD) and can be vertically superimposed on the floating diffusion region (FD).

[0079] Between the second source / drain (SD2) and the floating diffusion region (FD), the first lower bonding pad (240) and the upper bonding pad (115) that are bonded to each other may be disposed. The first lower bonding pad (240) and the upper bonding pad (115) that are bonded to each other may overlap perpendicularly with the floating diffusion region (FD). Therefore, since the signal transmission path between the second source / drain (SD2) and the floating diffusion region (FD) can be minimized, the performance of the image sensor (1) can be improved.

[0081] In one example, a pair of adjacent transistors among the plurality of transistors (TR1, TR2, TR3, TR4) may share a single source / drain region. For example, a pair of first and second transistors (TR1, TR2) among the plurality of transistors (TR1, TR2, TR3, TR4) may share a single source / drain (SD1). Accordingly, the first transistor (TR1) may include a gate (G1), a shared source / drain (SD1) on one side of the gate (G1), and a source / drain (SD2) on the other side of the gate (G1), and the second transistor (TR2) may include a gate (G2), a shared source / drain (SD1) on one side of the gate (G2), and a source / drain (SD3) on the other side of the gate (G2).

[0082] In another example, the first and second transistors (TR1, TR2) may each include a source / drain without sharing a single source / drain (SD1).

[0083] Each of the above third and fourth transistors (TR3, TR4) may include gates (G) and source / drains (S / D).

[0084] In an embodiment, a dummy structure (DT) may be disposed on at least one side of each of the plurality of transistors (TR1, TR2, TR3, TR4). Among the plurality of transistors (TR1, TR2, TR3, TR4), the dummy structure (DT) may be disposed next to a source / drain that needs to be electrically isolated from an adjacent component. The dummy structure (DT) may be any one of a trench isolation layer, a dummy structure including a dummy gate, and a dummy isolation structure.

[0085] In one example, to minimize the signal transmission path so as to improve the performance of the image sensor (1), the second source / drain (SD2), the first lower wiring structure (220), the first lower bonding pad (240), the upper bonding pad (115), the upper wiring structure (112), the floating diffusion contact (FD_C), and the floating diffusion region (FD) may be vertically aligned.

[0086] The first lower bonding pads (240) may include the same material as the upper bonding pads (115), for example, copper. The first lower bonding pads (240) may be bonded while in contact with the upper bonding pads (115). The upper surface of the first lower insulating structure (250) and the lower surface of the upper insulating structure (109) may be bonded while in contact with each other. Accordingly, the bonding surface (B1) between the upper chip (CH_U) and the first lower chip (CH_L1) may be the bonding surfaces between the first lower bonding pads (240) and the upper bonding pads (115), and the bonding surface between the first lower insulating structure (250) and the upper insulating structure (109).

[0088] The first lower chip (CH_L1) may further include a device isolation region (206) within the first lower semiconductor substrate (203), a lower protective insulating layer (270) below the first lower semiconductor substrate (203), a second lower junction pad (280) having a lower surface that forms a co-surface with the lower surface of the lower protective insulating layer (270) within the lower protective insulating layer (270), a lower redistribution (275) disposed within the lower protective insulating layer (270) and in contact with the second lower junction pad (280), and a penetrating electrode structure (260) that penetrates the first lower semiconductor substrate (203) and the device isolation region (206) and electrically connects the first lower wiring structure (220) and the lower redistribution (275).

[0089] The above-mentioned through electrode structure (260) may include a through electrode (265) that can be formed of a conductive material and an insulating spacer (263) that can be formed of an insulating material and surrounds the side of the through electrode (265).

[0090] The penetrating electrode structure (260) can be vertically overlapped with the pixel separation region (PI). The penetrating electrode structure (260) can be vertically overlapped with the intersection region (PI_C) of the pixel separation region (PI). For example, the pixel separation region (PI) may include, in a top view, first line portions (PI_H1) extending in a first direction (X), second line portions (PI_H2) extending in a second direction (Y) perpendicular to the first direction (X), and intersection regions (PI_C) where the first line portions (PI_H1) and the second line portions (PI_H2) intersect. Accordingly, the penetrating electrode structure (260) can be vertically overlapped with the intersection region (PI_C) of the pixel separation region (PI) in the vertical direction (Z).

[0091] The second lower chip (CH_L2) may include a second lower semiconductor substrate (303), a plurality of lower transistors (TR_L1, TR_L2) disposed on the second lower semiconductor substrate (303), a first lower insulating structure (350) covering the plurality of lower transistors (TR_L1, TR_L2) on the second lower semiconductor substrate (303), third lower junction pads (340) embedded within the second lower insulating structure (350) and having upper surfaces that form a co-surface with the upper surface of the second lower insulating structure (350), and a second lower wiring structure (320) disposed within the second lower insulating structure (350) and electrically connecting the third lower junction pads (340) and the plurality of lower transistors (TR_L1, TR_L2).

[0092] The third lower bonding pads (340) may include the same material as the second lower bonding pads (280), for example, copper material. The third lower bonding pads (340) may be bonded while in contact with the second lower bonding pads (280). The upper surface of the second lower insulating structure (350) and the lower surface of the lower protective insulating layer (270) may be bonded while in contact with each other. Accordingly, the bonding surface (B2) between the second lower chip (CH_L2) and the first lower chip (CH_L1) may be the bonding surfaces between the third lower bonding pads (340) and the second lower bonding pads (280), and the bonding surface between the second lower insulating structure (350) and the lower protective insulating layer (270).

[0093] The above plurality of lower transistors (TR_L1, TR_L2) may include a first lower transistor (TR_L1) including a gate (GL1) and a source / drain (SD1), and a second lower transistor (TR_L2) including a gate (GL2) and a source / drain (SD2).

[0094] The above plurality of lower transistors (TR_L1, TR_L2) may be transistors constituting the logic circuit (20) described in FIG. 1.

[0095] The plurality of transistors (TR1, TR2, TR3, TR4) and the plurality of lower transistors (TR_L1, TR_L2) can be formed as three-dimensional transistors including a channel with a three-dimensional structure.

[0096] The plurality of transistors (TR1, TR2, TR3, TR4) and the plurality of lower transistors (TR_L1, TR_L2) may be composed of a first three-dimensional transistor (TR_A in FIG. 7-9) having a first channel structure and a second three-dimensional transistor (TR_B in FIG. 7-9) having a second channel structure different from the first channel structure.

[0097] In one example, the plurality of transistors (TR1, TR2, TR3, TR4) may be composed of the first three-dimensional transistor (TR_A in FIG. 7-9) and the second three-dimensional transistor (TR_B in FIG. 7-9), and the plurality of lower transistors (TR_L1, TR_L2) may be composed of the first three-dimensional transistor (TR_A in FIG. 7-9) and the second three-dimensional transistor (TR_B in FIG. 7-9).

[0098] In another example, the plurality of transistors (TR1, TR2, TR3, TR4) may be composed of the first three-dimensional transistor (TR_A in FIG. 7-9).

[0099] In one example, among the plurality of transistors (TR1, TR2, TR3, TR4), the transistors that may be the first and second driving transistors (DX1, DX2) may be configured as the first three-dimensional transistor (TR_A in FIG. 7-9), and the transistors that may be the reset transistor (RX) and the select transistor (SX) may be configured as the second three-dimensional transistor (TR_B in FIG. 7-9).

[0101] Hereinafter, with reference to FIGS. 7, 8, and 9, exemplary examples of the first three-dimensional transistor (TR_A of FIGS. 7-9) including the first channel structure and the second three-dimensional transistor (TR_B of FIGS. 7-9) including the second channel structure will be described. FIG. 7 is a top view schematically showing exemplary examples of the first three-dimensional transistor (TR_A of FIGS. 7-9) including the first channel structure and the second three-dimensional transistor (TR_B of FIGS. 7-9) including the second channel structure; FIG. 8 is a cross-sectional view schematically showing regions taken along the IVa-IVa' and Va-Va' lines of FIG. 7; and FIG. 9 is a cross-sectional view schematically showing regions taken along the IVb-IVb' and Vb-Vb' lines of FIG. 7.

[0102] First, referring to FIGS. 7 and 8, a first active pin (409a) may be disposed on a semiconductor substrate (403a) that is defined by a device isolation region (406a) and extends in a first direction (D1). The first three-dimensional transistor (TR_A) may include first source / drains (SD_A) spaced apart from each other on the first active pin (409a), a plurality of channel layers (CH_A) stacked spaced apart from each other in a vertical direction (Z) on the first active pin (409a) and disposed between the first source / drains (SD_A), and a first gate (G_A) that crosses the active pin (409a) in a second direction (D2) perpendicular to the first direction (D1) on the active pin (409a) and surrounds each of the plurality of channel layers (CH_A).

[0103] The above plurality of channel layers (CH_A) can be formed of a semiconductor material such as silicon.

[0104] The first gate (G_A) may include a first gate dielectric (GI_A) and a first gate electrode (GE_A) on the first gate dielectric (GI_A).

[0105] The first gate dielectric (GI_A) may include the plurality of channel layers (CH_A) and portions in contact with the first active pin (409a).

[0106] The first gate electrode (GE_A) can fill the space between the plurality of channel layers (CH_A) together with the first gate dielectric (GI_A), and can fill the space between the plurality of channel layers (CH_A) and the first active pin (409a).

[0107] The first gate dielectric (GI_A) can cover the lower surface and side surface of the first gate electrode (GE_A) at a level higher than the uppermost channel layer among the plurality of channel layers (CH_A).

[0108] The first three-dimensional transistor (TR_A) mentioned above is a Gate-All-Around Field-Effect Transistor (MBCFET). TM It can be a transistor with a (Multi-Bridge Channel FET) structure.

[0109] An insulating gate capping layer (GC_A) may be disposed on the first gate (G_A), and insulating gate spacers (GS_A) may be disposed on both sides of the first gate (G_A) and the gate capping layer (GC_A).

[0110] Dummy structures (D_A) adjacent to the first source / drain (SD_A) may be placed on both sides of the first gate (G_A). Between the dummy structures (D_A), the first three-dimensional transistor (TR_A) may be placed. The dummy structures (D_A) may be placed in various forms, such as dummy gates or dummy isolation structures.

[0112] Next, referring to FIGS. 7 and 9, a second active pin (409b) may be disposed on a semiconductor substrate (403b) that is defined by a device isolation region (406b) and extends in a first direction (D1). The second three-dimensional transistor (TR_B) may include second source / drains (SD_B) spaced apart from each other on the second active pin (409b), first semiconductor layers (S_1) and second semiconductor layers (S_2) alternately and repeatedly stacked in a vertical direction (Z) on the second active pin (409b), a channel structure (CH_B) disposed between the second source / drains (SD_B), and a second gate (G_B) that crosses the second active pin (409b) in the second direction (D2) on the second active pin (409b) and covers the upper surface and side surface of the channel structure (CH_B).

[0113] In the above channel structure (CH_B), the first semiconductor layers (S_1) may be formed of a first material, and the second semiconductor layers (S_2) may be formed of a second material different from the first material. For example, the first semiconductor layers (S_1) may be silicon layers, and the second semiconductor layers (S_2) may be silicon-germanium layers.

[0114] The second gate (G_B) may include a second gate dielectric (GI_B) and a second gate electrode (GE_B) on the second gate dielectric (GI_B).

[0115] The second three-dimensional transistor (TR_B) may further include a buffer layer (PL) between the second gate (G_B) and the channel structure (CH_B). The buffer layer (PL) may be formed as a semiconductor layer epitaxially grown from the channel structure (CH_B).

[0116] An insulating gate capping layer (GC_B) may be disposed on the second gate (G_B), and insulating gate spacers (GS_B) may be disposed on both sides of the second gate (G_B) and the gate capping layer (GC_B).

[0117] Dummy structures (D_B) adjacent to the second source / drain (SD_B) may be placed on both sides of the second gate (G_B). Between the dummy structures (D_B), the second three-dimensional transistor (TR_B) may be placed. The dummy structures (D_B) may be placed in various forms, such as dummy gates or dummy isolation structures.

[0119] According to the embodiments described above, by dividing and arranging the elements constituting the pixel circuit of the image sensor (1) within the vertically joined upper chip (CH_U) and the first lower chip (CH_L1), the size of each pixel (PX) included in the pixel array (10) can be reduced, and more pixels (PX) can be arranged within the pixel array (10) of the same area. Thus, an image sensor (1) capable of generating high-resolution images can be provided.

[0120] In addition, some of the transistors among the elements constituting the pixel circuit can be formed as high-performance transistors with a gate-all-around-gate structure, for example, the first three-dimensional transistor (TR_A).

[0121] In addition, by configuring the transistors constituting the logic circuit (20) with the first three-dimensional transistor (TR_A) and the second three-dimensional transistor (TR_B), the performance of the image sensor (1) can be improved.

[0122] In addition, by joining the upper chip (CH_U), the first lower chip (CH_L1), and the second lower chip (CH_L2) using intermetallic bonding, the vertical thickness can be minimized and the signal transmission path can be minimized. Therefore, the performance of the image sensor (1) can be improved.

[0124] Hereinafter, various modified examples of the image sensor (1) will be described. The various modified examples of the image sensor (1) described below will be described focusing on the modified components or replaced components. First, modified examples of the image sensor (1) will be described with reference to FIG. 10 and FIG. 11, respectively. FIG. 10 is a schematic perspective view showing a modified example of an image sensor according to one embodiment of the present invention, and FIG. 11 is a schematic perspective view showing another modified example of an image sensor according to one embodiment of the present invention.

[0125] In a modified example, referring to FIG. 10, the image sensor (1') may include a lower chip (CH_L') and an upper chip (CH_U') that are bonded and stacked in sequence. The upper chip (CH_U') may include the pixel array (10) described in FIG. 1, and the lower chip (CH_L') may include the logic circuit (20) described in FIG. 1. The upper chip (CH_U') may include elements of each of the pixels (PX in FIG. 1) constituting the pixel array (10). For example, the upper chip (CH_U') may include the reset transistor (RX), the driving transistors (DX1, DX2), and the select transistor (SX) described in FIG. 3b, along with all the elements of the upper chip (CH_U in FIG. 6) described in FIG. 6.

[0126] In one example, the reset transistor (RX), the driving transistors (DX1, DX2), and the select transistor (SX) may be composed of the first three-dimensional transistor (TR_A in FIGS. 7-9) described in FIGS. 7 to 9.

[0127] In another example, the reset transistor (RX), the driving transistors (DX1, DX2), and the select transistor (SX) may be composed of the first three-dimensional transistor (TR_A in FIG. 7-9) and the second three-dimensional transistor (TR_B in FIG. 7-9) described in FIG. 7 to 9. For example, the driving transistors (DX1, DX2) may be composed of the first three-dimensional transistor (TR_A in FIG. 7-9) described in FIG. 7 to 9, and the reset transistor (RX) and the select transistor (SX) may be composed of the second three-dimensional transistor (TR_B in FIG. 7-9) described in FIG. 7 to 9.

[0129] In a modified example, referring to FIG. 11, the image sensor (1") may include the upper chip (CH_U), the first lower chip (CH_L1), and the second lower chip (CH_L2) as in FIG. 3. The image sensor (1") may further include a third lower chip (CH_L3) disposed below the second lower chip (CH_L2). The third lower chip (CH_L3) may include a logic circuit (LOGIC) and a memory (MEMORY). In the third lower chip (CH_L3), the logic circuit (LOGIC) may include a circuit for artificial intelligence (AI). In the third lower chip (CH_L3), the memory (MEMORY) may include a volatile memory capable of storing information and / or a non-volatile memory capable of storing information.

[0130] In the third lower chip (CH_L3) above, the transistors used in the logic circuit (LOGIC) and the memory (MEMORY) may be configured using at least one of the first three-dimensional transistor (TR_A in FIG. 7-9) and the second three-dimensional transistor (TR_B in FIG. 7-9) described in FIG. 7 to 9.

[0132] Referring to FIG. 12, a modified example of the image sensor (1) will be described. FIG. 12 is a cross-sectional view schematically showing regions that correspond to regions taken along the lines I-I', II-II', and III-III' of FIG. 6, respectively.

[0133] Referring to FIG. 12, the image sensor (1a) may include a ground region (GND'), a floating diffusion region (FD'), and a transmission gate (TG') that are modified versions of the ground region (GND), the floating diffusion region (FD), and the transmission gate (TG) described in FIG. 5 and FIG. 6, respectively.

[0134] The image sensor (1a) may include an insulating layer (ILD) disposed below the first surface (103S1) of the upper semiconductor substrate (103).

[0135] The ground region (GND') may be in the shape of a pillar protruding in a direction toward the first lower chip (CH_L1) from the first surface (103S1) of the upper semiconductor substrate (103). The pillar-shaped ground region (GND') may penetrate the insulating layer (ILD).

[0136] At least a portion of the floating diffusion region (FD') may be pillar-shaped, protruding from the first surface (103S1) of the upper semiconductor substrate (103) toward the first lower chip (CH_L1). At least a portion of the pillar-shaped floating diffusion region (FD') may penetrate the insulating layer (ILD).

[0137] The transmission gate (TG') may cover the side of the pillar-shaped floating diffusion region (FD'), i.e., the pillar portion, below the insulating layer (ILD). The transmission gate (TG') may include a transmission gate electrode (TGb) and a gate dielectric (TGa) between the transmission gate electrode (TGb) and the floating diffusion region (FD').

[0139] Referring to FIGS. 13 and FIGS. 14, a modified example of the image sensor (1) will be described. FIGS. 13 is a top view schematically showing one pixel in a modified example of the image sensor, and FIGS. 14 is a cross-sectional view schematically showing regions that correspond to regions taken along the lines Ia-Ia', IIa-IIa', and IIIa-IIIa' of FIGS. 13, respectively.

[0140] Referring to FIGS. 13 and 14, in an image sensor (1) comprising the upper chip (CH_U), the first lower chip (CH_L1), and the second lower chip (CH_L2) as in FIG. 3, the upper chip (CH_U) may include at least one upper transistor (TR'). Accordingly, an image sensor (1b) comprising the upper chip (CH_U) including the at least one upper transistor (TR') can be provided.

[0141] In the upper chip (CH_U), the at least one upper transistor (TR') may include at least one of the reset transistor (RX), the select transistor (SX), and the drive transistor (DX) described in FIG. 3a, or at least one of the reset transistor (RX), the first and second drive transistors (DX1, DX2), and the select transistor (SX) described in FIG. 3b. The at least one upper transistor (TR') may include an upper gate (G') and a source / drain (SD'). The upper gate (G') may be electrically connected to the upper wiring structure (112) by an upper gate contact (G_C).

[0142] The at least one upper transistor (TR') may be composed of either the first three-dimensional transistor (TR_A of FIG. 7-9) and the second three-dimensional transistor (TR_B of FIG. 7-9) described in FIG. 7 to 9, for example, the first three-dimensional transistor (TR_A of FIG. 7-9) comprising the plurality of channel layers (CH_A of FIG. 8). Accordingly, the at least one upper transistor (TR') may include a plurality of channel layers (CH_A') that are substantially identical to the plurality of channel layers (CH_A of FIG. 8).

[0143] In one example, the ground region (GND) and the floating diffusion region (FD) may be formed with a structure substantially identical to the channel structure (CH_B) comprising the first semiconductor layers (S_1) and the second semiconductor layers (S_2) described in FIG. 9. For example, the ground region (GND) and the floating diffusion region (FD) may include first semiconductor layers and second semiconductor layers that are alternately and repeatedly stacked. Here, the first semiconductor layers may be formed of a first material, and the second semiconductor layers may be formed of a second material different from the first material. For example, the first semiconductor layers may be silicon layers, and the second semiconductor layers may be silicon-germanium layers.

[0145] Referring to FIG. 15, a modified example of the image sensor (1) will be described. FIG. 15 is a cross-sectional view schematically showing a part of the upper chip (CH_U) in the image sensor (1) described above.

[0146] Referring to FIG. 15, the image sensor (1c) may include the insulating structure (ARL), the grid structure (120), and the color filters (125) as described above.

[0147] The image sensor (1c) may further include a prism structure disposed on the grid structure (120) and the color filters (125). The prism structure may include an interface material (135) and a meta pattern (137a, 137b) embedded within the interface material (135). The prism structure (135, 137a, 137b) may be a planar lens. Such a prism structure (135, 137a, 137b) may replace the micro lens (130 of FIG. 6) described in FIG. 6.

[0149] Referring to FIG. 16, a modified example of the image sensor (1) will be described. FIG. 16 is a cross-sectional view that further includes the cross-sectional structure of the pad area (PAD of FIG. 2) in the image sensor (1) described above.

[0150] Referring to FIG. 16, the image sensor (1d) may further include an upper through-electrode structure (180) disposed within the pad area (PAD) of the upper chip (CH_U) and a pad pattern (190) on the upper through-electrode structure (180). The upper through-electrode structure (180) may penetrate the insulating structure (ARL) and the upper semiconductor substrate (103) and come into contact with the upper wiring structure (112). The through-electrode structure (180) may include a through-electrode (180b) and an insulating spacer (180a) covering the side of the through-electrode (180b).

[0151] The pad pattern (190) can be electrically connected to the logic circuit (20) of the second lower chip (CH_L2) through the upper through-electrode structure (180), the upper wiring structure (112), the upper bonding pad (115) and the first lower bonding pad (240), the first lower wiring structure (220), the through-electrode structure (260), the lower redistribution (275), the second and third lower bonding pads (280, 340), and the second lower wiring structure (320).

[0153] Referring to FIG. 17, a modified example of the image sensor (1) will be described. FIG. 17 is a cross-sectional view that further includes the cross-sectional structure of the pad area (PAD of FIG. 2) in the image sensor (1) described above.

[0154] Referring to FIG. 17, the image sensor (1e) may further include an upper penetrating electrode structure (180') that penetrates the pad region (PAD) of the upper chip (CH_U) and contacts the first lower wiring structure (220) of the first lower chip (CH_L1), and a pad pattern (190) on the upper penetrating electrode structure (180). The upper penetrating electrode structure (180') may include a penetrating electrode (180b) and an insulating spacer (180a) covering the side of the penetrating electrode (180b).

[0155] The pad pattern (190) can be electrically connected to the logic circuit (20) of the second lower chip (CH_L2) through the upper through-electrode structure (180), the first lower wiring structure (220), the through-electrode structure (260), the lower rewiring (275), the second and third lower bonding pads (280, 340), and the second lower wiring structure (320).

[0157] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing its technical concept or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive.

Claims

Claim 1 A first lower chip; and an upper chip bonded to the first lower chip on the first lower chip, wherein the first lower chip and the upper chip share a plurality of pixels, and each of the plurality of pixels comprises: a photoelectric conversion element, a floating diffusion region, a ground region, and a transmission gate disposed within the upper chip; and a plurality of lower transistors disposed within the first lower chip, wherein the first lower transistor among the plurality of lower transistors comprises a plurality of first channel layers stacked in a vertical direction, a first gate traversing the plurality of first channel layers and surrounding each of the plurality of first channel layers, and a source / drain electrically connected to the floating diffusion region and overlapping with the floating diffusion region in the vertical direction, and the upper chip comprises a floating diffusion contact connected to the floating diffusion region below the floating diffusion region; and an upper wiring structure connected to the floating diffusion contact below the floating diffusion contact. and includes an upper junction pad connected to the upper wiring structure below the upper wiring structure, and the first lower chip includes a lower junction pad connected to the upper junction pad below the upper junction pad; and between the lower junction pad and the source / drain of the first lower transistor, the lower junction pad and the source / drain are connected to the lower wiring structure, and the source / drain of the first lower transistor, the lower wiring structure, the lower junction pad, the upper junction pad, the floating diffusion contact, and the floating diffusion region are superimposed in the vertical direction of the image sensor. Claim 2 delete Claim 3 In claim 1, the second lower transistor among the plurality of lower transistors comprises a channel structure including first semiconductor layers and second semiconductor layers that are alternately and repeatedly stacked, and a second gate covering both sides and the top surface of the channel structure, and the material of the first semiconductor layers and the material of the second semiconductor layers are different image sensors. Claim 4 delete Claim 5 An image sensor according to claim 1, wherein the upper chip further comprises a ground contact in contact with the ground region; and a transmission gate contact in contact with the transmission gate electrode of the transmission gate. Claim 6 An image sensor according to claim 1, wherein the upper chip further comprises: a semiconductor substrate having a first surface and a second surface facing each other; an insulating structure on the second surface of the semiconductor substrate; a pixel separation structure within the semiconductor substrate; and color filters on the insulating structure, wherein the photoelectric conversion element is disposed within the semiconductor substrate between the pixel separation structures, and the floating diffusion region and the ground region are disposed within the semiconductor substrate adjacent to the first surface. Claim 7 An image sensor according to claim 6, wherein the upper chip further comprises a device isolation layer between the ground region and the floating diffusion region, and at least a portion of the transmission gate is disposed within a recessed region in a direction from the first surface of the semiconductor substrate toward the second surface of the semiconductor substrate. Claim 8 The image sensor according to claim 1, wherein the upper chip further comprises: a semiconductor substrate having a first surface and a second surface facing each other; an insulating structure on the second surface of the semiconductor substrate; a pixel separation structure within the semiconductor substrate; and color filters on the insulating structure, wherein the photoelectric conversion element is disposed within the semiconductor substrate between the pixel separation structures, and at least a portion of the floating diffusion region is disposed within a pillar portion protruding from the first surface of the semiconductor substrate toward the first lower chip, and the transmission gate covers at least a portion of the side of the pillar portion of the floating diffusion region. Claim 9 An image sensor according to claim 1, further comprising an upper transistor disposed within the upper chip, wherein the upper transistor comprises a plurality of upper channel layers stacked in the vertical direction and an upper gate structure surrounding each of the plurality of upper channel layers. Claim 10 In claim 9, the floating diffusion region comprises alternately stacked first semiconductor layers and second semiconductor layers, and the material of the first semiconductor layers and the material of the second semiconductor layers are different image sensors. Claim 11 An image sensor according to claim 1, further comprising a second lower chip below the first lower chip, wherein the second lower chip comprises a circuit for controlling a pixel array including the plurality of pixels. Claim 12 In claim 11, the circuit of the second lower chip comprises at least one of a first three-dimensional transistor and a second three-dimensional transistor, wherein the first three-dimensional transistor comprises a plurality of lower channel layers stacked in the vertical direction and a first lower gate surrounding each of the plurality of lower channel layers, and the second three-dimensional transistor comprises a lower channel structure comprising first lower semiconductor layers and second lower semiconductor layers that are alternately and repeatedly stacked, and a second lower gate covering both sides and the top surface of the lower channel structure, an image sensor. Claim 13 A first lower chip; an upper chip bonded to the first lower chip on the first lower chip; and a second lower chip joined to the first lower chip below the first lower chip, wherein the first lower chip and the upper chip each comprise a pixel array including a plurality of pixels, and the second lower chip includes a control circuit for controlling the pixel array, and each of the plurality of pixels includes a photoelectric conversion element, a floating diffusion region, a ground region, a transmission gate, a reset transistor, a select transistor, and a driving transistor, and the upper chip includes the photoelectric conversion element, the floating diffusion region, the ground region, and the transmission gate, and the first lower chip includes at least one transistor among the reset transistor, the select transistor, and the driving transistor, and the at least one transistor of the first lower chip is a first three-dimensional transistor including a plurality of first channel layers stacked in a vertical direction and a first gate that spans the plurality of first channel layers and surrounds each of the plurality of first channel layers, and the upper chip comprises a semiconductor substrate having a first surface facing the first lower chip and a second surface opposite to the first surface; An image sensor further comprising: a pillar portion protruding in a direction toward the first lower chip from the first surface of the semiconductor substrate; and color filters on the second surface of the semiconductor substrate, wherein the photoelectric conversion element is disposed within the semiconductor substrate, at least a portion of the floating diffusion region is disposed within the pillar portion, and the transmission gate covers at least a portion of the side of the pillar portion where the floating diffusion region is disposed. Claim 14 In claim 13, the at least one transistor is an image sensor that is the driving transistor. Claim 15 In claim 13, in the first sub-chip, the reset transistor, the select transistor, and the driving transistor are composed of the first three-dimensional transistor and a second three-dimensional transistor different from the first three-dimensional transistor, and the second three-dimensional transistor includes a channel structure comprising first semiconductor layers and second semiconductor layers that are alternately and repeatedly stacked, and a second gate that crosses the channel structure and covers both sides and the top surface of the channel structure, and the material of the first semiconductor layers and the material of the second semiconductor layers are different image sensors. Claim 16 In claim 15, the control circuit of the second lower chip is an image sensor composed of the first three-dimensional transistor and the second three-dimensional transistor. Claim 17 A first lower chip; an upper chip bonded to the first lower chip on the first lower chip; and a second lower chip bonded to the first lower chip below the first lower chip, wherein the first lower chip and the upper chip comprise a pixel array comprising a plurality of pixels, and the second lower chip comprises a control circuit for controlling the pixel array, and each of the plurality of pixels comprises a photoelectric conversion element, a floating diffusion region, a ground region, a transmission gate, a reset transistor, a select transistor, and a driving transistor, and the upper chip comprises the photoelectric conversion element, the floating diffusion region, the ground region, and the transmission gate, and the first lower chip comprises at least one transistor among the reset transistor, the select transistor, and the driving transistor, and the upper chip comprises an upper semiconductor substrate having a first surface and a second surface facing each other; color filters on the second surface of the upper semiconductor substrate; a pixel isolation structure within the upper semiconductor substrate; and an upper insulating structure below the first surface of the upper semiconductor substrate. and further comprising: a first upper junction pad having a lower surface that is embedded within the upper insulating structure and forms a co-plane with the lower surface of the upper insulating structure; an upper wiring structure between the upper semiconductor substrate and the first upper junction pad, wherein the photoelectric conversion element is disposed within the upper semiconductor substrate between the pixel separation structures, and the floating diffusion region and the ground region are disposed within the upper semiconductor substrate adjacent to the first surface of the upper semiconductor substrate, and the first lower chip comprises: a first lower semiconductor substrate; a first lower insulating structure on the first lower semiconductor substrate; a first lower junction pad having an upper surface that is embedded within the first lower insulating structure and forms a co-plane with the upper surface of the first lower insulating structure; and a lower protective insulating layer below the first lower semiconductor substrate.The image sensor further comprises a lower wiring structure between the first lower junction pad and the first lower semiconductor substrate, wherein the second lower chip further comprises a second lower semiconductor substrate; and a second lower insulating structure on the second lower semiconductor substrate, wherein the first lower junction pad and the first upper junction pad are joined while in contact with each other, and the floating diffusion region and the source / drain of the reset transistor are electrically connected by the lower wiring structure, the first lower junction pad, the first upper junction pad, and the upper wiring structure, and wherein the floating diffusion region, the source / drain of the reset transistor, the lower wiring structure, the first lower junction pad, the first upper junction pad, and the upper wiring structure overlap in a vertical direction, and the at least one transistor of the first lower chip is a first three-dimensional transistor comprising a plurality of first channel layers stacked in the vertical direction and a first gate surrounding each of the plurality of first channel layers. Claim 18 In claim 17, in the first sub-chip, the reset transistor, the select transistor, and the driving transistor are composed of the first three-dimensional transistor and a second three-dimensional transistor different from the first three-dimensional transistor, and the second three-dimensional transistor includes a channel structure comprising first semiconductor layers and second semiconductor layers that are alternately and repeatedly stacked, and a second gate that crosses the channel structure and covers both sides and the top surface of the channel structure, and the material of the first semiconductor layers and the material of the second semiconductor layers are different image sensors. Claim 19 In claim 17, the upper chip further comprises: an upper wiring structure within the upper insulating structure; an upper through-electrode structure penetrating the upper semiconductor substrate and in contact with the upper wiring structure; and a pad pattern on the upper through-electrode structure, and the first lower chip further comprises: a first lower wiring structure within the first lower insulating structure; and a lower through-electrode structure penetrating the first lower semiconductor substrate, and the pixel separation structure comprises a first line portion extending in a first direction, a second line portion extending in a second direction intersecting the first direction, and an intersection region where the first line portion and the second line portion intersect, and the lower through-electrode structure is an image sensor that overlaps the intersection region in the vertical direction. Claim 20 An image sensor according to claim 17, further comprising an upper penetrating electrode structure penetrating a pad area of ​​the upper chip and extending into the first lower chip, wherein the first lower chip comprises: a first lower wiring structure within the first lower insulating structure; and a lower penetrating electrode structure penetrating the first lower semiconductor substrate, wherein the pixel separation structure comprises a first line portion extending in a first direction, a second line portion extending in a second direction intersecting the first direction, and an intersection area where the first line portion and the second line portion intersect, wherein the lower penetrating electrode structure overlaps the intersection area in the vertical direction, and the upper penetrating electrode structure is electrically connected to the first lower wiring structure.

Images