Semiconductor device

Abstract

A semiconductor device comprises: a bit line structure formed on a substrate; a lower contact plug formed on the substrate adjacent to the bit line structure; an upper contact plug including a first metal pattern formed on the lower contact plug and a second metal pattern in contact with the upper surface and upper sidewall of the first metal pattern; and a capacitor formed on the upper contact plug, wherein the upper surface of the first metal pattern is higher than the upper surface of the bit line structure.

Description

Technology Field

[0001] The present invention relates to a semiconductor device, and more specifically, to a DRAM device. Background Technology

[0002] In a method for manufacturing a DRAM device, a lower contact plug is formed between bit line structures, an upper contact plug film is formed on the lower contact plug, and then the upper part of the upper contact plug film is partially etched to form upper contact plugs that serve as landing pads for capacitors.

[0003] As the integration density of the elements of the DRAM device increases, the spacing between the bit line structures decreases, so the process margin for etching the upper contact plug film to form the upper contact plugs decreases. Prior art literature

[65535] US Public Patent US 20200203354 The problem to be solved

[0004] The objective of the present invention is to provide a semiconductor device having improved electrical characteristics. means of solving the problem

[0005] A semiconductor device according to exemplary embodiments for achieving the above-mentioned objective may include: a bit line structure formed on a substrate; a lower contact plug formed on the substrate adjacent to the bit line structure; an upper contact plug comprising a first metal pattern formed on the lower contact plug and a second metal pattern in contact with the upper surface and upper sidewall of the first metal pattern; and a capacitor formed on the upper contact plug, wherein the upper surface of the first metal pattern may be higher than the upper surface of the bit line structure.

[0006] A semiconductor device according to other embodiments for achieving the above-mentioned objective may include: a bit line structure formed on a substrate; a lower contact plug formed on the substrate adjacent to the bit line structure; an upper contact plug comprising a first metal pattern formed on the lower contact plug, a barrier pattern covering the bottom surface and bottom sidewall of the first metal pattern, and a second metal pattern in contact with the top surface and top sidewall of the first metal pattern and the top surface of the barrier pattern; and a capacitor formed on the upper contact plug, wherein the top surface of the barrier pattern may have a certain height.

[0007] A semiconductor device according to another embodiment for achieving the above-mentioned objective may include: an active pattern formed on a substrate; a gate structure extending in a first direction parallel to the upper surface of the substrate and embedded on the upper portion of the active pattern; a bit line structure extending in a second direction parallel to the upper surface of the substrate and perpendicular to the first direction and formed on the central portion of the active pattern; a spacer structure formed on the side wall of the bit line structure; a contact plug structure formed on each end of the active pattern; and a capacitor formed on the contact plug structure. The contact plug structure may include a lower contact plug; a metal silicide pattern formed on the lower contact plug; a barrier pattern formed on the metal silicide pattern; a first metal pattern in which the bottom surface and bottom side wall are covered by the barrier pattern; and a second metal pattern in contact with the top surface and top side wall of the first metal pattern, and the top surface of the bit line structure and the spacer structure, wherein the top surface of the first metal pattern may be higher than the top surface of the bit line structure. Effects of the invention

[0008] In a method for manufacturing a semiconductor device according to exemplary embodiments, a plurality of upper contact plugs formed between bit line structures and electrically connected to capacitors can be formed such that a lower metal pattern is first formed on a lower contact plug, and an upper metal pattern is formed to contact the upper surface and upper sidewall of the lower metal pattern through a damascene process, so that the upper metal pattern that contacts each capacitor and acts as a landing pad and the lower metal pattern formed on the lower contact plug electrically connected to the source / drain region are connected without being separated from each other. Brief explanation of the drawing

[0009] FIGS. 1 to 18 are plan and cross-sectional views for illustrating a method of manufacturing a semiconductor device according to exemplary embodiments. FIGS. 19 and 20 are cross-sectional views illustrating a method for manufacturing a semiconductor device according to exemplary embodiments. Specific details for implementing the invention

[0010] Hereinafter, a semiconductor device and a method for manufacturing the same according to preferred embodiments of the present invention will be described in detail with reference to the attached drawings. Where materials, layers (films), regions, pads, electrodes, patterns, structures, or processes are referred to as "first," "second," and / or "third" in this specification, it is not intended to limit these components but merely to distinguish each material, layer (film), region, electrode, pad, pattern, structure, and process. Accordingly, "first," "second," and / or "third" may be used selectively or interchangeably for each material, layer (film), region, electrode, pad, pattern, structure, and process.

[0011] [Example]

[0012] FIGS. 1 to 18 are plan views and cross-sectional views for illustrating a method of manufacturing a semiconductor device according to exemplary embodiments. Specifically, FIGS. 1, 3, 6, 10 and 16 are plan views, and FIGS. 2, 4-5, 7-9, 11-15 and 17-18 include cross-sections obtained by cutting the corresponding plan views along the A-A' line and the B-B' line, respectively.

[0013] In the following, two directions parallel to the upper surface of the substrate and orthogonal to each other are defined as the first and second directions (D1, D2), respectively, and a direction parallel to the upper surface of the substrate and forming an acute angle with each of the first and second directions (D1, D2) is defined as the third direction (D3).

[0014] Referring to FIGS. 1 and 2, after removing the upper part of the substrate (300) to form a first recess, a device separation pattern (310) that fills the first recess can be formed.

[0015] The substrate (300) may include, for example, a semiconductor material such as silicon, germanium, silicon-germanium, etc., or a Group III-V compound such as GaP, GaAs, GaSb, etc. According to some embodiments, the substrate (300) may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0016] As a device isolation pattern (310) is formed on the substrate (300), an active pattern (305) can be defined in which the sidewalls are covered by the device isolation pattern (310). The active pattern (305) may be formed in multiple numbers such that each extends in a third direction (D3) and is spaced apart from each other along the first and second directions (D1, D2). The device isolation pattern (310) may include an oxide, for example, silicon oxide.

[0017] Subsequently, the active pattern (305) and the device isolation pattern (310) formed on the substrate (300) may be partially etched to form a second recess extending in a first direction (D1), and then a gate structure (360) may be formed inside the second recess. The gate structure (360) may include a gate insulation pattern (330) formed on the bottom surface and side wall of the second recess, a gate electrode (340) formed on the portion of the gate insulation pattern (330) formed on the bottom surface and lower side wall of the second recess, and a gate mask (350) formed on the gate electrode (340) to fill the upper part of the second recess.

[0018] The gate insulation pattern (330) may include an oxide such as silicon oxide, for example, and the gate electrode (340) may include a metal, metal nitride, metal silicide, impurity-doped polysilicon, etc., and the gate mask (350) may include a nitride such as silicon nitride, for example.

[0019] In exemplary embodiments, the gate structure (360) may be extended along a first direction (D1) and may be formed in multiple numbers spaced apart from each other along a second direction (D2).

[0020] Referring to FIGS. 3 and 4, an insulating film structure (430) can be formed on an active pattern (305), a device isolation pattern (310), and a gate structure (360). The insulating film structure (430) may include first to third insulating films (400, 410, 420) stacked sequentially, and the first and third insulating films (400, 420) may include oxides such as silicon oxide, for example, and the second insulating film (410) may include nitrides such as silicon nitride, for example.

[0021] Subsequently, an insulating film structure (430) can be patterned and used as an etching mask to partially etch the gate mask (350) included in the lower active pattern (305), device isolation pattern (310), and gate structure (360), thereby forming a first opening (440). In exemplary embodiments, the insulating film structure (430) remaining after the etching process may have a circular or elliptical shape when viewed from above, and may be formed in multiple numbers spaced apart from each other along the first and second directions (D1, D2) on the substrate (300). At this time, each insulating film structure (430) may overlap in a vertical direction perpendicular to the upper surface of the substrate (300) with the ends of the adjacent active patterns (305) facing each other in the third direction (D3).

[0022] Referring to FIG. 5, a first conductive film (450), a first barrier film (460), a second conductive film (470), and a first mask film (480) can be sequentially stacked on an insulating film structure (430), an active pattern (305) exposed by a first opening (440), a device isolation pattern (310), and a gate structure (360), and these can together form a conductive structure film. At this time, the first conductive film (450) can fill the first opening (440).

[0023] The first conductive film (450) may include, for example, polysilicon doped with impurities, the first barrier film (460) may include, for example, a metallic silicon nitride such as titanium silicon nitride (TiSiN), the second conductive film (470) may include, for example, a metal such as tungsten, and the first mask film (480) may include, for example, a nitride such as silicon nitride.

[0024] Referring to FIGS. 6 and 7, a first etch stop layer and a first capping layer can be sequentially stacked on a first mask layer (480) of the conductive structure film, and then the first capping layer can be etched to form a first capping pattern (585), and the first etch stop layer, the first mask layer (480), the second conductive film (470), the first barrier layer (460), and the first conductive film (450) can be sequentially etched using this as an etching mask.

[0025] In exemplary embodiments, the first capping pattern (585) may be formed in multiple numbers so as to extend in the second direction (D2) and be spaced apart from each other along the first direction (D1).

[0026] As the above etching process is performed, a first conductive pattern (455), a first barrier pattern (465), a second conductive pattern (475), a first mask (485), a first etching stop pattern (565), and a first capping pattern (585) may be formed sequentially on the first opening (440), and a third insulating pattern (425), a first conductive pattern (455), a first barrier pattern (465), a second conductive pattern (475), a first mask (485), a first etching stop pattern (565), and a first capping pattern (585) may be formed sequentially on the second insulating film (410) of the insulating film structure (430) outside the first opening (440).

[0027] Hereinafter, the first conductive pattern (455), the first barrier pattern (465), the second conductive pattern (475), the first mask (485), the first etching stop pattern (565), and the first capping pattern (585) that are sequentially stacked will be referred to together as a bit line structure (595). At this time, the first conductive pattern (455), the first barrier pattern (465), and the second conductive pattern (475) can form a conductive structure together, and the first mask (485), the first etching stop pattern (565), and the first capping pattern (585) can form an insulating structure together. In exemplary embodiments, the bit line structure (595) can be extended in a second direction (D2) on the substrate (300) and can be formed in multiple numbers spaced apart from each other along a first direction (D1).

[0028] Referring to FIG. 8, after forming a first spacer film on a substrate (300) on which a bit line structure (595) is formed, fourth and fifth insulating films can be sequentially formed on the first spacer film.

[0029] The first spacer film can also cover the sidewall of the third insulating pattern (425) below the bit line structure (595) formed on the second insulating film (410), and the fifth insulating film can fill the remaining part of the first opening (440).

[0030] The first spacer film may include a nitride such as silicon nitride, for example, the fourth insulating film may include an oxide such as silicon oxide, for example, and the fifth insulating film may include a nitride such as silicon nitride.

[0031] Subsequently, an etching process may be performed to etch the fourth and fifth insulating films. In exemplary embodiments, the etching process may be performed by a wet etching process using, for example, phosphoric acid (H2PO3), SC1, and hydrofluoric acid (HF) as etchants, and all of the fourth and fifth insulating films except for the portion formed within the first opening (440) may be removed. Accordingly, most of the surface of the first spacer film, that is, the portion of the first spacer film other than the portion formed within the first opening (440), may be exposed, and the portions of the fourth and fifth insulating films remaining within the first opening (440) may form the fourth and fifth insulating patterns (610, 620), respectively.

[0032] Afterward, a second spacer film may be formed on the exposed first spacer film surface and the fourth and fifth insulating patterns (610, 620) formed within the first opening (440), and then anisotropically etched to form a second spacer (630) covering the sidewall of the bit line structure (595) on the first spacer film surface and the fourth and fifth insulating patterns (610, 620). The second spacer film may include an oxide, for example, silicon oxide.

[0033] Subsequently, a dry etching process using the first capping pattern (585) and the second spacer (630) as an etching mask can be performed to form a second opening (640) that exposes the upper surface of the active pattern (305), and the upper surface of the device isolation pattern (310) and the upper surface of the gate mask (350) can also be exposed by the second opening (640).

[0034] By the above dry etching process, the first spacer film portion formed on the upper surface of the first capping pattern (585) and the upper surface of the second insulating film (410) can be removed, and accordingly, a first spacer (600) covering the side wall of the bit line structure (595) can be formed. In addition, in the above dry etching process, the first and second insulating films (400, 410) can also be partially removed and remain as first and second insulating patterns (405, 415), respectively, on the lower part of the bit line structure (595). The first to third insulating patterns (405, 415, 425) sequentially stacked on the lower part of the bit line structure (595) can together form an insulating pattern structure.

[0035] Referring to FIG. 9, a third spacer film can be formed on the upper surface of the first capping pattern (585), the outer wall of the second spacer (630), a portion of the upper surface of the fourth and fifth insulating patterns (610, 620), and the upper surface of the active pattern (305), device isolation pattern (310), and gate mask (350) exposed by the second opening (640), and then the third spacer film can be anisotropically etched to form a third spacer (650) covering the side wall of the bit line structure (595). The third spacer film may include a nitride, for example, silicon nitride.

[0036] The first to third spacers (600, 630, 650) sequentially stacked along a horizontal direction parallel to the upper surface of the substrate (300) on the side wall of the bit line structure (595) may be collectively referred to as a spacer structure (660).

[0037] Afterward, a first sacrificial film (not shown) filling the second opening (640) can be formed on the substrate (300) to a sufficient height, and then the upper surface of the first capping pattern (585) can be flattened until the upper surface of the first capping pattern (585) is exposed to form a first sacrificial pattern (680). In exemplary embodiments, the first sacrificial pattern (680) may extend in a second direction (D2) and may be formed in multiple numbers spaced apart from each other by bit line structures (595) along the first direction (D1). The first sacrificial pattern (680) may include, for example, an oxide such as silicon oxide.

[0038] Referring to FIGS. 10 and 11, a second mask (not shown) including a plurality of third openings that are each extended in a first direction (D1) and spaced apart from each other in a second direction (D2) can be formed on a first capping pattern (585), a first sacrifice pattern (680), and a spacer structure (660), and an etching process can be performed using the first mask as an etching mask to etch the first sacrifice pattern (680), thereby forming a fourth opening that exposes the upper surface of the gate mask (350) of the gate structure (360).

[0039] In exemplary embodiments, each of the third openings may overlap the gate structure (360) in the vertical direction, and the fourth opening may be formed in multiple numbers spaced apart from each other along the second direction (D2) between bit line structures (595) adjacent to each other in the first direction (D1).

[0040] After removing the second mask, a second capping pattern (685) that fills each of the fourth openings can be formed. Depending on the layout of the fourth openings, the second capping pattern (685) may be formed in multiple numbers spaced apart from each other along the second direction (D2) between bit line structures (595) adjacent to each other in the first direction (D1). The second capping pattern (685) may include a nitride, for example, silicon nitride.

[0041] Meanwhile, the first sacrifice pattern (680) can be separated into multiple parts and remain spaced apart from each other in the second direction (D2) between the bit line structures (595).

[0042] Afterward, the remaining second sacrifice patterns (680) can be removed to form fifth openings that expose the upper surface of the active pattern (305) and the device isolation pattern (310). At this time, the fifth openings may be formed in multiple numbers so as to be spaced apart from each other along the second direction (D2) between bit line structures (595) adjacent to each other in the first direction (D1).

[0043] Subsequently, a lower contact plug membrane filling the fifth openings can be formed to a sufficient height, and the upper surface can be flattened until the upper surface of the first and second capping patterns (585, 685) and the spacer structure (660) is exposed. Accordingly, the lower contact plug membrane can be converted into a plurality of lower contact plugs (675) spaced apart from each other by the second capping patterns (685) along the second direction (D2) between the bit line structures (595).

[0044] The lower contact plug (675) may include, for example, polysilicon doped with impurities.

[0045] Referring to FIG. 12, the upper part of the lower contact plug (675) can be removed to expose the upper part of the spacer structure (660) formed on the side wall of the bit line structure (595).

[0046] Subsequently, a metal silicide pattern (700) can be formed on the upper surface of the lower contact plug (675). In exemplary embodiments, the metal silicide pattern (700) can be formed by forming a first metal film on the bit line structure (595), the spacer structure (660), the second capping pattern (685), and the lower contact plug (675), heat treating the first metal film, and then removing the unreacted portion from the first metal film. The metal silicide pattern (700) may include, for example, cobalt silicide, nickel silicide, titanium silicide, etc.

[0047] Referring to FIG. 13, after forming a second barrier film (730) on a bit line structure (595), a spacer structure (660), a second capping pattern (685), and a metal silicide pattern (700) formed on a substrate (300), a second metal film (740) can be formed on the second barrier film (730) to fill the space between the bit line structures (595).

[0048] The second barrier film (730) may include a metal nitride such as titanium nitride (TiN), for example, and the second metal film (740) may include a metal such as tungsten, for example.

[0049] Referring to FIG. 14, a planarization process can be performed on the upper surface of the second metal film (740) and the second barrier film (730) until the upper surface of the bit line structure (595), the spacer structure (660), and the second capping pattern (685) is exposed. The planarization process may include, for example, a chemical mechanical polishing (CMP) process and / or an etch back process.

[0050] As the above planarization process is performed, the second metal film (740) and the second barrier film (730) can be converted into a second metal pattern (745) and a second barrier pattern (735), respectively. In exemplary embodiments, the second metal pattern (745) may be formed in multiple numbers spaced apart from each other along each first and second direction (D1, D2).

[0051] Afterward, the upper portions of the first and second capping patterns (585, 685) and the spacer structure (660), and the upper portion of the adjacent second barrier pattern (735) can be removed, for example, through a dry etching process, thereby exposing the upper sidewall of the second metal pattern (745).

[0052] In exemplary embodiments, the upper surface of the second metal pattern (745) may be higher than the upper surface of the second barrier pattern (735), the first capping pattern (585), and the spacer structure (660), and the upper surface of the second barrier pattern (735) may be formed at substantially the same height as the upper surface of the first capping pattern (585) and the spacer structure (660).

[0053] Meanwhile, in one embodiment, an air gap may be formed by removing the second spacer (630) included in the spacer structure (660).

[0054] Referring to FIG. 15, first and second interlayer insulating films and a third mask film can be sequentially formed on a bit line structure (595), a spacer structure (660), a second capping pattern (685), a second barrier pattern (735), and a second metal pattern (745).

[0055] In exemplary embodiments, the first interlayer insulating film may comprise an oxide, for example, silicon oxide, and the second interlayer insulating film may comprise a nitride, for example, silicon nitride, and the third mask film may comprise a photoresist film or, in addition thereto, may further comprise, for example, a spin-on-hard mask (SOH) or an amorphous carbon film (ACL).

[0056] Afterwards, the third mask film can be patterned to form a third mask (930), and by using this as an etching mask to etch the first and second interlayer insulating films, the first and second interlayer insulating patterns (910, 920) can be formed, respectively.

[0057] A sixth opening (940) may be formed in the first and second interlayer insulation patterns (910, 920) that penetrates the first and second layers and exposes the upper surface and upper sidewall of the second metal pattern (745), the second barrier pattern (735), the spacer structure (660), and the upper surface of the first capping pattern (585). In exemplary embodiments, the sixth opening (940) may be formed in multiple numbers spaced apart from each other along each first and second direction (D1, D2) and may be arranged in a honeycomb shape when viewed from above. In this case, each sixth opening (940) may have a circular, elliptical, or polygonal shape when viewed from above.

[0058] Referring to FIGS. 16 and 17, a third metal pattern (950) can be formed to fill the sixth opening (940).

[0059] A third metal pattern (950) can be formed by forming a third metal film filling the sixth opening (940) on the upper surface and upper sidewall of the second metal pattern (745), the second barrier pattern (735), the spacer structure (660) and the upper surface of the first capping pattern (585), and the second interlayer insulation pattern (920), and flattening the third metal film until the upper surface of the second interlayer insulation pattern (920) is exposed. The third metal pattern (950) may include a metal such as tungsten, for example.

[0060] Since the third metal pattern (950) is formed within the sixth opening (940), it can be formed according to the shape and arrangement of the sixth opening (940). That is, the third metal pattern (950) can be formed in multiple numbers spaced apart from each other along each of the first and second directions (D1, D2), and can be arranged in a honeycomb shape when viewed from above. At this time, each third metal pattern (950) can have a circular, elliptical, or polygonal shape when viewed from the top surface.

[0061] In exemplary embodiments, the third metal pattern (950) and the second metal pattern (745) may be offset from each other when viewed from the top surface or in a vertical cross-sectional view. In exemplary embodiments, the bottom surface of the third metal pattern (950) may be in contact with the top surface and upper side wall of the second metal pattern (745), the top surface of the second barrier pattern (735), the top surface of the spacer structure (660), and the top surface of the first capping pattern (585).

[0062] The second metal pattern (745), the second barrier pattern (735), and the third metal pattern (950) can together form an upper contact plug (960), and the lower contact plug (675), the metal silicide pattern (700), and the upper contact plug (960) sequentially stacked on the substrate (300) can together form a contact plug structure.

[0063] In exemplary embodiments, the second and third metal patterns (745, 950) may be combined to include the same metal. Alternatively, the second and third metal patterns (745, 950) may include different metals, or even if they include the same metal, they may be distinguished from each other by a natural oxide film formed on the second metal pattern (745).

[0064] Meanwhile, when the second spacer (630) is removed to form the air gap, the upper end thereof may be covered by the first interlayer insulation pattern (910) and / or the third metal pattern (950) to form an air spacer. At this time, the air spacer formed on the first side wall of the bit line structure (595) may come into contact with the first interlayer insulation pattern (910), and the air spacer formed on the second side wall of the bit line structure (595) may come into contact with the third metal pattern (950).

[0065] Referring to FIG. 18, a capacitor (865) in contact with the upper surface of the upper contact plug (960) can be formed.

[0066] That is, on the upper contact plug (960) and the second interlayer insulation pattern (920) 2 An etch stop layer (830) and a mold layer (not shown) may be formed sequentially, and partially etched to form a seventh opening that partially exposes the upper surface of the upper contact plug (960). The second etch stop layer (830) may include a nitride such as silicon boron nitride (SiBN), silicon carbonitride (SiCN), etc.

[0067] A lower electrode film (not shown) is formed on the side wall of the seventh opening, the upper surface of the exposed upper contact plug (960), and the mold film, and a sacrificial film (not shown) that sufficiently fills the remaining portion of the seventh opening is formed on the lower electrode film, and then the lower electrode film can be node-separated by flattening the upper portions of the lower electrode film and the sacrificial film until the upper surface of the mold film is exposed. The remaining sacrificial film and the mold film can be removed, for example, by performing a wet etching process using LAL as an etchant, and accordingly, a cylindrical lower electrode (840) can be formed on the upper surface of the exposed upper contact plug (960). Alternatively, a pillar-shaped lower electrode (840) that completely fills the seventh opening may be formed. The lower electrode (840) may include a metal, for example, a metal nitride such as titanium nitride, a metal silicide, or polysilicon doped with impurities.

[0068] In one embodiment, a first interface film may be further formed between the lower electrode (840) and the dielectric film (850). In this case, the first interface film may include at least one of niobium, silicon, and titanium.

[0069] Subsequently, a dielectric film (850) is formed on the surface of the lower electrode (840) and the second etching stop layer (830), and an upper electrode (860) is formed on the dielectric film (850), thereby forming a capacitor (865) that includes the lower electrode (840), the dielectric film (850), and the upper electrode (860), respectively.

[0070] The dielectric film (850) may include, for example, a metal oxide such as hafnium nitride, zirconium nitride, aluminum nitride, etc., and the upper electrode (860) may include a metal, for example, a metal nitride such as titanium nitride, a metal silicide, silicon-germanium (SiGe) doped with impurities, etc.

[0071] In one embodiment, a second interface film may be further formed between the dielectric film (850) and the upper electrode (860). The second interface film may include, for example, at least one of niobium and titanium.

[0072] Afterwards, the semiconductor device can be manufactured by forming an upper interlayer insulating film, upper wiring, etc. on the capacitor (865).

[0073] As described above, the upper contact plug (960) can be formed by forming a second barrier film (730) and a second metal film (740) on a bit line structure (595), a spacer structure (660), and a metal silicide pattern (700), and then flattening the second barrier film (730) and the second metal film (740) until the upper surface of the bit line structure (595) and the spacer structure (660) is exposed to form a second barrier pattern (735) and a second metal pattern (745), respectively, and then removing the upper portion of the bit line structure (595), the spacer structure (660), and the second barrier pattern (735) to expose the upper sidewall of the second metal pattern (745), and then forming a third metal pattern (950) to contact the upper surface and upper sidewall of the exposed second metal pattern (745) through a damascene process.

[0074] The third metal pattern (950) is formed to form the first and second interlayer insulating films (910, 920), and then to form a sixth opening (940) that penetrates through them to expose the upper surface and upper sidewall of the second metal pattern (745) and fills it, so the third metal pattern (950) can be formed to contact not only the upper surface of the second metal pattern (745) but also the upper sidewall. Accordingly, the contact area between the lower second metal pattern (745) and the upper third metal pattern (950) can be increased.

[0075] For example, if a plurality of upper contact plugs form a second barrier film (730) and a second metal film (740) and partially etch them to form a landing pad for contacting a capacitor (865) on pillar structures including a bit line structure (595) and a spacer structure (660) formed on the side wall thereof, the spacing between the pillar structures may be narrow, making it difficult to form the upper contact plugs so that they are spaced apart from each other through the etching process. That is, in order to form the upper contact plugs so that they are sufficiently spaced apart without being connected to each other, the second barrier film (730) and the second metal film (740) must be sufficiently etched; however, in this case, the portion of the second barrier film (730) and the second metal film (740) formed between the adjacent pillar structures is locally removed, so that the upper part where the landing pad is formed and the lower part formed on the lower contact plug (675) may not be connected to each other.

[0076] However, in exemplary embodiments, a plurality of upper contact plugs (960) first form a second metal pattern (745) and then form a third metal pattern (950) through a damascene process to contact the upper surface and upper side wall of the second metal pattern (745), so that the third metal pattern (950) acting as a landing pad and the second metal pattern (745) formed on the lower contact plug (675) can be formed to be connected without being separated from each other.

[0077] Meanwhile, the above semiconductor device may include the following structural features.

[0078] That is, the semiconductor device may include an active pattern (305) formed on a substrate (300); a gate structure (360) extending in a first direction (D1) and embedded on the upper part of the active pattern (305); a bit line structure (595) extending in a second direction (D2) and formed on the central part of the active pattern (305); a spacer structure (660) formed on the side wall of the bit line structure (595); the contact plug structure formed on each end of the active pattern (305); and a capacitor (865) formed on the contact plug structure.

[0079] In exemplary embodiments, the contact plug structure may include a lower contact plug (675); a metal silicide pattern (700) formed on the lower contact plug (675); a barrier pattern (735) formed on the metal silicide pattern (700); a second metal pattern (745) in which the bottom surface and bottom sidewall are covered by the barrier pattern (735); and a third metal pattern (950) in contact with the top surface and top sidewall of the second metal pattern (745), and the top surface of the bit line structure (595) and the spacer structure (660).

[0080] In exemplary embodiments, the upper surface of the second metal pattern (745) may be higher than the upper surface of the bit line structure (595).

[0081] In exemplary embodiments, the active pattern (305) may be extended in a third direction (D3) and may be formed in multiple numbers spaced apart from each other along the first and second directions (D1, D2), the gate structure (360) may be formed in multiple numbers spaced apart from each other along the second direction (D2), and the bit line structure (595) may be formed in multiple numbers spaced apart from each other along the first direction (D1).

[0082] In exemplary embodiments, the contact plug structures may be formed in multiple numbers spaced apart from each other along first and second directions (D1, D2) and may be arranged in a honeycomb shape when viewed from above.

[0083] In exemplary embodiments, the upper surface of the second metal pattern (745) may be flat.

[0084] In exemplary embodiments, the upper surface of the barrier pattern (735) may have a constant height.

[0085] In exemplary embodiments, the bit line structure (595) may include the conductive structure and the insulating structure stacked on the substrate (100). In this case, the conductive structure may include a first conductive pattern (455), a first barrier pattern (465), and a second conductive pattern (475), and the insulating structure may include a first mask (485), a first etch stop pattern (565), and a first capping pattern (585).

[0086] FIGS. 19 and 20 are cross-sectional views illustrating a method for manufacturing a semiconductor device according to exemplary embodiments. Since the method for manufacturing the semiconductor device includes processes that are substantially identical or similar to the processes described with reference to FIGS. 1 to 18, a redundant description thereof is omitted.

[0087] Referring to FIG. 19, after performing processes substantially identical or similar to those described with reference to FIG. 1 to 15, the side of the first interlayer insulation pattern (910) can be partially removed to expand the lower part of the sixth opening (940), thereby forming a third recess (945) communicating therewith.

[0088] The third recess (945) can be formed, for example, through a dry etching process or a wet etching process.

[0089] As the third recess (945) is formed and the lower portion of the sixth opening (940) is expanded, the upper surface area of ​​the second metal pattern (745) exposed by the sixth opening (940) may be increased, and the upper surface area of ​​the spacer structure (660) and the first capping pattern (585) adjacent to the second metal pattern (745) exposed by the sixth opening (940) may also be increased.

[0090] Referring to FIG. 20, the semiconductor device can be manufactured by performing processes that are substantially identical or similar to the processes described with reference to FIG. 16 to FIG. 18.

[0091] When forming the third metal pattern (950) by performing the processes described with reference to FIGS. 16 and 17, the area of ​​the upper surface of the second metal pattern (745) exposed by the sixth opening (940) is increased, so the area of ​​contact between the third metal pattern (950) and the second metal pattern (745) can be increased.

[0092] In addition, since the upper surface area of ​​the spacer structure (660) and the first capping pattern (585) adjacent to the second metal pattern (745) exposed by the sixth opening (940) has been increased, the possibility of a defect occurring in which the lower part of the third metal pattern (950) cannot contact the upper side wall of the second metal pattern (745) due to misalignment, etc., can be prevented.

[0093] In the semiconductor device, the third metal pattern (950) included in the upper contact plug may include an upper portion having a first width and a lower portion having a second width greater than the first width. Accordingly, the contact area of ​​the third metal pattern (950) with the lower second metal pattern (745) may be increased, and even if misalignment occurs during the formation process, they may be better connected without being separated from each other. Explanation of the symbols

[0094] 300: Substrate 305: Active pattern 310: Device isolation pattern 330: Gate isolation pattern 340: Gate electrode 350: Gate mask 360: Gate structure 400, 410, 420: First to third insulating films 405, 415, 425, 610, 620: 1st to 5th insulation patterns 430: Insulating film structure 440, 640, 940: 1st, 2nd, 6th openings 450, 470: 1st and 2nd Challenge Stages 455, 475: 1st and 2nd Challenge Patterns 460, 730: 2nd, 2nd barrier membrane 465, 735: 1st, 2nd barrier pattern 480: 1st mask 485, 930: 1st and 3rd masks 565: 1st etch stop pattern 585, 685: 1st and 2nd capping patterns 595: Bit line structure 600, 630, 650: 1st to 3rd spacers 660: Spacer structure 675: Lower contact plug 700: Metal silicide pattern 740: Second metal film 745, 950: Second and third metal patterns 830: Second etch stop layer 840, 860: Lower, upper electrodes 850: Dielectric film 865: Capacitor 910, 920: Insulation pattern between the first and second layers 945: 3rd recess 960: Upper contact plug

Claims

Claim 1 A semiconductor device comprising: a bit line structure formed on a substrate; a lower contact plug formed on the substrate adjacent to the bit line structure; a first metal pattern formed on the lower contact plug; an upper contact plug including a second metal pattern in contact with the upper surface and upper sidewall of the first metal pattern; and a capacitor formed on the upper contact plug, wherein the upper surface of the first metal pattern is higher than the upper surface of the bit line structure, and the upper sidewall of the first metal pattern extends toward the upper surface of the first metal pattern from the same level as the upper surface of the bit line structure. Claim 2 In claim 1, the upper surface of the first metal pattern is a flat semiconductor device. Claim 3 A semiconductor device according to claim 1, further comprising a barrier pattern covering the bottom surface and lower sidewall of the first metal pattern. Claim 4 In paragraph 3, the bottom surface of the second metal pattern is in contact with the upper surface of the barrier pattern of the semiconductor device. Claim 5 In paragraph 3, the upper surface of the barrier pattern is a semiconductor device having a certain height. Claim 6 A semiconductor device according to claim 1, further comprising a spacer structure formed on the side wall of the bit line structure, wherein the bottom surface of the second metal pattern contacts the top surface of the bit line structure and the top surface of the spacer structure. Claim 7 A semiconductor device according to claim 1, wherein the second metal pattern comprises an upper portion having a first width and a lower portion having a second width greater than the first width. Claim 8 In claim 1, the bit line structure is a semiconductor device comprising a conductive structure and an insulating structure stacked on the substrate. Claim 9 A semiconductor device comprising: a bit line structure formed on a substrate; a lower contact plug formed on the substrate adjacent to the bit line structure; a first metal pattern formed on the lower contact plug; a barrier pattern covering the bottom surface and lower sidewall of the first metal pattern; an upper contact plug including a second metal pattern in contact with the top surface and upper sidewall of the first metal pattern and the top surface of the barrier pattern; and a capacitor formed on the upper contact plug, wherein the top surface of the barrier pattern has a certain height and the upper sidewall of the first metal pattern extends toward the top surface of the first metal pattern from the same level as the top surface of the bit line structure. Claim 10 An active pattern formed on a substrate; a gate structure extending in a first direction parallel to the upper surface of the substrate and embedded in the upper portion of the active pattern; a bit line structure extending in a second direction parallel to the upper surface of the substrate and perpendicular to the first direction and formed on the central portion of the active pattern; a spacer structure formed on the side wall of the bit line structure; a contact plug structure formed on each end of the active pattern; and a capacitor formed on the contact plug structure, wherein the contact plug structure comprises: a lower contact plug; a metal silicide pattern formed on the lower contact plug; a barrier pattern formed on the metal silicide pattern; and a first metal pattern whose bottom surface and bottom side wall are covered by the barrier pattern. A semiconductor device comprising a first metal pattern and an upper side wall, and a second metal pattern in contact with the upper surface of the bit line structure and the spacer structure, wherein the upper surface of the first metal pattern is higher than the upper surface of the bit line structure, and the upper side wall of the first metal pattern extends toward the upper surface of the first metal pattern from the same level as the upper surface of the bit line structure.

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