Systems and methods for processing semiconductor wafers using front-end processed wafer geometry metrics

Abstract

A method for processing semiconductor wafers includes the step of obtaining measurement data from the surface of a semiconductor wafer processed by a front-end process tool. The method includes the steps of determining the center plane of the wafer based on the measurement data, generating raw shape profiles, and generating ideal shape profiles. The method further includes the steps of generating Gapi profiles based on the raw shape profiles and the ideal shape profiles, and calculating the Gapi value of the semiconductor wafer based on the Gapi profiles. The generated Gapi profiles and / or the calculated Gapi value may be used to tune the front-end process tool and / or to sort the semiconductor wafer for polishing. Systems include at least a front-end process tool, a flatness measurement tool, and a computing device.

Description

Technology Field

[0001] Cross-reference regarding related applications

[0002] This application claims priority to U.S. provisional patent application No. 63 / 260,295 filed on August 16, 2021, the entirety of which is incorporated by reference.

[0003] field

[0004] The present disclosure generally relates to the processing of semiconductor wafers, and more specifically, to systems and methods for processing semiconductor wafers using front-end processed wafer geometry metrics. Background Technology

[0005] Generally, semiconductor wafers are used in the production of integrated circuit (IC) chips on which circuits are printed. The circuits are printed as identical integrated circuits ("dies") in a miniaturized form on the surfaces of the wafers in a multi-stage fabrication process. Specifically, the process includes various stages of electron beam lithography or photolithography processing steps ("lithography") and chemical or physical processing steps (e.g., chemical mechanical polishing, etching, and passivation). In each stage, a new pattern layer is added to the surface of the wafer, or an existing layer is modified. The precise alignment ("overlay") of the layers is critical to the final performance of the chips.

[0006] Chip manufacturers require wafers with extremely flat and parallel surfaces to mitigate or eliminate overlay errors and ensure that the maximum number of chips can be fabricated from each wafer. Initially, wafers are obtained from single-crystal ingots of suitable material (e.g., silicon). Wafers can be sliced ​​from the ingot, for example, using a wire saw. Subsequently, the surfaces of the raw wafers undergo preliminary planarization and etching using additional front-end process tools, such as grinding, lapping, or etching tools. Edges can also be ground and / or rounded using a beveling tool. Subsequently, the surfaces are polished to create a smooth, highly reflective, mirrored wafer surface.

[0007] Conventional metrology tools can be used to determine whether the surface(s) of a polished wafer satisfy geometric (e.g., shape and / or flatness) specifications prior to lithography. Shape is the long-wavelength component of the wafer geometry in an unchucking state, which is defined as the deviation of the wafer's median surface relative to the best-fit median surface reference plane. This can be characterized by global parameters such as warping, which is the sum of maximum positive and negative deviations from the best-fit plane, and bending, which is the distance between the best-fit plane and the surface at the center of the wafer. Flatness is the variation in wafer thickness relative to the reference plane. This can be characterized by global parameters such as the maximum variation in wafer thickness from the ideal flat back surface (GBIR), or by local parameters such as site flatness, the front reference surface, the least squares reference plane, and the range (SFQR).

[0008] In the case of conventional wafer metrics, these measurements are sufficient only to predict overlay errors early in the fabrication process (e.g., between the first patterned layers). As more layers are formed on the wafer, elastic deformation occurs, which can lead to changes in wafer geometry. Overlay errors can be characterized by in-plane and out-of-plane distortion of the wafer. Patterned wafer geometry measurement systems (such as those manufactured by KLA-Tencor Corporation) can be used to measure these distortions between patterning steps to account for overlay errors and to provide wafer metrics. However, these conventional systems utilize high-accuracy inspection tools, require polished surfaces, and perform measurements after at least part of the fabrication process has begun. There are no solutions to provide a pre-fabrication wafer distortion prediction index using flatness inspection measurements of front-end processed wafers.

[0009] This background section is intended to introduce the reader to various aspects of the relevant art, which may relate to the various aspects of the present disclosure described and / or claimed below. This discussion is considered useful for providing background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements should be read in that context and not as an acknowledgment of the prior art.

[0010] In one embodiment, a method for processing semiconductor wafers comprises the steps of providing a first semiconductor wafer processed by a front-end process tool, and acquiring measurement data from scan lines along the surface of the first semiconductor wafer. The measurement data of each scan line includes a thickness profile and a surface profile. The method further comprises the steps of determining a center plane of the wafer based on the measurement data of the scan lines, generating a raw shape profile for each scan line based on the measurement data of the scan line and the center plane of the wafer, and generating an ideal shape profile for each scan line based on polynomial regression of the raw shape profile. The method further comprises the steps of generating a Gapi profile for each scan line based on the raw shape profile and the ideal shape profile, and calculating a Gapi value of the first semiconductor wafer based on the Gapi profiles of the scan lines. The method further comprises the step of determining whether the Gapi value of the first semiconductor wafer is within a predetermined threshold. If the Gapi value of the first semiconductor wafer is not within a predetermined threshold, the method comprises the steps of tuning a front-end process tool based on at least one of the Gapi profiles of the scan lines of the first semiconductor wafer, and processing the second semiconductor wafer with the tuned front-end process tool. If the Gapi value of the first semiconductor wafer is within a predetermined threshold, the method comprises the step of sorting the first semiconductor wafer for polishing.

[0011] In another embodiment, a system for processing semiconductor wafers includes a front-end process tool for front-end processing of a semiconductor wafer, and a flatness inspection tool for acquiring measurement data from scan lines following the surface of a front-end processed wafer. The measurement data for each scan line includes a thickness profile and a surface profile. The system also includes a computing device connected to the flatness inspection tool and the front-end process tool. The computing device is configured to receive measurement data of scan lines from the flatness inspection tool, determine the center plane of the wafer based on the measurement data of scan lines, generate a raw shape profile for each scan line based on the measurement data of the scan line and the center plane of the wafer, and generate an ideal shape profile for each scan line based on polynomial regression of the raw shape profile. The computing device is also configured to generate a Gapi profile for each scan line based on the raw shape profile and the ideal shape profile, calculate the Gapi value of the front-end processed wafer based on the Gapi profiles of the scan lines, and determine whether the Gapi value of the front-end processed wafer is within a predetermined threshold. If the Gapi value of the front-end processed wafer is not within a predetermined threshold, the computing device is configured to modify the front-end process tool based on at least one of the Gapi profiles of the scan lines.

[0012] In another aspect, a method for processing semiconductor wafers comprises the steps of providing a first semiconductor wafer processed by a front-end process tool and acquiring measurement data of an edge profile of the first semiconductor wafer. The method further comprises the steps of determining an edge profile center point based on the measurement data, generating a raw height profile based on the measurement data and the edge profile center point, and generating an ideal edge profile based on polynomial regression of the raw height profile. The method further comprises the steps of generating a Gapi edge profile of the first semiconductor wafer based on the raw height profile and the ideal edge profile, calculating a Gapi edge value of the first semiconductor wafer based on the Gapi edge profile, and determining whether the Gapi edge value of the first semiconductor wafer is within a predetermined threshold. If the Gapi edge value of the first semiconductor wafer is not within the predetermined threshold, the method comprises the steps of tuning a front-end process tool based on the Gapi edge profile of the first semiconductor wafer and processing a second semiconductor wafer with the tuned front-end process tool. If the Gapi edge value of the first semiconductor wafer is within a predetermined threshold, the method includes the step of sorting the first semiconductor wafer for polishing.

[0013] In another embodiment, a system for processing semiconductor wafers includes a front-end processing tool for front-end processing of a semiconductor wafer, and a flatness inspection tool for acquiring measurement data of an edge profile of a front-end processed wafer. The system also includes a computing device connected to the flatness inspection tool and the front-end processing tool. The computing device is configured to receive measurement data from the flatness inspection tool, determine an edge profile center point based on the measurement data, generate a raw height profile based on the measurement data and the edge profile center point, and generate an ideal edge profile based on polynomial regression of the raw height profile. The computing device is also configured to generate a Gapi edge profile of the front-end processed wafer based on the raw height profile and the ideal edge profile, calculate a Gapi edge value of the front-end processed wafer based on the Gapi edge profile, and determine whether the Gapi edge value of the front-end processed wafer is within a predetermined threshold. If the Gapi edge value of the front-end processed wafer is not within a predetermined threshold, the computing device is configured to modify the front-end process tool based on the Gapi edge profile of the front-end processed wafer.

[0014] Various improvements to the features mentioned in relation to the embodiments mentioned above exist. Additionally, additional features may also be included in the embodiments mentioned above. These improvements and additional features may exist individually or in any combination. For example, various features discussed below in relation to any of the exemplified embodiments may be included in any of the embodiments described above, either alone or in any combination. Brief explanation of the drawing

[0015] Figure 1 is a process flow of a method for processing a wafer using a polished wafer geometric metric. FIG. 2 is a process flow of a method for processing a wafer using a front-end processed wafer geometry metric according to the present disclosure. Figure 3 is a schematic diagram of four scan lines on a front-end processed wafer surface used to acquire front-end processed wafer geometric measurement data by a geometric measurement tool. Figure 4 is a schematic diagram of eight scan lines on a front-end processed wafer surface used to acquire front-end processed wafer geometric measurement data by a geometric measurement tool. FIG. 5 is a schematic diagram of a spiral scan on a front-end processed wafer surface used to acquire front-end processed wafer geometric measurement data by a geometric measurement tool. Figure 6 is a schematic cross-sectional view of a front-end processed wafer. FIGS. 7a and FIGS. 7b are sets of plots generated using measurement data obtained by the wafer surface scan and geometric measurement tool of FIGS. 3 to 5. FIG. 8 is a process flow of a method for calculating the Gapi value of a front-end processed wafer according to the present disclosure. Figure 9 is a contour map of a front-end processed wafer showing the raw profile of the wafer. Figure 10 is a contour map of the front-end processed wafer of Figure 9 showing the Gapi profile of the wafer. Figure 11 is a contour map of the front-end processed wafer of Figure 9 illustrating the in-plane distortion (IPD) profile of the wafer. Figure 12 is a plot showing the correlation between the Gapi values ​​calculated for front-end processed wafers and the root mean square IPD values ​​calculated for the wafers. Figure 13 is a bar graph illustrating the relationship between the calculated Gapi values ​​of front-end processed wafers and the back-end yield percentages of the wafers. Figure 14 is a process flow of a method for adjusting a front-end process tool based on Gapi values. Figure 15 is a contour map of a front-end processed wafer showing the raw profile of the wafer before tuning of the front-end process tool. Figure 16 is a plot generated using measurement data of the front-end processed wafer of Figure 15, obtained by a wafer surface scan and geometric measurement tool following a scan line. Figure 17 is a contour map of the front-end processed wafer of Figure 15 showing the Gapi profile of the wafer and the Gapi value calculated from the Gapi profile. Figure 18 is a contour map of the front-end processed wafer of Figure 15 showing the IPD profile of the wafer and the root mean square of the IPD calculated from the IPD profile. Figure 19 is a contour map of a front-end processed wafer showing the raw profile of the wafer after tuning of the front-end process tool. FIG. 20 is a plot generated using measurement data of the front-end processed wafer of FIG. 19, obtained by a wafer surface scan and geometric measurement tool along the scan line. Figure 21 is a contour map of the front-end processed wafer of Figure 19 showing the Gapi profile of the wafer and the Gapi value calculated from the Gapi profile. Figure 22 is a contour map of the front-end processed wafer of Figure 19 showing the IPD profile of the wafer and the root mean square of the IPD calculated from the IPD profile. FIG. 23 is a process flow of a method for calculating Gapi edge values ​​of a front-end processed wafer according to the present disclosure. FIGS. 24 to 26 are plots of edge profiles of front-end processed wafers. FIG. 27 is a block diagram of an exemplary system for processing a wafer using a front-end processed wafer geometry metric according to the present disclosure. Specific details for implementing the invention

[0016] Exemplary systems and methods use Gapi wafer geometry metrics generated and / or calculated from measurement data of semiconductor wafers. Generally and in the embodiments of this disclosure, suitable semiconductor wafers (which may also be referred to as “wafers” or “silicon wafers”) include single-crystal silicon wafers, such as substrate wafers obtained by slicing wafers from ingots formed by, for example, the Czochralski method or the float zone method. Each semiconductor wafer includes a central axis, a front surface, and a rear surface parallel to the front surface. The front and rear surfaces are generally perpendicular to the central axis. A circumferential edge connects the front surface and the rear surface. Semiconductor wafers may be made of any diameter suitable for use by a person skilled in the art, such as wafers with diameters of 200 mm, 300 mm, greater than 300 mm, or even 450 mm.

[0017] The Gapi metric can be used as an in-plane distortion (IPD) prediction index and to sort semiconductor wafers based on the correlation between predicted IPD and expected back-end yield. The Gapi metric can be appropriately generated and / or calculated from measurement data of front-end processed semiconductor wafers, but it can also be used in other applications. The Gapi metric can be utilized to tune front-end process tools, or alternatively, to sort wafers with acceptable Gapi metrics for further processing.

[0018] FIG. 1 illustrates a conventional general process flow (100) for processing semiconductor wafers. In step (102), a front-end processed wafer is provided for further processing. As used herein, "front-end processed" is a wafer processed by a front-end processing tool, for example, a wafer sliced ​​from a single-crystal ingot of a semiconductor material (e.g., silicon). The front-end processed wafer may also have one or both surfaces etched, lapped, or ground, and / or edges rounded. Examples of front-end processing tools include wire saws, lapping tools, grinding tools, beveling tools, and etching tools.

[0019] The surface conditions of the front-end processed wafers provided by step (102) are still relatively rough and are generally not suitable for lithography processing, particularly for applications requiring a flat surface. In step (104), the front-end processed wafer is polished. The polishing operation in step (104) may be an intermediate polishing operation and / or a finishing polishing operation. In the intermediate polishing operation, the front surface of the front-end processed wafer is polished to improve flatness and remove handling scratches. In the finishing polishing operation, the front surface of the wafer is finished polished to remove fine or “micro” scratches from the front surface and to create a damage-free front surface with high reflectivity of the wafer. As used herein, “in process” is a wafer having an intermediate and / or finishing polished front surface and optionally undergoing one or more patterning processing steps as described below. After polishing in step (104) and optionally after additional patterning processing steps, to determine the shape and flatness of the wafer during the process as well as other parameters such as nanotopography, a high-accuracy inspection tool (e.g., WaferSight manufactured by KLA-Tencor Corporation) TM A 2 or 2+ bare wafer geometry measurement system) may be used. From these measurements, conventional metrics may be used in step (106) to predict overlay errors for at least the first patterning step.

[0020] In step (108), a series of patterning processing steps involving lithography and other chemical and / or mechanical processing (e.g., chemical mechanical polishing, etching, passivation, diffusion, etc.) are performed to form integrated circuit(s) ("dies") on a wafer. Various layers, which may include photomasked resist patterns, oxide layers, and metal layers, are deposited on the wafer. Each layer formed on the surface has non-uniform intrinsic stress, which can cause elastic deformation of the wafer shape (e.g., IPD). To mitigate the impact of overlay errors on product yield, steps (106 and 108) may be repeated sequentially, thereby correcting overlay errors during the process by adjusting the lithography tool. However, as design rules for lithography patterns continue to shrink (e.g., to less than 10 nm), controlling the overlay during the process becomes more difficult. If a correction action cannot be taken by the lithography tool, uncorrectable overlay errors occur. As a result, a low back-end yield of high-quality wafers is realized in the wafer grading step (110).

[0021] Referring to FIG. 2, an exemplary general process flow (200) for processing semiconductor wafers with improved overlay and process control is illustrated. In process (100), a wafer is provided in a step (202) similar to the step (102) discussed above. An additional process step (204) is included in process (200), where grading of the front-end processed wafer is performed prior to further processing and / or fabrication of the wafer. For example, the front-end wafer grading step (204) may occur prior to the wafer polishing step (208) and / or prior to the patterning and layer formation step (212). In step (204), a wafer metric, such as the Gapi metric as discussed in more detail herein, is determined based on the shape and / or flatness of the front-end processed wafer. Subsequently, in step (206), the wafer is sorted based on this metric. For example, in step (206), the wafer may be determined to be outside the desired specifications based on a metric and is discarded or identified for further front-end processing. If the wafer is determined to satisfy the desired specifications, the wafer may be further processed, for example, starting from the polishing step (208). The desired specifications may be, for example, a tolerance level of the predicted IPD during wafer processing based on the correlated back-end yield.

[0022] One advantage of the process (200) is that wafer grading occurs before certain irreversible processing steps occur. Out-of-specification wafers sorted in step (206) can be salvaged by further processing using front-end tools to ensure that the wafer metric is within the desired specifications. For example, wrapping or grinding processes can be repeated to adjust the shape and / or flatness of the wafer. Additionally, by identifying out-of-specification wafers early in wafer processing, an improved back-end yield of the processed wafers can be achieved in the wafer grading step (214). This ultimately increases the quantity of high-quality grade dies formed and reduces costs associated with uncorrectable overlay errors occurring during manufacturing. Furthermore, because the wafers being further processed have been inspected for the predicted IPD, the need for overlay control during the process can be reduced or eliminated. In this regard, more efficient sequencing between overlay control in step (210) and wafer patterning in step (212) can be realized.

[0023] Referring to FIGS. 3 through 8, an exemplary method for determining a Gapi metric for a front-end processed wafer (300) is described. FIG. 8 illustrates a process flow (400) for determining a Gapi metric. In step (402), a geometric measurement tool (also referred to herein as a flatness inspection tool) is used to obtain measurement data from a front-end processed wafer (300) (illustrated in FIGS. 3 through 6). Examples of suitable geometric measurement tools include Kobelco SBW series tools, Kobelco LGW series tools, and Kobelco LSW series tools. The geometric measurement tool appropriately obtains measurement data of one or both surfaces, including the thickness and surface height of points along one or both surfaces of the wafer (300), using a capacitance probe or an interferometer. In one example, the geometric measurement tool is a Kobelco SBW-330 tool.

[0024] As illustrated in FIGS. 3 through 5, a geometric measurement tool may acquire measurement data by scanning along diameter lines (302) (also referred to herein as scan lines (302) or scan diameter lines (302)) extending across the surface (304) (e.g., the front surface) of a wafer (300) (Fig. 3 and 4) or by a spiral scan of the surface (304) of the wafer (300) (Fig. 5). The geometric measurement tool may acquire measurement data by scanning along two or more diameter lines (302), such as four diameter lines (302) (illustrated in FIG. 3) or eight diameter lines (302) (illustrated in FIG. 4). The wafer (300) being measured may be in an un-chucked (i.e., freestanding) state.

[0025] Measurement data obtained by a geometric measurement tool includes surface profiles of a wafer (300). Each surface profile is obtained along a scan diameter line (302) by measuring surface heights at points on the surface (304) (shown in FIG. 6) positioned along the individual scan diameter line (302). For example, each surface profile may include surface heights measured at more than 100, more than 200, or more than 290 points along the individual diameter line (302). Each point has a position along the diameter line (302) extending across the surface (304) measured as a distance (in millimeters, in mm) from the center (306) of the surface (304). The surface height measured at each point is H n It can be expressed as (x), where n identifies the scan diameter line, and x is the relative distance (in mm) of a point from the center (306) of the wafer (300) measured along the scan diameter line n. The surface height is the reference height H ref = is determined as a distance from 0. The surface profile obtained by scanning along each diameter line (302) includes a range of surface heights measured at points along the individual diameter line (302). In one embodiment, the surface profiles are obtained by scanning the diameter lines (302) only along the surface (304) (e.g., the front surface) of the wafer (300). In other embodiments, the surface profiles are obtained by scanning the diameter lines (302) along both the surface (304) and the surface (308) (shown in FIG. 6) (i.e., the front and rear surfaces) of the wafer (300).

[0026] The measurement data obtained by the geometric measurement tool also includes thickness profiles of the wafer (300). Each thickness profile is obtained along the scan diameter line (302) by measuring the thickness at points along the individual scan diameter line (302). The thickness at each point along each diameter line (302) is measured as the distance between the point and the corresponding point at the same position on another surface (308) of the wafer (300). Thus, the thickness is the surface height (H) of the point on the surface (304). n (x)) and the surface height of the corresponding point on the surface (308) can be determined by the thickness at each point along the diameter line (302) T n It can be expressed as (x), where n identifies the scan diameter line, and x is the relative distance (in mm) of a point from the center (306) of the wafer (300) measured along the scan diameter line n. The thickness profile obtained by scanning along each diameter line (302) includes a range of thickness values ​​measured at points along the individual diameter line (302).

[0027] Referring again to FIG. 8, in step (404), the center plane (CP) (shown in FIG. 6) of the wafer (300) is determined based on surface profiles and thickness profiles obtained by scanning along the diameter lines (302). The center plane (CP) may be based on the thickness plane (TP) (shown in FIG. 6) of the wafer (300). The thickness plane (TP) is located between the front surface (304) and the rear surface (308) of the wafer (300). In one example, the thickness plane (TP) is the surface height (H) at each point along the scan diameter lines (302). n (x)) plus thickness (T nIt is mapped as half of (x). In this regard, the thickness plane (TP) may include points corresponding to each measured point of the scan lines (302) along the surface(s) (304 and 308) of the wafer (300). Subsequently, the center plane (CP) may be determined based on the regression analysis of the points along the thickness plane (TP), such as by least squares optimal fitting, moving average, or polynomial fitting. In one exemplary embodiment, the center plane (CP) is determined by least squares optimal fitting of the points along the thickness plane (TP).

[0028] FIG. 6 illustrates a schematic cross-sectional view of a scanned front-end processed wafer (300) having a front surface (304) and a rear surface (308) taken along one of the diameter lines (302). Measurement data including surface profiles and thickness profiles of the wafer (300) at points along the scan diameter lines (302) (shown in FIG. 3 and FIG. 4) extending across the front surface (304) and optionally across the rear surface (308) surface height (H n (x)) and thickness (T n It can be obtained by measuring (x). The thickness (T) at each point n (x)) is the distance between a point on the front surface (304) and a corresponding point on the rear surface (308). The thickness plane (TP) of the wafer (300) is the surface height (H) at each point. n (x)) and thickness (T n It can be determined based on (x). As described above, the center plane (CP) of the wafer (300) is determined by regression analysis of points along the thickness plane (TP). The drawing shown in FIG. 6 is for reference only and is not intended to depict the surface height or thickness at measured points on the wafer in actual scale.

[0029] Referring again to FIG. 8, in step (406), a raw shape profile is generated for the wafer (300) along each scan diameter line (302). Each raw shape profile is generated based on acquired measurement data including a surface profile and a thickness profile along the determined center plane (CP) of the wafer (300) and the individual scan diameter line (302). Each raw shape profile includes raw shape values ​​calculated at each scanned point along the individual scan diameter line (302). The raw shape includes the surface height (H) at each point. n (x)) and thickness (T n It can be calculated as a function of the height of a corresponding point at the same position on (x) and the center plane (CP). In one example, the primitive shape (RS n ) is calculated at each point by the following formula:

[0030] RS n (x) = H n (x) + 0.5*(T n (x) - CP n (x)

[0031] Here, n identifies the scan diameter line, x is the relative distance (in mm) of a point from the center (306) of the wafer (300) measured along the scan diameter line n, and H n (x) is the measured surface height of a point along the scan diameter line n at x, and T n (x) is the measured thickness of a point along the scan diameter line n at x, and CP n (x) is the height of a point on the center plane corresponding to a point following the scan diameter line n at x.

[0032] In some embodiments, the raw shape profile may be smoothed by a moving average. For example, defined windows may be set along individual scan diameter lines (302) for the raw shape profile. The windows may have a size of less than 10 mm, less than 5 mm, or 3 mm. The moving average of the raw shapes at points within the windows is calculated for each window. Then, the raw shapes at points within each window are set as the calculated moving average for the windows.

[0033] In step (408), an ideal shape profile is generated for the wafer (300) along each scan diameter line (302). Each ideal shape profile may be generated based on polynomial regression of the raw shape profile generated for each individual scan diameter line (302). In one example, each ideal shape profile is generated based on a second-order polynomial fitting of the raw shape values ​​calculated at points along each individual scan diameter line (302). Each ideal shape profile includes ideal shape values ​​calculated at each scanned point along each individual scan diameter line (302). In one example, the ideal shape (IS n ) is calculated at each point by the following formula:

[0034] IS n (x) = a*(RS n (x) 2 + b*(RS n (x)) + c

[0035] Here, n identifies the scan diameter line, x is the relative distance (in mm) of a point from the center (306) of the wafer (300) measured along the scan diameter line n, and RS n(x) is the raw feature value generated for the scan diameter line n at x, a and b are the polynomial coefficients, and c is the error determined by the polynomial fitting analysis. The polynomial fitting analysis is performed, for example, using Python's NumPy (i.e., the np.polyfit curve fitting function).

[0036] In step (410), a Gapi profile is generated for the wafer (300) along each scan diameter line (302). Each Gapi profile may be generated based on a raw shape profile and an ideal shape profile generated for each individual scan diameter line (302). In one example, each Gapi profile is generated by generating a delta shape profile for each individual scan diameter line (302). Each delta shape profile includes delta shape values ​​calculated at points along each individual scan diameter line (302). Each delta shape may be calculated by comparing the ideal shape and the raw shape at each point along each individual scan diameter line (302). In one example, the delta shape (DS n ) is calculated at each point by the following formula:

[0037] DS n (x) = IS n (x) - RS n (x)

[0038] Here, n identifies the scan diameter line, x is the relative distance (in mm) of a point from the center (306) of the wafer (300) measured along the scan diameter line n, and RS n (x) is the raw feature value generated for the scan diameter line n at x, and IS n(x) is an ideal shape value generated for a scan diameter line n at x. The delta shape profile can describe the wafer shape and flatness for each scan diameter line (302) by quantifying the deviations of each of the generated raw shape profiles from the individual ideal shape profiles. In some embodiments, each Gapi profile is generated based only on the delta shape profile generated for each scan diameter line (302).

[0039] Each Gapi profile may be based on a delta shape profile generated for each individual scan diameter line (302) and weighting factors applied to the delta shape profile. Weighting factors may be applied to account for specific variations in the delta shape profile (e.g., shape variations and slope variations) that may have a greater impact on wafer deformation (e.g., IPD distortion) during processing (e.g., multiplied by delta shape values). Delta shape profile variations may be quantified as standard variation, variance, or range based on delta shape values ​​within defined moving windows following the direction of each individual scan diameter line (302). A threshold for the amount of acceptable variation may be determined in advance before applying the weighting factors. For example, if the delta shape profile variation (e.g., shape variation or slope variation) determined based on the delta shape values ​​within the defined windows exceeds the predetermined threshold, a weighting factor may be applied to each delta shape value within the defined windows.

[0040] Weighting factors may be applied based on area variation within defined moving windows following the direction of individual scan diameter lines (302). High variation in area within a relatively narrow window (e.g., less than 20 mm) can cause wafer distortion because the wafer is susceptible to higher chucking pressure within that window. Area variation may be quantified, for example, as standard variation, variance, or range of the area of ​​a delta shape profile within the defined windows. The defined windows may have a size of, for example, less than 20 mm, less than 15 mm, or 11 mm. If the area variation of the delta shape profile within the window exceeds a predetermined threshold, a weighting factor is applied to the delta shape values ​​within the window. In one exemplary embodiment, the area variation is quantified as standard variation, and the threshold is greater than or equal to 0.3, greater than or equal to 0.4, or greater than or equal to 0.5. In these embodiments, the weighting factor may be the standard variation itself. Therefore, in one example, if the standard deviation is 0.4 or greater in the defined window, a weighting factor of 0.4 is applied, and if the standard deviation is less than 0.4 in the defined window, no weighting factor is applied (i.e., the weighting factor is zero).

[0041] Weighting factors may also be applied based on slope variations of the delta shape profile within defined moving windows following the direction of individual scan diameter lines (302). Significant turning points of the wafer surface profile within a relatively narrow window (e.g., less than 10 mm) can cause wafer distortion because the wafer is susceptible to higher chucking pressure within that window. Slope variations of the delta shape profile can be quantified, for example, by comparing the direction and amount of slope within two adjacent defined windows. Each adjacent defined window may have a size of, for example, less than 20 mm, less than 10 mm, or 5 mm. If the slope variation is outside a predetermined threshold, a weighting factor is applied to the delta shape values ​​within the defined windows. In one embodiment, the slopes are compared by multiplying the slopes, and the threshold is less than -0.3, less than -0.35, less than -0.4, less than -0.45, less than -0.5, or a negative value (representing a slope variation) less than -0.5. The weighting factors in these embodiments may be greater than 1 to 3, or 1.1 to 2, or 1.2 to 1.4, or 1.3. If the threshold is not satisfied, the weighting factor may be set to 1. Thus, in one example, if the slope change is determined to be less than -0.4, a weighting factor of 1.3 is applied, and if the slope change is determined not to be less than -0.4, a weighting factor of 1 is applied.

[0042] Both the area variation and the slope variation of delta shape profiles within defined windows can be used to determine the weighting factors applied to delta shape profiles when generating Gapi profiles. In these embodiments, the weighting factors to be applied (e.g., multiplied by delta shape values ​​within appropriate windows) can be determined by multiplying the weighting factors determined for the area variation and slope variation. For example, each weighting factor (SW) to be applied to the delta shape values ​​calculated for each scan diameter line (302) within the defined windows n ) can be calculated by the following formula:

[0043] SW n (x) = (SV n (x) + 1)*(SC n (x)

[0044] Here, n identifies the scan diameter line, x is the relative distance (in mm) of a point from the center (306) of the wafer (300) measured along the scan diameter line n, and SV n (x) is a weighting factor applied based on standard variation when the point at x is within the appropriate window, and SC n (x) is a weighting factor applied based on gradient changes when the point at x is within the appropriate window. In this example, SC n (x) is 1 (default when no weighting factor is applied) or greater than 1 (i.e., determined weighting factor).

[0045] Referring to FIGS. 7a and 7b, an exemplary set of plots generated using measurement data obtained by a geometric measurement tool according to the present disclosure (e.g., by scanning the surface (304) of a wafer (300) along scan lines as shown in FIGS. 3 through 5) is shown. Scan profiles were obtained by scanning the front-end processed wafer surface along eight diameter lines (indicated as lines 0 through 7 in FIGS. 7a and 7b). Raw shape profiles and ideal shape profiles were generated for each scan diameter line and are shown in each plot. Delta shape profiles (not shown) for each diameter line were also generated based on the raw shape and ideal shape profiles as described above. In this example, weighting factors were determined based on shape deviations and / or slope changes in the delta shape profiles within defined windows. Gapi profiles (shape delta * shape weight) for each diameter line were generated by applying weighting factors to delta shape values ​​within appropriate windows.

[0046] Referring again to FIG. 8, in step (412), a Gapi value for the wafer is calculated based on Gapi profiles generated for the scan diameter lines (302). The Gapi value is a global metric that can be used to describe the overall variation in wafer flatness and / or shape relative to an ideal plane. It can be calculated based on the Gapi profiles, for example, as the root mean square value of the values ​​included in the Gapi profiles. Thus, the Gapi value may also be referred to herein as "Gapi root mean square" or "Gapi rms".

[0047] Referring to FIGS. 9 through 12, the Gapi value calculated for a front-end processed wafer is a patterned wafer geometry (PWG) metrology system (e.g., WaferSight manufactured by KLA-Tencor Corporation). TM PWG5 TM It was shown that it has a good correlation with the IPD prediction index provided by the platform. The PWG metrology system evaluates wafer distortion during the process and predicts overlay errors based on wafer shape variations using high-accuracy inspection tools (e.g., WaferSight manufactured by KLA-Tencor Corporation). TM Raw PWG data obtained from a 2 or 2+ bare wafer metrology system is used. Fig. 9 illustrates a contour map of the raw local feature of the front-end processed wafer. As shown in Figs. 10 and 11, the contour maps of the Gapi profiles generated for the front-end processed wafer (Fig. 10) and the IPD map generated using the PWG metrology system based on wafer data during processing (Fig. 11) indicate that the IPD can be predicted based on the Gapi profiles generated for the front-end processed wafer. More specifically, the generated Gapi profile features of the wafer in Fig. 10 (having a Gapi value of 4.324) correlate well with the IPD map of Fig. 11 and the calculated IPD site root mean square (root mean square) metrics of the same wafer (having the local feature of Fig. 9), where the IPD metrics and the IPD map are determined after the final polishing step. Figure 12 shows that the calculated global metrics of the IPD values ​​and Gapi profiles (both taken as the root mean square of the local values) have a strong correlation, and R 2 It illustrates that the value is greater than 0.7 for various wafer shapes.

[0048] Referring to FIG. 13, the Gapi value of a front-end processed wafer can be used to predict the back-end yield of high-quality wafers. The graph in FIG. 13 illustrates that a high back-end yield of over 50% can be obtained for Gapi values ​​of 4 or less, specifically 3.6 or less, and more specifically 3.2 or less. Back-end yield percentages can be obtained from empirical data from wafer grading or from wafer metrics based on wafer distortion during the process (e.g., yield based on the IPD metric of the wafer after polishing). Since the Gapi metrics according to the present disclosure have a strong correlation with wafer metrics during the process, it can be assumed that the predicted back-end yields correlated with wafer metrics during the process will correlate similarly with the individual Gapi metrics. If the calculated Gapi value of the wafer does not satisfy a predetermined threshold, the front-end processed wafers may be sorted (as in step (206) in the process (200)). The threshold can be set to a Gapi value corresponding to a high back-end yield percentage (e.g., over 50%, over 60%, or over 70%). In this regard, benefits such as higher back-end yield, reduced need for overlay error control, and relief of poorer quality wafers can be achieved.

[0049] Referring to FIG. 14, an exemplary process flow (500) for adjusting a front-end process tool based on a calculated Gapi value is illustrated. In step (502), a wafer is processed by a front-end process tool (e.g., the front-end process tool (702) illustrated in FIG. 27). For example, the wafer may be sliced ​​from a single-crystal ingot of a semiconductor material (e.g., silicon) using a wire saw. The wafer may also be made to a desired thickness using a front-end process tool such as a lapping tool or a grinding tool.

[0050] In step (504), the Gapi value of the front-end processed (e.g., wire sawing, wrapping, and / or grinding) wafer is calculated according to the present disclosure (e.g., by the process (400) illustrated in FIG. 8). In step (506), the Gapi value is compared to a predetermined threshold. The predetermined threshold may be based on historical data correlating the Gapi value with a back-end yield percentage. For example, the threshold may be set to a Gapi value that correlates with a back-end yield percentage greater than 50%. In one exemplary embodiment, the threshold is set based on data illustrated in the graph of FIG. 13. In some examples, the predetermined threshold for the Gapi value is less than 6, less than 5.5, less than 5, less than 4.5, e.g., less than 4 or less than 3.5. If the Gapi value is within a predetermined threshold (e.g., below the threshold Gapi value, such as 5 or less), in step (508), the front-end processed wafer is sorted for polishing.

[0051] If the Gapi value is not within a predetermined threshold (e.g., exceeding the threshold Gapi value), the wafer may not be sorted for polishing. In step (510), one or more of the front-end process tools may be tuned after determining that the Gapi value of the front-end processed wafer is not within a predetermined threshold (e.g., may be adjusted and / or modified). One or more of the front-end process tools may be tuned based on at least one of the Gapi profiles of the wafer having a Gapi value outside the predetermined threshold.

[0052] Extending step (510) of process (500), FIGS. 15 through 22 are additionally referenced. FIGS. 15 through 18 illustrate a contour map (Fig. 15) of raw local shape features of a front-end processed wafer having a Gapi value of 5.41 that is not within (e.g., exceeding) a predetermined threshold for step (506) of process flow (500) in this exemplary embodiment, a chart of plots of the raw shape profile, ideal shape profile, and Gapi profile for a single scan diameter line (Fig. 16), a contour map of the Gapi profiles (Fig. 17), and an IPD contour map (Fig. 18). Accordingly, in step (508), the front-end processed wafer of FIGS. 15 through 18 is not sorted for polishing.

[0053] In step (510), one or more front-end process tools may be tuned based on at least one of the Gapi profiles used to calculate the Gapi value shown in FIG. 17, such as the Gapi profile shown in FIG. 16 (e.g., modified and / or adjusted). In this exemplary embodiment, the wire saw may be tuned based on at least one Gapi profile of the wafer. The Gapi profile plot of FIG. 16 shows the Gapi profile of the diameter line of the wafer (i.e., line: 5) parallel (or substantially parallel) to the cutting direction of the wire saw. As shown in FIG. 16, it is observed that relatively high Gapi values ​​of the Gapi profile are located at certain points along the diameter line in the direction of the scan diameter line at distances near the radial edges of the wafer. Based on this observation, the wire saw may be tuned to correct the high fluctuations at these points. For example, the values ​​of the bearing temperature or slurry temperature at points corresponding to these high variation points near the radial edge of the wafer can be adjusted to provide a smoother wafer shape when the wire enters and exits as the wafer is cut from the single-crystal ingot.

[0054] Next, in step (512), a tuned front-end process tool is used to provide a second front-end processed wafer. FIGS. 19 through 22 illustrate a contour map of the raw local shape features of the second front-end processed wafer after the front-end process tool has been tuned based on observations from FIGS. 15 through 18 (Fig. 19), a chart of plots of the raw shape profile, ideal shape profile, and Gapi profile for a single scan diameter line (Fig. 20), a contour map of the Gapi profiles (Fig. 21), and an IPD contour map (Fig. 22). As illustrated in FIGS. 19 through 22, tuning of the front-end process tool produces a second front-end processed wafer having improved Gapi profiles (having less variation at radial edges) as well as a lower Gapi value (3.42) and an IPD root mean square value (16.45). The second front-end processed wafer provided after the tuning step may be the same wafer processed in the rescued step (502) by repeating the front-end process step. The second front-end processed wafer processed by the tuned front-end tool may also be a different wafer.

[0055] One advantage of the process (500) is that adjustments and / or modifications to the front-end tools can be made more quickly and efficiently using metrics generated and / or calculated early in the wafer process (e.g., before polishing). Conventional metrics used to predict wafer deformation during fabrication require the wafer to be polished to obtain high-quality shape and / or flatness data of the wafer. Consequently, process anomalies in the front-end tools (e.g., wire saw, lapping tool, or grinding tool) cannot be identified until the front-end processed wafer is polished. Typically, a significant amount of time (hours, days, weeks) elapses between the front-end processing and polishing of a given wafer. During this time, a large volume of wafers may be processed by the front-end tool(s), and consequently, there is a risk of unacceptable Gapi values ​​and surface variations that will not be identified until the initial wafer is polished and scanned. In this regard, the process (500) provides a significant improvement by affecting fewer wafers by providing early detection of process anomalies within the front-end process that can be corrected by tuning the front-end tool(s).

[0056] Referring to FIGS. 23 through 26, a method for determining Gapi edge metrics for a front-end processed wafer is described. In addition to the Gapi metrics used according to the present disclosure, Gapi edge metrics may be used to characterize wafer edge profiles. Wafer edge conditions are known to significantly affect edge die yield. For example, problems associated with film layer delamination (i.e., delamination), particle contamination, and photoresist coating offset errors (each of which has a negative impact on edge die yield) are known to arise from wafer edge defects. Using Gapi edge metrics according to the present disclosure ensures that wafers with sufficiently smooth edges are fabricated, and thus can provide similar improvements in back-end yield as discussed above with respect to Gapi metrics.

[0057] In FIG. 23, a process (600) for calculating Gapi edge values ​​of a front-end processed wafer is illustrated. In step (602), measurement data of the edge profile of the front-end processed wafer is obtained. For example, the edge profile data may be obtained using commercial 3D microscopes, such as a coherent scan interferometer, a confocal laser scan, or a laser scan microscope (such as those manufactured by Zygo, Olympus, or Keyence). The wafer being measured may be in an un-chucked (i.e., freestanding) state.

[0058] In step (604), a simplification algorithm is used to convert edge profile data into a simplified curve by reducing the set of points included in the edge profile. For example, the simplified curve of the edge profile data may be generated based on the Ramer-Douglas-Peucker algorithm (i.e., an iterative endpoint fitting algorithm). In this example, as understood by a person skilled in the art, the number of points including the edge profile may be set by tuning the epsilon (ε) parameter used in the Ramer-Douglas-Peucker algorithm. In one embodiment, ε is tuned to reduce the number of curve points to three. The profile center point is determined as the middle point on the simplified curve. For example, in one embodiment, the profile center point is determined as the middle of the three points on the simplified curve.

[0059] In step (606), a center raw height profile is generated based on the edge profile data obtained in step (602) and the profile center point determined in step (604). Raw height points are extracted from the edge profile based on the profile center point. For example, raw height points located at a number of points (N) + / - from the edge profile center point are extracted. N is adjusted to block forward or backward points. For example, N may be more than 200 points and less than 400 points, more than 300 points and less than 375 points, or 350 points. Since the number of raw points extracted from each side of the profile center point is the same value (N), the edge profile center point will be a turning point of the curve (as illustrated in FIGS. 24 to 26).

[0060] In step (608), an ideal edge profile is generated based on the center raw height profile. The ideal edge profile may be generated based on polynomial regression of the center raw height profile. In one example, the ideal edge profile includes ideal edge values ​​calculated based on a third-order polynomial fitting of the raw height values ​​of the points included in the center raw height profile. Each ideal edge value may be expressed by the following exemplary formula:

[0061] IE(x) = a*(RH(x)) 3 + b*(RH(x)) 2 + c*(RH(x)) + d

[0062] Here, x is the relative distance along the center edge profile direction from the reference point x = 0, RH(x) is the raw height value of the center raw height edge profile at x, a, b, and c are polynomial coefficients, and d is the error determined by polynomial fitting analysis. Polynomial fitting analysis is performed, for example, using Python's NumPy (i.e., the np.polyfit curve fitting function).

[0063] In step (610), a Gapi edge profile is generated for the wafer. The Gapi edge profile can be generated based on an ideal edge profile and a center raw height profile. In one exemplary embodiment, the Gapi profile is generated by generating a delta edge profile. The delta edge profile includes delta edge values ​​that can be calculated by comparing the ideal edge value and the raw height value at each point along the center raw height profile. For example, the delta edge profile can be expressed by the following formula:

[0064] DE(x) = IE(x) - RH(x)

[0065] Here, x is the relative distance along the center edge profile direction from the reference point x = 0, RH(x) is the raw height value of the center raw height edge profile at x, and IE(x) is the ideal edge value of the ideal edge profile at x. The delta edge profile can describe the wafer edge conditions of the wafer by quantifying the deviations of the center raw height profile from the ideal edge profile. In some embodiments, the Gapi edge profile is generated based solely on the delta edge profile.

[0066] The Gapi edge profile may be based on the generated delta edge profile and weighting factors applied to the delta edge profile. Weighting factors may be applied to account for specific delta edge profile variations (e.g., shape variations and slope variations) of the delta edge profile that may have a greater impact on wafer deformation (e.g., IPD distortion) during processing (e.g., multiplied by delta edge values). Delta edge profile variations may be quantified as standard variation, variance, or range based on the delta edge profile within defined movement windows following the center edge profile direction. A threshold may be predetermined for the amount of acceptable slope variation or variation of the delta edge profile before applying the weighting factors. For example, if the variation determined based on the delta edge values ​​within the defined window exceeds the predetermined threshold, a weighting factor may be applied to each delta edge value within the defined window.

[0067] Weighting factors may be applied based on area variation within defined windows following the center edge profile direction. High variation in the area of ​​the edge profile within a relatively narrow window (e.g., fewer than 20 points) can lead to wafer distortion because the wafer is susceptible to higher chucking pressure within that window. Area variation may be quantified, for example, as standard variation, variance, or range of the area of ​​the delta edge profile within the defined windows. The defined windows may have a size of, for example, fewer than 20 points, fewer than 15 points, or 11 points. If the area variation of the delta edge profile within the window exceeds a predetermined threshold, weighting factors are applied to the delta edge values ​​within the window. In one exemplary embodiment, area variation is quantified as standard variation, and the threshold is greater than 800 nm, greater than 900 nm, greater than 1000 nm, greater than 1100 nm, or greater than 1200 nm. The weighting factor in these embodiments can be calculated by dividing the standard variation itself by a threshold value. Thus, in one example, if the standard variation (SV) is 1000 nm or greater in a defined window, a weighting factor of (SV / 1000) is applied, and if the standard deviation is less than 1000 nm in a defined window, no weighting factor is applied (i.e., the weighting factor is zero).

[0068] Weighting factors can also be applied based on slope variations of delta edge profile defined windows following the center edge profile direction. Significant turning points in the wafer edge profile following a narrow window size (e.g., fewer than 70 points) can cause wafer distortion because the wafer is susceptible to higher chucking pressure within that window. Slope variations of the delta edge profile can be quantified, for example, by comparing the direction and amount of slope within two adjacent defined windows. Each adjacent defined window can have a size of, for example, fewer than 50 points, fewer than 40 points, or 33 points. If the slope variation is outside a predetermined threshold, weighting factors are applied to the delta edge values ​​within the defined windows. In one exemplary embodiment, slopes are compared by multiplying the slopes, and the threshold is a negative value (representing a slope change) less than -0.3, less than -0.35, less than -0.4, less than -0.45, less than -0.5, or less than -0.55. The weighting factors in these embodiments may be 3 to 9, or 4 to 8, or 6. If the threshold is not satisfied, the weighting factor may be set to 1. Thus, in one example, a weighting factor of 6 is applied when it is determined that the slope change is less than -0.45, and a weighting factor of 1 is applied when it is determined that the slope change is not less than -0.45.

[0069] Both the area variations and slope variations of delta edge profiles within defined windows can be used to determine the weighting factors applied to the delta edge profiles when generating Gapi edge profiles. In these embodiments, the weighting factors to be applied (e.g., multiplied by the delta edge values ​​within appropriate windows) can be determined by multiplying the weighting factors determined for the area variations and slope variations. For example, each weighting factor (SW) to be applied to the delta edge values ​​within defined windows E ) can be calculated by the following formula:

[0070] SW E (x) = (SV E (x) / 1000 + 1)*(SC E (x)

[0071] Here, x is the relative distance along the center edge profile direction from the reference point x = 0, and SV E (x) is a weighting factor applied based on the standard variation of the delta edge profile when the point at x is within the appropriate window, and SC E (x) is a weighting factor applied based on the gradient changes of the delta edge profile when the point at x is within the appropriate window. In this example, SC E (x) is 1 (default when no weighting factor is applied) or greater than 1 (i.e., determined weighting factor).

[0072] Referring to FIGS. 24 through 26, an exemplary set of plots generated according to process (600) is illustrated. In particular, Gapi edge plots for wafer edges having the worst edge profile, wafer edges having the poor edge profile, and wafer edges having the ideal edge profile are illustrated. Measurement data of the edge profiles of each wafer edge were acquired using commercial 3D microscopes (such as those described above in step (602)). The ideal edge profile and center raw height profile generated for each wafer edge are illustrated in their respective plots. Delta edge profiles (not illustrated) for each wafer edge were also generated based on the center raw height profile and the ideal edge profile. As discussed above, in this example, weighting factors were determined based on shape deviations and / or slope changes in the delta edge profiles of each wafer edge within defined windows. The Gapi edge profile (edge ​​delta * edge weight) for each wafer edge was generated by applying weighting factors to delta edge values ​​within appropriate windows.

[0073] Referring again to FIG. 23, in step (412), a Gapi edge value for the wafer is calculated based on the Gapi edge profile of the wafer edge. The Gapi edge value is a global metric that can be used to describe the overall variations of the wafer edge profile with respect to an ideal plane. In one exemplary embodiment, the Gapi edge value is calculated based on the Gapi edge profile as, for example, the root mean square value of the values ​​including the Gapi edge profile (also referred to as "Gapi edge root mean square" or "Gapi edge rms"). In another exemplary embodiment, the Gapi edge value is calculated as the maximum edge value of the Gapi edge profile (also referred to as "Gapi edge maximum value" or "Gapi edge maximum").

[0074] As illustrated in FIGS. 24 through 26, Gapi edge values ​​calculated as the root mean square and / or maximum values ​​of the Gapi edge profile can describe the wafer edge profile. For example, a good edge profile can be characterized by having Gapi edge values ​​within a predetermined threshold (e.g., Gapi edge maximum of less than 90 and / or Gapi edge rms of less than 10). The predetermined threshold can be determined, for example, by the correlation between the Gapi edge values ​​and the back-end yield percentage, as discussed above for the Gapi values. In some examples, the predetermined threshold for the Gapi edge values ​​calculated as the root mean square of the Gapi edge profile may be less than 10, less than 9, less than 8, less than 7, less than 6, less than 5, less than 4, or less than 3. In some examples, a predetermined threshold for the Gapi edge value calculated as the maximum value of the Gapi edge profile may be less than 90, less than 80, less than 70, less than 60, less than 50, less than 40, less than 30, less than 20, or less than 10.

[0075] Referring again to FIG. 14, a process flow (500) for adjusting a front-end process tool may include adjusting the front-end process tool using a calculated Gapi edge value as described herein. In step (502), as described above, a first wafer is processed by a front-end process tool (e.g., a front-end process tool (702) shown in FIG. 27). In step (504), a Gapi edge value of the first front-end processed wafer is calculated according to the present disclosure (e.g., by the process (600) shown in FIG. 23). In step (506), the Gapi edge value is compared with a predetermined threshold value. If the Gapi edge value is within a predetermined threshold (e.g., below the Gapi edge maximum value, e.g., 90 or less, or below the threshold Gapi edge rms value, e.g., 10 or less), in step (508), the first front-end processed wafer is sorted for polishing. If the Gapi edge value is not within the predetermined threshold (e.g., above the threshold Gapi edge maximum value or Gapi edge rms value), the first wafer may not be sorted for polishing. In step (510), one or more of the front-end process tools may be tuned (e.g., adjusted and / or modified) after it is determined that the Gapi edge value of the first front-end processed wafer is not within the predetermined threshold. One or more front-end process tools may be tuned based on the Gapi edge profile of the wafer having a Gapi edge value outside the predetermined threshold. Next, in step (512), the tuned front-end process tool is used to provide a second front-end processed wafer, which may be the same as or different from the first front-end processed wafer.

[0076] Referring to FIG. 27, a block diagram of a system (700) for processing a wafer using a front-end processed wafer geometry metric according to the present disclosure is shown. The system (700) includes a front-end processing tool (702), a flatness inspection tool (704), and a computing device (706) connected to or communicably coupled to the front-end processing tool (702) and / or the flatness inspection tool (704).

[0077] The front-end process tool (702) may be any machining tool configured to provide a front-end processed wafer according to the present disclosure. In an exemplary embodiment, the front-end process tool (702) is a wire saw. In other embodiments, the front-end process tool (702) may be a grinding tool, a lapping tool, a beveling tool, or an etching tool.

[0078] The flatness inspection tool (704) is a wafer geometry measurement tool configured to acquire measurement data from a front-end processed wafer. For example, the flatness inspection tool (704) may acquire measurement data by scanning the surface of the front-end processed wafer using a capacitance probe or an interferometer (e.g., by the scan diameter lines shown in FIGS. 3 and 4 or the spiral scan shown in FIGS. 5 on the wafer (300)). The measurement data acquired by scanning one or both surfaces of the wafer includes surface profile data and thickness profile data of the wafer. In one example, the flatness inspection tool (704) is a Kobelco SBW-330 tool. The flatness inspection tool (704) may have the same function as the geometry measurement tool discussed in detail above in relation to FIGS. 3 through 5. In another example, the flatness inspection tool (704) acquires measurement data of the edge profile of the wafer. In this example, the flatness inspection tool (704) may be a commercial 3D microscope suitable for acquiring edge profile data of a wafer, such as a coherent scan interferometer, a confocal laser scan or a laser scan microscope.

[0079] The computing device (706) includes a processor (708) for executing instructions. In some embodiments, executable instructions are stored in a memory region (710). The processor (708) may include one or more processing units (e.g., in a multi-core configuration). The memory region (710) may be any device that allows information, such as executable instructions and / or data, to be stored and retrieved. The memory region (710) may include one or more computer-readable storage devices or other computer-readable media, including transient and non-transient computer-readable media.

[0080] The computing device (706) also includes at least one media output component (712) for presenting information to a user (e.g., wafer end user, quality control personnel, etc.). The media output component (712) is any component capable of delivering information to the user. In some embodiments, the media output component (712) includes an output adapter, such as a video adapter and / or an audio adapter. The output adapter is operablely connected to the processor (708) and operablely connected to an output device, such as a display device (e.g., a liquid crystal display (LCD), an organic light-emitting diode (OLED) display, a cathode ray tube (CRT), or "electronic ink" display) or an audio output device (e.g., a speaker or headphones). In some embodiments, at least one such display device and / or audio device is included in the media output component (712).

[0081] In some embodiments, the computing device (706) includes an input device (714) for receiving input from a user. For example, the input device (714) may include a keyboard, a pointing device, a mouse, a stylus, a touch-sensitive panel (e.g., a touchpad or a touchscreen), a gyroscope, an accelerometer, a position detector, or an audio input device. A single component, such as a touchscreen, may function as both the output device of the media output component (712) and the input device (714).

[0082] The computing device (706) may also include a communication interface (716) that can be communicateably connected to one or more remote devices. For example, the communication interface (716) may include a wired or wireless network adapter or a wireless data transceiver for use with a mobile phone network (e.g., GSM (Global System for Mobile communications), 3G, 4G, or Bluetooth) or another mobile data network (e.g., WIMAX (Worldwide Interoperability for Microwave Access)).

[0083] For example, processor executable instructions for receiving and processing input from a flatness inspection tool (704) and modifying a front-end process tool (702) based on the processed input received from the flatness inspection tool (704) are stored in a memory area (710). For example, the memory area (710) may store instructions that cause the processor (708) to perform the process (400) shown in FIG. 8, the process (500) shown in FIG. 14, and / or the process (600) shown in FIG. 23 (each of which is described in detail above).

[0084] The memory region (710) may include, but is not limited to, any computer operating hardware suitable for storing and / or retrieving processor executable instructions and / or data. The memory region (710) may include random access memory (RAM), such as dynamic RAM (DRAM) or static RAM (SRAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), and non-volatile RAM (NVRAM). Additionally, the memory region (710) may include multiple storage units, such as hard disks or solid-state disks in a redundant array of inexpensive disks (RAID) configuration. The memory region (710) may include a storage area network (SAN) and / or network attached storage (NAS) system. In some embodiments, the memory region (710) includes memory integrated into the computing device (706). For example, the computing device (706) may include one or more hard disk drives as memory regions (710). The memory regions (710) may also include memory located outside the computing device (706) and may be accessed by multiple computing devices. The above memory types are merely exemplary and, accordingly, are not a limitation on the types of memory available for storing processor executable instructions and / or data.

[0085] When introducing elements of the invention or its embodiments, the articles (“a,” “an,” “the,” and “said”) are intended to indicate that there is one or more elements. The terms “comprising,” “including,” and “having” are intended to be inclusive and to indicate that there may be additional elements other than those listed.

[0086] Since various modifications to the above configurations and methods may be made without departing from the scope of the invention, all matters included in the above description and illustrated in the accompanying drawings are intended to be interpreted as exemplary rather than restrictive.

Claims

Claim 1 A method for processing semiconductor wafers, comprising: providing a first semiconductor wafer processed by a front-end process tool; acquiring measurement data of an edge profile of the first semiconductor wafer; determining an edge profile center point based on the measurement data; generating a raw height profile based on the measurement data and the edge profile center point; generating an ideal edge profile based on polynomial regression of the raw height profile; generating a Gapi edge profile of the first semiconductor wafer, wherein the Gapi edge profile of the first semiconductor wafer comprises: generating a delta edge profile by comparing the raw height profile and the ideal edge profile; and generating a weighted profile based on variations in the delta edge profile following the direction of the edge profile. A method comprising: generating a Gapi edge profile based on the delta edge profile and the weighted profile; calculating a Gapi edge value of a first semiconductor wafer based on the Gapi edge profile; determining whether the Gapi edge value of the first semiconductor wafer is within a predetermined threshold; tuning a front-end process tool based on the Gapi edge profile of the first semiconductor wafer if the Gapi edge value of the first semiconductor wafer is not within the predetermined threshold if the front-end process tool is not within the predetermined threshold if the front-end process tool is not within the predetermined threshold if the front-end process tool is not within the Gapi edge profile of the first semiconductor wafer, and processing a second semiconductor wafer with the tuned front-end process tool; and sorting the first semiconductor wafer for polishing if the Gapi edge value of the first semiconductor wafer is within the predetermined threshold. Claim 2 The method according to claim 1, wherein the step of determining the edge profile center point includes the step of applying a simplification algorithm to convert the edge profile measurement data into a simplified curve including three points, and the edge profile center point is the middle point among the three points. Claim 3 In paragraph 2, the method wherein the simplification algorithm is an iterative end-point fit algorithm. Claim 4 A method according to claim 1, wherein the step of generating the raw height profile includes the step of extracting an equal number of raw height points on both sides of the edge profile center point. Claim 5 In claim 1, the step of generating the ideal edge profile is based on a third-order polynomial fitting of the raw height profile. Claim 6 delete Claim 7 A method according to claim 1, wherein the weighted profile is generated based on at least one of the shape variation and the slope variation of the delta edge profile, and each of the shape variation and the slope variation is determined within defined moving windows following the direction of the edge profile. Claim 8 A method according to claim 1, wherein the front-end process tool is selected from a group consisting of a wire saw, a lapping tool, and a grinding tool. Claim 9 A method according to claim 1, wherein the Gapi edge value of the first semiconductor wafer is calculated based on the root mean square value of the Gapi edge profile. Claim 10 A method according to claim 9, wherein the predetermined threshold for the Gapi edge value is 10 or less. Claim 11 A method according to claim 1, wherein the Gapi edge value of the first semiconductor wafer is calculated based on the maximum value of the Gapi edge profile. Claim 12 A method according to claim 11, wherein the predetermined threshold for the above Gapi edge value is 90 or less. Claim 13 A method according to claim 1, wherein the second semiconductor wafer is the same wafer as the first semiconductor wafer. Claim 14 A system for processing semiconductor wafers, comprising: a front-end process tool for front-end processing of a semiconductor wafer; a flatness inspection tool for acquiring measurement data of an edge profile of a front-end processed wafer; and a computing device connected to the flatness inspection tool and the front-end process tool, wherein the computing device receives the measurement data from the flatness inspection tool, determines an edge profile center point based on the measurement data, generates a raw height profile based on the measurement data and the edge profile center point, generates an ideal edge profile based on polynomial regression of the raw height profile, and generates a Gapi edge profile of the front-end processed wafer, wherein the Gapi edge profile of the front-end processed wafer comprises: generating a delta edge profile by comparing the raw height profile and the ideal edge profile; A system configured to generate a weighted profile based on at least one of a shape variation and a slope variation of a delta edge profile following the direction of the edge profile, wherein each of the shape variation and the slope variation is determined within defined moving windows following the direction of the edge profile; and to generate a Gapi edge profile based on the delta edge profile and the weighted profile, calculate a Gapi edge value of the front-end processed wafer based on the Gapi edge profile, determine whether the Gapi edge value of the front-end processed wafer is within a predetermined threshold, and if the Gapi edge value of the front-end processed wafer is not within the predetermined threshold, modify the front-end process tool based on the Gapi edge profile of the front-end processed wafer. Claim 15 In claim 14, the computing device is configured to determine the edge profile center point by applying an iterative endpoint fitting algorithm to convert the edge profile measurement data into a simplified curve including three points, and the edge profile center point is the middle point among the three points, a system. Claim 16 In claim 14, the system is configured such that the computing device generates the raw height profile by extracting an equal number of raw height points on both sides of the edge profile center point. Claim 17 In claim 14, the system is configured such that the computing device generates the ideal edge profile based on a third-order polynomial fitting of the raw height profile. Claim 18 delete Claim 19 In claim 14, the computing device is further configured to calculate the Gapi edge value of the front-end processed wafer based on the root mean square value of the Gapi edge profile, and the predetermined threshold for the Gapi edge value is 10 or less, a system. Claim 20 In claim 14, the computing device is further configured to calculate the Gapi edge value of the front-end processed wafer based on the maximum value of the Gapi edge profile, and the predetermined threshold for the Gapi edge value is 90 or less, a system.

Images