Single-Inductor n-channel-Output DC-DC Converter with Compensator-sharing Technique, compensation circuit and ramp generator

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The compensation circuit sharing technique in SIMO DC-DC buck converters enhances efficiency and reduces chip area, addressing the limitations of multiple compensators and transient response, making it suitable for wearable devices with diverse power requirements.

KR103000569B1Active Publication Date: 2026-08-05UNIV OF SEOUL IND COOP FOUND

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Patent Information

Application Number: KR1020240057762
Authority / Receiving Office: KR · KR
Patent Type: Patents
Current Assignee / Owner
Filing Date: 2024-04-30
Publication Date: 2026-08-05
Estimated Expiration: 2044-04-30

Application Information

Patent Timeline

30 Apr 2024

Application

KR1020240057762

05 Aug 2026

Publication

KR103000569B1

IPC: H02M1/00; H02M3/155

CPC: H02M1/0045; H02M1/0029; H02M1/009; H02M3/155

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Application Domain

Dc-dc conversion Electric variable regulation

Technology Topics

Converters Hemt circuits

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AI Technical Summary

Technical Problem

Existing SIMO DC-DC buck converters face challenges with large area requirements due to multiple compensators and slow transient response, which are not suitable for wearable devices that require miniaturization and high performance.

Method used

A compensation circuit sharing technique is introduced, where multiple output converters share a single error amplifier and compensation circuit, utilizing a ramp generation circuit to store and manage error amplifier output information efficiently, reducing the need for multiple PI compensation circuits.

Benefits of technology

This approach achieves high efficiency and reduces the chip area, maintaining high performance while addressing the transient response issues, suitable for wearable devices with varying power supply needs.

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Abstract

One embodiment of the present invention relates to a ramp signal generator for a single inductor DC-DC converter in which n output converters share an error amplifier and a compensation circuit, wherein the generator includes a first capacitor (CGM01) connected to a current source through a switch controlled by an ON1 signal, which stores error amplifier output information (VCGM01) of converter 1 among the n converters, and a second capacitor (CGM02) connected to the current source through a switch controlled by an ON2 signal, which stores error amplifier output information (VCGM02) of converter 2 among the n converters, and wherein the error amplifier output information (VCGM01) of converter 1 and the error amplifier output information (VCGM02) of converter 2 are optionally provided as inputs to the error amplifier.

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