Single-Inductor n-channel-Output DC-DC Converter with Compensator-sharing Technique, compensation circuit and ramp generator

Abstract

One embodiment of the present invention relates to a ramp signal generator for a single inductor DC-DC converter in which n output converters share an error amplifier and a compensation circuit, wherein the generator includes a first capacitor (CGM01) connected to a current source through a switch controlled by an ON1 signal, which stores error amplifier output information (VCGM01) of converter 1 among the n converters, and a second capacitor (CGM02) connected to the current source through a switch controlled by an ON2 signal, which stores error amplifier output information (VCGM02) of converter 2 among the n converters, and wherein the error amplifier output information (VCGM01) of converter 1 and the error amplifier output information (VCGM02) of converter 2 are optionally provided as inputs to the error amplifier.

Description

Technology Field

[0001] The present invention relates to a single inductor 2-channel output DC-DC converter applying a compensation circuit sharing technique, a compensation circuit used therein, and a ramp generation circuit. Background Technology

[0003] The power management IC (PMIC) market, which is centered around smartphones, is continuously growing in scale alongside the development of wearable devices and the expansion of the market size. PMICs for wearable devices must be capable of handling various input voltages depending on the input power source, and the output of the PMIC must drive loads with various output voltage values, such as sensors, BLE communication, small MCUs, and LEDs.

[0004] In addition, to achieve a small footprint, PMICs require the development of technologies such as small-area ICs and packages, and technologies to minimize the use of external components. Wearable devices are becoming increasingly thinner, lighter, and faster. To keep up with these trends, internal ICs must also simultaneously meet the requirements for miniaturization and high performance.

[0005] The SIMO (Single-Inductor Multiple-Output) DC-DC converter proposed in response to these requirements is described as follows.

[0006] Due to their characteristics, wearable devices require various power supply voltages depending on the configuration blocks. As shown in Fig. 1, various power supply voltages can be provided by using multiple DC-DC buck converters. However, the method of using multiple DC-DC buck converters has the disadvantages of being expensive and having a large area because it requires using inductors for each required power supply voltage, and it is not suitable for the characteristics of wearable devices that are becoming lighter and thinner.

[0007] Another method for generating various power supply voltages is to use a single DC-DC buck converter and multiple linear regulators, as shown in Fig. 2. Multiple linear regulators receive the output of a single DC-DC buck converter as input and output it. Since a single inductor is used, it has the advantages of being inexpensive and having a small footprint, but it has the disadvantages of reduced efficiency due to the drop output voltage of the linear regulators and performance degradation due to heat dissipation, which does not meet the characteristics of wearable devices that require high performance.

[0008] A SIMO DC-DC converter, which is a structure designed to improve these disadvantages, is shown in Fig. 3. The SIMO DC-DC buck converter generates multiple output voltages by sharing a single inductor with multiple output channels. Since the SIMO DC-DC converter uses only one inductor, it is more advantageous than Fig. 1 in terms of cost and area. In addition, unlike Fig. 2, it does not use a linear regulator, so it can generate multiple output voltages while maintaining high efficiency.

[0009] The basic structure of the SIMO DC-DC buck converter is described below.

[0010] The basic structure of a time-division SIMO DC-DC buck converter having N output channels is shown in Fig. 4. The time-division SIMO DC-DC buck converter has a structure similar to a DC-DC buck converter, but shares a single inductor with multiple output channels, has a switch added at the output terminal, and provides the required voltage to multiple channels in a time-division manner based on clocks having N different phases.

[0011] Figure 5 is a timing diagram illustrating the operation of a time-division SIMO DC-DC buck converter. Converter 1 is controlled when Ψ1=H, and the inductor current is at on-time. , during off-time It has a slope. When Ψ1=L and Ψ2=H, it controls converter 2. The inductor current during on-time , during off-time It has a slope of . Ψ in chronological order N When this H is reached, it controls the converter N and repeats on-time and off-time operations for each converter to generate an output voltage.

[0012] Figure 6 shows a block diagram of a time-division SIMO DC-DC buck converter. The time-division SIMO DC-DC buck converter has the disadvantage of slow transient response and large output ripple because the inductor supplies energy to only one output during a single switching cycle. Additionally, it requires N compensators for N outputs, resulting in a large area. The problem to be solved

[0014] This invention was conceived against this technical background and proposes a compensation circuit sharing technique using a single compensation circuit to overcome the limitation of having a large area due to time-division control. The proposed compensation circuit sharing technique prevents the output delay of the error amplifier caused by using a single compensation circuit. means of solving the problem

[0016] To solve the above technical problem, one embodiment of the present invention relates to a ramp signal generator of a single inductor DC-DC converter in which n output converters share an error amplifier and a compensation circuit, wherein the error amplifier output information (V) of converter 1 among the n converters CGM01 A first capacitor (C) that stores ) and is connected to a current source through a switch controlled by the ON1 signal. GM01 ) and the error amplifier output information (V) of converter 2 among the n converters above CGM02 A second capacitor (C) that stores ) and is connected to the current source through a switch controlled by the ON2 signal. GM02Includes ), and error amplifier output information (V) of the converter 1. CGM01 ) and the error amplifier output information (V) of the converter 2 CGM02 ) is optionally given as the input to the error amplifier.

[0017] When the first switch is turned on, the current source is connected to the first capacitor to generate a ramp signal, and at the point where the generated ramp signal becomes greater than the output of the error amplifier, the first switch is turned off so that the error amplifier output information of the channel 1 ( VCGMO1 ) the first capacitor (C GMO1 Save to ).

[0018] When the second switch is turned on, the current source is the second capacitor (C GMO2 It is connected to ) to generate a ramp signal, and at the point where the generated ramp signal becomes larger than the output of the error amplifier, the second switch is turned off so that the second capacitor (C GMO2 Error amplifier output information for Channel 2 (V) in ) CGMO2 Saves ).

[0019] Another embodiment of the present invention relates to a compensation circuit of a single inductor DC-DC converter in which n output converters share an error amplifier and a compensation circuit, wherein, as the (+) input of the error amplifier, the error amplifier output information (V) of converter 1 among the n converters is obtained through a switch controlled by an OFF2 signal. CGM01 ), through a switch controlled by the OFF1 signal, the error amplifier output information (V) of converter 2 among the n converters CGM02 ), a reference voltage is selectively input through a switch controlled by the ON1 signal, and as the (-) input of the error amplifier, the feedback voltage (V) of the converter 1 is input through the switch controlled by the ON1 signal. FB1 ), feedback voltage (V) of converter 2 through a switch controlled by the ON2 signal FB2) is optionally input, and includes a switch that connects the output of the error amplifier to the (-) input and is controlled by an OFF signal.

[0020] When the above ON1 signal is given, the reference voltage (V) to the error amplifier REF ) and the feedback voltage (V) of the above converter 1 FB1 When ) is connected and the OFF1 signal is given, the (+) input of the error amplifier is the error amplifier output information (V) of the converter 2 CGM02 ) is input, and the (-) input is connected to the output of the error amplifier.

[0021] When the above ON2 signal is given, the reference voltage (V) to the error amplifier REF ) and the feedback voltage (V) of the above converter 2 FB2 When ) is connected and the Off2 signal is given, the (+) input of the error amplifier is the error amplifier output information (V) of the converter 1 CGM01 ) is input, and the (-) input is connected to the output of the error amplifier.

[0022] In addition, another embodiment of the present invention discloses a single inductor DC-DC converter configured to include the compensation circuit and the ramp generation circuit described above. Effects of the invention

[0024] A single-inductor multiple-output DC-DC converter applying a compensation circuit sharing technique according to one embodiment is designed based on a 0.18 µm BCDMOS process, and the converter operates at an input voltage of 4.5 to 5.0 V and has an output voltage of 1.2 to 4.0 V. The converter of one embodiment operates in a load range of 25 to 250 mA. It has a maximum efficiency of 93.2% when the load is 200 mA at a switching frequency of 1 MHz. Brief explanation of the drawing

[0026] Figure 1 illustrates a power source composed of multiple DC-DC buck converters. Figure 2 illustrates a power source composed of one DC-DC buck converter and multiple linear regulators. Figure 3 shows the schematic configuration of a SIMO DC-DC converter. Figure 4 shows a schematic configuration of a time-division SIMO DC-DC buck converter having N output channels. Figure 5 is a timing diagram showing the operation of a time-division SIMO DC-DC buck converter. Figure 6 shows a block diagram of a time-division structure SIMO DC-DC buck converter. FIG. 7 is a block diagram of a SIMO DC-DC buck converter according to the present invention. Figure 8 is a frequency compensation circuit of a voltage mode DCM DC-DC buck converter. Figure 9 illustrates a typical compensation circuit. Figure 10 shows the operation of the compensation circuit illustrated in Figure 9. Figure 11 shows the on / off signal of the SIMO DC-DC buck converter of the present invention. Figure 12 shows the general configuration of a lamp generation circuit. Figure 13 shows a timing diagram of a PWM control circuit. FIG. 14 shows a lamp generating circuit according to the present invention. FIG. 15 shows a timing diagram of a lamp generation circuit according to the present invention. FIG. 16 shows a compensation circuit according to the present invention. FIG. 17 shows a timing diagram of a compensation circuit according to the present invention. FIG. 18 exemplarily shows the main configuration of the overall structure of a single inductor multiple output DC-DC converter according to the present invention. Specific details for implementing the invention

[0027] Embodiments of the present invention will be described in detail below with reference to the drawings. However, detailed descriptions of known functions or configurations that may obscure the essence of the present invention in the following description and the attached drawings are omitted. Additionally, throughout the specification, the term 'comprising' a component means that, unless specifically stated otherwise, it does not exclude other components but may include additional components.

[0028] Additionally, terms such as first, second, etc. may be used to describe various components, but said components should not be limited by said terms. said terms may be used for the purpose of distinguishing one component from another component. For example, without departing from the scope of the present invention, the first component may be named the second component, and similarly, the second component may be named the first component.

[0029] The terms used in this invention are used merely to describe specific embodiments and are not intended to limit the invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, terms such as "comprising" or "comprising" are intended to specify the existence of the described features, numbers, steps, actions, components, parts, or combinations thereof, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0030] Unless specifically defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as generally understood by those skilled in the art to which the present invention pertains. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an ideal or overly formal sense unless explicitly defined in this application.

[0032] The following describes a SIMO DC-DC buck converter to which the compensation circuit sharing technique proposed in the present invention is applied. Prior to the detailed description of the present invention, the structure and main blocks of the SIMO DC-DC buck converter that form the basic configuration will be described, and then the compensation circuit sharing technique according to the present invention will be described. Prior to the description, the present invention relates to a single inductor DC-DC converter in which n outputs share an error amplifier and a compensation circuit; however, for convenience, the following description uses the case with two outputs as an example, but the present invention is not intended to be limited thereto.

[0034] 1. Structure of a SIMO DC-DC Buck Converter

[0035] A DC-DC converter must provide a constant output voltage even if the input voltage and load change. To provide a constant output voltage, the DC-DC converter must form a negative feedback system, and depending on how this negative feedback system is formed, it is classified into voltage mode and current mode.

[0036] A voltage mode DC-DC converter uses an error amplifier to compare the feedback voltage with the output voltage and the reference voltage to output error information, which is then compared with a ramp signal to perform pulse width modulation (PWM) operation. A DC-DC converter operating in voltage mode has the advantage of simple analysis and design by configuring a single feedback loop.

[0037] The SIMO DC-DC buck converter with the compensation circuit sharing technique proposed in the present invention has a time-division structure and operates in voltage mode DCM. FIG. 7 is a block diagram of the SIMO DC-DC buck converter according to the present invention.

[0038] The converter includes a ramp generation circuit for operating in voltage mode and a reverse current protection circuit for DCM operation. In addition, a soft start-up circuit and an overvoltage protection circuit are implemented to prevent inrush current during the initial operation of the converter.

[0039] The illustrated SIMO DC-DC buck converter has two output channels. Channel 1 (referred to as converter 1) operates at an output voltage of 2.6 to 4.0[V], and Channel 2 (referred to as converter 2) operates at an output voltage of 1.2 to 2.8[V]. The output voltage of the SIMO DC-DC buck converter can be adjusted by an external resistor, and a back gate control circuit is implemented to prevent reverse current flow when the difference in output voltage is greater than the forward voltage of a parasitic diode. Additionally, the designed SIMO DC-DC buck converter includes a compensation circuit sharing technique in which the compensation circuits of the two output channels are shared.

[0041] Voltage mode CCM DC-DC buck converters have two poles, making the system unstable, whereas voltage mode DCM DC-DC buck converters have one pole, making the system stable. However, due to the low crossover frequency, transient response performance is poor, and the output voltage error in the steady state is large due to the low DC gain. Therefore, a frequency compensation circuit is required for the converter, and DCM DC-DC buck converters have the advantage of simple implementation of the frequency compensation circuit because they have only one pole.

[0042] Equation 1 is the transfer function of a voltage-mode DCM DC-DC buck converter, Equation 2 represents the poles of the transfer function, and Equation 3 represents the gain of the transfer function. D represents the duty cycle of the converter, and M is the ratio of the output voltage to the input voltage. R o is the load resistance, C o is the output capacitor. R esr represents the parasitic resistance of the output capacitor, and the zero point generated by the parasitic resistance is given by Equation 4.

[0043]

[0044]

[0045]

[0046]

[0047] Output voltage V for converter 1 of the SIMO DC-DC buck converter OUT1 = 4.0[V], output voltage V for converter 2 OUT2 For =1.5[V], V IN =5[V], C o =44[uF], L=0.47[uH], f sw =1[MHz], I LOAD1,2When =200[mA], the DC gains for converters 1 and 2 are 0.4[dB] and 9.4[dB], respectively, and the crossover frequencies are 317[Hz] and 3.2[kHz], respectively, which are very low, so a frequency compensation circuit is required.

[0048] Figure 8 is the frequency compensation circuit of a voltage mode DCM DC-DC buck converter. R OUT represents the output impedance of the error amplifier. A compensation resistor R is attached to the error amplifier output to increase DC gain and crossover frequency. C and compensation capacitor C C A PI controller with an added structure was used.

[0049] The transfer function of the frequency compensation circuit is given by Equation 5 below.

[0050]

[0051] The poles formed in the frequency compensation circuit are as shown in Equation 6 and perform the function of increasing the DC gain.

[0052]

[0053] The zero formed in the frequency compensation circuit performs the function of raising the phase margin that was lowered due to the pole formed to increase the DC gain, and the zero is given by Equation 7.

[0054]

[0056] Hereinafter, the compensation circuit proposed in the present invention will be described.

[0057] 2. Existing compensation circuit

[0058] As shown in FIG. 9, the conventional compensation circuit uses as many error amplifiers as there are output channels of the converter and applies PI compensation to each error amplifier. A switch is connected to the output of each error amplifier and is controlled by the Ψ1 and Ψ2 signals. When Ψ1=H and Converter 1 operates, the error amplifier output V for Converter 1GMOUT1 Error amplifier output V for converter 2 when converter 2 operates with Ψ2=H outputting GMOUT2 Sends out.

[0059] Since conventional compensation circuits perform PI compensation for each output channel, V GMOUT1 ul C C1 Save to and V GMOUT2 ul C C2 It is stored in. Since the output information for converters 1 and 2 is multiplexed at the error amplifier output stage, when the phases of Ψ1 and Ψ2 change, the compensation capacitor C C1 , C C2 The output information of the error amplifier stored in is sent directly to the output without delay. The operation of the existing compensation circuit is shown in FIG. 10.

[0060] However, with this method, as the number of output channels of the converter increases, the number of required error amplifiers and PI compensation circuits also increases. The increased number of error amplifiers and PI compensation circuits leads to an increase in chip area, which is not suitable for the characteristics of wearable devices that require a small area.

[0062] 3. Proposed compensation circuit sharing technique

[0063] 3.1. Ramp Generation Circuit

[0064] The SIMO DC-DC buck converter according to the present invention operates in voltage mode. A DC-DC converter operating in voltage mode requires a ramp signal for PWM control. A ramp generation circuit is shown in FIG. 12.

[0065] The lamp generation circuit has a constant current I B A ramp signal V with a linearly increasing slope is generated by charging a capacitor. RAMP Generates the converter's period T sThe NMOS is turned on with a short pulse set signal to discharge the capacitor. This operation is repeated to generate a ramp signal at each switching cycle of the converter. The rising slope of the ramp signal is shown in Equation 8.

[0066]

[0068] 3.2. PWM Control Circuit

[0069] The PWM control circuit performs the function of providing a constant output voltage by detecting fluctuations in the input voltage and load of the converter, controlling the on and off switches, and adjusting the duty cycle. The PWM control circuit includes dead time control, an overvoltage protection circuit, and a reverse current protection circuit.

[0070] Figure 9 shows the timing diagram of the PWM control circuit. Error amplifier output V GMOUT and lamp signal V RAMP By applying as the input to the comparator, V GMOUT The converter's duty cycle is adjusted according to changes in . When the reference clock CLK is applied to the SR latch, the converter's on switch is turned on and transitions to on-time. V RAMP Ga V GMOUT When it becomes larger, the comparator detects this and applies a reset signal to the SR latch. Accordingly, the on switch is turned off and the off switch is turned on, causing the converter to switch to off-time. This operation is repeated to control the converter's duty cycle according to changes in the input voltage and load.

[0071] In PWM control, if the on and off switches are turned on simultaneously, a large current flows temporarily through the switches, reducing the efficiency of the converter. The dead time control circuit prevents the on and off switches from turning on simultaneously, thereby preventing the reduction in converter efficiency.

[0072] The reverse current protection circuit performs the function of enabling the converter to operate in DCM mode. It detects the moment when the inductor current becomes zero during the off-time and turns off the off switch to prevent reverse current from flowing. As a result, there is a period during which no current flows through the inductor.

[0074] The present invention proposes a compensation circuit sharing technique that uses a single error amplifier and a PI compensation circuit to maintain a small area. The proposed compensation circuit prevents the output delay of the error amplifier caused by sharing the compensation circuit. The proposed compensation circuit stores the error amplifier output information for the output channel of the converter in a capacitor and sends the stored error amplifier output information to the output of the unity-gain amplifier in advance before the phase of the control signals Ψ1 and Ψ2 changes.

[0075] In the present invention, the on and off signals for converter 1 are defined as on1 and off1 signals, and the on and off signals for converter 2 are defined as on2 and off2 signals. The proposed converter includes an on-off signal separation circuit that separates the on signal and the off signal. A timing diagram of the on-off signal separation circuit is shown in FIG. 11.

[0076] A ramp generation circuit for storing error amplifier output information for each channel of the converter is as shown in FIG. 14. C GMO1 is a capacitor that stores the error amplifier output information of converter 1, and C GMO2 is a capacitor that stores the error amplifier output information of Converter 2. When the ON switch of Converter 1 is turned on, current source I B Ga C GMO1 It is connected to generate a ramp signal. The generated ramp signal is V GMOUT The switch is turned off the moment it becomes larger, so the error amplifier output information V of converter 1 CGMO1 ul C GMO1 Save to.

[0077] Similarly, when the ON switch of converter 2 is turned on, current source I B is C GMO2 It is connected to generate a ramp signal, and the generated ramp signal is V GMOUT Turn off the switch at the point where it becomes larger, C GMO2 Error amplifier output information V for converter 2 CGMO2 It stores the. The timing diagram of the proposed ramp generation circuit is shown in Fig. 15.

[0078] FIG. 16 is a compensation circuit according to the present invention to which a compensation circuit sharing technique is applied to pre-output error amplifier output information stored before the phases of control signals Ψ1 and Ψ2 change to the output of a unity-gain amplifier. The compensation circuit has a structure in which a switch is added for multiplexing each error amplifier output information stored in the ramp generation circuit, and V CGMO1 is the off2 signal, V CGMO2 It is controlled by the off1 signal. The operating range of the proposed compensation circuit is divided into four categories: ON1, OFF1, ON2, and OFF2.

[0079] When ON1, the reference voltage V at the input of the error amplifier REF and the feedback voltage V of converter 1 FB1 This is connected. It outputs the error amplifier output for converter 1, and when on1=L, the error amplifier output is C of the proposed ramp generation circuit. GMO1 It is saved again in.

[0080] When OFF1, the compensation circuit uses the previously stored V at the (+) input of the error amplifier. CGMO2 It is connected, and the (-) input is connected to the output of the error amplifier, forming a unity-gain error amplifier structure. V is the output of the error amplifier. CGMO2 Since it outputs, error information for converter 2 is prepared in advance before ON2 is turned on.

[0081] When ON2, the reference voltage V at the input of the error amplifier REFand the feedback voltage V of converter 2 FB2 This is connected. It outputs the error amplifier output for converter 2, and when on2=L, the error amplifier output is C of the proposed ramp generation circuit. GMO2 It is saved again in.

[0082] When OFF2, the compensation circuit uses the previously stored V at the (+) input of the error amplifier. CGMO1 It is connected, and the (-) input is connected to the output of the error amplifier, forming a unity-gain error amplifier structure. V is the output of the error amplifier. CGMO1 Since it outputs, error information for converter 2 is prepared in advance before on1 is turned on again. Figure 17 shows the timing diagram of the proposed compensation circuit.

[0083] FIG. 18 illustrates only the major components of the overall structure of the single inductor multi-output DC-DC converter according to the present invention described above.

[0085] The present invention has been described above with reference to various embodiments. Those skilled in the art will understand that the present invention may be implemented in modified forms without departing from the essential characteristics of the invention. Therefore, the disclosed embodiments should be considered in an illustrative rather than a restrictive sense. The scope of the invention is defined by the claims, not by the foregoing description, and all variations within the scope of the claims should be interpreted as being included in the invention.

Claims

Claim 1 delete Claim 2 delete Claim 3 delete Claim 4 delete Claim 5 delete Claim 6 delete Claim 7 A single inductor DC-DC converter operating in a discontinuous current mode (DCM) in which a converter having n outputs shares one error amplifier and one compensation circuit in a time-division manner, comprising: a first capacitor (CGM01) connected to a current source through a first switch controlled by an ON1 signal, which stores error amplifier output information (VCGM01) of a first converter among the n converters; a second capacitor (CGM02) connected to the current source through a second switch controlled by an ON2 signal, which stores error amplifier output information (VCGM02) of a second converter among the n converters; an input terminal in which, as a positive (+) input of the error amplifier, error amplifier output information (VCGM01) of the first converter is selectively input through a third switch controlled by an OFF2 signal, error amplifier output information (VCGM02) of the second converter is selectively input through a fourth switch controlled by an OFF1 signal, and a reference voltage is selectively input through a fifth switch controlled by an ON1 signal; and as a negative (-) input of the error amplifier, A single inductor DC-DC converter comprising: an input terminal in which the feedback voltage (VFB1) of the first converter is selectively input through a sixth switch controlled by an ON1 signal and the feedback voltage (VFB2) of the second converter is selectively input through a seventh switch controlled by an ON2 signal; and an eighth switch controlled by an OFF signal that connects the output of the error amplifier to the negative (-) input, wherein the error amplifier output information (VCGM01) of the first converter and the error amplifier output information (VCGM02) of the second converter are selectively provided as inputs to the error amplifier, wherein n is a natural number greater than or equal to 2, the ON1 signal is an operation control signal of the first converter, the ON2 signal is an operation control signal of the second converter, the OFF1 signal is a non-operation control signal of the first converter, the OFF2 signal is a non-operation control signal of the second converter, and the OFF signal is a feedback control signal of the error amplifier. Claim 8 A single inductor DC-DC converter according to claim 7, wherein when the first switch is turned on, the current source is connected to the first capacitor to generate a ramp signal, and at the point where the generated ramp signal becomes greater than the output of the error amplifier, the first switch is turned off to store the error amplifier output information (VCGM01) of the first converter in the first capacitor (CGM01). Claim 9 A single inductor DC-DC converter according to claim 7, wherein when the second switch is turned on, the current source is connected to the second capacitor (CGM02) to generate a ramp signal, and at the point where the generated ramp signal becomes greater than the output of the error amplifier, the second switch is turned off to store error amplifier output information (VCGMO2) for the second converter in the second capacitor (CGM02). Claim 10 A single inductor DC-DC converter according to claim 7, wherein when the ON1 signal is given, the reference voltage (VREF) and the feedback voltage (VFB1) of the first converter are connected to the error amplifier, and when the OFF1 signal is given, the positive (+) input of the error amplifier is input to the error amplifier output information (VCGM02) of the second converter, and the negative (-) input is connected to the output of the error amplifier. Claim 11 A single inductor DC-DC converter according to claim 7, wherein when the ON2 signal is given, the reference voltage (VREF) and the feedback voltage (VFB2) of the second converter are connected to the error amplifier, and when the OFF2 signal is given, the positive (+) input of the error amplifier is input to the error amplifier output information (VCGM01) of the first converter, and the negative (-) input is connected to the output of the error amplifier.

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