Method and apparatus for erasing data in a memory device

Abstract

The aspects of the present disclosure provide a method for erasing data in a memory device. The data erasure method During an erasure operation in a memory cell string, the method includes the step of providing a first erasure carrier from a main body portion for the memory cell string. The first erasure carrier flows in a first direction from the source side of the memory cell string to the drain side of the memory cell string. Additionally, the data erasure method includes the step of providing a second erasure carrier from a junction on the drain side of the memory cell string. The second erasure carrier flows in a second direction from the drain side of the memory cell string to the source side of the memory cell string. Then, the data erasure method includes the step of injecting the first erasure carrier and the second erasure carrier into a charge storage portion of a memory cell within the memory cell string.

Description

Technology Field

[0001] The present invention relates to a method and apparatus for erasing data in a memory device. Background Technology

[0002] Semiconductor memory devices can be classified into volatile memory devices and non-volatile memory devices. Data is lost when the power is turned off in volatile memory devices. Non-volatile memory devices can retain stored data even when the power is cut off. To achieve higher data storage density, semiconductor manufacturers have developed vertical device technologies, such as three-dimensional (3D) NAND flash memory technology. 3D NAND flash memory devices are a type of non-volatile memory device.

[0003] An aspect of the present disclosure provides a method for erasing data in a memory element. The data erasing method comprises the step of providing a first erase carrier from a body portion for a memory cell string during an erase operation for resetting a plurality of memory cells connected in series within a memory cell string. The first erase carrier flows in a first direction between the source side of the memory cell string and the drain side of the memory cell string. Additionally, the data erasing method comprises the step of providing a second erase carrier from a junction on the drain side of the memory cell string during the erase operation. The second erase carrier flows in a second direction opposite to the first direction. Then, the data erasing method comprises the step of injecting the first erase carrier and the second erase carrier into a charge storage portion of a memory cell within the memory cell string during the erase operation. The injected first erase carrier and the second erase carrier are stored in the charge storage portion of the memory cell.

[0004] In some embodiments, the first erase carrier and the second erase carrier are holes. To provide the first erase carrier, in some embodiments, the data erasure method comprises the steps of making the source terminal on the source side of the memory cell string float, and applying a positive voltage to a P-type well corresponding to the main body portion of the memory cell string. The positive voltage causes the first erase carrier to flow in the first direction.

[0005] To provide the second erase carrier, the data erasure method includes the step of negatively biasing the gate terminal of the first select transistor in the memory cell string with respect to the drain terminal of the first select transistor. The negative biasing causes the generation of the second erase carrier at the PN junction on the drain side of the memory cell string due to band-to-band tunneling at the PN junction. In some embodiments, the first select transistor is the closest select transistor with respect to the drain side of the memory cell string, and the data erasure method further includes the step of negatively biasing the gate terminal of the second select transistor of the memory cell string with respect to the drain terminal of the second select transistor positioned next to the first select transistor.

[0006] In some embodiments, the data erasure method comprises the steps of applying an erasure voltage to a drain terminal on the drain side of the memory cell string, applying a first voltage lower than the erasure voltage to a gate terminal of the first selection transistor, and applying a second voltage lower than the first voltage to a gate terminal of the second selection transistor.

[0007] In some embodiments, the data erasure method further includes the step of negatively biasing the gate terminal of the first select transistor on the source side of the memory cell string with respect to the source / drain terminal of the first select transistor. Negative biasing causes the generation of additional erasure carriers at the PN junction on the source side of the memory cell string due to inter-band tunneling at the PN junction.

[0008] In one embodiment, the first selection transistor is the nearest selection transistor to the source side of the memory cell string. The data erasure method further includes the step of negatively biasing the gate terminal of the second selection transistor in the memory cell string with respect to the drain terminal of the second selection transistor disposed next to the first selection transistor. In one example, the data erasure method includes the step of applying a first voltage lower than a positive voltage applied to a P-type well of the memory cell string, and the step of applying a second voltage lower than the first voltage to the gate terminal of the second selection transistor.

[0009] According to one aspect of the present disclosure, the first erase carrier and the second erase carrier are provided in the same erase cycle.

[0010] An aspect of the present disclosure may provide a semiconductor memory device. The semiconductor memory device comprises a memory cell array comprising one or more memory cell strings having a plurality of memory cells connected in series within a memory cell string. The semiconductor memory device also comprises a peripheral circuit comprising a control circuit. The control circuit is configured to cause the peripheral circuit to provide a signal to the memory cell array to perform a method of erasing data in the memory cell array. Brief explanation of the drawing

[0011] Aspects of the present disclosure are best understood from the following detailed description when read together with the accompanying drawings. Please note that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of various features may be increased or decreased at will for the sake of clarity of discussion. FIG. 1 illustrates a block diagram of a semiconductor memory device according to some embodiments. FIG. 2 illustrates a cross-sectional view of a semiconductor memory device and a schematic symbol of a memory cell string according to some embodiments. FIG. 3 illustrates a flowchart outlining a process example according to some embodiments. FIG. 4 illustrates a waveform diagram of a signal of a semiconductor memory device according to some embodiments. FIG. 5 illustrates a waveform diagram of a signal of a semiconductor memory device according to some embodiments. Specific details for implementing the invention

[0012] The disclosure below provides many different embodiments or examples for implementing different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or on a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature are not in direct contact. Additionally, the disclosure may repeat reference numbers and / or letters in various examples. Such repetition is for simplicity and clarity and does not, in itself, indicate a relationship between the various embodiments and / or configurations discussed.

[0013] Additionally, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" are used herein for convenience of explanation to describe the relationship of one element or feature to other element(s) or feature(s) exemplified in the drawings. Spatially relative terms are intended to include other orientations of the device during use or operation in addition to the orientations shown in the drawings. The device may be oriented differently (rotated 90 degrees or oriented in a different way), and the spatially relative descriptors used herein may be interpreted accordingly.

[0014] An aspect of the present disclosure provides a mixed erase mechanism for erasing data in a non-volatile memory device, such as a NAND flash memory device. Generally, in the case of a NAND flash memory device, memory cells are arranged in a memory cell string. To achieve higher data storage, the memory cell string may be relatively long. Each memory cell string includes a memory cell transistor and a select transistor connected in series. The two ends of the memory cell string may be referred to as the source side and the drain side of the memory cell string. The mixed erase mechanism utilizes both a body erase mechanism and a gate-induced drain leakage (GIDL) erase mechanism during the erase operation, and the mixed erase mechanism may provide erase carriers from both the source side and the drain side of the memory cell string. Thus, memory cells can be effectively erased along a long memory cell string.

[0015] FIG. 1 illustrates a block diagram of a semiconductor memory device (100) according to some embodiment of the present invention. The semiconductor memory device (100) includes a memory array (102) and peripheral circuits (101) coupled together. In some examples, the memory array (102) and the peripheral circuits (101) are placed on the same die (chip). In other examples, the memory array (102) is placed on an array die, and the peripheral circuits (101) are placed on another die, such as a die implemented using complementary metal-oxide-semiconductor (CMOS) technology and referred to as a CMOS die. The array die and the CMOS die are appropriately joined and electrically coupled together. In one example, the semiconductor memory device (100) is an integrated circuit (IC) package encapsulating one or more array dies and CMOS dies.

[0016] A semiconductor memory device (100) is configured to store data in a memory array (102) and to perform operations in response to a received command (CMD). In some examples, the semiconductor memory device (100) may receive a write command (also called a program command), a read command, an erase command, etc., and perform operations accordingly. In one example, when the semiconductor memory device (100) receives a write command along with an address (ADDR) and data (DATA), the semiconductor memory device (100) stores data in the memory array (102) at that address. In another example, when the semiconductor memory device (100) receives a read command along with an address, the semiconductor memory device (100) accesses the memory array (102) and outputs the data stored in the memory array (102) at that address. In another example, when a semiconductor memory device (100) receives an erase command along with an address, the semiconductor memory device (100) resets one or more blocks of memory cells at that address to an unprogrammed state (also called an erased state), such as "1" in the case of a NAND memory cell.

[0017] Generally, the memory array (102) may include one or more memory planes (160), and each memory plane (160) may include a plurality of memory blocks, such as block-1 to block-N, as illustrated in FIG. 1. In some examples, simultaneous operations may occur on different memory planes (160). In some embodiments, each memory block (block-1 to block-N) is the minimum unit for performing erase operations. Each memory block includes multiple pages. In some examples, a page is the minimum unit that can be programmed (i.e., written).

[0018] In some embodiments, the memory array (102) is a flash memory array and is implemented using 3D NAND flash memory technology. Each memory block (block-1 to block-N) includes a plurality of memory cell strings arranged vertically (e.g., perpendicular to the main surface of the die). Each memory cell string includes a plurality of transistors connected in series. Details regarding the memory cell strings will be described later with reference to FIG. 2.

[0019] In some embodiments, the peripheral circuit (101) includes a row decoder circuit (110), a page buffer circuit (120), a data input / output (I / O) circuit (130), a voltage generator (140), and a control circuit (150) combined together as shown in FIG. 1.

[0020] A row decoder circuit (110) receives an address referred to as a row address (R-ADDR), generates a selection signal based on the row address, such as a word line (WL) signal and top select gate (TSG) signal(s), bottom select gate (BSG) signal(s), etc., and can provide the WL signal and the selection signal to the memory cell array (102). In some examples, during a write operation, the row decoder circuit (110) provides the WL signal and the selection signal to the memory cell array (102) to select a page to program. During a read operation, the row decoder circuit (110) can provide the WL signal and the selection signal to select a page for buffering. During an erase operation, the row decoder circuit (110) can provide appropriate WL signal and selection signal according to the present disclosure, which will be further explained, for example, with reference to FIGS. 4 and FIGS. 5.

[0021] A page buffer circuit (120) is coupled to a bit line (BL) of a memory cell array (102) and configured to buffer data, such as data from one or more pages, during read and write operations. In one example, during a write operation, the page buffer circuit (120) may buffer data to be programmed and drive data to the bit line of the memory cell array (102) to write data to the memory cell array (102). In another example, during a read operation, the page buffer circuit (120) may detect data on the bit line of the memory cell array (102) and buffer the detected data for output.

[0022] In the example of FIG. 1, the data I / O circuit (130) is coupled to the page buffer circuit (120) via a data line (DL). In one example (e.g., during a write operation), the data I / O circuit (130) is configured to receive data from an external circuit of the semiconductor memory device (100) and to provide the received data to the memory cell array (102) via the page buffer circuit (132). In another example (e.g., during a read operation), the data I / O circuit (130) is configured to output data from the memory cell array (102) to the external circuit based on an address referred to as a column address (C-ADDR).

[0023] The voltage generator (140) is configured to generate a voltage level suitable for the proper operation of the semiconductor memory device (100). For example, during a read operation, the voltage generator (140) can generate a voltage level suitable for the source voltage, body voltage, various WL voltages, select voltages, etc. for the read operation. In some examples, the source voltage is provided as an array common source (ACS) voltage to the source terminal of the memory cell array (102) during the read operation; and the body voltage is provided to the P-type well (PW), which is the body portion of the memory cell strings, during the read operation. The body voltage is labeled as the PW voltage in FIG. 1, for example. The WL voltage and select voltage are provided to the row decoder (110), so that the row decoder (110) can output the WL signal and select signal (e.g., TSG signal and BSG signal) at a suitable voltage level during the read operation.

[0024] In another example, during an erase operation, the voltage generator (140) can generate a voltage of a level suitable for the erase operation, such as a source voltage, body voltage, various WL voltages, select voltages, BL voltages, etc. In some examples, the source voltage is provided as an ACS voltage to the source terminal of the memory cell array (102) during the erase operation; and the PW voltage is provided to the P-type well, which is the body portion of the memory cell strings, during the erase operation. The WL voltage and select voltage are provided to the row decoder (110), so that the row decoder (110) can output the WL signal and the BSG and TSG signals at a suitable voltage level during the erase operation. The BL voltage is provided to the page buffer circuit (120), so that the page buffer circuit (120) can drive the bit line (BL) at an appropriate voltage level during the erase operation. Note that the BL voltage can be applied to the bit line without passing through the page buffer circuit (120).

[0025] The control circuit (150) is configured to receive a command (CMD) and an address (ADDR) and to provide control signals to other circuits, such as a row decoder circuit (110), a page buffer circuit (120), a data I / O circuit (130), and a voltage generator (140), based on the command and address. For example, the control circuit (150) may generate a row address (R-ADDR) and a column address (C-ADDRC) based on the address (ADDR), provide the row address (R-ADDR) to the row decoder (110), and provide the column address to the data I / O circuit (130). In another example, the control circuit (150) may control the voltage generator (140) to generate a voltage of a suitable level based on the received CMD. The control circuit (150) may coordinate other circuits to provide signals to the memory cell array (102) at a suitable time and a suitable voltage level.

[0026] In the example of FIG. 1, the control circuit (150) includes a part (155) configured to generate an appropriate control signal to control another circuit for providing a signal suitable for an erase operation using both the body erase mechanism and the GIDL erase mechanism to the memory cell array (102). A signal having appropriate timing and voltage levels for the memory cell array (102) can cause the use of both the body erase mechanism and the GIDL erase mechanism for an erase operation. The waveform of the signal will be described in detail in FIG. 4 and FIG. 5.

[0027] FIG. 2 illustrates a cross-sectional view of a semiconductor memory device (200) according to some embodiments of the present invention. In some examples, the semiconductor memory device (200) may be a semiconductor memory device (100). According to some embodiments of the present disclosure, the semiconductor memory device (200) includes an array die (202) and a CMOS die (201) joined together.

[0028] Please note that in some embodiments, the semiconductor memory device may include a plurality of array dies and CMOS dies. The plurality of array dies and CMOS dies may be stacked and bonded together. Each CMOS die is connected to a plurality of array dies and may drive each array die to operate in a manner similar to that of the semiconductor memory device (200).

[0029] The array die (202) includes a substrate (203) and a memory cell formed on the substrate (203). The CMOS die (201) includes a substrate (204) and a peripheral circuit formed on the substrate (204). For simplification, the main surface of the substrate (203) is referred to as the XY plane, and the direction perpendicular to the main surface is referred to as the Z direction.

[0030] The substrate (203) and the substrate (204) may each be any suitable substrate, such as a silicon (Si) substrate, a germanium (Ge) substrate, a silicon-germanium (SiGe) substrate, and / or a silicon-on-insulator (SOI) substrate. The substrate (203) and the substrate (204) may each comprise a semiconductor material, for example, a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI oxide semiconductor. The group IV semiconductor may comprise Si, Ge, or SiGe. The substrate (203) and the substrate (204) may each be a bulk wafer or an epitaxial layer.

[0031] A semiconductor memory device (200) includes a memory cell array (e.g., a memory circuit array (102)) and peripheral circuits (e.g., a row decoder circuit (110), a page buffer circuit (120), a data I / O circuit (130), a voltage generator (140), a control circuit (150), etc.). In the example of FIG. 2, the memory cell array is formed on the substrate (203) of the array die (202) and the peripheral circuits are formed on the substrate (204) of the CMOS die (201). The array die (202) and the CMOS die (201) are placed face-to-face (the surface on which the circuits are placed is called the front face and the opposite surface is called the back face) and are joined together.

[0032] In some examples, wells may be formed on the substrate (202) for each block as a body portion for the block. In the example of FIG. 2, a P-type well (205) is formed on the substrate (203), and a block of a three-dimensional (3D) NAND memory cell string may be formed within the P-type well (205). The P-type well (205) may form a body portion for the 3D NAND memory cell strings (e.g., in relation to the PW terminal), and a voltage referred to as PW may be applied to the P-type well (205) through the PW terminal. Generally, the memory cell array is formed in the core region (206) as an array of vertical memory cell strings. In addition to the core region (206) and the peripheral region, the array die (202) includes a step region (207) (also referred to as a connection region in some examples) to facilitate connections to the gates of memory cells, the gates of select transistors, etc., within the vertical memory cell string. The gates of the memory cells within the vertical memory cell string correspond to the word lines of the NAND memory architecture.

[0033] In the example of FIG. 2, a vertical memory cell string (280) is illustrated as a representation of an array of vertical memory cell strings formed in a core region (206). FIG. 2 also illustrates a schematic symbol version of a vertical memory cell string (280') corresponding to the vertical memory cell string (280). The vertical memory cell string (280) is formed as a stack of layers (290). The stack of layers (290) includes alternating stacked gate layers (295) and insulating layers (294). The gate layers (295) and insulating layers (294) are configured to form vertically stacked transistors. In some examples, the stack of transistors includes memory cells and select transistors, such as one or more bottom select transistors, one or more top select transistors, etc. In some examples, the stack of transistors may include one or more dummy select transistors. The gate layer (295) corresponds to the gate of the transistor. The gate layer (295) is made of a gate stack material such as a high-k gate insulator layer, a metal gate (MG) electrode, etc. The insulating layer (294) is made of insulating material(s) such as silicon nitride, silicon dioxide, etc.

[0034] According to some aspects of the present disclosure, a vertical memory cell string is formed by channel structures (281) that extend vertically (in the Z direction) into a stack (290) of layers. The channel structures (281) may be arranged separately from each other in the XY plane. In some embodiments, the channel structures (281) are arranged in an array form between gate line cut structures (not shown). The gate line cut structures are used to facilitate the replacement of the sacrificial layer with the gate layer (295) in the gate final process. The array of channel structures (281) may have any suitable array shape, such as a matrix array shape along the X and Y directions, a zigzag array shape along the X or Y direction, a honeycomb (e.g., hexagonal) array shape, etc. In some embodiments, each channel structure has a circular shape in the XY plane and a columnar shape in the XZ and YZ planes. In some embodiments, the number and arrangement of channel structures between the gate line cut structures are not limited.

[0035] In some embodiments, the channel structure (281) is a pillar shape extending in the Z direction perpendicular to the main direction of the substrate (203). In one embodiment, the channel structure (281) is circular in the XY plane and extends in the Z direction. For example, the channel structure (281) includes functional layers such as a blocking insulating layer (282) (e.g., silicon oxide), a charge storage layer (e.g., silicon nitride) (283), a tunneling insulating layer (284) (e.g., silicon oxide), a semiconductor layer (285), and an insulating layer (286) having a circular shape in the XY plane and extending in the Z direction. In one example, a blocking insulating layer (282) (e.g., silicon oxide) is formed on the hole sidewall for the channel structure (281) (into the stack of layers (280)), and then a charge storage layer (e.g., silicon nitride) (283), a tunneling insulating layer (284), a semiconductor layer (285), and an insulating layer (286) are sequentially stacked from the sidewall. The semiconductor layer (285) may be any suitable semiconductor material, such as polysilicon or single-crystal silicon, and the semiconductor material may be undoped or may contain p-type or n-type dopants. In some examples, the semiconductor material is an undoped intrinsic silicon material. However, due to defects, the intrinsic silicon material in some examples 10 10 cm -3 It may have a carrier density of a certain degree. The insulating layer (286) may be formed of an insulating material such as silicon oxide and / or silicon nitride, or may be formed of an air gap.

[0036] According to some aspects of the present disclosure, a channel structure (281) and a stack of layers (290) together form a memory cell string (280). For example, a semiconductor layer (285) corresponds to a channel portion for a transistor within the memory cell string (280), and a gate layer (295) corresponds to a gate of a transistor within the memory cell string (280). Generally, a transistor has a gate that controls the channel and has a drain and a source on each side of the channel. For simplification, in the example of FIG. 2, the upper side of the channel for the transistor is referred to as the drain, and in FIG. 2, the bottom side of the channel for the transistor is referred to as the source. Note that the drain and source may be switched under a specific driving configuration. In the example of FIG. 2, the semiconductor layer (285) corresponds to a connected channel of the transistor. In the case of a specific transistor, the drain of the specific transistor is connected to the source of the upper transistor above the specific transistor, and the source of the specific transistor is connected to the drain of the lower transistor below the specific transistor. Therefore, the transistors in the memory cell string (280) are connected in series.

[0037] A memory cell string (280) includes a memory cell transistor (or referred to as a memory cell). The memory cell transistor may have different threshold voltages based on carrier trapping in a portion of the charge storage layer (283) corresponding to a floating gate for the memory cell transistor. For example, when a significant amount of holes are trapped (stored) in the floating gate of the memory cell transistor, if the threshold voltage of the memory cell transistor is lower than a predefined value, the memory cell transistor is in an unprogrammed state (also referred to as an erased state) corresponding to logic "1". When holes are ejected from the floating gate, the threshold voltage of the memory cell transistor is higher than a predefined value, and thus the memory cell transistor is in a programmed state corresponding to logic "0" in some examples.

[0038] A memory cell string (280) includes one or more upper select transistors configured to couple / decouple memory cells within the memory cell string (280) with bit lines, and one or more lower select transistors configured to couple / decouple memory cells within the memory cell string (280) with ACS. For example, a symbolic version (280') of the memory cell string includes one upper select transistor and one lower select transistor, and a symbolic version (280") of the memory cell string includes one upper select transistor and two lower select transistors.

[0039] The top select transistor is controlled by the top select gate (TSG). For example, when the TSG voltage (voltage applied to the TSG) is greater than the threshold voltage of the top select transistor, the top select transistor is turned on and the memory cell is connected to the bit line; when the TSG voltage (voltage applied to the TSG) is less than the threshold voltage of the top select transistor, the top select transistor is turned off and the memory cell is disconnected from the bit line.

[0040] Similarly, the bottom select transistor is controlled by the bottom select gate (BSG). For example, when the BSG voltage (voltage applied to the BSG) is greater than the threshold voltage of the bottom select transistor, the bottom select transistor is turned on and the memory cell is coupled to the ACS; when the BSG voltage (voltage applied to the BSG) is less than the threshold voltage of the bottom select transistor, the bottom select transistor is turned off and the memory cell is separated from the ACS.

[0041] According to some aspects of the present disclosure, the bottom portion of the semiconductor layer (285) within the channel hole corresponds to the source side of the vertical memory cell string (280), and the bottom portion is labeled 285(S). A common source layer (289) is formed in a conductive connection with the source of the vertical memory cell string (280). The common source layer (289) may comprise one or more layers. In some examples, the common source layer (289) comprises a silicon material such as intrinsic polysilicon, doped polysilicon (e.g., N-type doped silicon, P-type doped silicon), etc. In some examples, the common source layer (289) may comprise a metal silicide to enhance conductivity. The common source layer (289) is similarly in a conductive connection with the source of another vertical memory cell string (not shown) and thus forms an array common source (ACS).

[0042] In some examples, when the vertical memory cell string (280) is configured to be erased in blocks, the common source layer (289) may extend and cover the core area of ​​the block and the step area for the block. In some examples, for different blocks that are erased individually, the common source layer (289) may be appropriately insulated for those different blocks.

[0043] In the example of FIG. 2, in the channel structure (281), the semiconductor layer (285) extends vertically upward from the source side of the channel structure (281) and forms an upper portion corresponding to the drain side of the vertical memory cell string (280). The upper portion of the semiconductor layer (285) is labeled 285(D). Please note that the drain side and the source side are named for convenience of explanation. The drain side and the source side may function differently from their names.

[0044] In the example of FIG. 2, a connection structure, such as a via (272) with a metal wire (273), a bonding structure (274), etc., can be formed to electrically bond the upper portion of the semiconductor layer (285(D)) to the bit line (BL).

[0045] Additionally, in the example of FIG. 2, the step region (207) includes steps formed to facilitate word line connection to the gate of a transistor (e.g., memory cell, top select transistor(s), bottom select transistor(s)). For example, the word line connection structure (270) includes a contact structure (271), a via structure (272), and a metal wire (273) that are conductively coupled together. The word line connection structure (270) can electrically couple the WL to the gate terminal of a transistor within a memory cell string (280).

[0046] In the example of FIG. 2, the array die (202) and the CMOS die (201) are placed face-to-face (the circuit side is the front and the substrate side is the back) and joined together. Generally, peripheral circuits on the CMOS die interface the semiconductor memory device (200) with external circuits.

[0047] In the example of FIG. 2, the CMOS die (201) and the array die (202) each include a bonding structure that can be aligned with each other. For example, the CMOS die (201) includes a bonding structure (234) and the array die (202) includes a corresponding bonding structure (274). The array die (202) and the CMOS die (201) can be properly aligned, so that the bonding structure (234) is aligned with the bonding structure (274). When the array die (202) and the CMOS die (201) are bonded together, the bonding structure (234) is bonded to the bonding structure (274) and electrically coupled.

[0048] According to some aspects of the present disclosure, in the case of a memory cell string (280) of a NAND configuration, an erase operation resets the memory cell. For example, during an erase operation, holes are injected into and captured in the charge storage layer (283) (or electrons are ejected from the charge storage layer (283)). When holes are captured in the charge storage layer (283) of the memory cell, the threshold voltage of the memory cell is reduced, and the memory cell can enter an unprogrammed state (also called an erased state).

[0049] In a related example using a body erasure mechanism, during the erasure operation, a ground level voltage may be applied to the gate of a memory cell within a memory cell string (280), the source and drain of the memory cell string (280) are floating, and a relatively high voltage (e.g., about 20 V) is applied to the P-type well (205). The P-type well (205) may provide holes (erasure carriers), and the holes may be injected from the P-type well (205) into the semiconductor layer (285) in a downward direction (from the source side to the drain side of the memory cell string (280)) and then injected into the charge storage layer (283) due to the negative biasing of the gate with respect to the channel voltage. In a related example, if there are many memory cells in the memory cell string (280), it is difficult to push holes up to the upper part of the semiconductor layer (285), and some memory cells close to the drain side of the memory cell string (280) may not be completely erased (meaning there are not enough holes captured in the upper part of the charge storage layer (283) to lower the threshold voltage below a preset value).

[0050] According to some aspects of the present disclosure, both the main body erase mechanism and the GIDL erase mechanism are used during the erase operation to effectively reset the memory cells along the memory cell string (280) to an erased state, even if the number of memory cells in the memory cell string (280) is relatively large. For example, during the erase operation, a ground level voltage may be applied to the gate of a memory cell in the memory cell string (280), the source of the memory cell string (280) is floating, and a relatively high voltage (e.g., about 20 V) is applied to the P-type well (205). The P-type well (205) may provide an erase carrier (e.g., a hole denoted by 291), and the hole is driven upward from the P-type well (205) toward the semiconductor layer (285) (as shown as 291' and 291") and then injected into the charge storage layer (283) when the gate of the memory cell is negatively biased toward the channel.

[0051] Additionally, the GIDL erasure mechanism is induced on the drain side of the memory cell string (280). In some embodiments, negative biasing is applied to the gate(s) of the top select transistor(s) (next to the drain of the memory cell string (280)) with respect to the drain of the memory cell string (280). Due to the negative biasing, a P-type region is created and a PN junction is formed on the drain side of the semiconductor layer (285). Additionally, when a high electric field is applied to the PN junction, gate-induced drain leakage (GIDL) occurs due to inter-band tunneling, and a hole current is generated and flows downward from the drain as indicated by 292. The holes are injected into the upper portion of the charge storage layer (283) when the gate of the memory cell is negatively biased with respect to the channel.

[0052] Please note that when both the main body erasure mechanism and the GIDL erasure mechanism are used, holes can be generated and driven from both the source side and the drain side of the memory cell string (280), and thus memory cells can be erased relatively easily along the memory cell string (280).

[0053] FIG. 3 illustrates a flowchart outlining a process (300) according to some embodiments of the present disclosure. In some examples, the process (300) is executed in a semiconductor memory device, such as a semiconductor memory device (100) or a semiconductor memory device (200), during an erase operation. The semiconductor memory device comprises an array of memory cell strings. The memory string comprises transistors, such as upper select transistor(s), memory cell transistors, and lower select transistor(s), connected in series. The process starts at S301 and proceeds to S310. During the erase operation, the memory cells in the memory cell string are reset to an unprogrammed state, such as a low threshold voltage state corresponding to a logic "1" in the example of a NAND memory.

[0054] In S310, a first erase carrier is provided from the main body portion of the memory cell string during an erase operation to reset a memory cell within the memory cell string. The first erase carrier flows in a first direction from the source side of the memory cell string to the drain side of the memory cell string. The first erase carrier is generated and provided according to the main body erase mechanism. Specifically, in one example, a relatively large voltage is applied to the main body terminal, such as the P-type well in the example of FIG. 2, and the ACS is in a floating state. Accordingly, holes in the P-type well can be driven into the semiconductor layer (285) in the direction from the source side to the drain side of the memory cell string.

[0055] In S320, a second erase carrier is provided from the junction on the drain side of the memory cell string. The second erase carrier flows in a second direction from the drain side of the memory cell string to the source side of the memory cell string. The second erase carrier is generated and provided according to the GIDL erase mechanism. Specifically, in one example, one or more top select gates of the top select transistor(s) may be negatively biased with respect to the drain(s) of the top select transistor. Due to the negative biasing, a P-type region may be created on the drain side of the semiconductor layer (285) and a PN junction may be formed. Additionally, a high electric field may be applied to the PN junction. The high electric field may cause gate-induced drain leakage (GIDL) due to inter-band tunneling, and a hole current is generated and flows downward from the drain side to the source side, as illustrated in the example of FIG. 2.

[0056] In S330, the first erase carrier and the second erase carrier are injected into the charge storage portion of the memory cell within the memory cell string. For example, the gate of the memory cell is negatively biased with respect to the channel (e.g., semiconductor layer (285)), and thus holes in the channel, such as the first erase carrier and the second erase carrier, can be injected into the charge storage layer (283). The injected holes are captured in the charge storage portion of the memory cell. When enough holes are captured, the threshold voltage of the memory cell is lowered below a predetermined specific value, and the memory cell enters an unprogrammed state. Then, in one example, the process proceeds and terminates.

[0057] FIG. 4 illustrates a waveform diagram (400) for a signal provided to a memory cell string, such as a memory cell string indicated by the symbol (280'), according to some embodiments. The diagram (400) includes a first waveform (410) for a BL signal, a second waveform (420) for a TSG signal, a third waveform (430) for a WL signal (or dummy WL signal), a fourth waveform (440) for a BSG signal, and a fifth waveform (450) for a PW signal. In some embodiments, a control circuit (155) for mixed erasure controls a peripheral circuit (101) to generate a BL signal having the first waveform (410), generate a TSG signal having the second waveform (420), generate a WL signal having the third waveform (430), generate a BSG signal having the fourth waveform (440), and generate a PW signal having the fifth waveform (450). One of the BL signal, TSG signal, WL signal, BSG signal and PW signal may be provided to a memory cell string represented, for example, by the symbol 280'.

[0058] In the example of Fig. 4, the erasure operation is performed for a time duration T.

[0059] At time t0, in one example, the peripheral circuit (101) receives a command to erase a block at an address. For example, a memory cell string represented by the symbol 280' is placed in the block. Then, the control circuit for mixed erase (155) provides control signals to other components of the peripheral circuit (101) to generate PW signal, ACS signal, WL signal, TSG signal, BSG signal, and BL signal. In the example of FIG. 4, at time t0, note that the PW signal, WL signal, TSG signal, BSG signal, and BL signal are at ground level or floating state in one example. Note that the ACS signal may be a floating signal that is not connected to any absolute voltage level during time T for the erase operation, and is not shown in FIG. 2.

[0060] At time t1, the peripheral circuit (101) outputs a PW signal, a WL signal, a TSG signal, a BSG signal, and a BL signal. In the example of FIG. 4, at time t1, the voltage levels of the PW signal, the TSG signal, the BSG signal, and the BL signal begin to rise. The peripheral circuit (101) outputs a WL signal at ground level in one example. The PW signal is provided, for example, to drive a P-type well (205). The common source layer (289) may have a floating voltage level. The gate layer (295) is driven according to the TSG signal, the WL signal, and the BSG signal. The junction structure (234, 274) is driven according to the BL signal.

[0061] At t2, the BL signal rises to an erase voltage level, such as, for example, about 20 V, and maintains the erase voltage level as illustrated in 411. The TSG signal rises to a first select gate voltage lower than the erase voltage level, such as, for example, in the range of 10 V to 14 V, and maintains the first select gate voltage as illustrated in 421. The WL signal is maintained at a ground level in one example. In some examples, the WL signal may rise and be maintained at a level within the range of 0 V to 3 V. The BSG signal rises to a relatively high voltage level, such as, for example, in the range of 10 V to 20 V, and maintains the voltage level as illustrated in 441. The PW signal rises to an erase voltage level, such as, for example, about 20 V, and maintains the erase voltage level as illustrated in 451.

[0062] According to one aspect of the present disclosure, a PW signal, a BSG signal, a floating ACS signal, and a WL signal applied to a memory cell string can induce a main body erasure mechanism in the memory cell string. For example, holes in a P-type well (205) are driven into a semiconductor layer (285) corresponding to the channel portion of the memory cell string. A BSG signal of a relatively high voltage allows holes to flow into the channel portion of the memory cell, for example, in an upward direction. Additionally, negative biasing of the WL with respect to the channel portion can inject holes into a charge storage layer (283), for example, a lower portion of the charge storage layer (283).

[0063] According to another aspect of the present disclosure, the BL signal, TSG signal, and WL signal applied to the memory cell string can induce a GIDL erasure mechanism. For example, the gate of the top select transistor is negatively biased due to the voltage difference between the TSG signal and the BL signal. Due to the negative bias, a P-type region may be created and a PN junction may be formed at the drain of the top select transistor. Additionally, due to the voltage difference between the TSG signal and the BL signal, a high electric field is applied to the PN junction. The high electric field may cause gate-induced drain leakage (GIDL) due to inter-band tunneling, and a hole current is generated in the semiconductor layer (285) and flows downward from the drain side to the source side. Additionally, the negative bias of WL on the channel portion may inject holes into the charge storage layer (283), for example, the upper portion of the charge storage layer (283).

[0064] At t3, the BL signal, TSG signal, BSG signal, and PW signal begin to decrease.

[0065] At t4, the BL signal, TSG signal, BSG signal, and PW signal return to ground level in one example.

[0066] At t5, the erase cycle ends.

[0067] Please note that in some examples, a verification operation may be performed after an erase operation. The verification operation can verify whether the memory cells within the memory cell string have been reset to an unprogrammed state. For example, the control circuit (155) generates a PW signal, an ACS signal, a WL signal, a TSG signal, and a BSG signal, and then provides control signals to other components of the peripheral circuit (101) to detect the BL signal. For example, to check the unprogrammed state of the memory cells, the PW signal is set to a ground level, as illustrated in 452; the BSG signal is set to a turn-on level for the bottom select transistor, such as about 3V to 5V, as illustrated in 442; and the TSG signal is set to a turn-on level for the top select transistor, such as about 3V to 5V, as illustrated in 422; As illustrated in 432, the WL signal is set to a level between a first threshold voltage (e.g., for an unprogrammed state) and a second threshold voltage (e.g., for a programmed state), such as about 3V to 5V in one example. The voltage level of the bit line (illustrated in 412) can be detected and amplified. If the voltage level corresponds to logic "0", the memory cell is in an unprogrammed state, and the erase operation is verified as successful. If the voltage level corresponds to logic "1", the erase operation is not successfully performed, and in one example, another erase operation may be performed.

[0068] Please note that in some examples, the memory cell string includes a dummy memory cell (DMY) that can be controlled similarly to the WL signal for the memory cell.

[0069] FIG. 5 illustrates a diagram (500) of waveforms for signals provided to a memory cell string, such as a memory cell string represented by the symbol 280", according to some embodiments. The diagram (500) includes a first waveform (510) for a BL signal, a second waveform (520) for a TSG signal, a third waveform (530) for a WL signal (or dummy WL signal), a fourth waveform (540) for a BSG1 signal, a fifth waveform (550) for a BSG2 signal, and a sixth waveform (560) for a PW signal. In some embodiments, a control circuit (155) for mixed erasure controls a peripheral circuit (101) to generate a BL signal having a first waveform (510), generate a TSG signal having a second waveform (520), generate a WL signal having a third waveform (530), generate a BSG1 signal having a fourth waveform (540), and a fifth A BSG2 signal having a waveform (550) can be generated, and a PW signal having a sixth waveform (560) can be generated. One of the BL signal, TSG signal, WL signal, BSG1 signal, BSG2 signal and PW signal can be provided to a memory cell string represented, for example, by the symbol 280".

[0070] In the example of Fig. 5, the erasure operation is performed for a duration T.

[0071] At time t0, in one example, the peripheral circuit (101) receives a block erase command at an address. For example, a memory cell string represented by the symbol 280" is placed in the block. Then, the control circuit for mixed erase (155) provides control signals to other components of the peripheral circuit (101) to generate the PW signal, ACS signal, WL signal, TSG signal, BSG1 signal, BSG2 signal, and BL signal. Note that in the example of FIG. 5, at time t0, the PW signal, WL signal, TSG signal, BSG1 signal, BSG2 signal, and BL signal are at ground level or floating in one example. Note that the ACS signal may be a floating signal not connected to an absolute voltage level during the duration T for the erase operation, and is not shown in FIG. 5.

[0072] At time t1, the peripheral circuit (101) outputs a PW signal, a WL signal, a TSG signal, a BSG1 signal, a BSG2 signal, and a BL signal. In the example of FIG. 5, at time t1, the voltage levels of the PW signal, the TSG signal, the BSG1 signal, and the BL signal begin to rise. The peripheral circuit (101) outputs a WL signal at ground level in one example. The PW signal is provided, for example, to drive a P-type well (205). The common source layer (289) may have a floating voltage level. The gate layer (295) is driven according to the TSG signal, the WL signal, the BSG1 signal, and the BSG2 signal. The junction structure (234, 274) is driven according to the BL signal.

[0073] At t2, the BL signal rises to an erase voltage level, such as about 20 V in one example, and maintains the erase voltage level as illustrated in Fig. 511. The TSG signal rises to a first select gate voltage lower than the erase voltage level, such as in the range of 10 V to 14 V in one example, and maintains the first select gate voltage as illustrated in Fig. 521. The WL signal is maintained at a ground level in one example. In some examples, the WL signal may rise to and maintain a level in the range of 0 V to 3 V. The BSG1 signal rises to a first high voltage level, such as in the range of 10 V to 20 V in one example, and maintains that voltage level as illustrated in Fig. 541. The PW signal rises to an erase voltage level, such as about 20 V in one example, and maintains the erase voltage level as illustrated in Fig. 561. In some examples, the BSG2 signal begins to rise at t2.

[0074] According to one aspect of the present disclosure, a PW signal, a BSG1 signal, a floating ACS signal, and a WL signal applied to a memory cell string can induce a main body erasure mechanism in the memory cell string. For example, holes in a P-type well (205) are driven into a semiconductor layer (285) corresponding to the channel portion of the memory cell string. A relatively high voltage of the BSG1 signal allows holes to flow into the channel portion of the memory cell, for example, in an upward direction. Additionally, negative biasing of the WL with respect to the channel portion can inject holes into a charge storage layer (283), for example, a bottom portion of the charge storage layer (283).

[0075] According to another aspect of the present disclosure, the BL signal, TSG signal, and WL signal applied to the memory cell string can induce a GIDL erasure mechanism. For example, the gate of the top select transistor is negatively biased due to the voltage difference between the TSG signal and the BL signal. Due to the negative bias, a P-type region may be created and a PN junction may be formed at the drain of the top select transistor. Additionally, due to the voltage difference between the TSG signal and the BL signal, a high electric field is applied to the PN junction. The high electric field can cause gate-induced drain leakage (GIDL) due to inter-band tunneling, and a hole current is generated in the semiconductor layer (285) and flows from the drain side to the source side. Additionally, the negative bias of WL on the channel portion can inject holes into the charge storage layer (283), for example, the upper portion of the charge storage layer (283).

[0076] At t3, the BSG2 signal rises to a second high voltage level, such as within the range of 8V to 10V in one example, and maintains that voltage level as illustrated in 551. According to one aspect of the present disclosure, the BSG1 signal, BSG2 signal, and WL signal applied to the memory cell string can induce a GIDL erasure mechanism. For convenience of explanation, the bottom selection transistor placed closest to the source side of the memory cell string is referred to as the first bottom selection transistor, and the bottom selection transistor above the first bottom selection transistor is referred to as the second bottom selection transistor. The gate of the second selection transistor is negatively biased due to the voltage difference of the BSG2 signal to the BSG1 signal. Due to the negative bias, a P-type region may be created at the source of the second bottom selection transistor, and a PN junction may be formed at the source of the second bottom selection transistor. Additionally, due to the voltage difference between the BSG2 signal and the BSG1 signal, a high electric field is applied to the PN junction. A high electric field can cause gate-induced drain leakage (GIDL) due to inter-band tunneling, and a hole current is generated in the semiconductor layer (285) and flows upward from the source side to the drain side. Additionally, negative biasing of the WL with respect to the channel portion can inject holes into the charge storage layer (283), for example, the upper portion of the charge storage layer (283).

[0077] Please note that the second bottom-select transistor is placed closer to the memory cell within the memory cell string than the first bottom-select transistor and the P-type well, and it may be easier to drive the hole current from the source of the second bottom-select transistor to the channel portion for the memory cell.

[0078] At t4, the BL signal, TSG signal, BSG1 signal, BSG2 signal, and PW signal begin to decrease.

[0079] At t5, the BL signal, TSG signal, BSG1 signal, BSG2 signal, and PW signal return to ground level in one example.

[0080] At t6, the erase cycle ends.

[0081] Please note that in some examples, a verification operation may be performed after an erase operation. The verification operation can verify whether the memory cells within the memory cell string have been reset to an unprogrammed state. For example, the control circuit (155) provides control signals to other components of the peripheral circuit (101) to generate PW signals, ACS signals, WL signals, TSG signals, BSG1 signals, and BSG2 signals, and then detects the BL signal. For example, to verify the unprogrammed state of the memory cells, the PW signal is set to a ground level as shown in 562. The BSG1 signal is set to a turn-on level for the first bottom select transistor, such as about 3V to 5V, as shown in 542; the BSG2 signal is set to a turn-on level for the second bottom select transistor, such as about 3V to 5V, as shown in 552; The TSG signal is set to a turn-on level for the top select transistor, such as about 3V to 5V, as shown in 522; and the WL signal is set to a level between a first threshold voltage (e.g., for an unprogrammed state) and a second threshold voltage (e.g., for a programmed state), such as about 3V to 5V, as shown in 532. The voltage level of the bit line (shown in 512) can be sensed and amplified. If the voltage level corresponds to logic "0", the memory cell is in an unprogrammed state and the erase operation is verified to be successful. If the voltage level corresponds to logic "1", the erase operation is not successfully performed and, for example, another erase operation may be performed.

[0082] Please note that in some examples, the memory cell string includes a dummy memory cell (DMY) that can be controlled similarly to the WL signal for the memory cell.

[0083] Please also note that in some examples, the memory cell string includes a number of top select transistors. In some embodiments, the TSG signal for controlling the top select transistor may be configured similarly to the BSG1 signal and the BSG2 signal, and thus the GIDL may be derived from the top select transistor closest to the memory cell.

[0084] The foregoing is a schematic description of the features of various embodiments to enable those skilled in the art to better understand aspects of the present disclosure. Those skilled in the art should recognize that the present disclosure can be readily used as a basis for designing or modifying other processes and structures to perform the same purpose and / or achieve the same benefits as the present disclosure set forth herein. Furthermore, those skilled in the art should recognize that such equivalent configurations do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the present disclosure.

Claims

Claim 1 A method for erasing operation in a memory device comprises: a step of applying a P-type well signal and a word line signal to a memory cell string, wherein the P-type well signal has an erasure voltage level for generating a first erasure carrier from a main body portion of the memory cell string during the erasure operation, and the first erasure carrier flows from the source side to the drain side of the memory cell string; and a step of applying a bit line signal to the memory cell string, wherein the voltage level of the bit line signal is greater than the first voltage level of a first select gate signal of the memory cell string during the same period, and the bit line signal has the erasure voltage level, and the step of applying the bit line signal to the memory cell string comprises: a step of applying the bit line signal to a bit line connected to the drain terminal of a first select transistor of the memory cell string; A method for erasing, comprising: a step of applying a first selection gate signal having a first voltage level to the gate terminal of the first selection transistor, wherein the first selection transistor is the closest select transistor to the drain side of the memory cell string, and the first selection gate signal has a first voltage level lower than the voltage level of the bit line signal; and a step of applying a second selection gate signal having a second voltage level to the gate terminal of the second selection transistor of the memory cell string, which is positioned next to the first selection transistor from the drain side of the memory cell string, wherein the second voltage level is lower than the first voltage level, thereby negatively biasing the gate terminal of the second selection transistor with respect to the drain terminal of the second selection transistor to generate a second erasure carrier. Claim 2 A method of erasure operation according to claim 1, wherein the step of applying the P-type well signal and the word line signal to the memory cell string comprises: applying the word line signal to the gate terminal of a memory cell of the memory cell string; and applying the P-type well signal, which is a positive voltage, to a P-type well corresponding to a main body portion of the memory cell string - wherein the positive voltage causes the first erasure carrier to flow in a first direction - and wherein the word line signal has a voltage level lower than a ground voltage level or a predefined threshold value, and the voltage level lower than the predefined threshold value is lower than the positive voltage level. Claim 3 A method of erasure operation according to claim 1, wherein the first erasure carrier and the second erasure carrier are provided in the same erasure cycle. Claim 4 A memory element comprising: a memory cell array comprising a memory cell string including at least memory cells connected in series in the memory cell string; and a peripheral circuit coupled to the memory cell array, wherein the peripheral circuit applies a P-type well signal and a word line signal to the memory cell string, wherein the P-type well signal has an erase voltage level for generating a first erase carrier from a main body portion of the memory cell string during an erase operation, and the first erase carrier flows from the source side to the drain side of the memory cell string. and configured to apply a bit line signal to the memory cell string, wherein the voltage level of the bit line signal is greater than the first voltage level of the first select gate signal of the memory cell string during the same period, and the bit line signal has the erase voltage level; applying the bit line signal to the memory cell string comprises applying the bit line signal to a bit line connected to the drain terminal of the first select transistor of the memory cell string; applying a first select gate signal having a first voltage level to the gate terminal of the first select transistor - wherein the first select transistor is the closest select transistor for the drain side of the memory cell string, and the first select gate signal has a first voltage level lower than the voltage level of the bit line signal -; A memory device comprising applying a second selection gate signal having a second voltage level to the gate terminal of a second selection transistor of the memory cell string, which is disposed next to the first selection transistor from the drain side of the memory cell string, wherein the second voltage level is lower than the first voltage level, thereby negatively biasing the gate terminal of the second selection transistor with respect to the drain terminal of the second selection transistor to generate a second erase carrier. Claim 5 In claim 4, the peripheral circuit is configured to apply the word line signal to the gate terminal of a memory cell of the memory cell string and to apply the P-type well signal, which is a positive voltage, to a P-type well corresponding to the main body portion of the memory cell string, wherein the positive voltage causes the first erase carrier to flow in a first direction, and the word line signal has a voltage level lower than a ground voltage level or a predefined threshold value, and the voltage level lower than the predefined threshold value is lower than the positive voltage level, a memory device. Claim 6 In paragraph 4, the memory element is configured such that the peripheral circuit provides the first erase carrier and the second erase carrier for the erase operation in the same erase cycle. Claim 7 delete Claim 8 delete Claim 9 delete Claim 10 delete Claim 11 delete Claim 12 delete Claim 13 delete Claim 14 delete Claim 15 delete Claim 16 delete Claim 17 delete Claim 18 delete Claim 19 delete Claim 20 delete

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