Low power intermediate pre-charge operations in memory

Abstract

A memory device, a circuit, and a method for operating the memory device are disclosed. In one embodiment, the memory device includes a memory cell coupled between a first bit line and a second bit line. The memory device includes a recording circuit configured to write data to the memory cell through the first bit line and the second bit line during a recording operation. The memory device includes a voltage equalization device configured to equalize the voltage of the first bit line and the second bit line after a recording operation for the memory cell and before a second memory operation.

Description

Technology Field

[0001] Cross-reference regarding related applications

[0002] This application claims the benefit and priority of U.S. Provisional Application No. 63 / 615,239 filed December 27, 2023, the contents of which are incorporated herein by reference in their entirety for all purposes. Background Technology

[0003] The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has resulted from iterative reductions in minimum feature sizes, which enable more components to be integrated within a given area. Prior art literature

[65535] Registered Patent Publication No. 10-2279046 (July 16, 2021) Brief explanation of the drawing

[0004] The aspects of the present disclosure are best understood from the following detailed description when read together with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not depicted to scale. In practice, the dimensions of various features may be increased or decreased at will for clarity of description. FIG. 1 illustrates a diagram of an exemplary memory circuit having a device that equalizes the bit line voltage during dual-pumping memory operation according to some embodiments. FIG. 2 illustrates a diagram showing an exemplary waveform of a signal that can be propagated through the memory circuit illustrated in FIG. 1 during dual pumping memory operation according to some embodiments. FIG. 3 illustrates a diagram of an exemplary memory circuit having two complementary devices that equalize the bit line voltage during dual-pumping memory operation, according to some embodiments. FIG. 4 illustrates a diagram of an exemplary memory circuit having a device for equalizing bit line voltages during dual-pumping memory operation and a voltage clamping device coupled to each bit line, according to some embodiments. FIG. 5 illustrates a diagram of an exemplary memory circuit similar to the memory circuit illustrated in FIG. 4, having a complementary device that equalizes the bit line voltage during memory operation, according to some embodiments. FIG. 6 illustrates a diagram of an exemplary memory circuit similar to the memory circuit illustrated in FIG. 4, having a voltage clamping device coupled to each bit line receiving a clamping voltage, according to some embodiments. FIG. 7 illustrates a diagram of an exemplary memory circuit similar to the memory circuit illustrated in FIG. 6, having a complementary device that equalizes the bit line voltage during memory operation, according to some embodiments. FIG. 8 illustrates a diagram of an exemplary memory circuit including an alternative configuration of a voltage clamping device according to some embodiments. FIG. 9 illustrates a diagram showing exemplary waveforms of a signal during different dual-pumping memory operations according to some embodiments. FIG. 10 illustrates a flowchart of an exemplary method for operating an exemplary memory circuit that implements voltage equalization for intermediate pre-charge during dual-pumping memory operation according to some embodiments. Specific details for implementing the invention

[0005] The disclosure below provides many different embodiments or examples for implementing various features of the invention provided. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to be limiting. For example, in the following detailed description, the formation of the first feature on the second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features so that the first and second features do not come into direct contact. Additionally, the disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplification and clarification and does not itself determine the relationship between the various embodiments and / or configurations discussed.

[0006] Additionally, spatial relative terms such as "bottom," "below," "lower," "top," "upper," "top," and "bottom" may be used herein for ease of explanation to describe the relationship of one element or feature to other element(s) or feature(s), as exemplified in the drawings. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the drawings. The device may be oriented differently (rotated 90 degrees or oriented in a different way), and the spatially relative terms used herein may likewise be interpreted accordingly.

[0007] Memory circuits, such as Dynamic Random-Access Memory (DRAM), can implement "double pumping" operations in which multiple memory operations are performed within a single clock cycle. For example, a read operation followed by a write operation, or a write operation followed by a read operation, can be performed within a single memory clock cycle rather than two clock cycles. In conventional memory systems, double pumping operations require the bit lines of the memory circuit to be pre-charged between operations. Pre-charging involves raising the voltage level of a selected bit line to nearly the supply voltage level. However, such a conventional approach results in excessive power consumption. As the density and performance requirements of semiconductor technology increase, double pumping using such an approach becomes technically unfeasible.

[0008] The present disclosure provides various techniques for implementing low-power intermediate pre-charging operations. Such techniques do not require that the voltage level of a selected bit line be pre-charged to nearly the supply voltage. Instead, the techniques described herein implement circuits that omit pre-charging of bit line pairs between a first memory operation and a second memory operation of a dual-pumping operation. To this end, the various circuits described herein equalize the voltage between bit line pairs during intermediate pre-charging to ensure a stable margin of memory cell operation. These techniques reduce the overall power consumption of the memory circuit, thereby enabling the implementation of higher-density memory circuits across smaller process nodes.

[0009] FIG. 1 illustrates a diagram of an exemplary memory circuit having a device that equalizes the bit line voltage during dual-pumping memory operation according to some embodiments. The memory circuit (100) may be included in any type of memory device or integrated circuit (IC) device. In at least one embodiment, the memory device is a separate IC device. In some embodiments, the memory device is included as part of a larger IC device that includes other circuit parts other than the memory device for other functions.

[0010] Each component shown in the memory circuit (100) can receive power from one or more voltage sources (e.g., supply voltage shown herein as VDD). The memory circuit (100) may include one or more logic gates and subcircuits, each of which may be composed of one or more logic gates. A logic gate is an electronic device that performs a logic operation on one or more input signals to generate a single output signal.

[0011] Various embodiments of the circuit and logic gate implementing the memory circuit (100) may include various transistors. The transistors described herein may have a specific type (N-type or P-type), but the embodiments are not limited thereto. The transistor may be any suitable type of transistor including, but not limited to, a metal oxide semiconductor field effect transistor (MOSFET), a complementary metal oxide semiconductor (CMOS) transistor, a P-channel metal-oxide semiconductor (PMOS), an N-channel metal-oxide semiconductor (NMOS), a bipolar junction transistor (BJT), a high-voltage transistor, a high-frequency transistor, a P-channel and / or N-channel field effect transistor (PFET / NFET), a FinFET, a planar MOS transistor with raised source / drain, a nanosheet FET, a nanowire FET, etc.

[0012] It should be understood that the memory circuit (100) illustrated in FIG. 1 may be part of a larger memory circuit comprising any number of bit line pairs (BL and BLB) that can be addressed by a corresponding memory cell selection circuit. Likewise, although not illustrated herein for visual clarity, various additional circuits may be included to address (e.g., select) various parts of the memory cell, or to perform different memory operations, including but not limited to, compute-in-memory (CIM) operations, write operations, or read operations.

[0013] The memory circuit (100) is illustrated as comprising at least one memory cell (112) positioned between a pair of bit lines (BL and BLB). The memory cell (112) may be any type of memory device capable of storing at least one bit of memory data, including, but not limited to, a static random access memory (SRAM) cell or a dynamic random access memory (DRAM) cell, among other things. The bit lines (BL and BLB) and the memory cell (112) between them may be included as part of a column of a memory array in some embodiments. In such embodiments, a plurality of memory cells (112) may be arranged in a plurality of rows and may be coupled to each of a pair of bit lines (BL and BLB). The memory array may include a plurality of columns, each column comprising a corresponding set of bit lines to which a plurality of memory cells (112) are coupled.

[0014] Individual memory cells (112) of a memory array may be addressed by accessing corresponding bit lines (BL and BLB) (selected by column) and / or corresponding word lines or source lines (selected by row). Addressed memory cells may be selected for write and / or read operations. The memory array may be implemented for dual pumping operations, in which multiple memory operations can be performed in a single memory clock cycle. Signals for selecting memory cells and coordinating read / write / double pumping operations may be provided by a memory control circuit. The memory control circuit may include any type of control circuit that provides signals for coordinating read or write operations through a circuit portion of the memory circuit (100). The memory control circuit may provide any signal described herein to control the function of the memory circuit (100).

[0015] The memory circuit (100) is illustrated as receiving a write clock (WCLK) signal. The WCLK signal is a timing signal that controls the timing of a write operation within the memory circuit (100). During a write operation, the WCLK signal ensures that data is synchronized with other signals and processes within the memory circuit (100) and written to the memory cell at the correct time. As illustrated, the WCLK signal is provided to the inverter (102) as an input to generate a WCLKB signal. As used herein, the signal to which the term "B" is added is the logical inverse of the same signal without the "B" suffix. In situations where the corresponding signal without the "B" suffix does not exist or is not referenced, the "B" suffix may indicate that the corresponding signal is an active low signal (e.g., active when in a logical low, logical zero, or ground state).

[0016] As illustrated, the memory circuit (100) comprises seven transistors (M1, M2, M3, M4, M5, M6, and M7), each of which implements a portion of the circuit to perform a low-power dual-pumping operation. Each of the transistors (M1 to M7) in FIG. 1 is illustrated as a single transistor, but embodiments are not limited thereto. For example, each transistor may include a plurality of transistors ("sub-transistor(s)") connected in parallel with one another. For example, in an embodiment, each sub-transistor of any transistor described herein may include its own gate, drain, and source terminals, which may each be connected in parallel with one another.

[0017] The circuit (100) includes transistors (M1, M2, M3, M4, M5, M6, and M7). In some embodiments, transistors (M1, M2, M3, M4, and M5) each include a pMOSFET, and transistors (M6 and M7) each include an nMOSFET. It is recognized that each of transistors (M1 to M7) may include any various other types of transistors (e.g., bipolar junction transistors, high-electron-mobility transistors, etc.) while remaining within the scope of the present disclosure. As illustrated, the sources of transistors (M1, M2, M4, and M5) are electrically coupled to the supply voltage (VDD), and the sources of transistors (M6 and M7) are connected to the ground voltage. The drain terminals of transistors (M4 and M5) are each coupled to the drain terminals of transistors (M6 and M7). The drain terminals of transistors (M4 and M6) are connected to the first bit line (BL), and the drain terminals of transistors (M5 and M7) are connected to the second bit line (BLB). The drain terminals of transistors (M1 and M2) are connected to the bit lines (BL and BLB), respectively.

[0018] Transistors (M1, M2) are activated during a pre-charge operation to set the voltage level of bit lines (BL, BLB) to nearly the supply voltage (VDD). As illustrated, the gate terminals of transistors (M1 and M2) are coupled to receive an active-low bit line pre-charge signal (BLPREB). When the BLPREB signal is logic high (e.g., logic 1, supply voltage near VDD, etc.), each of transistors (M1 and M2) is turned off and conduction ceases. The voltage of bit lines (BL and BLB) in such a state is therefore set according to other circuit elements (e.g., transistors (M4 and M6), transistors (M5 and M7), etc.).

[0019] When the BLPREB signal is logic low (e.g., logic 0, nearly equal to ground voltage, etc.), each of the transistors (M1 and M2) is turned on and begins to conduct. When transistor (M1) is turned on and conducts, the voltage on the first bit line (BL) is set to nearly the supply voltage (VDD). When transistor (M2) is turned on and conducts, the voltage on the second bit line (BLB) is set to nearly the supply voltage (VDD). As described in relation to FIG. 2, the BLPREB signal may be maintained in a logic low state (e.g., by a memory control circuit) until the bit line is sufficiently pre-charged (e.g., after a predetermined amount of time). The pre-charge operation may be performed prior to a read and / or write operation, including prior to a double pumping operation.

[0020] Prior to the read operation, the bit lines (BL and BLB) are pre-charged to a reference voltage. This prepares the bit lines for detecting and amplifying voltage changes induced by the memory cell during the read operation. Likewise, prior to the write operation, the bit lines are pre-charged to a reference voltage level. This ensures a well-defined starting point for the voltage difference to be induced during the subsequent write operation. However, during the double pumping operation, the transistor (M3) may be activated as part of an intermediate pre-charge instead of a full pre-charge to equalize the voltages of the first bit line and the second bit line.

[0021] The transistor (M3) has a first source / drain terminal coupled to a first bit line (BL) and a second source / drain terminal coupled to a second bit line (BLB). In this example, the transistor (M3) may have a gate terminal that receives a bit line voltage equalization signal (illustrated as active low), denoted as BLEQB. As described in relation to FIG. 2, the equalization voltage at which the first bit line (BL) and the second bit line (BLB) are set may be less than the supply voltage (VDD) but greater than the ground voltage for the memory circuit. The transistor (M3) is in parallel with the memory cell (112) as illustrated. In this example, the source / drain terminal of the transistor (M3) is also coupled to the corresponding source / drain terminals of the transistors (M1 and M2), respectively. It should be understood that while the transistor (M3) is illustrated as a p-type device, any suitable transistor device including but not limited to an n-type device may be utilized.

[0022] The first bit line and the second bit line (BL and BLB) are each illustrated as including a recording circuit. The first recording circuit includes a NAND gate (104), a NOR gate (108), a transistor (M4), and a transistor (M6). The gate terminal of the transistor (M4) is coupled to the output of the NAND gate (104), and the gate terminal of the transistor (M6) is coupled to the output of the NOR gate (108). The NAND gate (104) receives an input data signal (DATA) as an input and receives a recording clock signal (WCLK) as an input. The NOR gate (108) receives an input data signal (DATA) as an input and receives a logic inversion (WCLKB) of the recording clock signal as an input. As described herein, the logic inversion (WCLKB) of the recording clock signal can be generated as an output by an inverter (102).

[0023] The input data signal (DATA) may be a logic high signal or a logic low signal indicating a bit to be written to the memory cell (112). For example, in some embodiments, the input data signal (DATA) may be a logic high signal to indicate that a logic binary value "1" will be written to the memory cell (112), and the input data signal (DATA) may be a logic low signal to indicate that a logic binary value "0" will be written to the memory cell (112), or vice versa. In some embodiments, the memory circuit (100) may include one or more inverters to generate a logic inversion of the data signal (DATAB).

[0024] When the write clock signal (WCLK) is in a logic low state (e.g., ground state, logic 0 state, etc.), a read operation for the memory cell (112) is indicated. During the read operation, since the WCLK signal is logic low, the output of the NAND gate (104) is always logic high regardless of the input data signal (DATA). Accordingly, the gate terminal of the p-type transistor (M4) is provided with a logic high signal during the read operation, which causes the transistor (M4) to turn off and not conduct. Likewise, when the WCLK signal is logic low, the logic inverse of the write signal (WLKB) is logic high. When the WCLKB signal is logic high (e.g., logic 1, near supply voltage (VDD)), the output of the NOR gate (108) is always logic low regardless of the input data signal (DATA). As the output of the NOR gate (108) is provided to the gate terminal of the n-type transistor (M6), the transistor (M6) is turned off and does not conduct during the read operation.

[0025] A second recording circuit for a second complementary bit line (BLB) includes a NAND gate (106), a NOR gate (110), a transistor (M5), and a transistor (M7). The gate terminal of the p-type transistor (M5) is coupled to the output of the NAND gate (106), and the gate terminal of the n-type transistor (M7) is coupled to the output of the NOR gate (110). The NAND gate (106) receives an input data signal (DATA) as an input and receives a recording clock signal (WCLK) as an input. The NOR gate (110) receives an input data signal (DATA) as an input and receives a logic inversion (WCLKB) of the recording clock signal as an input.

[0026] As described in this specification, during a read operation, the write clock signal (WCLK) is in a logic low state (e.g., ground state, logic 0 state, etc.). When the WCLK signal is logic low, the output of the NAND gate (106) is always logic high regardless of the input data signal (DATA). Accordingly, the gate terminal of the p-type transistor (M5) is provided with a logic high signal during the read operation, which causes the transistor (M5) to turn off and not conduct. Likewise, when the WCLK signal is logic low, the logic inverse of the write signal (WLKB) is logic high. When the WCLKB signal is logic high (e.g., logic 1, near supply voltage (VDD)), the output of the NOR gate (110) is always logic low regardless of the input data signal (DATA). As the output of the NOR gate (110) is provided to the gate terminal of the n-type transistor (M7), the transistor (M7) is turned off and not conduct during the read operation.

[0027] Accordingly, the first and second recording circuits do not substantially change the voltage of the bit lines (BL and BLB) during the read operation. Instead, the memory cell (112) itself, coupled between the bit lines (BL and BLB), generates a voltage difference between the bit lines (BL and BLB) depending on its state. For example, if the memory cell (112) stores a charge (e.g., representing logic 1), the memory cell (112) may cause one of the bit lines (BL or BLB) to discharge, thereby causing a voltage drop between the bit lines (BL and BLB). In this example, if the memory cell (112) does not store a charge (e.g., representing logic 0), the bit lines (BL and BLB) will maintain their pre-charged voltage levels. A differential sensing circuit can compare the voltages of the bit lines (BL and BLB) to determine the logic state of the memory cell (112) during the read operation. The difference in voltage levels can be amplified and used to generate an output signal that displays stored data (e.g., logic 0 or logic 1).

[0028] During the write operation, the WCLK signal may be in a logic high state, and its logic inversion WCLKB may be in a logic low state. The input data signal (DATA) may be in a logic low state indicating that a logic 0 should be written to the memory cell (112), or in a logic high state indicating that a logic 1 should be written to the memory cell (112). During the write operation, when the data signal is in a logic high state, the NAND gate receives two logic high signals (from WCLK and DATA) and generates a logic low output at the gate terminal of the transistor (M4). The logic low signal at the gate terminal of the p-type transistor (M4) causes the transistor (M4) to turn on and conduct. Going further in this example, the NOR gate (108) receives one logic high signal (DATA) and one logic low signal (WCLKB). Accordingly, the output of the NOR gate (108) is a logic low signal, which causes the n-type transistor (M6) to turn off and not conduct. When the transistor (M4) is turned on and conducts, the supply voltage (VDD) is subsequently coupled to the bit line (BL), causing the voltage of the bit line (BL) to rise to almost the supply voltage (VDD).

[0029] Going further to the example where the input data signal (DATA) is in a logic high state during the write operation, the NAND gate (106) receives one logic high signal (WCLK) and one logic low signal (DATAB, the inversion of DATA). Accordingly, the output of the NAND gate (106) provided to the gate terminal of transistor (M5) is in a logic high state, which causes transistor (M5) to turn off and not conduct. The NOR gate (110) receives two logic low signals (both DATAB and WCLKB), which causes the NOR gate (110) to generate a logic high output and provide it to the gate terminal of transistor (M7). The logic high at the gate terminal of transistor (M7) substantially connects the second bit line (BLB) to ground (e.g., by setting it to nearly 0), causing transistor (M7) to turn on and conduct. Accordingly, during the operation to write logical data to the memory cell (112), the bit line (BL) can be set to the supply voltage and the complementary bit line (BLB) can be set to the ground voltage.

[0030] The inversion of the above example may occur when the input data signal (DATA) to be written to the memory cell (112) is logic 0. For example, when DATA is in a logic low state during the write operation, the output of the NAND gate (104) is logic high, which turns off the transistor (M4) and prevents it from conducting, and the output of the NOR gate (108) is also logic high, which turns on the transistor (M6) and prevents it from conducting, thereby drawing the voltage of the bit line (BL) to nearly ground voltage. Similarly, when DATA is in a logic low state during the write operation, the output of the NAND gate (106) is logic low, which turns on the transistor (M4) and prevents it from conducting, and the output of the NOR gate (110) is logic low, which turns off the transistor (M7) and prevents it from conducting, thereby drawing the voltage of the complementary bit line (BLB) to nearly supply voltage. Accordingly, during the operation to write a logic 0 to the memory cell (112), the bit line (BL) can be set to a near-ground voltage and the complementary bit line (BLB) can be set to a near-supply voltage. The voltage difference between BL and BLB causes the memory cell (112) to store data in the input data signal (DATA).

[0031] FIG. 2 illustrates a diagram (200) illustrating an exemplary waveform of a signal that can be propagated through the memory circuit illustrated in FIG. 1 during a double-pumping memory operation according to some embodiments. The exemplary waveform illustrated in the diagram (200) represents a double-pumping operation that may occur during a single memory clock cycle in some embodiments. The double-pumping operation includes a read operation during a time interval (202), a voltage equalization during a time interval (204), and a write operation during a time interval (206) following the voltage equalization.

[0032] In this example, the double pumping operation is initialized by pre-charging the bit lines (e.g., BL and BLB) of the memory cell prior to the operation by setting the active-low pre-charge signal (BLPREB) to logic 0 prior to the time interval (202). This ensures that both bit lines (BL and BLB) are approximately equal to the supply voltage (VDD) as illustrated. During the read operation, the word line (WL) select signal for the corresponding memory cell (e.g., memory cell (112)) is logic high, which causes the memory cell to be selected for the read operation. At the same time, the active-low pre-charge signal (BLPREB) transitions to a logic high state to disable the pre-charge operation. The active-low voltage equalization signal (BLEQB) is also driven to a logic high state, which disables voltage equalization between the bit lines (BL and BLB).

[0033] Since the first operation is a read operation, the logic inversion (WCLKB) of the write clock is maintained in a logic high state, which indicates a read operation. During the time interval (202), as illustrated, the voltage of the bit lines (BL and BLB) diverges slightly as the memory cell discharges, which indicates that the memory cell has stored a logic 1. As described herein, the voltage of the bit lines during the read operation is not modified after the pre-charge operation, which allows any charge stored in the memory cell to modify the voltage difference across the bit lines (BL and BLB). The voltage difference between the bit lines (BL and BLB) can be amplified to detect data stored in the memory cell.

[0034] After the read operation, the word line select signal (WL) can be returned to a logic low state, and the active-low pre-charge signal (BLPREB) and the logic inversion of the write clock (WCLKB) remain in a logic high state. However, instead of performing a second pre-charge operation, the active-low voltage equalization signal (BLEQB) is drawn out to a logic low state. As illustrated, during the dual pump equalization time interval (204), a voltage equalization device (e.g., transistor (M3)) makes the voltage between the bit lines (BL and BLB) nearly equal at a voltage level (Vequ). As illustrated, the voltage level (Vequ) is smaller than the supply voltage (VDD) and larger than the ground voltage.

[0035] When the voltage is equalized during the time interval (204), the write operation is performed as a second operation in the double pumping operation. As illustrated, during the time interval (206), the word line (WL) select signal for the corresponding memory cell (e.g., memory cell (112)) is set to logic high, which causes the memory cell to be selected for the write operation. At the same time, the active-low voltage equalization signal (BLEQB) is transitioned to a logic high state that disables voltage equalization. The active-low pre-charge signal (BLPREB) is maintained in a logic high state. During the time interval (206) of the write operation, the logic inversion of the write clock (WCLKB) is transitioned to a logic low state that indicates the write operation.

[0036] As illustrated, the bit lines (BL and BLB) are voltage-divided, one of the bit lines is transitioned to the near supply voltage (VDD), and the other complementary bit line is transitioned to the near ground voltage during the duration (206) of the write operation. When the write operation is completed following the time interval (206), pre-charging for the next operation may be initiated by transitioning the inversion of the write clock (WCLKB) to a logic high state and transitioning the word line (WL), BLEQB, and BLPREB to a logic low state. This causes all bit lines of the memory cell to be set to the near supply voltage for the next set of operations, as illustrated. A similar waveform is provided for the dual pumping operation starting with the write operation in FIG. 9.

[0037] Referring to FIG. 9, a diagram (900) illustrating an exemplary waveform of a signal during another double-pumping memory operation according to some embodiments is illustrated. The exemplary waveform illustrated in the diagram (900) represents a double-pumping operation that may occur during a single memory clock cycle in some embodiments. The double-pumping operation includes a write operation during a time interval (902), a voltage equalization during a time interval (904), and a read operation during a time interval (906) following the voltage equalization.

[0038] In this example, the double pumping operation is initialized by pre-charging the bit lines (e.g., BL and BLB) of the memory cell prior to the operation by setting the active-low pre-charge signal (BLPREB) to logic 0 prior to the time interval (902). This ensures that both bit lines (BL and BLB) are approximately equal to the supply voltage (VDD) as illustrated. During the first write operation, the word line (WL) select signal for the corresponding memory cell (e.g., memory cell (112)) is set to logic high, which causes the memory cell to be selected for the write operation. At the same time, the active-low pre-charge signal (BLPREB) is transitioned to a logic high state to disable the pre-charge operation. The active-low voltage equalization signal (BLEQB) is also driven to a logic high state, which disables voltage equalization between the bit lines (BL and BLB).

[0039] Since the first operation is a write operation, the logic inversion (WCLKB) of the write clock is set to a logic low state, which indicates a write operation. During the time interval (902), as illustrated, the voltage of the bit line is branched to VDD and ground (e.g., based on the state of the input data signal), which causes the input data to be written to the memory cell. As described herein, one of the bit lines (BL and BLB) is set to logic high and the other is set to logic low, causing the circuit component of the memory cell (e.g., a capacitor) to be charged or discharged to store data.

[0040] After the write operation, the word line select signal (WL) can be returned to a logic low state, the active-low pre-charge signal (BLPREB) is maintained in a logic high state, and the logic inversion of the write clock (WCLKB) is driven to a logic high state. However, instead of performing a second pre-charge operation, the active-low voltage equalization signal (BLEQB) is drawn out to a logic low state. As illustrated, during the dual pump equalization time interval (904), a voltage equalization device (e.g., transistor (M3)) is set so that the voltage between the bit lines (BL and BLB) is nearly equal to the voltage level (Vequ). As illustrated, the voltage level (Vequ) is smaller than the supply voltage (VDD) and larger than the ground voltage.

[0041] When the voltage is equalized during the time interval (904), the read operation is performed as a second operation in the double pumping operation. As illustrated, during the time interval (906), the word line (WL) select signal for the corresponding memory cell (e.g., memory cell (112)) is set to logic high, which causes the memory cell to be selected for the read operation. At the same time, the active-low voltage equalization signal (BLEQB) is transitioned to a logic high state that disables voltage equalization. The active-low pre-charge signal (BLPREB) is maintained in a logic high state. During the time interval (906) for the read operation, the logic inversion of the write clock (WCLKB) is maintained in a logic high state that indicates the write operation.

[0042] As illustrated, the bit lines (BL and BLB) diverge slightly as the memory cell discharges, indicating that the memory cell has stored a logic 1. As described herein, the voltage of the bit lines during the read operation is not modified after the pre-charge operation, allowing any charge stored in the memory cell to modify the voltage difference across the bit lines (BL and BLB). The voltage difference between the bit lines (BL and BLB) can be amplified to detect the data stored in the memory cell. When the read operation is completed following the time interval (906), pre-charging for the next operation may be initiated by transitioning the word line (WL), BLEQB, and BLPREB to a logic low state while keeping the inversion of the write clock (WCLKB) in a logic high state. This causes all bit lines of the memory cell to be set to nearly the supply voltage for the next set of operations, as illustrated. Various configurations for a memory circuit capable of implementing the waveforms illustrated in FIGS. 2 and FIGS. 9 are described in relation to FIGS. 3 through 8.

[0043] FIG. 3 illustrates a diagram of an exemplary memory circuit (300) having two complementary devices that equalize the bit line voltage during dual-pumping memory operation according to some embodiments. The memory circuit (300) may be similar to the memory circuit (100) illustrated in FIG. 1, while including an additional complementary transistor (C10). As illustrated, the memory circuit (300) includes transistors (M8, M9, M10, C10, M11, M12, M13, and M14). The memory circuit (300) includes NAND gates (304 and 306) and NOR gates (308 and 310). In some embodiments, the transistors (M8, M9, M10, M11, and M12) each include a pMOSFET, and the transistors (C10, M13, and M14) each include an nMOSFET. It is recognized that each of the transistors (C10 and M7 to M14) may include any various other types of transistors (e.g., bipolar junction transistors, high-electron-mobility transistors, etc.) while remaining within the scope of the present disclosure.

[0044] Various embodiments of the circuit and logic gate implementing the memory circuit (300) may include various transistors. The transistors described herein may have a specific type (N-type or P-type), but the embodiments are not limited thereto. The transistor may be any suitable type of transistor including, but not limited to, MOSFETs, CMOS transistors, PMOS, NMOS, BJTs, high-voltage transistors, high-frequency transistors, PFETs / NFETs, FinFETs, planar MOS transistors with raised source / drain, nanosheet FETs, nanowire FETs, etc.

[0045] It should be understood that the memory circuit (300) illustrated in FIG. 3 may be part of a larger memory circuit comprising any number of bit line pairs (BL and BLB) that can be addressed by a corresponding memory cell selection circuit. Likewise, although not illustrated herein for visual clarity, various additional circuits may be included to address (e.g., select) various parts of the memory cell, or to perform different memory operations, including, but not limited to, CIM operations, write operations, or read operations.

[0046] As described, each of the transistors (M8, M9, M10, M11, M12, M13, and M14) may be similar to the transistors (M1, M2, M3, M4, M5, M6, and M7) described in relation to FIG. 1 and may include any of their structures and functions. Likewise, various logic components such as memory cell (312), inverter (302), NAND gate (304), NAND gate (306), NOR gate (308), and NOR gate (310) may be similar to the memory cell (112), inverter (102), NAND gate (104), NAND gate (106), NOR gate (108), and NOR gate (110) of FIG. 1 and may incorporate any of their corresponding structures and functions.

[0047] For example, the inverter (302), NAND gates (304 and 306), NOR gates (308 and 310), and transistors (M11, M12, M13 and M14) can receive data input signals (DATA) and write clock signals (WCLK and WLKB) as described in relation to FIG. 1 and write data to the memory cell (312) through bit lines (BL and BLB). Likewise, each of the transistors (M8 and M9) can receive a bit line pre-charge signal (BLPREB) to pre-charge each bit line during a double-pumping memory operation (e.g., a write followed by a read or a read followed by a write during a single clock cycle).

[0048] Additionally, the transistor (M10) may be similar to the transistor (M3) of FIG. 1 and may receive an active-low bit line voltage equalization signal (BLEQB) at its gate terminal. Additionally, the memory circuit (300) may include a second inverter (303) capable of generating an active-high counterpart to BLEQB, which is illustrated herein as BLEQ. As illustrated, the memory circuit (300) includes an additional complementary transistor (C10) in parallel with the transistor (M10). The complementary transistor (C10) is illustrated as being an n-type transistor having a first source / drain terminal coupled to a first bit line (BL) and a second source / drain terminal coupled to a second bit line (BLB). The gate terminal of the complementary transistor (C10) receives the active-high voltage equalization signal (BLEQ). The use of complementary transistors (M10 and C10) allows additional current to flow through the circuit and provides increased driving strength compared to a single transistor, reducing voltage stress compared to a single transistor approach.

[0049] FIG. 4 illustrates a diagram of an exemplary memory circuit (400) having a device for equalizing bit line voltages during dual-pumping memory operation and a voltage clamping device coupled to each bit line, according to some embodiments. The memory circuit (400) may be similar to the memory circuit (100) illustrated in FIG. 1, while including voltage clamping circuits (412 and 414). As illustrated, the memory circuit (400) includes transistors (M15, M16, M17, M18, M19, M20, and M21). A first voltage clamping circuit (412) operating as a diode clamping device coupled to a bit line (BL) includes transistors (D1 and D2). A second voltage clamping circuit (414) operating as a diode clamping device coupled to a bit line (BLB) includes transistors (D3 and D4).

[0050] The memory circuit (400) includes NAND gates (404 and 406) and NOR gates (408 and 410). In some embodiments, transistors (M15, M16, M17, M18, M19, D1, D2, D3, and D4) each include a pMOSFET, and transistors (M20 and M21) each include an nMOSFET. It is recognized that each of the transistors (M15 to M21 and D1 to D4) may include any various other types of transistors (e.g., bipolar junction transistors, high-electron-mobility transistors, etc.) while remaining within the scope of the present disclosure. Various embodiments of the circuit and logic gates implementing the memory circuit (400) may include various transistors. The transistors described herein may have a specific type (N-type or P-type), but the embodiments are not limited thereto. The transistor may be any suitable type of transistor including, but not limited to, MOSFETs, CMOS transistors, PMOS, NMOS, BJTs, high-voltage transistors, high-frequency transistors, PFETs / NFETs, FinFETs, planar MOS transistors with raised source / drain, nanosheet FETs, nanowire FETs, etc.

[0051] It should be understood that the memory circuit (400) illustrated in FIG. 4 may be part of a larger memory circuit comprising any number of bit line pairs (BL and BLB) that can be addressed by a corresponding memory cell selection circuit. Likewise, although not illustrated herein for visual clarity, various additional circuits may be included to address (e.g., select) various parts of the memory cell, or to perform different memory operations, including but not limited to CIM operations, write operations, or read operations, among others.

[0052] As described, each of the transistors (M15, M16, M17, M18, M19, M20, and M21) may be similar to the transistors (M1, M2, M3, M4, M5, M6, and M7) described in relation to FIG. 1 and may include any of their structures and functions. Likewise, various logic components such as memory cell (416), inverter (402), NAND gate (404), NAND gate (406), NOR gate (408), and NOR gate (410) may be similar to the memory cell (112), inverter (102), NAND gate (104), NAND gate (106), NOR gate (108), and NOR gate (110) of FIG. 1 and may incorporate any of their corresponding structures and functions.

[0053] For example, the inverter (402), NAND gates (404 and 406), NOR gates (408 and 410), and transistors (M18, M19, M20 and M21) can receive data input signals (DATA) and write clock signals (WCLK and WLKB) as described in relation to FIG. 1 and write data to the memory cell (416) via bit lines (BL and BLB). Likewise, each of the transistors (M15 and M16) can receive a bit line pre-charge signal (BLPREB) to pre-charge their respective bit lines during a dual-pumping memory operation (e.g., a write followed by a read or a read followed by a write during a single clock cycle). The transistor (M17) can be similar to the transistor (M3) of FIG. 1 and can receive an active-low bit line voltage equalization signal (BLEQB) at its gate terminal.

[0054] As illustrated, the memory circuit (400) includes a first voltage clamping circuit (412) and a second voltage clamping circuit (414) which can be activated during a non-write operation when the WCLK signal is in a logic low state. As illustrated, the first voltage clamping circuit (412) includes transistors (D1) and (D2). The first source / drain terminal of transistor (D1) is coupled to the supply voltage (VDD), and the second source / drain terminal of transistor (D1) is coupled to the first source / drain terminal of transistor (D2). The second source / drain terminal of transistor (D2) is coupled to the bit line (BL). The gate terminal of transistor (D1) is coupled to the source / drain terminals of transistors (D1 and D2) in a diode configuration as illustrated.

[0055] In this configuration, the transistor (D1) forms a PMOS diode-connected transistor and behaves as a diode-type circuit element. The gate terminal of the transistor (D2) is connected to a write clock signal (WCLK). Accordingly, when the memory circuit performs a write operation, the WCLK signal is in a logic high state and the transistor (D2) is turned off and not conducted. This prevents the first voltage clamping circuit (412) from being activated or affecting the voltage of the bit line (BL).

[0056] The memory circuit (400) includes a second voltage clamping circuit (414), which is illustrated as including transistors (D3) and (D4). The first source / drain terminal of transistor (D3) is coupled to the supply voltage (VDD), and the second source / drain terminal of transistor (D3) is coupled to the first source / drain terminal of transistor (D4). The second source / drain terminal of transistor (D4) is coupled to the bit line (BLB). The gate terminal of transistor (D3) is coupled to the source / drain terminals of transistors (D3 and D4) in a diode configuration as illustrated.

[0057] In this configuration, the transistor (D3) forms a PMOS diode-connected transistor and behaves as a diode-type circuit element. The gate terminal of the transistor (D4) is connected to the write clock signal (WCLK). Accordingly, when the memory circuit performs a write operation, the WCLK signal is in a logic high state and the transistor (D4) is turned off and not conducted. This prevents the second voltage clamping circuit (414) from being activated or affecting the voltage of the bit line (BLB).

[0058] When the WCLK signal is in a logic low state, during a non-write operation, transistors (D2) and (D4) are turned on and conducted. This substantially clamps the minimum voltage of the bit lines (BL and BLB) to the value of the supply voltage - threshold voltage of transistors (D1 and D3) + voltage drop across each of transistors (D2 and D4). Clamping the voltage drop during a read operation can improve the overall read performance of the device and facilitate an appropriate equalization voltage (Vequ) between the bit lines (BL and BLB) for dual-pumping memory operation.

[0059] FIG. 5 illustrates a diagram of an exemplary memory circuit (500) similar to the memory circuit (400) illustrated in FIG. 4, having a complementary device that equalizes the bit line voltage during memory operation, according to some embodiments. The memory circuit (500) may be similar to the memory circuit (100) illustrated in FIG. 1, but includes voltage clamping circuits (512, 514) similar to the voltage clamping circuits (412 and 414) described in relation to FIG. 4, respectively. As illustrated, the memory circuit (500) includes transistors (M22, M23, M24, C24, M25, M26, M27, and M28). A first voltage clamping circuit (512), which operates as a diode clamping device coupled to the bit line (BL), includes transistors (D5 and D6). A second voltage clamping circuit (514) operating as a diode clamping device coupled to a bit line (BLB) includes transistors (D7 and D8).

[0060] The memory circuit (500) includes NAND gates (504 and 506) and NOR gates (508 and 510). In some embodiments, transistors (M22, M23, M24, M25, M26, D5, D6, D7 and D8) each include a pMOSFET, and transistors (C24, M27 and M28) each include an nMOSFET. It is recognized that each of the transistors (C24 and M22 through M28) may include any various other types of transistors (e.g., bipolar junction transistors, high-electron-mobility transistors, etc.) while remaining within the scope of the present disclosure. Various embodiments of the circuit and logic gates implementing the memory circuit (500) may include various transistors. The transistors described herein may have a specific type (N-type or P-type), but the embodiments are not limited thereto. The transistor may be any suitable type of transistor including, but not limited to, MOSFETs, CMOS transistors, PMOS, NMOS, BJTs, high-voltage transistors, high-frequency transistors, PFETs / NFETs, FinFETs, planar MOS transistors with raised source / drain, nanosheet FETs, nanowire FETs, etc.

[0061] It should be understood that the memory circuit (500) illustrated in FIG. 5 may be part of a larger memory circuit comprising any number of bit line pairs (BL and BLB) that can be addressed by a corresponding memory cell selection circuit. Likewise, although not illustrated herein for visual clarity, various additional circuits may be included to address (e.g., select) various parts of the memory cell, or to perform different memory operations, including but not limited to, CIM operations, write operations, or read operations.

[0062] As described, each of the transistors (M22, M23, M24, C24, M25, M26, M27, and M28) may be similar to the transistors (M8, M9, M10, C10, M11, M12, M13, and M14) described in relation to FIG. 3 and may include any of their structures and functions. Likewise, various logic components such as memory cell (516), inverter (502), second inverter (503), NAND gate (504), NAND gate (506), NOR gate (508), and NOR gate (510) may be similar to the memory cell (312), inverter (302), second inverter (303), NAND gate (304), NAND gate (306), NOR gate (308), and NOR gate (310) of FIG. 3 and may incorporate any of their corresponding structures and functions.

[0063] For example, the inverter (502), NAND gates (504 and 506), NOR gates (508 and 510), and transistors (M25, M26, M27 and M28) can receive data input signals (DATA) and write clock signals (WCLK and WLKB) as described in relation to FIGS. 1 and 3, and write data to the memory cell (516) via bit lines (BL and BLB). Likewise, each of the transistors (M22 and M23) can receive a bit line pre-charge signal (BLPREB) to pre-charge their respective bit lines during a dual-pumping memory operation (e.g., a write followed by a read or a read followed by a write during a single clock cycle). The transistor (M24) may be similar to the transistor (M3) of FIG. 1 and can receive an active-low bit line voltage equalization signal (BLEQB) at its gate terminal.

[0064] Each of the voltage clamping circuits (512 and 514) and the transistors (D5, D6, D7 and D8) contained therein may be similar to the voltage clamping circuits (412 and 414) and transistors (D1, D2, D3 and D4) of FIG. 4 and may include any of the structures and functions thereof. As described herein, the voltage clamping circuits (512 and 514) may each clamp the minimum voltage of the bit lines (BL and BLB) by the supply voltage - the value of the threshold voltage of the transistors (D5 and D6), and the voltage drop across the transistors (D7 and D8) for each bit line (BL and BLB). Clamping the voltage drop during a read operation can improve the overall read performance of the device and facilitate an appropriate equalization voltage (Vequ) between the bit lines (BL and BLB) for dual-pumping memory operation.

[0065] As illustrated, the memory circuit (500) includes an additional complementary transistor (C24) in parallel with the transistor (M24). The complementary transistor (C24) is illustrated as being an n-type transistor having a first source / drain terminal coupled to a first bit line (BL) and a second source / drain terminal coupled to a second bit line (BLB). The gate terminal of the complementary transistor (C24) receives an active-high voltage equalization signal (BLEQ). The use of the complementary transistors (M24 and C24) allows additional current to flow through the circuit and provides increased driving strength compared to a single transistor, which reduces voltage stress compared to a single transistor approach.

[0066] FIG. 6 illustrates a diagram of an exemplary memory circuit (600) similar to the memory circuit (400) illustrated in FIG. 4, having a voltage clamping device coupled to each bit line receiving a clamping voltage according to some embodiments. The memory circuit (600) may be similar to the memory circuit (100) illustrated in FIG. 1, while including voltage clamping circuits (612 and 614). As illustrated, the memory circuit (600) includes transistors (M29, M30, M31, M32, M33, M34, and M35). A first voltage clamping circuit (612) operating as a configurable clamping device coupled to a bit line (BL) includes transistors (D9 and D10). A second voltage clamping circuit (614) operating as a configurable clamping device coupled to a bit line (BLB) includes transistors (D11 and D12).

[0067] The memory circuit (600) includes NAND gates (604 and 606) and NOR gates (608 and 610). In some embodiments, transistors (M29, M30, M31, M32, M33, D10 and D12) each include a pMOSFET, and transistors (D9, D11, M34 and M35) each include an nMOSFET. It is recognized that each of the transistors (M29 to M35 and D9 to D12) may include any various other types of transistors (e.g., bipolar junction transistors, high-electron-mobility transistors, etc.) while remaining within the scope of the present disclosure. Various embodiments of the circuit and logic gates implementing the memory circuit (600) may include various transistors. The transistors described herein may have a specific type (N-type or P-type), but the embodiments are not limited thereto. The transistor may be any suitable type of transistor including, but not limited to, MOSFETs, CMOS transistors, PMOS, NMOS, BJTs, high-voltage transistors, high-frequency transistors, PFETs / NFETs, FinFETs, planar MOS transistors with raised source / drain, nanosheet FETs, nanowire FETs, etc.

[0068] It should be understood that the memory circuit (600) illustrated in FIG. 6 may be part of a larger memory circuit comprising any number of bit line pairs (BL and BLB) that can be addressed by a corresponding memory cell selection circuit. Likewise, although not illustrated herein for visual clarity, various additional circuits may be included to address (e.g., select) various parts of the memory cell, or to perform different memory operations, including but not limited to, CIM operations, write operations, or read operations.

[0069] As illustrated, the memory circuit (600) includes a first voltage clamping circuit (612) and a second voltage clamping circuit (614) which can be activated during a non-write operation when the WCLK signal is in a logic low state. As illustrated, the first voltage clamping circuit (612) includes a transistor (D9) and a transistor (D10). The first source / drain terminal of the transistor (D9) is coupled to the supply voltage (VDD), and the second source / drain terminal of the transistor (D9) is coupled to the first source / drain terminal of the transistor (D10). The second source / drain terminal of the transistor (D10) is coupled to the bit line (BL). The gate terminal of the transistor (D9) receives a voltage clamp control signal (Vclamp) as illustrated.

[0070] In this configuration, the transistor (D9) forms a configurable resistor or current source, which can operate in the resistive or linear region by varying the voltage (Vclamp). The gate terminal of the transistor (D10) is connected to the write clock signal (WCLK). Accordingly, when the memory circuit performs a write operation, the WCLK signal is in a logic high state and the transistor (D10) is turned off and not conducted. This prevents the first voltage clamping circuit (612) from being activated or affecting the voltage of the bit line (BL). During the write operation, the voltage (Vclamp) can be set to turn off the transistors (D9 and D11).

[0071] The memory circuit (600) includes a second voltage clamping circuit (614), which is illustrated as including a transistor (D11) and a transistor (D12). A first source / drain terminal of transistor (D11) is coupled to a supply voltage (VDD), and a second source / drain terminal of transistor (D11) is coupled to a first source / drain terminal of transistor (D12). A second source / drain terminal of transistor (D12) is coupled to a bit line (BLB). Similar to the gate terminal of transistor (D9), the gate terminal of transistor (D11) receives a voltage clamp control signal (Vclamp), as illustrated.

[0072] In this configuration, the transistor (D11) forms a configurable resistor or current source, which can operate in the resistive or linear region by varying the voltage (Vclamp). The gate terminal of the transistor (D12) is connected to the write clock signal (WCLK). Accordingly, when the memory circuit performs a write operation, the WCLK signal is in a logic high state, and the transistor (D12) is turned off and not conducted. This prevents the second voltage clamping circuit (614) from being activated or affecting the voltage of the bit line (BLB).

[0073] When the WCLK signal is in a logic low state, during a non-write operation, transistors (D10) and (D12) are turned on and conducted according to their respective electrical characteristics, voltages in bit lines (BL and BLB), and configuration voltage signal (Vclamp). The first voltage clamping circuit (612) and the second voltage clamping circuit (614) substantially clamp the minimum voltage of the bit lines (BL and BLB) by the voltage drop across transistors (D9 and D10) and the voltage drop across transistors (D11, D12), respectively. Clamping the voltage drop during a read operation can improve the overall read performance of the device and facilitate an appropriate equalization voltage (Vequ) between the bit lines (BL and BLB) for dual-pumping memory operation. A settable voltage signal (Vclamp) can be provided by one or more control circuits and can be varied to achieve a desired minimum voltage at each of the bit lines (BL and BLB).

[0074] FIG. 7 illustrates a diagram of an exemplary memory circuit (700) similar to the memory circuit illustrated in FIG. 6, having a complementary device that equalizes the bit line voltage during memory operation, according to some embodiments. The memory circuit (700) may be similar to the memory circuit (100) illustrated in FIG. 1, but includes voltage clamping circuits (712, 714) similar to the voltage clamping circuits (612 and 614) described in relation to FIG. 6, respectively. As illustrated, the memory circuit (700) includes transistors (M36, M37, M38, C38, M39, M40, M41, and M42). A first voltage clamping circuit (712), which operates as a configurable voltage clamping device coupled to the bit line (BL), includes transistors (D13 and D14). A second voltage clamping circuit (714) operating as a configurable clamping device coupled to a bit line (BLB) includes transistors (D15 and D16).

[0075] The memory circuit (700) includes NAND gates (704 and 706) and NOR gates (708 and 710). In some embodiments, transistors (M36, M37, M38, C38, M39, M40, D14 and D16) each include a pMOSFET, and transistors (C24, M41, M42, D13 and M15) each include an nMOSFET. It is recognized that each of the transistors (C38, M36 to M42, and D13 to D16) may include any various other types of transistors (e.g., bipolar junction transistors, high-electron-mobility transistors, etc.) while remaining within the scope of the present disclosure. Various embodiments of the circuit and logic gates implementing the memory circuit (700) may include various transistors. The transistors described herein may have a specific type (N-type or P-type), but the embodiments are not limited thereto. The transistor may be any suitable type of transistor including, but not limited to, MOSFETs, CMOS transistors, PMOS, NMOS, BJTs, high-voltage transistors, high-frequency transistors, PFETs / NFETs, FinFETs, planar MOS transistors with raised source / drain, nanosheet FETs, nanowire FETs, etc.

[0076] It should be understood that the memory circuit (700) illustrated in FIG. 7 may be part of a larger memory circuit comprising any number of bit line pairs (BL and BLB) that can be addressed by a corresponding memory cell selection circuit. Likewise, although not illustrated herein for visual clarity, various additional circuits may be included to address (e.g., select) various parts of the memory cell, or to perform different memory operations, including, but not limited to, CIM operations, write operations, or read operations.

[0077] As described, each of the transistors (M36, M37, M38, C38, M39, M40, M41, and M42) may be similar to the transistors (M8, M9, M10, C10, M11, M12, M13, and M14) described in relation to FIG. 3 and may include any of their structures and functions. Likewise, various logic components such as the memory cell (716), inverter (702), second inverter (703), NAND gate (704), NAND gate (706), NOR gate (708), and NOR gate (710) may be similar to the memory cell (312), inverter (302), second inverter (303), NAND gate (304), NAND gate (306), NOR gate (308), and NOR gate (310) of FIG. 3 and may incorporate any of their corresponding structures and functions.

[0078] For example, the inverter (702), NAND gates (704 and 706), NOR gates (708 and 710), and transistors (M39, M40, M41 and M42) can receive data input signals (DATA) and write clock signals (WCLK and WLKB) as described in relation to FIGS. 1 and 3, and write data to the memory cell (716) via bit lines (BL and BLB). Likewise, each of the transistors (M36 and M37) can receive a bit line pre-charge signal (BLPREB) to pre-charge their respective bit lines during a dual-pumping memory operation (e.g., a write followed by a read or a read followed by a write during a single clock cycle). The transistor (M38) may be similar to the transistor (M3) of FIG. 1 and can receive an active-low bit line voltage equalization signal (BLEQB) at its gate terminal.

[0079] Each of the voltage clamping circuits (712 and 714) and the transistors (D13, D14, D15 and D16) contained therein may be similar to the voltage clamping circuits (612 and 614) and transistors (D9, D10, D11 and D12) of FIG. 6 and may include any of the structures and functions thereof. As described herein, the voltage clamping circuits (712, 714) may clamp the minimum voltage of the bit lines (BL and BLB) respectively, with a configurable value according to the configuration voltage (Vclamp) applied to the gate terminals of each of the transistors (D13, D15). During a write operation, the voltage (Vclamp) may be set to turn off the transistors (D13 and D15). Clamping the voltage drop during a read operation can improve the overall read performance of the device and facilitate an appropriate equalization voltage (Vequ) between bit lines (BL and BLB) for dual-pumping memory operation.

[0080] Clamping the voltage drop during a read operation can improve the overall read performance of the device and facilitate an appropriate equalization voltage (Vequ) between bit lines (BL and BLB) for dual-pumping memory operation. The complementary transistor (C38) is shown as an n-type transistor having a first source / drain terminal coupled to the first bit line (BL) and a second source / drain terminal coupled to the second bit line (BLB). The gate terminal of the complementary transistor (C38) receives an active-high voltage equalization signal (BLEQ). The use of the complementary transistors (M38 and C38) allows additional current to flow through the circuit and provides increased driving strength compared to a single transistor, which reduces voltage stress compared to a single transistor approach.

[0081] FIG. 8 illustrates a diagram of an exemplary memory circuit (800) including an alternative configuration of a voltage clamping device according to some embodiments. The memory circuit (800) may be similar to the memory circuit (100) illustrated in FIG. 1, but includes voltage clamping circuits (812 and 814) similar to the voltage clamping circuits (612 and 614) described in relation to FIG. 6, respectively. As illustrated, the memory circuit (800) includes transistors (M43, M44, M45, M46, M47, M48 and M49). A first voltage clamping circuit (812) operating as a configurable voltage clamping device coupled to a bit line (BL) includes transistors (D17 and D18). A second voltage clamping device (814) operating as a configurable clamping device coupled to a bit line (BLB) includes transistors (D19 and D20).

[0082] The memory circuit (800) includes NAND gates (804 and 806) and NOR gates (808 and 810). In some embodiments, transistors (M43, M44, M45, M46, M47, D17 and D19) each include a pMOSFET, and transistors (M48, M49, D18 and M20) each include an nMOSFET. It is recognized that each of the transistors (M43 to M49, and D17 to D20) may include any various other types of transistors (e.g., bipolar junction transistors, high-electron-mobility transistors, etc.) while remaining within the scope of the present disclosure. Various embodiments of the circuit and logic gates implementing the memory circuit (800) may include various transistors. The transistors described herein may have a specific type (N-type or P-type), but the embodiments are not limited thereto. The transistor may be any suitable type of transistor including, but not limited to, MOSFETs, CMOS transistors, PMOS, NMOS, BJTs, high-voltage transistors, high-frequency transistors, PFETs / NFETs, FinFETs, planar MOS transistors with raised source / drain, nanosheet FETs, nanowire FETs, etc.

[0083] It should be understood that the memory circuit (800) illustrated in FIG. 8 may be part of a larger memory circuit comprising any number of bit line pairs (BL and BLB) that can be addressed by a corresponding memory cell selection circuit. Likewise, although not illustrated herein for visual clarity, various additional circuits may be included to address (e.g., select) various parts of the memory cell, or to perform different memory operations, including but not limited to, CIM operations, write operations, or read operations.

[0084] As described, each of the transistors (M43, M44, M45, M46, M47, M48, and M49) may be similar to the transistors (M1, M2, M3, M4, M5, M6, and M7) described in relation to FIG. 1 and may include any of their structures and functions. Likewise, various logic components such as memory cell (816), inverter (802), NAND gate (804), NAND gate (806), NOR gate (808), and NOR gate (810) may be similar to the memory cell (112), inverter (102), NAND gate (104), NAND gate (106), NOR gate (108), and NOR gate (110) of FIG. 1 and may incorporate any of their corresponding structures and functions.

[0085] For example, the inverter (802), NAND gates (804 and 806), NOR gates (808 and 810), and transistors (M46, M47, M48, and M49) can receive data input signals (DATA) and write clock signals (WCLK and WLKB) as described in relation to FIG. 1 and write data to the memory cell (816) via bit lines (BL and BLB). Likewise, each of the transistors (M43 and M44) can receive a bit line pre-charge signal (BLPREB) to pre-charge their respective bit lines during a double-pumping memory operation (e.g., a write followed by a read or a read followed by a write during a single clock cycle). The transistor (M45) may be similar to the transistor (M3) of FIG. 1 and can receive an active-low bit line voltage equalization signal (BLEQB) at its gate terminal.

[0086] Each of the voltage clamping circuits (812 and 814) and the transistors (D13, D14, D15 and D16) contained therein may be similar to the voltage clamping circuits (612 and 614) and transistors (D17, D18, D19 and D20) of FIG. 6 and may include any of the structures and functions thereof. As described herein, the voltage clamping circuits (812 and 814) may clamp the minimum voltage of the bit lines (BL and BLB) respectively, with a configurable value according to the configuration voltage (Vclamp) applied to the gate terminals of each of the transistors (D17 and D19). During a write operation, the voltage (Vclamp) may be set to turn off the transistors (D17 and D19).

[0087] In the embodiment illustrated in FIG. 8, the voltage clamping circuits (812 and 814) are positioned on the "far side" of the BL circuit portion, for example, over one or more memory cells (816) coupled between bit lines (BL and BLB). For example, the voltage clamping circuits (812 and 814) may be coupled at opposite ends of the bit lines (BL and BLB) for the write circuit and pre-charge, as below the memory cell (816) within the memory circuit (800). In some embodiments, the memory circuit (800) may include a complementary n-type device in parallel with the transistor (M45), as described herein in relation to FIG. 5 and 7.

[0088] FIG. 10 illustrates a flowchart of an exemplary method (1000) for operating an exemplary memory circuit that implements voltage equalization for intermediate pre-charge during dual-pumping memory operation according to some embodiments. The method (1000) may be used to operate a memory circuit (e.g., memory circuits (100, 300, 400, 500, 600, 700, 800, etc.). For example, at least some of the operations described in the method (700) use the layouts and schematic diagrams described in FIG. 1 and FIG. 3 through 8. It should be noted that the method (1000) is merely an example and is not intended to limit the present disclosure. Accordingly, it is understood that additional operations may be provided before, during, and after the method (1000) of FIG. 10, and that some other operations may be described here only briefly.

[0089] In a brief overview, the method (1000) begins with an operation (1002) of pre-charging a first bit line and a second bit line coupled to a memory cell. The method (1000) proceeds to an operation (1004) of performing a first operation on the memory cell. The method (1000) proceeds to an operation (1006) of equalizing the voltage of the first bit line and the second bit line of the memory cell after the first memory operation and before the second memory operation. Following the equalization of the voltage of the first bit line and the second bit line, the method (1000) proceeds to an operation (1008) of performing a second memory operation on the memory cell.

[0090] Referring to operation (1002), a first bit line (e.g., BL) and a second bit line (e.g., BLB) coupled to a memory cell (e.g., memory cell (112)) are precharged. For example, a memory controller may use a control signal (e.g., BLPREB) to activate one or more precharge devices (e.g., turn on transistors (M1 and M2)) to set the voltage of the bit lines to nearly the supply voltage (e.g., VDD). The precharge operation may precede a dual-pumping memory operation that includes multiple memory operations in a single memory clock cycle (e.g., a write followed by a read, a read followed by a write, etc.). The precharge operation may be performed before the first operation.

[0091] Referring to operation (1004), a first memory operation (e.g., read, write) is performed on the memory cell. The first memory operation may be a write operation or a read operation. In the read operation, the voltage of the pre-charged bit line is not changed or modified; instead, a change in voltage caused by the memory cell that affects the voltage difference between the bit lines is detected as a logical value stored in the memory cell. In the write operation, the voltage across the bit line is set so that input data (e.g., a logical high bit value or a logical low bit value) is written to the memory cell. An additional circuit (e.g., a control circuit) may provide a signal to selectively enable the memory cell for memory operations.

[0092] Referring to operation (1006), the voltage across the bit line is equalized in an intermediate pre-charge operation after the first memory operation and before the second memory operation. As described herein, the dual-pumping memory operation includes multiple memory operations in a single clock cycle. To reduce overall dynamic power consumption, instead of pre-charging the bit line of the memory cell again before the memory operation, the voltage of the bit line can be set to be equal to each other using a voltage equalization device (e.g., transistor (M3), complementary transistors (M10 and C10), etc.). A control signal (e.g., BLEQB) may be provided to enable the voltage equalization device. The voltage at which the bit line is set (e.g., Vequ) may be less than the supply voltage but greater than the ground voltage.

[0093] Referring to operation (1008), the second operation may be performed on the memory cell following voltage equalization of the voltage between the first bit line and the second bit line. The second memory operation may be a read operation or a write operation and may be performed by providing a control signal (e.g., WCLK) corresponding to the memory cell. In some embodiments, the second memory operation may be different from the first memory operation. The second memory operation may be performed in the same clock cycle as the first memory operation, following an intermediate pre-charge operation.

[0094] In one aspect of the present disclosure, a memory device is disclosed. The memory device includes a memory cell coupled between a first bit line and a second bit line. The memory device includes a recording circuit configured to write data to the memory cell through the first bit line and the second bit line during a recording operation. The memory device includes a voltage equalization device configured to equalize the voltage of the first bit line and the second bit line after a recording operation for the memory cell and before a second memory operation.

[0095] In another aspect of the present disclosure, a circuit is disclosed. The circuit includes a first bit line and a second bit line coupled to a memory cell. The circuit includes a first transistor in parallel with the memory cell. A first source / drain terminal of the first transistor is coupled to the first bit line. A second source / drain terminal of the first transistor is coupled to the second bit line. The gate terminal of the first transistor receives a voltage equalization signal.

[0096] In another aspect of the present disclosure, a method is disclosed. The method comprises the step of pre-charging a first bit line and a second bit line coupled to a memory cell. The method comprises the step of performing a first memory operation for the memory cell. The method comprises the step of equalizing the voltage of the first bit line and the second bit line of the memory cell after the first memory operation and before the second memory operation. The method comprises the step of performing a second memory operation for the memory cell after equalizing the voltage of the first bit line and the second bit line.

[0097] When used herein, the terms “about” and “approximately” generally mean plus or minus 10% of the specified value. For example, about 0.5 will include 0.45 to 0.55, about 10 will include 9 to 11, and about 1000 will include 900 to 1100.

[0098] The foregoing describes the features of various embodiments to enable those skilled in the art to better understand aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to perform and / or perform the same purposes as the embodiments introduced herein, or to achieve the same advantages. Those skilled in the art should also understand that such equivalent configurations do not depart from the true meaning and scope of the present disclosure, and that various modifications, substitutions, and alternatives can be made without departing from the true meaning and scope of the present disclosure.

[0099] Examples

[0100] Example 1. In a memory device,

[0101] A memory cell combined between the first bit line and the second bit line;

[0102] A recording circuit configured to record data in the memory cell through the first bit line and the second bit line during a recording operation; and

[0103] A voltage equalization device configured to equalize the voltages of the first bit line and the second bit line after the write operation and before the read operation for the memory cell.

[0104] A memory device including

[0105] Example 2. The memory device of Example 1, wherein the voltage equalization device is also configured to set the voltage of the first bit line and the second bit line to a voltage lower than the supply voltage.

[0106] Example 3. A memory device in which, in Example 1, the voltage equalization device equalizes the voltages of the first bit line and the second bit line during a dual pump operation.

[0107] Example 4. A memory device according to Example 1, wherein the recording circuit comprises at least one NOR gate and at least one NAND gate.

[0108] Example 5. A memory device according to Example 1, wherein the voltage equalization device comprises at least one p-type device.

[0109] Example 6. A memory device according to Example 5, wherein the voltage equalization device further comprises at least one n-type device coupled in parallel to at least one p-type device.

[0110] Example 7. A memory device according to Example 1, further comprising at least one pre-charge device coupled to the first bit line and the second bit line.

[0111] Example 8. A memory device in which, in Example 7, at least one pre-charge device is coupled to the voltage equalization device.

[0112] Example 9. In Example 1,

[0113] At least one voltage clamping device coupled to the first bit line or the second bit line

[0114] A memory device that further includes

[0115] Example 10. A memory device according to Example 9, wherein the at least one voltage clamping device is also configured to clamp the voltage of the first bit line or the second bit line according to a control signal.

[0116] Example 11. In a memory circuit,

[0117] A first bit line and a second bit line coupled to a memory cell; and

[0118] A first transistor in parallel with the memory cell - the first source / drain terminal of the first transistor is coupled to the first bit line, the second source / drain terminal of the first transistor is coupled to the second bit line, and the gate terminal of the first transistor, upon receiving a voltage equalization signal, is configured to equalize the voltages of the first bit line and the second bit line between memory operations.

[0119] A memory circuit including

[0120] Example 12. In Example 11,

[0121] 2nd transistor and 3rd transistor

[0122] Includes more,

[0123] A memory circuit in which the second transistor is coupled to the supply voltage and the first bit line, the third transistor is coupled to the supply voltage and the second bit line, and each of the second transistor and the third transistor receives a pre-charge signal.

[0124] Example 13. In Example 11,

[0125] A memory circuit further comprising a second transistor in parallel with the first transistor.

[0126] Example 14. A memory circuit in which, in Example 11, the first transistor is a p-type transistor.

[0127] Example 15. In Example 11,

[0128] 2nd transistor and 3rd transistor

[0129] A memory circuit comprising, wherein the first source / drain terminal of the second transistor is coupled to a supply voltage, the second source / drain terminal of the second transistor is coupled to the first source / drain terminal of the third transistor, and the second source / drain terminal of the third transistor is coupled to the first bit line or the second bit line.

[0130] Example 16. A memory circuit in Example 15, wherein the gate terminal of the second transistor is coupled to the second source / drain terminal of the second transistor.

[0131] Example 17. A memory circuit according to Example 15, wherein the gate terminal of the second transistor receives a voltage clamp control signal.

[0132] Example 18. In the method,

[0133] A step of pre-charging a first bit line and a second bit line coupled to a memory cell;

[0134] A step of performing a first memory operation for the above memory cell;

[0135] A step of equalizing the voltage of the first bit line and the second bit line of the memory cell after the first memory operation and before the second memory operation; and

[0136] Step of performing a second memory operation for the memory cell following the equalization of the voltages of the first bit line and the second bit line.

[0137] A method including

[0138] Example 19. The method of Example 18, wherein the voltages of the 1-bit line and the 2-bit line are equalized to a voltage lower than the supply voltage.

[0139] Example 20. Method of Example 18, wherein the 1 memory operation is a read operation and the 2 memory operation is a write operation.

Claims

Claim 1 A memory device comprising: a memory cell coupled between a first bit line and a second bit line; a recording circuit configured to write data to the memory cell through the first bit line and the second bit line during a recording operation; and a voltage equalization device configured to equalize the voltage of the first bit line and the second bit line after the recording operation and before a reading operation for the memory cell, wherein the first bit line and the second bit line are not pre-charged after the recording operation and before the reading operation. Claim 2 A memory device according to claim 1, wherein the voltage equalization device is also configured to set the voltages of the first bit line and the second bit line to a voltage lower than the supply voltage. Claim 3 A memory device according to claim 1, wherein the voltage equalization device equalizes the voltages of the first bit line and the second bit line during a dual pump operation. Claim 4 A memory device according to claim 1, wherein the recording circuit comprises at least one NOR gate and at least one NAND gate. Claim 5 A memory device according to claim 1, wherein the voltage equalization device comprises at least one p-type device. Claim 6 A memory device according to claim 1, further comprising at least one pre-charge device coupled to the first bit line and the second bit line. Claim 7 A memory device according to claim 1, further comprising at least one voltage clamping device coupled to the first bit line or the second bit line. Claim 8 A memory circuit comprising: a first bit line and a second bit line coupled to a memory cell; and a first transistor in parallel with the memory cell, wherein the first source / drain terminal of the first transistor is coupled to the first bit line and the second source / drain terminal of the first transistor is coupled to the second bit line, and the gate terminal of the first transistor, upon receiving a voltage equalization signal, is configured to equalize the voltages of the first bit line and the second bit line between memory operations, wherein the first bit line and the second bit line are not pre-charged between memory operations. Claim 9 A memory circuit according to claim 8, further comprising a second transistor and a third transistor, wherein the second transistor is coupled to a supply voltage and the first bit line, the third transistor is coupled to the supply voltage and the second bit line, and each of the second transistor and the third transistor receives a pre-charge signal. Claim 10 A method of operating a memory device comprising: a step of pre-charging a first bit line and a second bit line coupled to a memory cell; a step of performing a first memory operation for the memory cell; a step of equalizing the voltage of the first bit line and the second bit line of the memory cell after the first memory operation and before the second memory operation, wherein the first bit line and the second bit line are not pre-charged after the first memory operation and before the second memory operation; and a step of performing the second memory operation for the memory cell following the equalization of the voltage of the first bit line and the second bit line.

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