Semiconductor device and method of making the same

Abstract

The semiconductor device comprises a silicon carbide (SiC) epitaxial substrate (2), two well regions (W), a junction field-effect transistor region (Jfet), two source regions (S), two low-concentration doping regions (3), two high-concentration doping regions (HW), a gate terminal (G), and a drain terminal (D). The well regions (W) are spaced apart from each other, extend downward from the top surface of the SiC epitaxial substrate (2), and are doped with a second type dopant. The junction field-effect transistor region (Jfet) extends downward between the well regions (W) without contacting the well regions (W) and is doped with a first type dopant. The source regions (S) are located within the two well regions (W). The two low-concentration doping regions (3) are each positioned side-by-side with the source regions (S) and each have a first low-concentration doping layer (31) and a second low-concentration doping layer (32). High-concentration doping regions (HW) are located below source regions (S). A gate terminal (G) is located between two source regions (S). Additionally, a method for manufacturing a semiconductor device is included.

Description

Technology Field

[0001] The present disclosure relates to a semiconductor device, and more specifically, to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] Silicon carbide (SiC) has many advantages, such as resistance to high pressure and high temperature, and is currently widely used in electronic components that require such characteristics.

[0003] Conventionally, in order to reduce power consumption by lowering the drain-source on-resistance (Rdson) of SiC planar metal oxide semiconductor field-effect transistors (MOSFETs), the cell pitch of SiC planar MOSFETs had to be reduced. However, reducing the cell pitch can cause various technical bottlenecks (e.g., misalignment or limitations on the metal filling capacity of the source contact pads), and the electrical characteristics of the SiC planar MOSFET may be affected and deviate from standard electrical characteristics. For example, U.S. Patent No. 10,096,680 B2 discloses a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device.

[0004] More specifically, the cell pitch of a SiC planar MOSFET can be reduced by narrowing the width of the junction field-effect transistor (JFET) region. However, doing so shortens the channel length, and due to the short channel effect, the channel threshold voltage (Vth) becomes unstable and the electric field increases, which can induce hot carrier injection. This can affect the reliability of the SiC planar MOSFET. Additionally, reducing the width of the JFET region increases the electrical resistance of the JFET region, resulting in an increase in Rdson. To prevent an increase in RJEFT caused by the reduction in the width of the JFET region of the SiC planar MOSFET, the JFET region is doped with a higher doping concentration (higher concentration doping) (JF injection) to offset the increase in resistance of the JFET region. However, due to bottlenecks in current process technology, the JFET region will partially overlap with the well region when manufacturing conventional semiconductor devices, and the highly doped JFET region will lower the doping concentration of the well region, thereby lowering the threshold voltage (Vth) of the semiconductor device. If the threshold voltage (Vth) is too low, conventional semiconductor devices are susceptible to signal noise. Prior art literature

[0005] U.S. Patent No. 10,096,680 B2 The problem to be solved

[0006] Accordingly, the object of the present disclosure is to provide a semiconductor device and a method for manufacturing the same that can mitigate at least one of the disadvantages of the prior art. means of solving the problem

[0007] According to a first aspect of the present disclosure, a semiconductor device comprises a silicon carbide (SiC) epitaxial substrate, two well regions, a junction field-effect transistor region, two source regions, two low-concentration doping regions, two high-concentration doping regions, a gate terminal, and a drain terminal. The SiC epitaxial substrate has a top surface and a bottom surface opposite to the top surface. The two well regions are spaced apart from each other, and each well region extends downward from the top surface of the SiC epitaxial substrate and is doped with a second type dopant. The junction field-effect transistor region extends downward from the top surface of the SiC epitaxial substrate, is located between the two well regions, and is doped with a first type dopant. The two source regions each extend downward from the top surface of the SiC epitaxial substrate and are located within the two well regions. Two low-concentration doping regions are each disposed within the well regions, and each low-concentration doping region has a first low-concentration doping layer extending downward from the top surface of the SiC epitaxial substrate and positioned parallel to the upper edge of a corresponding boundary edge of the source regions, and a second low-concentration doping layer extending downward from the first low-concentration doping layer and positioned parallel to the lower edge of a corresponding boundary edge of the source regions, and extending further downward to be located below a corresponding source region. The first low-concentration doping layer is doped with a first type dopant. The second low-concentration doping layer is doped with a second type dopant and has a width greater than the width of the first low-concentration doping layer. Two high-concentration doping regions are each formed below a corresponding source region without extending beyond the bottom surface of a corresponding well region. A gate terminal is located on the top surface of the SiC epitaxial substrate between the two source regions. The gate terminal has two opposite transverse ends that overlap with the source regions. The drain terminal is located on the bottom surface of the SiC epitaxial substrate.

[0008] According to a second aspect of the present disclosure, a semiconductor device comprises a SiC epitaxial substrate, two well regions, a junction field-effect transistor region, and two source regions. The SiC epitaxial substrate comprises a top surface and a bottom surface opposite to the top surface. The two well regions are spaced apart from each other, and each well region extends downward from the top surface of the SiC epitaxial substrate and is doped with a second type dopant. The junction field-effect transistor region extends downward from the top surface of the SiC epitaxial substrate, is located between the two well regions, and is doped with a first type dopant. The junction field-effect transistor region has a transverse width smaller than the distance between the two well regions, so that the junction field-effect transistor region does not contact the two well regions. The two source regions each extend downward from the top surface of the SiC epitaxial substrate and are located within the two well regions. A gate terminal is located on the top surface of the SiC epitaxial substrate between the two source regions. The gate terminal has two opposite transverse ends that overlap with the source regions. A drain terminal is located on the bottom surface of the SiC epitaxial substrate.

[0009] According to another aspect of the present disclosure, a method for making a semiconductor device comprises: A) forming a first hard mask unit on the top surface of a silicon carbide (SiC) epitaxial substrate, wherein the first hard mask unit has a first hard mask layer, a second hard mask layer, and a third hard mask layer sequentially stacked upward from the top surface of the SiC epitaxial substrate; B) etching the first hard mask unit from the third hard mask layer to the first hard mask layer through a photolithography process to form at least two first openings spaced apart from each other; C) doping the SiC epitaxial substrate by ion implantation through the first openings to each form a plurality of well regions spaced apart from each other and doped with a second type dopant; and D) forming a first mask film on the first hard mask unit, wherein the first mask film is etched to cover the third hard mask layer and the first openings, and then from each of the third hard mask layer and the first openings The remaining thickness portions of the first mask film are removed, and the remaining portions of the first mask film remain on the boundaries of the first openings to form the second openings, each of which has a size smaller than the size of each of the first openings - and, E) a step of forming a first low-concentration doping layer by performing a first ion implantation through each of the second openings, and then forming a second low-concentration doping layer under the first low-concentration doping layer having a width wider than the width of the first low-concentration doping layer by performing a second ion implantation through each of the second openings - the first low-concentration doping layer is doped with a first type dopant, and the second low-concentration doping layer is doped with a second type dopant - and, F) a third hard mask layer, a first mask film, and a fourth hard mask layer covering the first hard mask layer exposed from the second openings, and a second mask film covering the fourth hard mask layer, and then,A step of removing portions of a second mask film positionally corresponding to the third hard mask layer and the second openings—wherein portions of the remaining thickness of the second mask film remain on the boundaries of the second openings to form third openings, each of which has a diameter smaller than the diameter of each of the second openings—and G) a step of performing ion implantation through the third openings to form a plurality of source regions—wherein the plurality of source regions are doped with a first type dopant and have a doping concentration greater than the doping concentrations of the first low-concentration doping layer and the second low-concentration doping layer, and each source region extends downward from the top surface through the first low-concentration doping layer to the second low-concentration doping layer. Brief explanation of the drawing

[0010] Other features and advantages of the present disclosure will become apparent from the following detailed description of the embodiment(s) with reference to the accompanying drawings. It should be noted that various features may not be drawn to scale. FIG. 1 is a schematic cross-sectional view illustrating a first embodiment of a semiconductor device of the present disclosure. FIG. 2 is a schematic cross-sectional flowchart illustrating steps A) to C) of a second embodiment, which is a method for manufacturing a semiconductor device. FIG. 3 is a schematic cross-sectional flowchart illustrating steps D) to E) of the second embodiment. FIG. 4 is a schematic cross-sectional flowchart illustrating steps F) to G) of the second embodiment. FIG. 5 is a schematic cross-sectional flowchart illustrating steps H) to I) of the second embodiment. FIG. 6 is a schematic cross-sectional flowchart illustrating steps J) to K) of the second embodiment. Specific details for implementing the invention

[0011] Before describing the present disclosure in more detail, it should be noted that reference numbers or the ends of reference numbers are repeated between the drawings to indicate corresponding or similar elements that may optionally have similar characteristics, where deemed appropriate.

[0012] For clarity of explanation, it should be noted that spatially relative terms such as “top,” “bottom,” “upper,” “lower,” “on,” “on top,” “above,” “up,” “downward,” “upward,” etc. may be used throughout this disclosure while referring to the features illustrated in the drawings. Features may be oriented differently (e.g., rotated 90 degrees or in a different direction), and spatially relative terms used in this specification may be interpreted accordingly.

[0013] Referring to FIG. 1, a first embodiment of a semiconductor device according to the present disclosure comprises a silicon carbide (SiC) epitaxial substrate (2), two well regions (W), and a junction field-effect transistor region (J fet It includes two source regions (S), two low-concentration doping regions (3), two high-concentration doping regions (HW), a gate terminal (G), a drain terminal (D), an insulating layer (4), a conductive unit (5), a protective unit (6), and an electrical connection unit (7).

[0014] The SiC epitaxial substrate (2) is doped with a first type dopant and has a SiC substrate material (21), a SiC epitaxial film (22), an upper surface (23), and a lower surface (24) opposite the upper surface (23). It should be noted that the first type dopant used to dope the SiC epitaxial substrate (2) has first type conductivity, and the second type dopant has second type conductivity opposite to first type conductivity. For example, the first type dopant may be an N-type dopant and the second type dopant may be a P-type dopant. In another example, the first type dopant may be a P-type dopant and the second type dopant may be an N-type dopant. In this embodiment, the semiconductor device is a planar metal oxide semiconductor (MOS), the first type dopant is an N-type dopant, the N-type dopant may be nitrogen (N) or phosphorus (P), and the P-type dopant may be aluminum (Al).

[0015] Two well regions (W) are spaced apart from each other and each extend downward from the top surface (23) of the SiC epitaxial substrate (2) and are located within the SiC epitaxial film (22). In this embodiment, the two well regions (W) are each doped with a second type dopant (P-type dopant).

[0016] Junction field-effect transistor region (J fet ) extends downward from the top surface (23) of the SiC epitaxial substrate (2) and is located between two well regions (W). In this embodiment, the junction field-effect transistor region (J fet ) is located between the two well regions (W) without contacting the two well regions (W). The junction field-effect transistor region (J fet ) has a lateral width smaller than the distance between the two well regions (W), so the junction field-effect transistor region (J fet ) does not come into contact with the two well regions (W). In this embodiment, the junction field-effect transistor region (J fet ) is doped with a type 1 dopant (type N dopant).

[0017] Two source regions (S) extend downward from the top surface (23) of the SiC epitaxial substrate (2) and are each located within two well regions (W).

[0018] Two low-concentration doping regions (3) are each disposed within a well region (W), and each low-concentration doping region (3) has a first low-concentration doping layer (31) that extends downward from the top surface (23) of the SiC epitaxial substrate (2) and is disposed parallel to the upper boundary edge of the corresponding source region (S), and a second low-concentration doping layer (32) that extends downward from the first low-concentration doping layer (31), is disposed parallel to the lower boundary edge of the corresponding source region (S), and extends further downward to be located below the corresponding source region (S). Each source region (S) has a bottom end at a depth between the depth of the bottom end of the first low-concentration doping layer (31) and the depth of the bottom end of the second low-concentration doping layer (32).

[0019] In this embodiment, the first low-concentration doping layer (31) is doped with a first type dopant (N-type dopant), and the second low-concentration doping layer (32) is doped with a second type dopant (P-type dopant). The second low-concentration doping layer (32) has a width greater than the width of the first low-concentration doping layer (31). More specifically, the width between the edge of the first low-concentration doping layer (31) and the edge of each source region (S) is defined as a channel. The second low-concentration doping layer (32) is located below the first low-concentration doping layer (31), and the horizontal distance from the edge of the second low-concentration doping layer (32) to the edge of each well region (W) is shorter than the horizontal distance from the edge of the first low-concentration doping layer (31) to the edge of each well region (W). Accordingly, the edge of the second low-concentration doping layer (32) of each low-concentration doping region (3) is closer to the edge of each well region (W) than the edge of the first low-concentration doping layer (31) of the low-concentration doping region (3), and the second low-concentration doping layer (32) has a width greater than that of the first low-concentration doping layer (31). The second low-concentration doping layer (32) has a doping concentration lower than the doping concentration of the well region (W).

[0020] Two high-concentration doping regions (HW) are formed below the corresponding source region (S) without extending beyond the bottom surface of the corresponding well region (W). The second low-concentration doping layer (32) of each low-concentration doping region (3) extends downward from the bottom of the corresponding source region (S) and is positioned parallel to the boundary wall of the high-concentration doping region (HW). The two high-concentration doping regions (HW) are doped with the same type of dopant as the well region (W). Additionally, the high-concentration doping region (HW) has a higher doping concentration than the doping concentration of the well region (W).

[0021] The gate terminal (G) is located on the top surface (23) of the SiC epitaxial substrate (2) between the two source regions (S). The gate terminal (G) has two transverse ends that overlap with the source regions (S).

[0022] The insulating layer comprises a first insulating layer (41) composed of an oxide material and covering the top surface (23) of a SiC epitaxial substrate (2), and a second insulating layer (42) located on the first insulating layer (41), composed of a dielectric insulating material, and covering a gate terminal (G). The gate terminal (G) is located on the first insulating layer (41).

[0023] The conduction unit (5) has an ohmic contact layer (51) electrically connected to a source region (S) and a source electrode (52) electrically connected to the ohmic contact layer (51).

[0024] The protection unit (6) is made of insulating material, is positioned on the second insulating layer (42), and covers the source electrode (52).

[0025] The connection unit (7) has a plurality of conductive structures (71) that penetrate the protection unit (6) and electrically connect the gate terminal (G) and the source electrode (52), and an electric conductor (72) for external electrical connection. The electric conductor (72) is electrically connected to the conductive structures (71), is positioned over the protection unit (6), and electrically connects the source region (S) and the gate terminal (G) to the external electrical connection part through 3D wiring (only the conductive structures (71) connected to the source region (S) and the electric conductor (72) are shown in the drawing).

[0026] The ohmic contact layer (51) of the conductive unit (5) may be composed of a metal silicide such as nickel silicide (Ni silicide). The source electrode (52) may be a metal or alloy such as titanium (Ti), titanium nitride (TiN), or aluminum copper alloy (AlCu). The protective unit (6) may be composed of an insulating material such as an oxide or nitride and may be a single-layer or multi-layer structure. The electrical conductor (72) may be composed of a metal or alloy such as titanium (Ti), titanium nitride (TiN), or aluminum copper alloy (AlCu) and may be a single-layer or multi-layer structure.

[0027] A drain terminal (D) is located on the bottom surface (24) of a SiC epitaxial substrate (2). The drain terminal (D) comprises a metal silicon layer (D11) formed on the bottom surface (24) of the SiC epitaxial substrate (2) and a metal conductive layer (D12) formed on the metal silicon layer (D11). The metal conductive layer (D12) may be composed of the same material used for the source electrode (52) and the electrical conductor (72). The metal silicon layer (D11) may be composed of the same material used for the ohmic contact layer (51).

[0028] In a second embodiment of the present disclosure, a method for manufacturing a semiconductor device comprising steps A) through L) is provided. Referring to FIGS. 1 and 2, in step A), a SiC epitaxial substrate (2) is prepared, and a first hard mask unit (20) is formed on the top surface (23) of the SiC epitaxial substrate (2) (which may be the surface of a SiC epitaxial film (22) in the first embodiment). The first hard mask unit (20) has a first hard mask layer (HM1), a second hard mask layer (HM2), and a third hard mask layer (HM3) that are sequentially stacked upward from the top surface (23) of the SiC epitaxial substrate (2). More specifically, the first hard mask unit (20) may be formed by sequentially performing chemical vapor deposition (CVD) to form the first hard mask layer (HM1), the second hard mask layer (HM2), and the third hard mask layer (HM3). The first hard mask unit (20) may be composed of nitride, oxide, or polycrystalline silicon. Additionally, the first hard mask layer (HM1), the second hard mask layer (HM2), and the third hard mask layer (HM3) have high etching selectivity, facilitating the formation of an etching stop layer.

[0029] Next, in step B, a photoresist is formed on the third hard mask layer (HM3), and the photoresist is exposed to form a plurality of spaced-apart openings, and the hard mask unit (20) is etched from the third hard mask layer (HM3) to the first hard mask layer (HM1) through the openings by a photolithography process to form at least two spaced-apart first openings (OP1). Then, the photoresist is removed.

[0030] Subsequently, in step C), the SiC epitaxial substrate (2) is doped by ion implantation through the first opening (OP1) to form at least two well regions (W) that are spaced apart from each other and doped with a second type dopant within the SiC epitaxial film (22). In this embodiment, the second type dopant is a P-type dopant.

[0031] Referring to FIG. 3, in step D), after performing step C), a third hard mask layer (HM3) and a first mask film (SPA1) covering the first opening (OP1) are formed on the etched hard mask unit (20). The first mask film (SPA1) may be composed of an oxide material or a nitride material. Additionally, it should be noted that the first hard mask layer (HM1) and the third hard mask layer (HM3) have higher etching selectivity than the first mask film (SPA1). Next, the first mask film (SPA1) is removed from the third mask layer (HM3) and each of the first openings (OP1) through an etching back process. A portion of the remaining thickness of the first mask film (SPA1) remains on the interface of the first opening (OP1) to form a second opening (OP2) having a size smaller than that of each of the first openings (OP1).

[0032] Next, in step E), a first ion implantation is performed through each second opening (OP2) to form a first low-concentration doping layer (31), and then a second ion implantation is performed through each second opening (OP2) to form a second low-concentration doping layer (32) located below the first low-concentration doping layer (31) and having a width greater than that of the first low-concentration doping layer (31). The first low-concentration doping layer (31) is doped with a first type dopant, and the second low-concentration doping layer (32) is doped with a second type dopant. In this embodiment, the first low-concentration doping layer (31) is doped with an N-type dopant, and the second low-concentration doping layer (32) is doped with a P-type dopant. Additionally, when performing the second ion implantation, the ion implantation can be controlled to implant ions at a specific angle. Additionally, in some embodiments, when performing the first ion implantation, the implantation may be controlled to implant ions at an angle as needed, provided that the width of the second low-concentration doping layer (32) is greater than the width of the first low-concentration doping layer (31).

[0033] Referring to FIG. 4, next, in step F), a third hard mask layer (HM3), a first mask film (SPA1), and a fourth hard mask layer (HM4) covering the first hard mask layer (HM1) exposed from the second opening (OP2) are formed by deposition. A second mask film (SPA2) covering the fourth hard mask layer (HM4) is also formed. It should be noted that the second mask film (SPA2) may be composed of an oxide material or a nitride material, and that the fourth hard mask layer (HM4) has high etching selectivity. Subsequently, a portion of the second mask film (SPA2) positionally corresponding to the third hard mask layer (HM3) and the second opening (OP2) is removed through an etching back process. The remaining thickness portion of the second mask film (SPA2) remains at the boundary of the second opening (OP2) to form a third opening (OP3) having a diameter smaller than the diameter of each second opening (OP2).

[0034] Then, in step G), ion implantation is performed through the third opening (OP3) to form a plurality of source regions (S), each of which is doped with a first type dopant and has a doping concentration greater than that of the first and second low-concentration doping layers (31, 32), and extends downward from the top surface (23) of the SiC epitaxial substrate (2). Each source region (S) has a bottom end at a depth located between the depth of the bottom end of the first low-concentration doping layer (31) and the depth of the bottom end of the second low-concentration doping layer (32). In this embodiment, the source region (S) is doped with an N-type dopant.

[0035] Referring to FIG. 5, in step H), an acid (e.g., HF) is used to remove the first to fourth hard mask layers (HM1, HM2, HM3, HM4) and the first and second mask films (SPA1, SPA2). After a photoresist layer (not shown) is formed on the top surface (23) of the SiC epitaxial substrate (2), the patterned photoresist layer is formed by photolithography. The patterned photoresist layer defines at least two doping openings (not shown) having a width smaller than the source region (S). Then, high-concentration doping ion implantation is performed through the doping openings to form high-concentration doping regions (HW) doped with a second type dopant. Afterward, the patterned photoresist layer is removed.

[0036] Next, in step I), a second hard mask unit (30) is formed having a fifth hard mask layer (HM5), a sixth hard mask layer (HM6), and a seventh hard mask layer (HM7) that are sequentially stacked upward from the top surface (23) of the SiC epitaxial substrate (2). Subsequently, a photoresist (not shown) is formed on the second hard mask unit (30), which is patterned via photolithography to form a patterned photoresist having a photoresist opening between two well regions (W). Then, through the photoresist opening, the seventh hard mask layer (HM7), ​​the sixth hard mask layer (HM6), and the fifth hard mask layer (HM5) are etched to a depth within the fifth hard mask layer (HM5) to form an opening (OP) between the two well regions (W). Subsequently, the patterned photoresist is removed.

[0037] Referring to FIG. 6, in step J), after performing step I), a third mask film (SPA3) covering the second hard mask unit (30) is formed via CVD. Note that the third mask film (SPA3) may be composed of an oxide material or a nitride material, and that the fifth hard mask layer (HM5) and the seventh hard mask layer (HM7) have higher etching selectivity compared to the third mask film (SPA3). Next, the portion of the third mask film (SPA3) positionally corresponding to the seventh hard mask layer (HM7) and the opening (OP) is removed via an etching back process. The remaining thickness portion of the third mask film (SPA3) remains at the opening (OP) to form a fourth opening (OP4) having a width smaller than the minimum distance between the well regions (W).

[0038] Next, in step K), ion implantation is performed through the fourth opening (OP4) to form a junction field-effect transistor region (J) doped with a first type dopant. fetA ) is formed, which is located between the well regions (W) without contacting the well regions (W). Afterwards, the remaining portion of the third mask film (SPA3) and the second hard mask unit (30) are removed to expose the top surface (23) of the SiC epitaxial structure (2).

[0039] Subsequently, referring to FIGS. 1 and FIGS. 6, an insulating layer (4) is formed in step L). The insulating layer (4) comprises a first insulating layer (41) covering the top surface (23) of the SiC epitaxial substrate (2), a polycrystalline silicon layer (not shown) formed on the first insulating layer (41), and a second insulating layer (42) located on the first insulating layer (41). The first and second insulating layers (41, 42) (shown in FIG. 1) may be composed of an oxide material or a nitride material. If they are composed of an oxide material, they may be formed through thermal oxidation or deposition. If they are formed of a nitride material, they may be formed through CVD. Since oxide and nitride materials and methods of forming them are well known in the art, further details are omitted for brevity.

[0040] Next, the gate terminal (G) is formed to be positioned on the first insulating layer (41) and covered with the second insulating layer (42).

[0041] Next, a conductive unit (5) connected to a source region (S) is formed. The conductive unit (5) has an ohmic contact layer (51) formed on a high-concentration doping region (HW) through deposition and a source electrode (52) formed on the ohmic contact layer (51). The ohmic contact layer (51) and the source electrode (52) may be formed from a crystalline silicon material.

[0042] A conductive structure (7) is formed through the protection unit (6) and is electrically connected to the gate terminal (G) and source region (S), and an electrical conductor (72) is formed for external electrical connection. FIG. 1 shows only the conductive structure (71) connected to the electrical conductor (72) and source region (S). Finally, a drain terminal (D) is formed on the bottom surface (24) of the SiC epitaxial substrate (2).

[0043] Since reducing the size of a semiconductor device, such as a transistor, to miniaturize the semiconductor device will reduce the length of the transistor channel, the semiconductor device according to the present disclosure is provided with a first low-concentration doping layer (31) doped with a first type dopant and disposed on the side of each source region (S) near the channel, and a second low-concentration doping layer (32) located below the first low-concentration doping layer (31). The second low-concentration doping layer (32) has a transverse width that extends transversely toward the boundary of each well region (W) such that it is longer than the transverse width of the first low-concentration doping layer (31). This mitigates the negative effects caused by the reduced channel length. The first low-concentration doping layer (31) and the second low-concentration doping layer (32) help the semiconductor device to suppress short channel effects and reduce hot carrier injection.

[0044] Furthermore, reducing the transistor size will also reduce the distance between well regions. However, conventional photolithography cannot accurately etch narrow apertures. Therefore, when semiconductor devices are scaled down for miniaturization, the apertures of the mask used to dope and form the junction field-effect transistor region in conventional technology may overlap with the well region underneath, causing the formed junction field-effect transistor region to come into contact with the well region. Traditionally, when the size of a semiconductor device is reduced, the doping concentration of the junction field-effect transistor region is increased to lower the drain-source-on-resistance (Rdson). And if the junction field-effect transistor region comes into contact with the well region due to miniaturization, the electrical characteristics of the well region will be negatively affected by the highly doped junction field-effect transistor region, which may cause a decrease in the threshold voltage (Vth) and lead to failure of the semiconductor device.

[0045] Accordingly, in steps I), J), and K) of the method of the present disclosure, an opening (OP) having a larger hole (see FIG. 5) is first formed using a conventional photolithography process, and a third mask film (SPA3) is etched through an etching back process to leave a residual thickness portion on the boundary of the opening (OP) to define a smaller fourth opening (OP4) (see FIG. 5). To form the fourth opening (OP4) having a narrower profile (a higher depth-to-width ratio), the thickness of the third mask film (SPA3) and the parameters of the etching back process are carefully controlled to precisely control the residual thickness portion of the third mask film (SPA3). In this way, a fourth opening (OP4) of a small hole with high precision is formed, and a junction field-effect transistor region (J) formed through the fourth opening (OP4) fet ) can be precisely controlled to avoid contact with an adjacent well region (W). Accordingly, the junction field-effect transistor region (J) of the present invention fet) can be doped at a high concentration to reduce Rdson without affecting the threshold voltage (Vth) of the semiconductor device, and can enable the semiconductor device to function normally.

[0046] To summarize the above, the semiconductor device according to the present invention forms a first low-concentration doping layer (31) doped with a first type dopant through ion implantation through a second opening (OP2), and then forms a second low-concentration doping layer (32) doped with a second type dopant having a width greater than that of the first low-concentration doping layer (31), thereby suppressing hot carrier implantation and preventing short channel effects caused by the miniaturization of the semiconductor device. Additionally, the junction field-effect transistor region (J fet By controlling the manufacturing process so that it does not come into contact with any of the well regions (W), the negative impact on electrical characteristics caused by the highly doped junction field-effect transistor region can be mitigated. In this way, the semiconductor device according to the present disclosure can function without failure, and the objective of the present disclosure can be achieved.

[0047] In the foregoing description, numerous specific details have been presented for the purpose of explanation and to provide a complete understanding of the embodiment(s). However, it will be apparent to those skilled in the art that one or more other embodiments may be practiced without some of these specific details. Furthermore, it should be understood that references throughout this specification to “one embodiment,” “an embodiment,” or an embodiment with an ordinal number, etc., imply that a specific feature, structure, or characteristic may be included in the practice of this disclosure. Additionally, it should be understood that in this description, various features are sometimes grouped together in a single embodiment, drawing, or description to simplify the disclosure and aid in understanding various inventive aspects, and that this does not imply that such features must be practiced in the presence of all other features. In other words, in the described embodiment, if the implementation of one or more features or specific details does not affect the implementation of another one or more features or specific details, the above one or more features may be selected and practiced alone without the other one or more features or specific details. Additionally, it should be noted that in the practice of the present disclosure, where appropriate, one or more features or specific details from one embodiment may be practiced together with one or more features or specific details from another embodiment.

[0048] Although the present disclosure has been described in relation to what are considered exemplary embodiments(s), it is understood that the present disclosure is not limited to the disclosed embodiments(s) and is intended to encompass various arrangements included within the spirit and scope of the broadest interpretation to include all such modifications and equivalent arrangements.

Claims

Claim 1 A semiconductor device comprising: a silicon carbide (SiC) epitaxial substrate having a top surface and a bottom surface opposite to the top surface; two spaced-apart well regions—each well region extending downward from the top surface of the SiC epitaxial substrate and doped with a second type dopant—and a junction field-effect transistor region (J) extending downward from the top surface of the SiC epitaxial substrate, located between the two well regions, and doped with a first type dopant. fet ) and, two source regions extending downward from the top surface of the SiC epitaxial substrate and each located within the two well regions, and two low-concentration doping regions each disposed within the well regions - each low-concentration doping region has a first low-concentration doping layer extending downward from the top surface of the SiC epitaxial substrate and disposed parallel to the upper portion of a corresponding boundary edge of one of the source regions, and a second low-concentration doping layer extending downward from the first low-concentration doping layer and disposed parallel to the lower portion of the corresponding boundary edge of one of the source regions, and further extending downward to be located below the corresponding one of the source regions, wherein the first low-concentration doping layer is doped with the first type dopant, and the second low-concentration doping layer is doped with the second type dopant and has a width greater than the width of the first low-concentration doping layer - and two high-concentration doping regions - each A semiconductor device comprising: a high-concentration doping region formed below one of the corresponding source regions without extending beyond the bottom surface of one of the corresponding well regions; a gate terminal located on the top surface of the SiC epitaxial substrate between the two source regions and having two opposite transverse ends that respectively overlap with the source regions; and a drain terminal located on the bottom surface of the SiC epitaxial substrate. Claim 2 In claim 1, the junction field-effect transistor region (J fet ) has a lateral width smaller than the distance between the two well regions, so that the junction field-effect transistor region (J fet A semiconductor device that does not come into contact with the two well regions mentioned above. Claim 3 A semiconductor device according to claim 1, wherein the second low-concentration doping layer has a doping concentration lower than the doping concentration of the well regions, and the high-concentration doping regions have a doping concentration higher than the doping concentration of the well regions. Claim 4 A semiconductor device according to claim 1, wherein the second low-concentration doping layer of each of the low-concentration doping regions extends downward from the bottom of the corresponding one of the source regions and is positioned parallel to the boundary wall of the high-concentration doping region. Claim 5 A semiconductor device according to any one of claims 1 to 4, further comprising: an insulating layer having a first insulating layer covering the upper surface of the SiC epitaxial substrate and a second insulating layer located on the first insulating layer and covering the gate terminal, wherein the gate terminal is located on the first insulating layer; a conductive unit having an ohmic contact layer electrically connected to the source regions and a source electrode electrically connected to the ohmic contact layer; and a protective unit composed of an insulating material, located on the second insulating layer, and covering the source electrode. Claim 6 delete Claim 7 A method for manufacturing a semiconductor device comprising: A) forming a first hard mask unit on the top surface of a silicon carbide (SiC) epitaxial substrate, wherein the first hard mask unit has a first hard mask layer, a second hard mask layer, and a third hard mask layer sequentially stacked upward from the top surface of the SiC epitaxial substrate; B) etching the first hard mask unit from the third hard mask layer to the first hard mask layer through a photolithography process to form two first openings spaced apart from each other; C) doping the SiC epitaxial substrate by ion implantation through the first openings to form two well regions spaced apart from each other and doped with a second type dopant; and D) forming a first mask film on the first hard mask unit, wherein the first mask film is etched to cover the third hard mask layer and the first openings, and then the third hard mask layer and the first A portion of the openings is removed, and the remaining thickness portions of the first mask film remain on the boundaries of the first openings to define the second openings, each of which has a size smaller than the size of each of the first openings - and, E) a step of forming a first low-concentration doping layer by performing a first ion implantation through each of the second openings, and then forming a second low-concentration doping layer having a width wider than the width of the first low-concentration doping layer under the first low-concentration doping layer by performing a second ion implantation through each of the second openings - the first low-concentration doping layer is doped with a first type dopant, and the second low-concentration doping layer is doped with a second type dopant - and, F) forming a third hard mask layer, the first mask film, and a fourth hard mask layer covering the first hard mask layer exposed from the second openings, and a second hard mask layer covering the fourth hard mask layer After forming the mask film,A method for manufacturing a semiconductor device comprising: a step of removing portions of the second mask film positionally corresponding to the third hard mask layer and the second openings, wherein the remaining thickness portions of the second mask film remain on the boundaries of the second openings and define the third openings, each having a diameter smaller than the diameter of each of the second openings; and G) a step of performing ion implantation through the third openings to form a plurality of source regions, wherein the plurality of source regions extend downward from the upper surface of each of the source regions, are doped with a first type dopant, have a doping concentration greater than the doping concentrations of the first low-concentration doping layer and the second low-concentration doping layer, and each of the source regions has a lower end located at a depth between the depth of the lower end of the first low-concentration doping layer and the depth of the lower end of the second low-concentration doping layer. Claim 8 A method for manufacturing a semiconductor device according to claim 7, further comprising the step of: H) removing the first to fourth hard mask layers, the first mask film, and the second mask film, forming a patterned photoresist layer on the top surface of the SiC epitaxial substrate through photolithography, defining a plurality of doping openings having a width smaller than the width of the source regions, and forming two high-concentration doping regions doped with a second type dopant by performing high-concentration doping ion implantation through the doping openings, and then removing the patterned photoresist layer. Claim 9 In claim 7 or 8, I) forming a second hard mask unit having a fifth hard mask layer, a sixth hard mask layer, and a seventh hard mask layer sequentially stacked upward from the top surface of the SiC epitaxial substrate, and then etching the seventh hard mask layer and the sixth hard mask layer to reach the fifth hard mask layer to form an opening located between the well regions; and J) forming a third mask film covering the second hard mask unit and removing portions of the third mask film positionally corresponding to the seventh hard mask layer and the opening of the second hard mask unit—wherein the remaining thickness portion of the third mask film remains within the opening of the second hard mask unit to form a fourth opening having a diameter smaller than the minimum distance between the well regions— and K) performing ion implantation through the fourth opening to form a junction field-effect transistor doped with a first-type dopant and located between the well regions without contacting the well regions. A method for manufacturing a semiconductor device, further comprising the step of removing the remaining portion of the third mask film and the second hard mask unit after forming a region (Jfet). Claim 10 A method for manufacturing a semiconductor device according to claim 7, further comprising the steps of: forming an insulating layer having a first insulating layer covering the upper surface of the SiC epitaxial substrate and a second insulating layer located on the first insulating layer; forming a gate terminal located on the first insulating layer and covered by the second insulating layer; forming a conductive unit electrically connected to the source regions; and forming a protective unit composed of an insulating material and located on the second insulating layer and the conductive unit.

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