Display device and method of manufacturing display device

Abstract

A method for manufacturing a display device may include the steps of: forming an active pattern on a substrate comprising a first region, a second region spaced apart from the first region, and a third region located between the first region and the second region; forming an insulating layer on the active pattern; forming a first contact hole in the insulating layer that exposes a portion of the first region, a second contact hole that exposes a portion of the second region, and an opening that exposes the third region; forming a conductive pattern on the insulating layer substantially simultaneously filling the first and second contact holes and removing the third region; and forming a planarization layer on the conductive pattern.

Description

Technology Field

[0001] The present invention relates to a display device. More specifically, the present invention relates to an organic light-emitting display device and a method for manufacturing such an organic light-emitting display device. Background Technology

[0002] A display device may include a plurality of pixels that emit light for displaying an image. Each of the pixels may include a plurality of transistors that generate a driving current and a light-emitting element that emits light based on the driving current.

[0003] Each transistor of the pixels may include an active pattern comprising a semiconductor material. Meanwhile, if the active pattern includes regions that are electrically isolated from one another, the active pattern may be damaged by static electricity introduced during the manufacturing or use of the display device. The problem to be solved

[0004] One objective of the present invention is to provide a method for manufacturing a display device that prevents damage to the display device during the manufacturing process.

[0005] One objective of the present invention is to provide a display device with improved display quality.

[0006] However, the objectives of the present invention are not limited to such objectives, and may be expanded in various ways without departing from the spirit and scope of the invention. means of solving the problem

[0007] To achieve one objective of the present invention as described above, a method for manufacturing a display device according to embodiments may include the steps of: forming an active pattern on a substrate comprising a first region, a second region spaced apart from the first region, and a third region located between the first region and the second region; forming an insulating layer on the active pattern; forming a first contact hole in the insulating layer that exposes a portion of the first region, a second contact hole that exposes a portion of the second region, and an opening that exposes the third region; substantially simultaneously forming a conductive pattern on the insulating layer that fills the first and second contact holes and removes the third region; and forming a planarization layer on the conductive pattern.

[0008] In one embodiment, the step of substantially simultaneously forming the conductive pattern and removing the third region may include forming the first and second contact holes and a conductive layer filling the opening on the insulating layer, and etching a portion of the conductive layer filling the opening and the third region.

[0009] In one embodiment, the planarization layer may be in contact with the side of the first region and the side of the second region.

[0010] In one embodiment, the method for manufacturing the display device may further include the step of forming a buffer layer on the substrate before the step of forming the active pattern.

[0011] In one embodiment, the planarization layer may come into contact with the buffer layer.

[0012] In one embodiment, the step of substantially simultaneously forming the conductive pattern and removing the third region may include the step of partially etching the portion of the buffer layer that overlaps the third region.

[0013] In one embodiment, the first contact hole, the second contact hole, and the opening may be formed substantially simultaneously.

[0014] In one embodiment, the first region and the second region can be physically separated after the step of substantially simultaneously forming the conductive pattern and removing the third region.

[0015] In one embodiment, the insulating layer may include a gate insulating layer, a first interlayer insulating layer, and a second interlayer insulating layer stacked on the active pattern.

[0016] To achieve one objective of the present invention as described above, a display device according to embodiments may include an active pattern disposed on a substrate and comprising a first region and a second region spaced apart from the first region; an insulating layer disposed on the active pattern and having a first contact hole and a second contact hole that respectively expose a portion of the first region and a portion of the second region; a conductive pattern disposed on the insulating layer and contacting the first region and the second region respectively through the first contact hole and the second contact hole; and a flattening layer disposed on the conductive pattern and contacting the side of the first region and the side of the second region.

[0017] In one embodiment, the display device may further include a buffer layer disposed between the substrate and the active pattern.

[0018] In one embodiment, the insulating layer may have an opening that overlaps the portion between the first region and the second region.

[0019] In one embodiment, the planarization layer may contact the buffer layer through the opening.

[0020] In one embodiment, the buffer layer may have a trench that overlaps the portion between the first region and the second region.

[0021] In one embodiment, the display device may further include a driving transistor that generates a driving current, a light-emitting diode that emits light based on the driving current, a first initialization transistor that provides a first initialization voltage to the gate electrode of the driving transistor, and a second initialization transistor that provides a second initialization voltage different from the first initialization voltage to the anode electrode of the light-emitting diode.

[0022] In one embodiment, the first region may be the source electrode of the first initialization transistor, and the second region may be the source electrode of the second initialization transistor.

[0023] In one embodiment, the display device may further include a first initialization voltage line that transmits the first initialization voltage and is electrically connected to the first area, and a second initialization voltage line that transmits the second initialization voltage and is electrically connected to the second area.

[0024] In one embodiment, the display device may further include a driving transistor that generates a driving current, a storage capacitor comprising a first electrode connected to the gate electrode of the driving transistor and a second electrode superimposed on the first electrode, a light-emitting diode that emits light based on the driving current, an initialization transistor that provides an initialization voltage to the first electrode of the storage capacitor, and a reference transistor that provides a reference voltage to the second electrode of the storage capacitor.

[0025] In one embodiment, the first region may be the drain electrode of the initialization transistor, and the second region may be the drain electrode of the reference transistor.

[0026] In one embodiment, the display device may further include an initial voltage line that transmits the initial voltage and is electrically connected to the first area, and a reference voltage line that transmits the reference voltage and is electrically connected to the second area. Effects of the invention

[0027] In a method for manufacturing a display device according to embodiments of the present invention, by removing a third region of an active pattern and substantially simultaneously forming a conductive pattern connected to a first region and a second region of an active pattern, even if static electricity is introduced during the manufacturing process of the display device, the static electricity is dispersed so that the active pattern is not damaged.

[0028] In a display device according to embodiments of the present invention, since a first region and a second region of an active pattern that are spaced apart from each other are connected to a conductive pattern, even if static electricity is introduced during the manufacturing process or the use process of the display device, the static electricity is dispersed so that the active pattern is not damaged. Accordingly, the display quality of the display device can be improved.

[0029] However, the effects of the present invention are not limited to the effects described above, and may be extended in various ways without departing from the spirit and scope of the present invention. Brief explanation of the drawing

[0030] FIG. 1 is a plan view showing a display device according to one embodiment of the present invention. FIG. 2 is a circuit diagram showing a pixel according to one embodiment of the present invention. Figure 3 is a layout diagram showing the pixels of Figure 2. FIG. 4 is a cross-sectional view showing a display device cut along line II' of FIG. 3. FIGS. 5, FIGS. 6, FIGS. 7, FIGS. 8, FIGS. 9, FIGS. 10, FIGS. 11, FIGS. 12, and FIGS. 13 are drawings illustrating a method for manufacturing a display device according to an embodiment of the present invention. FIG. 14 is a circuit diagram showing a pixel according to one embodiment of the present invention. Figure 15 is a layout diagram showing the pixels of Figure 14. FIG. 16 is a cross-sectional view showing a display device cut along the line II-II' of FIG. 15. Specific details for implementing the invention

[0031] Hereinafter, a display device and a method for manufacturing a display device according to embodiments of the present invention will be described in more detail with reference to the attached drawings. Identical or similar reference numerals are used for identical components in the attached drawings.

[0032] Hereinafter, a display device according to an embodiment of the present invention will be described with reference to FIGS. 1 to 4.

[0033] FIG. 1 is a plan view showing a display device according to one embodiment of the present invention.

[0034] Referring to FIG. 1, a display device (1000) may include a plurality of pixels (PX). The pixels (PX) may be arranged in a matrix form along a first direction (DR1) and a second direction (DR2) that intersects the first direction (DR1). Each of the pixels (PX) emits light, and the display device (1000) may display an image based on the light.

[0035] FIG. 2 is a circuit diagram showing a pixel according to an embodiment of the present invention. For example, FIG. 2 may show an example of a pixel (PX) of a display device (1000) of FIG. 1.

[0036] Referring to FIG. 2, a pixel (PX) may include a plurality of transistors (T1, T2, T3, T4, T5, T6, T7), a storage capacitor (CST), and a light-emitting diode (LD). The transistors (T1, T2, T3, T4, T5, T6, T7) may include a first transistor (T1), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), a sixth transistor (T6), and a seventh transistor (T7).

[0037] The first transistor (T1) is electrically connected to the first power supply voltage line (ELVDD) and the anode electrode of the light-emitting diode (LD), and can provide a driving current to the light-emitting diode (LD) corresponding to the data signal provided by the data line (DATA). In other words, the first transistor (T1) may be a driving transistor.

[0038] The second transistor (T2) is connected between the data line (DATA) and the first electrode of the first transistor (T1), and can provide the data signal to the first electrode of the first transistor (T1) in response to a scan signal provided by the scan line (GW). In other words, the second transistor (T2) may be a switching transistor.

[0039] The third transistor (T3) is connected between the gate electrode and the second electrode of the first transistor (T1), and can compensate the threshold voltage of the first transistor (T1) by diode-connecting the first transistor (T1) in response to the scan signal. In other words, the third transistor (T3) can be a compensation transistor.

[0040] The fourth transistor (T4) is connected between the first initialization voltage line (VINT1) and the gate electrode of the first transistor (T1), and can provide the first initialization voltage provided by the first initialization voltage line (VINT1) to the gate electrode of the first transistor (T1) in response to the first initialization control signal provided by the first initialization control line (GI). In other words, the fourth transistor (T4) may be a driving initialization transistor.

[0041] The fifth transistor (T5) may be connected between the first power supply voltage line (ELVDD) and the first electrode of the first transistor (T1), and the sixth transistor (T6) may be connected between the second electrode of the first transistor (T1) and the anode electrode of the light-emitting diode (LD). Each of the fifth transistor (T5) and the sixth transistor (T6) may provide the driving current to the anode electrode of the light-emitting diode (LD) in response to a light-emitting control signal provided by the light-emitting control line (EM). In other words, each of the fifth transistor (T5) and the sixth transistor (T6) may be a light-emitting control transistor.

[0042] The seventh transistor (T7) is connected between the second initialization voltage line (VINT2) and the anode electrode of the light-emitting diode (LD), and can provide the second initialization voltage provided by the second initialization voltage line (VINT2) to the anode electrode of the light-emitting diode (LD) in response to the second initialization control signal provided by the second initialization control line (GB). In other words, the seventh transistor (T7) may be a diode initialization transistor. The voltage level of the second initialization voltage may be different from the voltage level of the first initialization voltage. In one embodiment, the voltage level of the second initialization voltage may be lower than the voltage level of the first initialization voltage.

[0043] In one embodiment, the first electrode and the second electrode of each of the transistors (T1, T2, T3, T4, T5, T6, T7) may each be a source electrode and a drain electrode. However, the present invention is not limited thereto, and the first electrode and the second electrode of each of the transistors (T1, T2, T3, T4, T5, T6, T7) may each be a drain electrode and a source electrode.

[0044] A storage capacitor (CST) can be connected between the first power supply voltage line (ELVDD) and the gate electrode of the first transistor (T1). The storage capacitor (CST) can maintain the voltage between the first power supply voltage line (ELVDD) and the gate electrode of the first transistor (T1).

[0045] A light-emitting diode (LD) can be connected between the second electrode of the sixth transistor (T6) and the second power supply voltage line (ELVSS). The light-emitting diode (LD) can emit light based on the driving current.

[0046] In the present embodiment, as the first initialization voltage line (VINT1) providing the first initialization voltage applied to the fourth transistor (T4) and the second initialization voltage line (VINT2) providing the second initialization voltage applied to the seventh transistor (T7) are separated, the first transistor (T1) and the light-emitting diode (LD) can be initialized by different voltages, and accordingly, when the pixel (PX) is driven in a low grayscale, the low grayscale stain of the display device can be improved.

[0047] FIG. 3 is a layout diagram showing the pixel (PX) of FIG. 2. FIG. 4 is a cross-sectional view showing a display device (1000) cut along line II' of FIG. 3.

[0048] Referring to FIGS. 2, FIGS. 3, and FIGS. 4, a display device (1000) may include a substrate (100), a buffer layer (101), an active pattern (110), a gate insulating layer (102), a first conductive pattern, a first interlayer insulating layer (103), a second conductive pattern, a second interlayer insulating layer (104), a third conductive pattern (145), a planarization layer (105), a first electrode (150), a pixel defining film (106), a light-emitting layer (160), a second electrode (170), and an encapsulation layer (180).

[0049] The substrate (100) may be formed of a transparent or opaque material. For example, the substrate (100) may include a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluorine-doped quartz (F-doped quartz) substrate, a sodalime glass substrate, a non-alkali glass substrate, etc. Optionally, the substrate (100) may include a flexible transparent resin substrate. For example, the transparent resin substrate may be a polyimide substrate.

[0050] A buffer layer (101) may be disposed on a substrate (100). The buffer layer (101) can prevent metal atoms or impurities from diffusing from the substrate (100) into the active pattern (110). Additionally, the buffer layer (101) can control the rate of heat transfer during the crystallization process for forming the active pattern (110), thereby enabling the acquisition of a substantially uniform active pattern (110).

[0051] The active pattern (110) may be disposed on the buffer layer (101). In one embodiment, the active pattern (110) may include polycrystalline silicon. In another embodiment, the active pattern (110) may include an oxide semiconductor. For example, the oxide semiconductor may include at least one oxide selected from indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn).

[0052] The active pattern (110) may include a first region (111) and a second region (112). The second region (112) may be spaced apart from the first region (111). In other words, the first region (111) and the second region (112) may be physically separated from each other.

[0053] In one embodiment, the first region (111) may be the source electrode of the fourth transistor (T4) and the second region (112) may be the source electrode of the seventh transistor (T7). For example, the fourth transistor (T4) may be included in the pixel of the Nth row and the seventh transistor (T7) may be included in the pixel of the N-1th row. However, the present invention is not limited thereto, and in another embodiment, the first region (111) may be the drain electrode of the fourth transistor (T4) and the second region (112) may be the drain electrode of the seventh transistor (T7).

[0054] The buffer layer (101) may have a trench (TCH) that overlaps the portion between the first region (111) and the second region (112) of the active pattern (110). The trench (TCH) may have a cross-sectional shape that is recessed from the upper surface of the buffer layer (101) toward the lower surface of the buffer layer (101).

[0055] A gate insulating layer (102) may be disposed on an active pattern (110). The gate insulating layer (102) may cover the active pattern (110) on a buffer layer (101) and may have substantially the same thickness along the profile of the active pattern (110). The gate insulating layer (102) may include a silicon compound, a metal oxide, etc.

[0056] The first conductive pattern may be disposed on a gate insulating layer (102). The first conductive pattern may include a scan line (GW), an initialization control line (GI(N) / GB(N-1)), a light emission control line (EM), and a first storage electrode (SE1). The first conductive pattern may be formed of a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc.

[0057] The scan line (GW) can be extended in the first direction (DR1). The active pattern (110) can form the second transistor (T2) and the third transistor (T3) together with the scan line (GW). The initialization control line (GI(N) / GB(N-1)) can be extended in the first direction (DR1). The active pattern (110) can form the fourth transistor (T4) included in the pixel of the Nth row and the seventh transistor (T7) included in the pixel of the N-1th row together with the initialization control line (GI(N) / GB(N-1)).

[0058] The light emission control line (EM) can be extended in a first direction (DR1). The active pattern (110) can form a fifth transistor (T5) and a sixth transistor (T6) together with the light emission control line (EM). A first storage electrode (SE1) can be placed between the scan line (GW) and the light emission control line (EM). The active pattern (110) can form a first transistor (T1) together with the first storage electrode (SE1).

[0059] The first interlayer insulating layer (103) may be disposed on the first conductive pattern. The first interlayer insulating layer (103) may cover the first conductive pattern on the gate insulating layer (102) and may have substantially the same thickness along the profile of the first conductive pattern. The first interlayer insulating layer (103) may include a silicon compound, a metal oxide, etc.

[0060] The second conductive pattern may be disposed on the first interlayer insulating layer (103). The second conductive pattern may include a first horizontal initial voltage line (VINT1_V), a second horizontal initial voltage line (VINT2_V), and a second storage electrode (SE2). The second conductive pattern may be formed of a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc.

[0061] The first horizontal initial voltage line (VINT1_V) can be extended in the first direction (DR1). The second horizontal initial voltage line (VINT2_V) can be extended in the first direction (DR1). The second storage electrode (SE2) can be extended in the first direction (DR1). The second storage electrode (SE2) can be superimposed on the first storage electrode (SE1) and together with the first storage electrode (SE1) can form a storage capacitor (CST). The first power voltage transmitted by the first power voltage line (ELVDD) can be applied to the second storage electrode (SE2).

[0062] A second interlayer insulating layer (104) may be disposed on the second conductive pattern. In one embodiment, the second interlayer insulating layer (104) may cover the second conductive pattern on the first interlayer insulating layer (103) and may have substantially the same thickness along the profile of the second conductive pattern. In another embodiment, the second interlayer insulating layer (104) may sufficiently cover the second conductive pattern on the first interlayer insulating layer (103) and may have a substantially flat upper surface without creating a step around the second conductive pattern. The second interlayer insulating layer (104) may be formed of an inorganic insulating material or an organic insulating material.

[0063] The gate insulating layer (102), the first interlayer insulating layer (103), and the second interlayer insulating layer (104) can form an insulating layer (ISL). In other words, the insulating layer (ISL) may include the gate insulating layer (102), the first interlayer insulating layer (103), and the second interlayer insulating layer (104) stacked on the active pattern (110).

[0064] The insulating layer (ISL) may have a first contact hole (CNT1), a second contact hole (CNT2), and an opening (OPN). The first contact hole (CNT1) may expose a portion of the first region (111) of the active pattern (110), and the second contact hole (CNT2) may expose a portion of the second region (112) of the active pattern (110).

[0065] The opening (OPN) can overlap the portion between the first region (111) and the second region (112) of the active pattern (110). In this case, the opening (OPN) can overlap the trench (TCH).

[0066] A third conductive pattern (145) may be disposed on the second interlayer insulating layer (104). The third conductive pattern (145) may include a data line (DATA), a first power voltage line (ELVDD), a first vertical initialization voltage line (VINT1_H), and a second vertical initialization voltage line (VINT2_H). The third conductive pattern (145) may be formed of a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc.

[0067] The data line (DATA) can be extended in a second direction (DR2). The data line (DATA) can be electrically connected to an active pattern (110) through contact holes formed in the second interlayer insulating layer (104), the first interlayer insulating layer (103), and the gate insulating layer (102).

[0068] The first power voltage line (ELVDD) can be extended in a second direction (DR2). The first power voltage line (ELVDD) can be electrically connected to an active pattern (110) through a contact hole formed in the second interlayer insulating layer (104), the first interlayer insulating layer (103), and the gate insulating layer (102), and can be electrically connected to a second storage electrode (SE2) through a contact hole formed in the second interlayer insulating layer (104).

[0069] The first vertical initial voltage line (VINT1_H) can be extended in a second direction (DR2). The first vertical initial voltage line (VINT1_H) can be electrically connected to the first horizontal initial voltage line (VINT1_V) through a contact hole formed in the second interlayer insulation layer (104). The first horizontal initial voltage line (VINT1_V) and the first vertical initial voltage line (VINT1_H) can form the first initial voltage line (VINT1).

[0070] The second vertical initial voltage line (VINT2_H) can be extended in the second direction (DR2). The second vertical initial voltage line (VINT2_H) can be electrically connected to the second horizontal initial voltage line (VINT2_V) through a contact hole formed in the second interlayer insulation layer (104). The second horizontal initial voltage line (VINT2_V) and the second vertical initial voltage line (VINT2_H) can form the second initial voltage line (VINT2).

[0071] The third conductive pattern (145) can contact the first region (111) and the second region (112), respectively, through the first contact hole (CNT1) and the second contact hole (CNT2). In this case, the first region (111) and the second region (112) of the active pattern (110) can each be electrically connected to other components of the display device (1000). In one embodiment, the first region (111) of the active pattern (110) can be electrically connected to the first initialization voltage line (VINT1), and the second region (112) of the active pattern (110) can be electrically connected to the second initialization voltage line (VINT2).

[0072] The flattening layer (105) may be disposed on the third conductive pattern (145). The flattening layer (105) may have a substantially flat upper surface that sufficiently covers the third conductive pattern (145) on the second interlayer insulating layer (104) and does not create a step around the third conductive pattern (145). The flattening layer (105) may be formed from an organic insulating material such as a photoresist, an acrylic resin, a polyimide resin, a polyamide resin, or a siloxane-based resin.

[0073] The flattening layer (105) can come into contact with the side of the first region (111) and the side of the second region (112). As the first region (111) and the second region (112) are spaced apart from each other and the opening (OPN) of the insulating layer (ISL) overlaps in the portion between the first region (111) and the second region (112), the flattening layer (105) can come into contact with the side of the first region (111) and the side of the second region (112).

[0074] In one embodiment, the flattening layer (105) may come into contact with the buffer layer (101) through an opening (OPN) of the insulating layer (ISL). The flattening layer (105) may fill the opening (OPN) of the insulating layer (ISL) and the trench (TCH) of the buffer layer (101).

[0075] The first electrode (150) may be disposed on the planarization layer (105). Depending on the light emission method of the display device (1000), the first electrode (150) may be formed of a reflective material or a transparent material. For example, the first electrode (150) may be aluminum (Al), an alloy containing aluminum (Al), or aluminum nitride (AlN x ), silver (Ag), alloy containing silver (Ag), tungsten (W), tungsten nitride (WN x ), copper (Cu), alloys containing copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN x ), molybdenum (Mo), alloys containing molybdenum (Mo), titanium (Ti), titanium nitride (TiN x ), platinum (Pt), tantalum (Ta), tantalum nitride (TaN x ), Neodymium (Nd), Scandium (Sc), Zinc oxide (ZnO x ), Indium Tin Oxide (ITO), Tin Oxide (SnO x ), Indium oxide (InO x ), gallium oxide (GaO xIt may include ), indium zinc oxide (IZO), etc. In one embodiment, the first electrode (150) may be formed as a single-layer or multi-layer structure including a metal film, an alloy film, a metal nitride film, a conductive metal oxide film and / or a transparent conductive oxide film.

[0076] A pixel defining film (106) may be disposed on a first electrode (150). The pixel defining film (106) may be formed from an organic insulating material, an inorganic insulating material, etc. For example, the pixel defining film (106) may be formed from a photoresist, a polyacrylic resin, a polyimide resin, an acrylic resin, a silicone compound, etc. In one embodiment, the pixel defining film (106) may include an opening that partially exposes the first electrode (150). The light-emitting region and the non-light-emitting region of the display device (1000) may be defined by the opening of the pixel defining film (106). For example, the portion where the opening of the pixel defining film (106) is located may correspond to the light-emitting region, and the non-light-emitting region may correspond to the portion adjacent to the opening of the pixel defining film (106).

[0077] The light-emitting layer (160) may be disposed on a first electrode (150) exposed through the opening of the pixel defining film (106). Additionally, the light-emitting layer (160) may extend onto the sidewall of the opening of the pixel defining film (106). In one embodiment, the light-emitting layer (160) may have a multilayer structure including an organic light-emitting layer, a hole injection layer, a hole transport layer, an electron transport layer, an electron injection layer, etc.

[0078] The second electrode (170) may be disposed on the pixel defining film (106) and the light-emitting layer (160). Depending on the light-emitting method of the display device (1000), the second electrode (170) may be formed of a light-transmitting material or a reflective material. For example, the second electrode (170) may be aluminum (Al), an alloy containing aluminum (Al), or aluminum nitride (AlN). x), silver (Ag), alloy containing silver (Ag), tungsten (W), tungsten nitride (WN x ), copper (Cu), alloys containing copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN x ), molybdenum (Mo), alloys containing molybdenum (Mo), titanium (Ti), titanium nitride (TiN x ), platinum (Pt), tantalum (Ta), tantalum nitride (TaN x ), Neodymium (Nd), Scandium (Sc), Zinc oxide (ZnO x ), Indium Tin Oxide (ITO), Tin Oxide (SnO x ), Indium oxide (InO x ), gallium oxide (GaO x It may include ), indium zinc oxide (IZO), etc. In one embodiment, the second electrode (170) may be formed as a single-layer or multi-layer structure including a metal film, an alloy film, a metal nitride film, a conductive metal oxide film and / or a transparent conductive oxide film.

[0079] The first electrode (150), the light-emitting layer (160), and the second electrode (170) can form a light-emitting diode (LD). In one embodiment, the first electrode (150) and the second electrode (170) may each be the anode electrode and the cathode electrode of the light-emitting diode (LD). However, the present invention is not limited thereto, and in another embodiment, the first electrode (150) and the second electrode (170) may each be the cathode electrode and the anode electrode of the light-emitting diode (LD).

[0080] The encapsulation layer (180) may be disposed on the second electrode (170). The encapsulation layer (180) may prevent the penetration of external moisture and oxygen. The encapsulation layer (180) may include at least one inorganic encapsulation layer and at least one organic encapsulation layer that are alternately stacked. At least one inorganic encapsulation layer and at least one organic encapsulation layer may be alternately stacked.

[0081] In one embodiment, the encapsulation layer (180) may include a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer. The first inorganic encapsulation layer, the organic encapsulation layer, and the second inorganic encapsulation layer may be sequentially laminated on the second electrode (170).

[0082] Hereinafter, a method for manufacturing a display device according to an embodiment of the present invention will be described with reference to FIGS. 5 to 13.

[0083] FIGS. 5, FIGS. 6, FIGS. 7, FIGS. 8, FIGS. 9, FIGS. 10, FIGS. 11, FIGS. 12, and FIGS. 13 are drawings illustrating a method for manufacturing a display device according to an embodiment of the present invention. For example, FIGS. 5 to 13 may illustrate a method for manufacturing the display device (1000) of FIGS. 3 and FIGS. 4.

[0084] Referring to FIGS. 5 and 6, a buffer layer (101) and an active pattern (110) can be formed on a substrate (100).

[0085] First, a buffer layer (101) can be formed on a substrate (100). For example, the buffer layer (101) can be formed from a silicon compound, a metal oxide, etc.

[0086] Next, an active pattern (110) can be formed on the buffer layer (101). For example, an active layer can be formed on the buffer layer (101) using polycrystalline silicon, an oxide semiconductor, etc., and the active layer can be patterned to form an active pattern (110).

[0087] The active pattern (110) may include a first region (111), a second region (112), and a third region (113). The second region (112) may be spaced apart from the first region (111). The third region (113) may be located between the first region (111) and the second region (112).

[0088] Referring to FIGS. 7 and 8, an insulating layer (ISL) can be formed on an active pattern (110). A gate insulating layer (102), the first conductive pattern, the first interlayer insulating layer (103), the second conductive pattern, and the second interlayer insulating layer (104) can be sequentially formed on the active pattern (110). The insulating layer (ISL) may include a gate insulating layer (102), a first interlayer insulating layer (103), and a second interlayer insulating layer (104) stacked on the active pattern (110).

[0089] Referring to FIG. 9, a first contact hole (CNT1), a second contact hole (CNT2), and an opening (OPN) can be formed in the insulating layer (ISL). The first contact hole (CNT1) may expose a portion of the first region (111) of the active pattern (110), and the second contact hole (CNT2) may expose a portion of the second region (112) of the active pattern (110). The opening (OPN) may expose a third region (113) of the active pattern (110).

[0090] In one embodiment, the first contact hole (CNT1), the second contact hole (CNT2), and the opening (OPN) can be formed substantially simultaneously. For example, the first contact hole (CNT1), the second contact hole (CNT2), and the opening (OPN) can be formed substantially simultaneously through a single photo process using a single photomask.

[0091] Referring to FIG. 10, a conductive layer (140) can be formed on an insulating layer (ISL). The conductive layer (140) can fill a first contact hole (CNT1), a second contact hole (CNT2), and an opening (OPN). Accordingly, the conductive layer (140) can contact the first region (111), the second region (112), and the third region (113) of the active pattern (110), respectively, through the first contact hole (CNT1), the second contact hole (CNT2), and the opening (OPN).

[0092] Referring to FIGS. 11 and 12, the conductive layer (140) can be patterned to form a third conductive pattern (145), and the third region (113) of the active pattern (110) can be removed.

[0093] In order to form a third conductive pattern (145), a portion of the conductive layer (140) filling the opening (OPN) of the insulating layer (ISL) can be etched using an etching material. Accordingly, the said portion of the conductive layer (140) filling the opening (OPN) of the insulating layer (ISL) is removed, and the third region (113) of the active pattern (110) can be exposed.

[0094] In the process of forming the third conductive pattern (145), the third region (113) of the active pattern (110) can be etched using the etching material. Accordingly, the third region (113) of the active pattern (110) is removed, and the first region (111) and the second region (112) of the active pattern (110) can be physically separated. In this case, the side of the first region (111) and the side of the second region (112) may be exposed. Additionally, a portion of the buffer layer (101) overlapping the third region (113) of the active pattern (110) may be exposed. Thus, substantially simultaneously, the third conductive pattern (145) can be formed and the third region (113) of the active pattern (110) can be removed.

[0095] In one embodiment, during the process of removing the third region (113) of the active pattern (110), the portion of the buffer layer (101) overlapping the third region (113) of the active pattern (110) can be partially etched using the etching material. Accordingly, a trench (TCH) can be formed in the portion of the buffer layer (101) overlapping the third region (113) of the active pattern (110). Meanwhile, although not shown in FIG. 12, during the process of etching the third region (113) of the active pattern (110) and partially etching the portion of the buffer layer (101), the portion of the insulating layer (ISL) exposed by the patterning of the conductive layer (140) may be partially etched.

[0096] Referring to FIG. 13, a flattening layer (105) can be formed on the third conductive pattern (145).

[0097] In one embodiment, the flattening layer (105) may come into contact with the side of the first region (111) and the side of the second region (112). The first region (111) and the second region (112) of the active pattern (110) are spaced apart from each other, and the opening (OPN) of the insulating layer (ISL) overlaps in the portion between the first region (111) and the second region (112), and as the third region (113) of the active pattern (110) is removed, the flattening layer (105) may come into contact with the side of the first region (111) and the side of the second region (112).

[0098] In one embodiment, the flattening layer (105) may come into contact with the buffer layer (101). The flattening layer (105) may come into contact with the trench (TCH) of the buffer layer (101) through the opening (OPN) of the insulating layer (ISL) and the portion between the first region (111) and the second region (112) of the active pattern (110).

[0099] In the method for manufacturing a display device according to a comparative example of the present invention, a third region may not be formed between a first region and a second region of an active pattern. In this case, as the first region and the second region of the active pattern are separated during the process of forming the active pattern and the insulating layer, the first region and the second region of the active pattern may be vulnerable to static electricity introduced from the outside.

[0100] However, in the method for manufacturing a display device (1000) according to an embodiment of the present invention, a third region (113) may be formed between a first region (111) and a second region (112) of an active pattern (110). In this case, as the first region (111) and the second region (112) of the active pattern (110) are physically connected through the third region (113) during the process of forming the active pattern (110) and the insulating layer (ISL), the active pattern (110) may be robust against static electricity introduced from the outside. Additionally, as the third conductive pattern (145) is formed substantially simultaneously and the third region (113) of the active pattern (110) is removed, the first region (111) and the second region (112) of the active pattern (110) are each electrically connected to other components of the display device (1000) through the third conductive pattern (145), and the first region (111) and the second region (112) of the active pattern (110) can be robust against static electricity introduced from the outside.

[0101] Hereinafter, a display device according to an embodiment of the present invention will be described with reference to FIGS. 14 and 15.

[0102] FIG. 14 is a circuit diagram showing a pixel according to one embodiment of the present invention. For example, FIG. 14 may show another example of a pixel (PX) of a display device (1000) of FIG. 1.

[0103] Referring to FIG. 14, a pixel (PX) may include a plurality of transistors (T1, T2, T3, T4, T5, T6, T7, T8, T9), a storage capacitor (CST), a hold capacitor (CHD), and a light-emitting diode (LD). The transistors (T1, T2, T3, T4, T5, T6, T7, T8, T9) may include a first transistor (T1), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), a sixth transistor (T6), a seventh transistor (T7), an eighth transistor (T8), and a ninth transistor (T9).

[0104] The first transistor (T1) is electrically connected between the first power supply voltage line (ELVDD) and the anode electrode of the light-emitting diode (LD), and the gate electrode of the first transistor (T1) can be connected to the first electrode of the storage capacitor (CST). The first transistor (T1) can provide a driving current to the light-emitting diode (LD) corresponding to a data signal provided by the data line (DATA). In other words, the first transistor (T1) can be a driving transistor.

[0105] The second transistor (T2) is connected between the data line (DATA) and the second electrode of the storage capacitor (CST), and can provide the data signal to the second electrode of the storage capacitor (CST) in response to a scan signal provided by the scan line (GW). In other words, the second transistor (T2) may be a switching transistor.

[0106] The third transistor (T3) is connected between the gate electrode and the second electrode of the first transistor (T1), and can compensate the threshold voltage of the first transistor (T1) by diode-connecting the first transistor (T1) in response to a compensation control signal provided by the compensation control line (GC). In other words, the third transistor (T3) can be a compensation transistor.

[0107] A storage capacitor (CST) can be connected between the gate electrode of the first transistor (T1) and the second electrode of the second transistor (T2). The storage capacitor (CST) can maintain a voltage between the gate electrode of the first transistor (T1) and the second electrode of the second transistor (T2).

[0108] The fourth transistor (T4) is connected between the initialization voltage line (VINT) and the first electrode of the storage capacitor (CST), and can provide the initialization voltage provided by the initialization voltage line (VINT) to the gate electrode of the first transistor (T1) in response to the first initialization control signal provided by the first initialization control line (GI). In other words, the fourth transistor (T4) may be a driving initialization transistor.

[0109] The fifth transistor (T5) is connected between the reference voltage line (VREF) and the second electrode of the storage capacitor (CST), and can provide the reference voltage provided by the reference voltage line (VREF) to the second electrode of the storage capacitor (CST) in response to the compensation control signal. In other words, the fifth transistor (T5) can be a reference transistor.

[0110] The ninth transistor (T9) may be connected between the first power supply voltage line (ELVDD) and the first electrode of the first transistor (T1), and the sixth transistor (T6) may be connected between the second electrode of the first transistor (T1) and the anode electrode of the light-emitting diode (LD). The ninth transistor (T9) and the sixth transistor (T6) may provide the driving current to the anode electrode of the light-emitting diode (LD) in response to the first light-emitting control signal provided by the first light-emitting control line (EM1) and the second light-emitting control signal provided by the second light-emitting control line (EM2), respectively. In other words, the ninth transistor (T9) and the sixth transistor (T6) may each be a light-emitting control transistor. In one embodiment, the first light-emitting control signal and the second light-emitting control signal may have substantially the same signal waveform and different signal timings.

[0111] The seventh transistor (T7) is connected between the initialization voltage line (VINT) and the anode electrode of the light-emitting diode (LD), and can provide the initialization voltage to the anode electrode of the light-emitting diode (LD) in response to a second initialization control signal provided by the second initialization control line (GB2). In other words, the seventh transistor (T7) may be a diode initialization transistor.

[0112] The eighth transistor (T8) is connected between the bias voltage line (VBIAS) and the first electrode of the first transistor (T1), and can provide the bias voltage provided by the bias voltage line (VBIAS) to the first electrode of the first transistor (T1) in response to the third initialization control signal provided by the third initialization control line (GB3). In one embodiment, the third initialization control signal may be the same as the second initialization control signal.

[0113] In one embodiment, the first electrode and the second electrode of each of the transistors (T1, T2, T3, T4, T5, T6, T7, T8, T9) may each be a source electrode and a drain electrode. However, the present invention is not limited thereto, and the first electrode and the second electrode of each of the transistors (T1, T2, T3, T4, T5, T6, T7, T8, T9) may each be a drain electrode and a source electrode.

[0114] A hold capacitor (CHD) can be connected between the first power supply voltage line (ELVDD) and the second electrode of the storage capacitor (CST). It can maintain the voltage between the first power supply voltage line (ELVDD) and the second electrode of the storage capacitor (CST).

[0115] A light-emitting diode (LD) can be connected between the second electrode of the sixth transistor (T6) and the second power supply voltage line (ELVSS). The light-emitting diode (LD) can emit light based on the driving current.

[0116] In this embodiment, as the scan line (GW) providing the scan signal controlling the second transistor (T2) and the compensation control line (GC) providing the compensation control signal controlling the third transistor (T3) are separated, sufficient time for the threshold voltage compensation of the first transistor (T1) by the third transistor (T3) in high frequency mode can be secured, and accordingly, the pixel (PX) can be driven in a variable frequency mode including a low frequency mode and a high frequency mode.

[0117] FIG. 15 is a layout diagram showing the pixel (PX) of FIG. 14. FIG. 16 is a cross-sectional view showing a display device (1000) cut along the line II-II' of FIG. 15.

[0118] Referring to FIGS. 14, 15, and 16, a display device (1000) may include a substrate (100), a buffer layer (101), an active pattern (110), a gate insulating layer (102), a first conductive pattern, a first interlayer insulating layer (103), a second conductive pattern, a second interlayer insulating layer (104), a third conductive pattern (145), a first planarization layer (105), a fourth conductive pattern (190), a second planarization layer (107), a first electrode (150), a pixel defining film (106), a light-emitting layer (160), a second electrode (170), and an encapsulation layer (180). In the display device (1000) described with reference to FIGS. 14, 15, and 16, descriptions of configurations that are substantially identical or similar to those of the display device (1000) described with reference to FIGS. 2, 3, and 4 are omitted.

[0119] In one embodiment, the first region (111) of the active pattern (110) may be the drain electrode of the fourth transistor (T4), and the second region (112) of the active pattern (110) may be the drain electrode of the fifth transistor (T5). However, the present invention is not limited thereto, and in another embodiment, the first region (111) of the active pattern (110) may be the source electrode of the fourth transistor (T4), and the second region (112) of the active pattern (110) may be the source electrode of the fifth transistor (T5).

[0120] The first conduction pattern may include first to ninth gate electrodes and a first hold electrode. The active pattern (110) may form first to ninth transistors (T1, T2, T3, T4, T5, T6, T7, T8, T9) together with the first to ninth gate electrodes.

[0121] The second conduction pattern may include a storage electrode and a second hold electrode. The storage electrode may overlap the first gate electrode and form a storage capacitor (CST) together with the first gate electrode. For example, the first gate electrode and the storage electrode may be the first electrode and the second electrode of the storage capacitor (CST), respectively. The second hold electrode may overlap the first hold electrode and form a hold capacitor (CHD) together with the first hold electrode.

[0122] The third challenge pattern (145) may include a scan line (GW), a compensation control line (GC), a first initialization control line (GI), an initialization voltage line (VINT), a reference voltage line (VREF), a first light emission control line (EM1), a second light emission control line (EM2), a second initialization control line (GB), and a bias voltage line (VBIAS).

[0123] The scan line (GW) can be extended in a first direction (DR1). The scan line (GW) can be electrically connected to the second gate electrode through a contact hole formed in the second interlayer insulating layer (104) and the first interlayer insulating layer (103).

[0124] The compensation control line (GC) can be extended in a first direction (DR1). The compensation control line (GC) can be electrically connected to the third and fifth gate electrodes, respectively, through contact holes formed in the second interlayer insulating layer (104) and the first interlayer insulating layer (103).

[0125] The first initialization control line (GI) can be extended in the first direction (DR1). The first initialization control line (GI) can be electrically connected to the fourth gate electrode through a contact hole formed in the second interlayer insulating layer (104) and the first interlayer insulating layer (103).

[0126] The initialization voltage line (VINT) can be extended in a first direction (DR1). The initialization voltage line (VINT) can be electrically connected to an active pattern (110) through a contact hole formed in the second interlayer insulating layer (104), the first interlayer insulating layer (103), and the gate insulating layer (102).

[0127] The horizontal reference voltage line (VREF1) can be extended in a first direction (DR1). The horizontal reference voltage line (VREF1) can be electrically connected to an active pattern (110) through contact holes formed in the second interlayer insulating layer (104), the first interlayer insulating layer (103), and the gate insulating layer (102).

[0128] The first light emission control line (EM1) can be extended in the first direction (DR1). The first light emission control line (EM1) can be electrically connected to the ninth gate electrode through a contact hole formed in the second interlayer insulating layer (104) and the first interlayer insulating layer (103).

[0129] The second light emission control line (EM2) can be extended in the first direction (DR1). The second light emission control line (EM2) can be electrically connected to the sixth gate electrode through a contact hole formed in the second interlayer insulating layer (104) and the first interlayer insulating layer (103).

[0130] The second initialization control line (GB) can be extended in the first direction (DR1). The second initialization control line (GB) can be electrically connected to the seventh and eighth gate electrodes, respectively, through contact holes formed in the second interlayer insulating layer (104) and the first interlayer insulating layer (103).

[0131] The bias voltage line (VBIAS) can be extended in a first direction (DR1). The bias voltage line (VBIAS) can be electrically connected to an active pattern (110) through contact holes formed in the second interlayer insulating layer (104), the first interlayer insulating layer (103), and the gate insulating layer (102).

[0132] The third conductive pattern (145) can contact the first region (111) and the second region (112), respectively, through the first contact hole (CNT1) and the second contact hole (CNT2). In this case, the first region (111) and the second region (112) of the active pattern (110) can each be electrically connected to other components of the display device (1000). In one embodiment, the first region (111) of the active pattern (110) can be electrically connected to an initial voltage line (VINT), and the second region (112) of the active pattern (110) can be electrically connected to a horizontal reference voltage line (VREF1).

[0133] The fourth conductive pattern (190) may be disposed on the first flattening layer (105). The fourth conductive pattern (190) may include a data line (DATA), a first power voltage line (ELVDD), and a longitudinal reference voltage line (VREF2). The fourth conductive pattern (190) may be formed of a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc.

[0134] The data line (DATA) can be extended in a second direction (DR2). The data line (DATA) can be electrically connected to an active pattern (110) through contact holes formed in the first flattening layer (105), the second interlayer insulating layer (104), the first interlayer insulating layer (103), and the gate insulating layer (102).

[0135] The first power voltage line (ELVDD) can be extended in a second direction (DR2). The first power voltage line (ELVDD) can be electrically connected to a third conductive pattern (145) through a contact hole formed in the first flattening layer (105).

[0136] The vertical reference voltage line (VREF2) can be extended in a second direction (DR2). The vertical reference voltage line (VREF2) can be electrically connected to the horizontal reference voltage line (VREF1) through a contact hole formed in the first flattening layer (105). The horizontal reference voltage line (VREF1) and the vertical reference voltage line (VREF2) can form a reference voltage line (VREF).

[0137] The second flattening layer (107) may be disposed between the fourth conductive pattern (190) and the first electrode (150). The second flattening layer (107) may have a substantially flat upper surface that sufficiently covers the fourth conductive pattern (190) on the first flattening layer (105) and does not create a step around the fourth conductive pattern (190). The second flattening layer (107) may be formed from an organic insulating material such as a photoresist, an acrylic resin, a polyimide resin, a polyamide resin, or a siloxane-based resin.

[0138] In the present embodiment, with reference to FIG. 15, the first region (111) of the active pattern (110) is described as the drain electrode of the fourth transistor (T4) and the second region (112) of the active pattern (110) is described as the drain electrode of the fifth transistor (T5), but the present invention is not limited thereto. In another embodiment, the first region (112) of the active pattern (110) may be the drain electrode of the first transistor (T1) and the second region (112) of the active pattern (110) may be the drain electrode of the second transistor (T2). Industrial applicability

[0139] A display device according to exemplary embodiments of the present invention can be applied to a display device including a computer, laptop, mobile phone, smartphone, smartpad, PMP, PDA, MP3 player, etc.

[0140] Although a display device and a method for manufacturing a display device according to exemplary embodiments of the present invention have been described above with reference to the drawings, the described embodiments are exemplary and may be modified and changed by those skilled in the art without departing from the technical spirit of the present invention as described in the following claims. Explanation of the symbols

[0141] 100: Substrate 101: Buffer layer 102: Gate insulating layer 103: First interlayer insulating layer 104: Second interlayer insulation layer 105: Flattening layer 110: Active Pattern 111: Area 1 112: Area 2 113: Area 3 140: Challenge Layer 145: Third Challenge Pattern ISL: Insulation layer

Claims

Claim 1 A method for manufacturing a display device, comprising: forming an active pattern on a substrate including a first region, a second region spaced apart from the first region, and a third region located between the first region and the second region; forming an insulating layer on the active pattern; forming a first contact hole in the insulating layer that exposes a portion of the first region, a second contact hole that exposes a portion of the second region, and an opening that exposes the third region; substantially simultaneously forming a conductive pattern on the insulating layer that fills the first and second contact holes and removes the third region; and forming a planarization layer on the conductive pattern. Claim 2 A method for manufacturing a display device according to claim 1, wherein the step of substantially simultaneously forming the conductive pattern and removing the third region comprises: forming the first and second contact holes and a conductive layer filling the opening on the insulating layer; and etching a portion of the conductive layer filling the opening and the third region. Claim 3 A method for manufacturing a display device according to claim 1, wherein the planarization layer contacts the side of the first region and the side of the second region. Claim 4 A method for manufacturing a display device according to claim 1, further comprising the step of forming a buffer layer on the substrate prior to the step of forming the active pattern. Claim 5 A method for manufacturing a display device, wherein, in claim 4, the planarization layer contacts the buffer layer. Claim 6 A method for manufacturing a display device according to claim 4, wherein the step of substantially simultaneously forming the challenge pattern and removing the third region includes the step of partially etching a portion of the buffer layer that overlaps the third region. Claim 7 A method for manufacturing a display device according to claim 1, wherein the first contact hole, the second contact hole, and the opening are formed substantially simultaneously. Claim 8 A method for manufacturing a display device according to claim 1, wherein the first region and the second region are physically separated after the step of substantially simultaneously forming the challenge pattern and removing the third region. Claim 9 A method for manufacturing a display device according to claim 1, wherein the insulating layer comprises a gate insulating layer, a first interlayer insulating layer, and a second interlayer insulating layer stacked on the active pattern. Claim 10 A display device comprising: an active pattern disposed on a substrate and including a first region and a second region spaced apart from the first region; an insulating layer disposed on the active pattern and having a first contact hole and a second contact hole that respectively expose a portion of the first region and a portion of the second region; a conductive pattern disposed on the insulating layer and contacting the first region and the second region respectively through the first contact hole and the second contact hole; and a flattening layer disposed on the conductive pattern and contacting a side of the first region and a side of the second region, wherein the insulating layer has an opening that overlaps a portion between the first region and the second region. Claim 11 A display device according to claim 10, further comprising a buffer layer disposed between the substrate and the active pattern. Claim 12 delete Claim 13 In claim 11, the flattening layer contacts the buffer layer through the opening, a display device. Claim 14 A display device according to claim 11, wherein the buffer layer has a trench overlapping the portion between the first region and the second region. Claim 15 A display device according to claim 10, further comprising: a driving transistor that generates a driving current; a light-emitting diode that emits light based on the driving current; a first initialization transistor that provides a first initialization voltage to the gate electrode of the driving transistor; and a second initialization transistor that provides a second initialization voltage different from the first initialization voltage to the anode electrode of the light-emitting diode. Claim 16 A display device according to claim 15, wherein the first region is the source electrode of the first initialization transistor and the second region is the source electrode of the second initialization transistor. Claim 17 A display device according to claim 15, further comprising: a first initialization voltage line that transmits the first initialization voltage and is electrically connected to the first area; and a second initialization voltage line that transmits the second initialization voltage and is electrically connected to the second area. Claim 18 A display device according to claim 10, further comprising: a driving transistor that generates a driving current; a storage capacitor comprising a first electrode connected to the gate electrode of the driving transistor and a second electrode superimposed on the first electrode; a light-emitting diode that emits light based on the driving current; an initialization transistor that provides an initialization voltage to the first electrode of the storage capacitor; and a reference transistor that provides a reference voltage to the second electrode of the storage capacitor. Claim 19 A display device according to claim 18, wherein the first region is the drain electrode of the initialization transistor and the second region is the drain electrode of the reference transistor. Claim 20 A display device according to claim 18, further comprising: an initial voltage line that transmits the initial voltage and is electrically connected to the first region; and a reference voltage line that transmits the reference voltage and is electrically connected to the second region.

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