Nanosecond pulser pulse generation

Abstract

Some embodiments include a high-voltage pulsing power supply. The high-voltage pulsing power supply includes: a high-voltage pulser that provides as output a pulse having an amplitude greater than about 1 kV, a pulse width greater than about 1 μs, and a pulse repetition frequency greater than about 20 kHz; a plasma chamber; and an electrode disposed within the plasma chamber that is electrically coupled to the output of the high-voltage pulser to generate a pulsing electric field within the chamber.

Description

Technology Field

[0001] This application claims priority to U.S. preliminary patent application No. 62 / 711,464, filed on July 27, 2018, under the title “Nanosecond pulser system,” which is incorporated by reference in its entirety.

[0002] This application claims priority to U.S. preliminary patent application No. 62 / 711,334 filed on July 27, 2018, titled “Nanosecond pulser thermal management,” which is incorporated by reference in its entirety.

[0003] This application claims priority to U.S. preliminary patent application No. 62 / 711,457, filed on July 27, 2018, titled “Pulse generation of a nanosecond pulser,” which is incorporated by reference in its entirety.

[0004] This application claims priority to U.S. preliminary patent application No. 62 / 711,347, filed on July 27, 2018, under the title “Nanosecond pulser ADC system,” which is incorporated by reference in its entirety.

[0005] This application claims priority to U.S. Preliminary Patent Application No. 62 / 711,467 “Edge Ring Power System” filed on July 27, 2018, which is incorporated by reference in its entirety.

[0006] This application claims priority to U.S. preliminary patent application No. 62 / 711,406, filed on July 27, 2018, under the title “Nanosecond pulser bias compensation,” which is incorporated by reference in its entirety.

[0007] This application claims priority to U.S. preliminary patent application No. 62 / 711,468, filed on July 27, 2018, under the title “Nanosecond pulser control module,” which is incorporated by reference in its entirety.

[0008] This application claims priority to U.S. preliminary patent application No. 62 / 711,523 filed on August 10, 2018, titled “Plasma sheath control for RF plasma reactor,” which is incorporated by reference in its entirety.

[0009] This application claims priority to U.S. preliminary patent application No. 62 / 789,523 filed on January 1, 2019, titled “Efficient nanosecond pulser with source and sink functions for plasma control applications,” the entirety of which is incorporated by reference.

[0010] This application claims priority to U.S. preliminary patent application No. 62 / 789,526 filed on January 1, 2019, titled “Efficient energy recovery of nanosecond pulse circuits,” the entirety of which is incorporated by reference.

[0011] This application claims priority to U.S. non-preliminary patent application No. 16 / 523,840 filed on July 26, 2019, titled “Nanosecond pulser bias compensation”, which is incorporated by reference in its entirety. Background Technology

[0012] Generating high-voltage pulses with fast rise and / or fall times is a difficult task. For example, to achieve fast rise and / or fall times (e.g., less than approximately 50ns) for high-voltage pulses (e.g., greater than about 5kV), the slope of the pulse rise and / or fall must be very steep (e.g., 10 11(Exceeding V / s). Such steep rise and / or fall times are very difficult to generate, especially in circuits driving loads with low capacitance. These pulses can be difficult to generate using standard electrical components, particularly in a compact manner; and / or as pulses with variable pulse width, voltage, and repetition rate; and / or within applications with capacitive loads, such as plasma. Some plasma deposition systems may be unable to generate similar pulses and may not be able to produce wafers efficiently.

[0013] Some embodiments include a high voltage pulser that provides as output a pulse having an amplitude greater than about 1 kV, a pulse width less than about 1 μs, and a pulse repetition frequency greater than about 20 kHz; a plasma chamber; and a high voltage pulsing power device comprising an electrode disposed within the plasma chamber that is electrically coupled to the output of the high voltage pulser to generate an electric field within the plasma chamber.

[0014] In some embodiments, the inductance between the output of the high-voltage pulser and the electrode may be less than about 10 μH. In some embodiments, the capacitance between the output of the high-voltage pulser and ground may be less than about 10 nF.

[0015] In some embodiments, the high voltage pulsing power supply may further include a control module that measures the voltage of the output pulse.

[0016] In some embodiments, the high voltage pulsing power supply may further include a bias capacitor disposed between the high voltage pulser and the electrode; and a bias compensation power supply electrically coupled to the high voltage pulser and the electrode, and the bias compensation power supply generates a voltage across the bias capacitor.

[0017] In some embodiments, the high voltage pulsing power supply may further include a resistive output stage electrically coupled to the high voltage pulser and the electrode to remove charge from the load on a rapid time scale.

[0018] In some embodiments, the resistive output terminal includes an inductor and a capacitor arranged in series, and the inductor has an inductance smaller than about 200 μH.

[0019] In some embodiments, the high-voltage pulsing power supply may further include an energy recovery circuit electrically coupled to the high-voltage pulser and the electrode to remove charge from the load on a rapid time scale.

[0020] In some embodiments, the high-voltage pulsing power supply may further include a control module electrically coupled to the high-voltage pulser that generates a low-voltage signal controlling the pulse width and the pulse repetition frequency of the output pulse.

[0021] In some embodiments, the high voltage pulsing power supply may further include a second high voltage pulser that provides as output a pulse having an amplitude greater than about 1 kV, a pulse width less than about 1 μs, and a pulse repetition frequency greater than about 20 kHz; and a second electrode disposed within the plasma chamber that is electrically coupled to the output of the second high voltage pulser to generate a pulsing electric field within the plasma chamber near the second electrode.

[0022] In some embodiments, the pulse from the high voltage pulser and the pulse from the second high voltage pulser may differ in at least one of the voltage, pulse width, and pulse repetition frequency.

[0023] In some embodiments, the high voltage pulsing power supply may further include a thermal management subsystem comprising one or more switch cooling plates and one or more transformer core cooling plates, and the high voltage pulser includes a plurality of switches coupled to the one or more switch cooling plates and a transformer coupled to the one or more transformer core cooling plates.

[0024] In some embodiments, the thermal management subsystem may include a fluid flowing through the switch cooling plate and the core cooling plate.

[0025] In some embodiments, the high-voltage pulsing power supply has a volume dimension of 1 m 3 A smaller enclosure is further included, wherein the high voltage pulser is disposed within the enclosure, and at least three of a thermal management system, a control system, a bias capacitor, a bias compensation power supply, a second nanosecond pulser, a resistive output terminal, and an energy recovery circuit are disposed within the enclosure. In one embodiment, the maximum electric field between any two components inside the enclosure is less than about 20 MV / m.

[0026] Some embodiments include a high-voltage pulser that provides as output a pulse having an amplitude greater than about 1 kV, a pulse width less than about 1 μs, and a pulse repetition frequency greater than about 20 kHz; a plasma chamber; and a high-voltage pulsing power supply including an electrode disposed within the plasma chamber that is electrically coupled to the output of the high-voltage pulser to generate an electric field within the plasma chamber. In some embodiments, the high-voltage pulsing power supply may further include a control module electrically coupled to the high-voltage pulser, wherein the control module measures the voltage of the pulse at the electrode and the control module modifies at least one of the voltage, pulse width, and pulse repetition frequency of the pulse in response to the measured voltage. In some embodiments, the high-voltage pulsing power supply may further include a thermal management subsystem comprising a plurality of cooling plates coupled to the high-voltage pulser.

[0027] In some embodiments, the high voltage pulser comprises a plurality of switches; and a transformer having a transformer core coupled to the plurality of switches and the output. In some embodiments, the plurality of cooling plates comprises: one or more switch cooling plates coupled to the plurality of switches; and one or more transformer core cooling plates coupled to the transformer core.

[0028] In some embodiments, the thermal management subsystem includes a fluid flowing through at least one of the plurality of cooling plates.

[0029] In some embodiments, the control module measures one or more parameters of the thermal management subsystem and stops the high voltage pulser from outputting a pulse if one or more of the parameters is out of tolerance.

[0030] Some embodiments include a first high-voltage pulser providing a first output pulse having a first amplitude greater than about 1 kV, a first pulse width less than about 1 μs, and a first pulse repetition frequency greater than about 20 kHz; a second high-voltage pulser providing a second output pulse having a second amplitude greater than about 1 kV, a second pulse width less than about 1 μs, and a second pulse repetition frequency greater than about 20 kHz; and a high-voltage pulsing power supply comprising a plasma chamber. In some embodiments, a first electrode may be disposed within the plasma chamber electrically coupled to the first output of the first high-voltage pulser; and a second electrode may be disposed within the plasma chamber electrically coupled to the second output of the second high-voltage pulser. In some embodiments, the high-voltage pulsing power supply comprises a first bias capacitor disposed between the first high-voltage pulser and the first electrode; and may further include a second bias capacitor disposed between the second high voltage pulser and the second electrode.

[0031] In some embodiments, the high voltage pulsing power supply further comprises a first bias compensation power supply electrically coupled to the first high voltage pulser and the first electrode—the first bias compensation power supply generates a voltage across the first bias capacitor—; and a second bias compensation power supply electrically coupled to the second high voltage pulser and the second electrode—the second bias compensation power supply generates a voltage across the second bias capacitor.

[0032] In some embodiments, the high voltage pulsing power supply may further include a thermal management subsystem comprising a plurality of cooling plates coupled to the first high voltage pulser and the second high voltage pulser.

[0033] In some embodiments, one or both of the first bias capacitor or the second bias capacitor have a capacitance greater than about 1 nF.

[0034] Some embodiments of the present invention include a first nanosecond pulser; a second nanosecond pulser; an interconnection board coupled with the first nanosecond pulser and the second nanosecond pulser; a resistive output terminal coupled with the interconnection board and ground—the resistive output terminal comprises at least a resistor and / or an inductor—; and a chamber interface board coupled with the interconnection board through a capacitor.

[0035] In some embodiments, the nanosecond pulse generating system outputs a pulse having an amplitude of at least 8 kV.

[0036] In some embodiments, the nanosecond pulse generating system outputs a pulse having a frequency of 10 kHz or higher.

[0037] In some embodiments, the nanosecond pulse generating system outputs pulses with 30 kW or power.

[0038] In some embodiments, the resistive output terminal includes a resistance of 140 ohms.

[0039] In some embodiments, the resistive output terminal includes a plurality of resistors having a coupling resistance of 140 ohms.

[0040] In some embodiments, the resistive output terminal includes an inductor having an inductance of 15 μH.

[0041] In some embodiments, the resistive output terminal includes a plurality of inductors having a combined inductance of 15 μH.

[0042] Some embodiments include a nanosecond pulser comprising a plurality of switches; one or more transformers; an output configured to output a high voltage waveform with an amplitude greater than 2 kV and a frequency greater than 1 kHz; and an ADC control module for detecting the output waveform:

[0043] A nanosecond pulser system is disclosed. In some embodiments, the nanosecond pulser system may include a nanosecond pulser, a pulser output, and a control system. In some embodiments, the nanosecond pulser comprises: a pulser input; a high-voltage DC power supply; one or more solid-state switches coupled to the high-voltage DC power supply and the pulser input—the one or more solid-state switches switching the high-voltage DC power supply based on an input pulse provided by the pulser input—; one or more transformers coupled to the one or more switches; and a pulser output coupled to one or more transformers that outputs a high-voltage waveform having an amplitude greater than about 2 kV and a pulse repetition frequency greater than about 1 kHz based on the pulser input. In some embodiments, the control system is coupled to the nanosecond pulser at a measurement point, and the control system provides the input pulse to the pulser input.

[0044] In some embodiments, the measurement point includes a point between the transformer and the pulser output.

[0045] In some embodiments, the nanosecond pulser system includes an electrode coupled with the pulse output; and the measurement point is at the electrode.

[0046] In some embodiments, the control system measures the voltage at a measurement point and adjusts the voltage, pulse repetition frequency, or duty cycle of the input pulse based on the measured voltage.

[0047] In some embodiments, the control system measures the pulse repetition frequency at a measurement point and adjusts the pulse repetition frequency of the input pulse based on the measured pulsing repetition frequency.

[0048] In some embodiments, the input pulse comprises a first burst comprising a first plurality of low voltage pulses, each comprising a first plurality of low voltage pulses having a first pulse width; the input pulse comprises a second burst comprising a second plurality of low voltage pulses, each comprising a second plurality of low voltage pulses having a second pulse width; and the second pulse width is greater than the first pulse width.

[0049] In some embodiments, the control system receives input data specifying a voltage and pulse repetition frequency corresponding to a desired high voltage waveform; compares an output pulse waveform measured at a measurement point with the desired high voltage waveform; and determines an adjustment for the pulse input to generate the desired high voltage waveform.

[0050] In some embodiments, the control system includes a voltage divider that reduces a high voltage waveform by 1,000 times.

[0051] In some embodiments, the control system includes an analog-to-digital converter that converts a measured high-voltage waveform into a digital signal.

[0052] In some embodiments, the nano second pulser system includes a metal shield placed between the nanosecond pulser and the control system.

[0053] In some embodiments, the nanosecond pulser includes a resistive output terminal, and the measurement point is both ends of the resistance of the resistive output terminal.

[0054] A nanosecond pulser system is disclosed. In some embodiments, the nanosecond pulser system comprises a nanosecond pulser,

[0055] A nanosecond pulser having a pulse output that outputs a high-voltage waveform including multiple bursts (each burst includes multiple pulses having an amplitude greater than 2 kV and a pulse repetition frequency greater than 1 kHz), and

[0056] A control system that controls various characteristics of a high-voltage waveform in real time, including the number of pulses, pulse repetition frequency, pulse width, and pulse voltage of each burst.

[0057] It may include.

[0058] In some embodiments, the pulser system controls at least one characteristic of a high voltage waveform with a resolution of less than about 1 μs.

[0059] In some embodiments, the pulser system is controlled in the period between pulses with an accuracy of less than about 10 μs.

[0060] In some embodiments, the control system controls the number of high voltage waveform characteristics in response to a plasma treatment recipe.

[0061] In some embodiments, the plasma treatment recipe includes a plurality of stages, and each stage is associated with an ion current, chamber pressure, and gas mixture.

[0062] In some embodiments, the plasma treatment recipe corresponds to an electric field or voltage on the wafer surface.

[0063] In some embodiments, the high voltage waveform comprises a first burst including a first plurality of pulses, each of the first plurality of pulses having a first pulse width; the high voltage waveform comprises a second burst including a second plurality of pulses, each of the second plurality of pulses having a second pulse width; and the second pulse width is greater than the first pulse width.

[0064] In some embodiments, the nanosecond pulser includes a transformer and an output that outputs a high voltage waveform; and a control system is coupled to the nanosecond pulser at a point between the transformer and the pulser output.

[0065] In some embodiments, the control system includes a voltage divider and a high-speed analog-to-digital converter.

[0066] Some embodiments include a nanosecond pulser having a pulser output that outputs a pulse with an amplitude greater than 2 kV and a pulse repetition frequency greater than 1 kHz; a plurality of sensors measuring environmental characteristics of the nanosecond pulser system - each of the plurality of sensors providing a sensor signal representing each environmental characteristic -; a sensor providing an electronic sensor signal representing a physical characteristic of the nanosecond pulser system; and a nanosecond pulser system comprising an interlock electrically coupled to the sensor and the nanosecond pulser that stops the operation of the nanosecond pulser when the electronic sensor signal exceeds a first threshold value.

[0067] In some embodiments, the nanosecond pulser system may further include a control module electrically coupled to a sensor that stops the operation of the nanosecond pulser when the electronic sensor signal is higher than a second threshold value, and the second threshold value is different from the first threshold value.

[0068] In some embodiments, the nanosecond pulser system may also include a liquid cooling subsystem. In some embodiments, the sensor includes a liquid flow sensor disposed within the liquid cooling subsystem; a first threshold includes a first flow rate; and a second threshold includes a second flow rate greater than the first flow rate.

[0069] In some embodiments, the nanosecond pulser system may also include a cooling subsystem. In some embodiments, one of the sensors includes a temperature sensor placed within the cooling subsystem; a first threshold includes a first temperature; and a second threshold includes a second temperature lower than the first temperature.

[0070] In some embodiments, the nanosecond pulser system may also further include a cooling subsystem comprising a liquid coolant; and a temperature sensor for measuring the temperature of the liquid coolant.

[0071] These exemplary embodiments are mentioned not to limit or restrict the disclosure, but to provide examples to aid understanding. Additional embodiments are discussed in the detailed description, and further description is provided. The benefits provided by one or more of the various embodiments may be further understood by reviewing this specification or by practicing one or more of the presented embodiments. Brief explanation of the drawing

[0072] These and other features, aspects, and advantages of the present disclosure are better understood when reading the following detailed description with reference to the accompanying drawings: FIG. 1 is a circuit diagram illustrating a nanosecond pulser according to some embodiments. Figure 2 illustrates an example waveform generated by a nanosecond pulser. FIG. 3 is another circuit diagram illustrating a nanosecond pulser according to some embodiments. FIG. 4 is a block diagram illustrating a space-variable wafer bias power system according to some embodiments. FIG. 5 is a circuit diagram illustrating a high-voltage power system having a plasma load according to some embodiments. FIG. 6 is a circuit diagram illustrating a high-voltage power system having a plasma load according to some embodiments. FIG. 7 is a block diagram illustrating a high-voltage switch having insulation power according to some embodiments. FIG. 8 is a block diagram illustrating an ADC control system for a nanosecond pulser system according to some embodiments. FIG. 9 is a functional block diagram illustrating a nanosecond pulser system according to some embodiments. FIG. 10 is a block diagram illustrating a thermal management system according to some embodiments. FIG. 11 illustrates an embodiment and / or configuration of a switch cooling plate system according to some embodiments. FIG. 12 illustrates an embodiment and / or arrangement of a cooling plate according to some embodiments. FIG. 13 illustrates an example and / or arrangement of a cooling plate according to some embodiments. FIG. 14 illustrates an example and / or arrangement of a cooling plate according to some embodiments. FIG. 15 is a block diagram illustrating the flowchart of a process according to some embodiments. FIG. 16 illustrates an exemplary computational system for performing functions to facilitate the implementation of the embodiments described in this specification. Specific details for implementing the invention

[0073] A nanosecond pulse generating system is disclosed. In some embodiments, the nanosecond pulse generating system may provide a burst of pulses having an amplitude of 2 kV or more to a plasma chamber. In some embodiments, the nanosecond pulse generating system may provide a waveform having a pulse repetition frequency greater than 10 kHz. In some embodiments, the nanosecond pulse generating system may include one or more nanosecond pulsers coupled to an NSP interconnect board and / or a resistive output terminal.

[0074] In some embodiments, the high-voltage nanosecond pulser system can pulse voltage with an amplitude of about 2 kV to about 40 kV. In some embodiments, the high-voltage nanosecond pulser system can switch at a pulse repetition frequency of up to about 500 kHz or higher. In some embodiments, the high-voltage nanosecond pulser system can provide a single pulse of varying pulse widths from about 50 nanoseconds to about 1 microsecond. In some embodiments, the high-voltage nanosecond pulser system can switch at a frequency greater than about 10 kHz. In some embodiments, the high-voltage nanosecond pulser system can operate with a rise time of less than about 20 ns up to about 200 ns.

[0075] In some embodiments, the high-voltage nanosecond pulser system may include a plurality of components or subsystems. These may include one or more of a resistive output terminal (e.g., resistive output terminal (102)), an energy recovery circuit (e.g., energy recovery circuit (165)), a spatially variable wafer bias system (e.g., spatially variable wafer bias power system (400)), a bias compensation circuit (e.g., bias compensation circuit (104, 514 or 614)), a control module (e.g., controller (825)), a first ADC (e.g., first ADC (820)), a multi-RAM second ADC (e.g., second ADC (845)), a plurality of sensors, a thermal management system (e.g., thermal management system (1000)), etc.

[0076] FIG. 1 is a circuit diagram illustrating a nanosecond pulser system (100) according to some embodiments. The nanosecond pulser system (100) may be implemented within a high-voltage nanosecond pulser system. The nanosecond pulser system (100) may be generalized into five stages (these stages may be divided into other stages or generalized into fewer stages and / or may or may not include the components illustrated in the drawing). The nanosecond pulser system (100) includes a pulser and transformer stage (101), a resistive output stage (102), a lead stage (103), a DC bias compensation circuit (104), and a load stage (106).

[0077] In some embodiments, the nanosecond pulser system (100) can generate pulses from a power source having a voltage greater than 2 kV, a rise time less than about 20 ns, and a frequency greater than about 10 kHz.

[0078] In some embodiments, the pulser and transformer stage (101) can generate multiple high-voltage pulses having high frequency and fast rise and fall times. In all illustrated circuits, the high-voltage pulse may include a nanosecond pulse.

[0079] In some embodiments, the pulser and transformer stage (101) may include one or more solid-state switches (S1) (e.g., solid-state switches such as IGBT, MOSFET, SiC MOSFET, SiC junction transistor, FET, SiC switch, GaN switch, photoconductive switch, etc.), one or more snubber resistors (R3), one or more snubber diodes (D4), one or more snubber capacitors (C5), and / or one or more freewheeling diodes (D2). One or more switches and / or circuits may be arranged in parallel or in series.

[0080] In some embodiments, the load terminal (106) may represent an effective circuit for a plasma deposition system, a plasma etching system, or a plasma sputtering system. Capacitance (C2) may represent the capacitance of a dielectric material on which a wafer may be placed, or capacitance (C2) may represent the capacitance between an electrode separated by a dielectric material and a wafer. Capacitance (C3) may represent the sheath capacitance of the plasma on the wafer. Capacitance (C9) may represent the capacitance within the plasma between the chamber wall and the upper surface of the wafer. Current sources (I2) and current sources (I1) may represent ion currents through the plasma sheath.

[0081] In some embodiments, the resistive output terminal (102) may include one or more inductive elements represented by an inductor (L1) and / or an inductor (L5). For example, the inductor (L5) may represent the parasitic inductance of the leads at the resistive output terminal (102). The inductor (L1) may be configured to minimize the power flowing directly from the pulser and transformer terminal (101) to the resistor (R1).

[0082] In some embodiments, the resistor (R1) can dissipate charge from the load terminal (106) over a rapid time scale, for example (e.g., a time scale of 1 ns, 10 ns, 50 ns, 100 ns, 250 ns, 500 ns, 1,000 ns, etc.). The resistance of the resistor (R1) is such that the pulse across the load terminal (106) has a rapid falling time (t f It can be low to ensure having ).

[0083] In some embodiments, the resistor (R1) may include a plurality of resistors arranged in series and / or parallel. The capacitor (C11) may represent the stray capacitance of the resistor (R1) including the capacitance of the series and / or parallel resistors. For example, the stray capacitance of the capacitor (C11) may be 5nF, 2nF, 1nF, 500pF, 250pF, 100pF, 50pF, 10pF, less than 1pF, etc. For example, the stray capacitance of the capacitor (C11) may be smaller than the load capacitance, such as being smaller than the capacitance of C2, C3 and / or C9.

[0084] In some embodiments, a plurality of pulser and transformer terminals (101) may be arranged in parallel and coupled to a resistive output terminal (102) across an inductor (L1) and / or a resistor (R1). Each of the plurality of pulser and transformer terminals (101) may also include a diode (D1) and / or a diode (D6).

[0085] In some embodiments, capacitor (C8) may represent the stray capacitance of the blocking diode (D1). In some embodiments, capacitor (C4) may represent the stray capacitance of the diode (D6).

[0086] In some embodiments, the DC bias compensation circuit (104) may include a DC voltage source (V1) that can be used to bias the output voltage positively or negatively. In some embodiments, a capacitor (C12) isolates / separates the DC bias voltage from the resistive output terminal and other circuit elements. Potential movement from one part of the circuit to another is possible. In some applications, this potential movement is used to hold the wafer in place. A resistor (R2) can protect / isolate the DC bias power supply from the high-voltage pulsed output at the pulser and transformer terminal (101).

[0087] In this example, the DC bias compensation circuit (104) is a passive bias compensation circuit and may include a bias compensation diode (D1) and a bias compensation capacitor (C15). The bias compensation diode (C15) may be arranged in series with the offset supply voltage (V1). The bias compensation capacitor (C15) may be placed on either or both of the offset supply voltage (V1) and the resistor (R2). The bias compensation capacitor (C15) may have a capacitance of less than 100 nH to 100 μF, such as, for example, about 100 μF, 50 μF, 25 μF, 10 μF, 2 μ, 500 nH, 200 nH, etc.

[0088] In some embodiments, the bias capacitor (C12) may enable a voltage offset between the output of the pulser and transformer terminal (101) (e.g., at the position marked 125) and the voltage on the electrode (e.g., at the position marked 124). During operation, the electrode may be at a DC voltage of -2 kV, for example, during a burst, while the output of the nanosecond pulser alternates between +6 kV during the pulse and 0 kV between pulses.

[0089] The bias capacitor (C12) may have, for example, 100nF, 10nF, 1nF, 100μF, 10μF, 1μF, etc. The resistor (R2) may have a high resistance, for example, about 1 kOhm, 10 kOhm, 100 kOhm, 1 MOhm, 10 MOhm, 100 MOhm, etc.

[0090] In some embodiments, the bias compensation capacitor (C15) and the bias compensation diode (D1) enable a voltage offset between the output of the pulser and transformer terminal (101) (e.g., at the position marked 125) and the voltage on the electrode (e.g., at the position marked 124), which is set when each burst starts, so that the required equilibrium state can be reached. For example, during a course of multiple pulses (e.g., about 5 to 100 pulses), charge is transferred from the bias capacitor (C12) to the bias compensation capacitor (C15) when each burst starts, so that the correct voltage can be set in the circuit.

[0091] In some embodiments, the DC bias compensation circuit (104) may include one or more high voltage switches disposed across the bias compensation diode (D1) and coupled with the power supply (V1). In some embodiments, the high voltage switch may include a plurality of switches arranged in series to collectively open and close the high voltage.

[0092] A high-voltage switch can be connected in series with one or both of an inductor and a resistor. The inductor can limit peak current through the high-voltage switch. For example, the inductor can have an inductance of less than about 100 μH, such as about 250 μH, 100 μH, 50 μH, 25 μH, 10 μH, 5 μH, 1 μH, etc. For example, the resistor can transfer power loss to the resistive output terminal (102). The resistance of the resistor can have a resistance of about 1,000 ohms, 500 ohms, 250 ohms, 100 ohms, 50 ohms, less than 10 ohms, etc.

[0093] In some embodiments, the high voltage switch may include a snubber circuit.

[0094] In some embodiments, the high voltage switch may include a plurality of switches arranged in series to collectively open and close the high voltage. For example, the high voltage switch may include any switch described in U.S. Patent Application No. 16 / 178,565 filed November 1, 2018, titled “High voltage switch having isolated power,” which is incorporated herein in its entirety for all purposes.

[0095] In some embodiments, the high voltage switch may be opened when the pulser and transformer terminal (101) is pulsing and closed when the pulser and transformer terminal (101) is not pulsing. For example, when the high voltage switch is closed, the current may be short-circuited across the bias compensation diode (C15). Short-circuiting this current allows the bias between the wafer and the chuck to be less than 2 kV, which may be within an acceptable tolerance.

[0096] In some embodiments, the pulser and transformer stage (101) has a high pulse voltage (e.g., voltage greater than 1 kV, 10 kV, 20 kV, 50 kV, 100 kV, etc.), a high pulse repetition frequency (e.g., frequency greater than 1 kHz, 10 kHz, 100 kHz, 200 kHz, 500 kHz, 1 MHz, etc.), a fast rise time (e.g., rise time of about 1 ns, 10 ns, 50 ns, 100 ns, 250 ns, 500 ns, less than 1,000 ns, etc.), a fast fall time (e.g., fall time of about 1 ns, 10 ns, 50 ns, 100 ns, 250 ns, 500 ns, less than 1,000 ns, etc.) and / or a short pulse width (e.g., about 1,000 ns, 500 ns, 250 ns, 100 ns, It is possible to generate a pulse having a pulse width of less than 20 ns.

[0097] FIG. 2 illustrates an exemplary waveform generated by a nanosecond pulser system (100). In this exemplary waveform, the pulse waveform (205) may represent the voltage provided by the pulser and transformer terminal (101). As illustrated, the pulse waveform (205) generates a pulse having the following amounts: a high voltage (e.g., greater than about 4 kV as indicated in the waveform), a fast rise time (e.g., less than about 200 ns as indicated in the waveform), a fast fall time (e.g., less than about 200 ns as indicated in the waveform), and a short pulse width (e.g., less than about 300 ns as indicated in the waveform). The waveform (210) may represent the voltage on the wafer surface or the voltage across the capacitor (C3) indicated by the nanosecond pulser system (100) at a point between capacitors (C2) and capacitor (C3). The pulse waveform (215) represents the current flowing into the plasma from the pulser and transformer terminal (101). The nanosecond pulser system (100) may or may not include one or both of the diodes (D1 or D2).

[0098] During the transient state (e.g., during an initial number of pulses not shown in the drawing), high voltage pulses at the pulser and transformer terminal (101) charge capacitor (C2). Because the capacitance of capacitor (C2) is larger than and / or larger than the capacitance of capacitor (C3) and / or capacitor (C1) or the pulse width of the pulse is short, capacitor (C2) can receive multiple pulses from the high voltage pulser to fully charge. When capacitor (C2) is charged, the circuit reaches a steady state as shown by the waveform in FIG. 2.

[0099] When the switch (S1) is open in the normal state, the capacitor (C2) is charged and slowly dissipates through the resistive output terminal (110), as illustrated by the slightly rising slope of the waveform (210). While the capacitor (C2) is charged and the switch (S1) is open, the voltage on the wafer surface (the point between the capacitor (C2) and the capacitor (C3)) is negative. This negative voltage may be the negative value of the voltage of the pulse provided by the pulser and transformer terminal (101). In the case of the example waveform shown in FIG. 2, the voltage of each pulse is about 4 kV; and the normal state voltage of the wafer is about -4 kV. This results in a negative potential across the plasma (e.g., capacitor (C3)) which accelerates positive ions from the plasma to the wafer surface. While the switch (S1) is open, the charge of the capacitor (C2) slowly dissipates through the resistive output terminal.

[0100] When the switch (S1) is closed, the voltage across the capacitor (C2) can be flipped as the capacitor (C2) is charged (the pulse from the pulser is high as shown in waveform (205)). Also, the voltage at a point between capacitor (C2) and capacitor (C3) (e.g., wafer surface) changes to about 0 as the capacitor (C2) is charged as shown in waveform (210). Thus, the pulse from the high-voltage pulser generates a plasma potential (e.g., plasma potential) that rises from a negative high voltage to 0 and returns to a negative high voltage at a high frequency with a fast rise time, a fast fall time, and / or a short pulse width.

[0101] In some embodiments, the action of the element represented by the resistive output terminal, i.e., the resistive output terminal (102), can rapidly discharge the stray capacitance (C1) and cause the voltage at the point between capacitors (C2) and (C3) to rapidly return to a stable negative value of about -4 kV, as illustrated by the waveform (210). The resistive output terminal can maximize the time the ions are accelerated to the wafer by ensuring that the voltage at the point between capacitors (C2) and (C3) exists for about % of the time. In some embodiments, the component included within the resistive output terminal may be specifically selected to optimize the time the ions are accelerated to the wafer and to maintain the voltage nearly constant during this time. Thus, for example, a short pulse with a fast rise time and a fast fall time may be useful, so there may be a long period of significantly uniform negative potential. Various other waveforms may be generated by the nanosecond pulser system (100).

[0102] FIG. 3 is a circuit diagram illustrating a nanosecond pulser system (150) having a pulser and a transformer terminal (101) and an energy recovery circuit (165) according to some embodiments. For example, the energy recovery circuit may replace the resistive output terminal (102) shown in FIG. 1. In this example, the energy recovery circuit (165) may be located on or electrically coupled to the secondary side of the transformer (T1). For example, the energy recovery circuit (165) may include a diode (180) (e.g., a clover diode) at both ends of the secondary side of the transformer (T1). For example, the energy recovery circuit (165) may include a diode (160) and an inductor (155) (arranged in series), thereby allowing current to flow from the secondary side of the transformer (T1) to charge the power supply (C7). The diode (160) and inductor (155) may be electrically connected to the secondary side of the transformer (T1) and the power supply (C7). In some embodiments, the energy recovery circuit (165) may include a diode (175) and / or an inductor (170) electrically coupled to the secondary side of the transformer (T1). The inductor (170) may represent a stray inductance and / or include the stray inductance of the transformer (T1).

[0103] When the nanosecond pulser is turned on, current can charge the load terminal (106) (e.g., charge capacitor (C3), capacitor (C2), or capacitor (C9)). For example, if the secondary voltage of the transformer (T1) rises above the charging voltage of the power supply (C7), some current can flow through the inductor (155). When the nanosecond pulser is turned off, current can be allowed to flow from the capacitor in the load terminal (106) through the inductor (155) until the voltage across the inductor (155) becomes zero, thereby charging the power supply (C7). The diode (180) can prevent the capacitor in the load terminal (106) from ringing into the inductance of the load terminal (106) or the bias compensation circuit (104).

[0104] The diode (160) can, for example, prevent charge from flowing from the power supply (C7) to the capacitor in the load terminal (106).

[0105] The value of the inductor (155) can be selected to control the current fall time. In some embodiments, the inductor (155) may have an inductance value between 1 μH and 500 μH.

[0106] In some embodiments, the energy recovery circuit (165) may include an energy recovery switch that can be used to control the flow of current through the inductor (155). For example, the energy recovery switch may be placed in series with the inductor (155). In some embodiments, the energy recovery switch may be closed when the switch (S1) is open and / or when no more pulses are generated to allow current to flow back from the load terminal (106) to the high voltage load (C7).

[0107] In some embodiments, the energy recovery switch may include a plurality of switches arranged in series to collectively switch high voltage. For example, the energy recovery switch may include the switch described in U.S. Patent Application No. 16 / 178,565, filed November 1, 2018, under the heading “High voltage switch using isolated power,” which is incorporated herein by reference in its entirety for all purposes.

[0108] In some embodiments, the stray capacitance between the pulser, the transformer terminal (101), and ground is less than about 10 nF. In some embodiments, the nanosecond pulser system (150) can generate a waveform similar to that shown in FIG. 2.

[0109] FIG. 4 is a block diagram illustrating a spatially variable wafer bias power system (400) according to some embodiments. The spatially variable wafer bias power system (400) may include a first high-voltage pulser (425) and a second high-voltage pulser (430).

[0110] The interconnect board (405) may be electrically coupled to the first high-voltage pulser (425) and the second high-voltage pulser (430) or additional high-voltage pulsers. In some embodiments, the interconnect board (405) may provide a high DC voltage to each of the first high-voltage pulser (425) or the second high-voltage pulser (430). In some embodiments, the interconnect board (405) may provide a trigger signal to the first high-voltage pulser (425) or the second high-voltage pulser (430). In some embodiments, the interconnect board (405) may provide a low-voltage pulse to the first high-voltage pulser (425) or the second high-voltage pulser (430).

[0111] In some embodiments, the interconnect board (405) may include a controller or processor comprising one or more components of the computing system (1600). In some embodiments, one or more sensors may be included to measure characteristics of the plasma chamber, such as, for example, the electric field on the wafer surface, the uniformity of the electric field, the voltage of the first electrode, the voltage of the second electrode, one or more resistive output terminals, or the voltage across the resistor of one or more energy recovery circuits. Based on measurements from the sensors, the voltage, pulse width, or pulse repetition frequency of the first high-voltage pulser (425) and the second high-voltage pulser (430) may be adjusted.

[0112] For example, if the voltage of the second electrode is measured and determined to be lower than the voltage of the first electrode, this may result in electric field non-uniformity on the wafer surface (e.g., a difference of about 5%, 10%, 15%, or less than 20%). The controller may adjust the pulse width of the control pulse transmitted to the second high-voltage pulser (430), which can increase the electric field of the second electrode by increasing the voltage generated by the second high-voltage pulser (430) (e.g., by increasing the capacitive charging time). This process may be repeated until the electric field across the wafer surface is uniform (e.g., within 10%, 15%, 20%, 25%, etc.).

[0113] As another example, the voltage across the first resistive output stage and the second resistive output stage may be measured. This voltage may correspond to the current flowing from the chamber to ground as the capacitance of the chamber discharges. This current may be proportional to the ion energy. If the ion energy is at the first electrode and the ion energy at the second electrode is non-uniform or misaligned (e.g., a difference greater than 10%, 20%, or 30%), the controller may adjust the pulse width of the control pulse transmitted to the first high-voltage pulser (425) or the second high-voltage pulser (430), which may increase the voltage generated by the nanosecond pulser (e.g., increase the capacitive charge time), and thus increase the electric field of the corresponding electrode.

[0114] In some embodiments, pulses from the first high-voltage pulser (425) and the second high-voltage pulser (430) may pass through the chamber interface board to the energy recovery circuit (440) and the plasma chamber (435). For example, the energy recovery circuit (440) may include a resistive output terminal (102) of the nanosecond pulser system (100). As another example, the energy recovery circuit (440) may include an energy recovery circuit (165). As another example, the energy recovery circuit (440) may not be used. As another example, the energy recovery circuit (440) may be coupled with one or both of the first high-voltage pulser (425) or the second high-voltage pulser (430). In some embodiments, the plasma chamber (435) may include a plasma chamber, an etching chamber, a deposition chamber, etc. In some embodiments, the effective circuit of the plasma chamber (435) may include a load terminal (106).

[0115] In some embodiments, the bias compensation circuit (410) may include any or all components shown in the bias compensation circuit (104, 514, or 614). In some embodiments, a plurality of bias compensation circuits may be used. For example, a first bias compensation circuit may be coupled to a first high voltage pulser (425) and a first electrode; and a second bias compensation circuit may be connected to a second high voltage pulser (430) and a second electrode. For example, the bias compensation circuit may include a bias compensation capacitor (C12) having a capacitance of 100pF, 10pF, 1pF, 100μF, 10μF, 1μF, etc.

[0116] Two high-voltage pulsers are shown, but any number may be used. For example, multiple electrode rings may be combined with multiple high-voltage pulsers.

[0117] In some embodiments, the first high voltage pulser (425) may generate a pulse different from the pulse generated by the second high voltage pulser (430). For example, the first high voltage pulser (425) may provide a pulse of at least 2 kV generated. In some embodiments, the second high voltage pulser (430) may provide a pulse of at least 2 kV with a pulse output that is the same or different from the pulse provided by the first high voltage pulser (425).

[0118] As another example, the first high-voltage pulser (425) can generate a pulse having a first pulse repetition frequency, and the second high-voltage pulser (430) can generate a pulse having a second pulse repetition frequency. The first pulse repetition frequency and the second pulse repetition frequency may be the same or different. The first pulse repetition frequency and the second pulse repetition frequency may be in the same phase or different phase with respect to each other.

[0119] As another example, the first high-voltage pulser (425) may generate a first plurality of bursts having a first burst repetition frequency, and the second high-voltage pulser (430) may generate a second plurality of bursts having a second burst repetition frequency. Each burst may include a plurality of pulses. The first burst repetition frequency and the second burst repetition frequency may be the same or different. The first burst repetition frequency and the second burst repetition frequency may be in the same phase or different phase with respect to each other.

[0120] In some embodiments, the first high voltage pulser (425) and the second high voltage pulser (430) may be water-cooled or dielectric-cooled.

[0121] In some embodiments, the cable or transmission line between the output of the first high-voltage pulser (425), the output of the second high-voltage pulser (430), and the plasma chamber (435) (or electrode) may exceed 5m, 10m, 15m, etc.

[0122] In some embodiments, the inductance between any of the first high-voltage pulser (425), the second high-voltage pulser (430), and the plasma chamber (435) may be less than about 100 μH.

[0123] In some embodiments, the stray capacitance between the first high voltage pulser (425) or the second high voltage pulser (430) and ground is less than about 10 nF.

[0124] FIG. 5 is a circuit diagram illustrating a high-voltage power system (500) having a plasma load according to some embodiments. High-voltage power system with plasma load (500) It is similar to a high voltage power system (500) having a plasma load.

[0125] In this embodiment, the bias compensation circuit (514) may include a high voltage switch (505) coupled to both ends of the bias compensation diode (506) and coupled to the power supply (V1). In some embodiments, the high voltage switch (505) may include a plurality of switches (505) arranged in series to collectively open and close the high voltage. For example, the high voltage switch (505) may include the high voltage switch (700) described in FIG. 7. In some embodiments, the high voltage switch (505) may be coupled to a switch trigger (V4).

[0126] The high voltage switch (505) may be connected in series with one or both of the inductor (L9) and the resistor (R11). The inductor (L9) may limit the peak current through the high voltage switch (505). The inductor (L9) may have an inductance of less than about 100 μH, for example, about 250 μH, 100 μH, 50 μH, 25 μH, 10 μH, 5 μH, 1 μH, etc. For example, the resistor (R11) may divert power loss to the resistive output terminal (102). For example, the resistance of the resistor (R11) may have a resistance of less than about 1,000 ohms, 500 ohms, 250 ohms, 100 ohms, 50 ohms, 10 ohms, etc.

[0127] In some embodiments, the high voltage switch (505) may include a snubber circuit. The snubber circuit may include a resistor (R9), a snubber diode (D8), a snubber capacitor (C15), and a snubber resistor (R10).

[0128] In some embodiments, the resistor (R8) may represent the stray resistance of the offset supply voltage (V1). For example, the resistor (R8) may have a high resistance such as about 10 kOhm, 100 kOhm, 1 MOhm, 10 MOhm, 100 MOhm, 1 GOhm, etc.

[0129] In some embodiments, the high voltage switch (505) may include a plurality of switches arranged in series to collectively open and close the high voltage. For example, the high voltage switch (505) may include the high voltage switch (700) described in FIG. 7. As another example, the high voltage switch (505) may include, for example, any switch described in U.S. Patent Application No. 16 / 178,565 filed November 1, 2018, titled “High voltage switch having isolated power,” which is incorporated herein by reference in its entirety for all purposes.

[0130] In some embodiments, the high voltage switch (505) may be open while the pulser and transformer terminal (101) is pulsing and closed when the pulser and transformer terminal (101) is not pulsing. For example, when the high voltage switch (505) is closed, the current may be short-circuited across the bias compensation diode (506). Short-circuiting this current may result in a bias of less than 2 kV, which can be within an acceptable tolerance for the wafer and the chuck.

[0131] In some embodiments, the high voltage switch (505) can cause the electrode voltage (position indicated by 124) and the wafer voltage (position indicated by 122) to be quickly restored to the chucking potential (position indicated by 121) (e.g., about 100ns, 200ns, 500ns, less than 1μs).

[0132] FIG. 6 is a circuit diagram illustrating a high-voltage power system (600) having a plasma load according to some embodiments. The high-voltage power system (600) having a plasma load includes a bias compensation circuit (614) including a second pulser (601) and a switch (610).

[0133] The bias compensation circuit (614) may include a second pulser (601). For example, the second pulser (601) may include one or more or all components of the pulser and transformer stage (101) shown in FIG. 1 or FIG. 3. For example, the pulser and transformer stage (101) may include a nanosecond pulser or a high-voltage switch as disclosed herein (e.g., FIG. 7 and related paragraphs). In some embodiments, the second pulser (601) may be configured to turn off when the pulser stage (101) is pulsing (e.g., during a burst), and the second pulser (601) may be configured to turn on when the pulser stage (101) is not pulsing (e.g., between bursts).

[0134] The bias compensation circuit (614) may also include an inductor (L9) on the secondary side of the transformer (T2), and the switch (610) may be coupled to a voltage source (V6). The inductor (L9) may represent the stray inductance of the bias compensation circuit (614) and may have a low inductance, such as, for example, about 500 nH, 250 nH, 100 nH, 50 nH, less than 25 nH. In some embodiments, the voltage source (V6) may represent a trigger for the switch (610).

[0135] In some embodiments, the bias compensation circuit (614) may include a blocking diode (D7). The blocking diode (D7) may ensure that current flows from the switch (610) to the load terminal (106), for example. For example, a capacitor (C14) may represent the stray capacitance of the blocking diode (D7). For example, the capacitance of the capacitor (C14) may have a low capacitance such as about 1 nF, 500 pF, 200 pF, 100 pF, 50 pF, less than 25 pF, etc.

[0136] In some embodiments, the switch (610) may be opened when the pulser and transformer terminal (101) is pulsing and closed when the pulser and transformer terminal (101) is not pulsing and offset (or bias) the voltage provided by the pulser terminal.

[0137] In some embodiments, the switch (610) may include a plurality of switches arranged in series to collectively open and close a high voltage. In some embodiments, the switch (610) may include the high voltage switch (700) described in FIG. 7. As another example, the high voltage switch (505) may include, for example, any switch described in U.S. Patent Application No. 16 / 178,565 filed November 1, 2018, titled “High voltage switch having isolated power,” which is incorporated herein by reference in its entirety for all purposes.

[0138] FIG. 7 is a block diagram illustrating a high-voltage switch (700) having isolation power according to some embodiments. The high-voltage switch (700) may include a plurality of switch modules (705) (collectively or individually 705, and 705A, 705B, 705C, and 705D) capable of switching a voltage from a high-voltage source (760) with a fast rise time and / or high frequency and / or variable pulse width. Each switch module (705) may include a switch (710), such as a solid-state switch, for example.

[0139] In some embodiments, the switch (710) may be electrically coupled to a gate driver circuit (730) which may include a power supply (740) and / or an isolated optical fiber trigger (745) (also referred to as a gate trigger or switch trigger). For example, the switch (710) may include a collector, an emitter, and a gate (or a drain, a source, and a gate), and the power supply (740) may drive the gate of the switch (710) through the gate driver circuit (730). The gate driver circuit (730) may be isolated from other components of the high-voltage switch (700), for example.

[0140] In some embodiments, the power supply unit (740) may be isolated, for example, using an isolation transformer. The isolation transformer may include a low-capacitance transformer. For example, the low capacitance of the isolation transformer may allow the power supply unit (740) to be charged on a rapid time scale without requiring a significant current. The isolation transformer may have, for example, a capacitance of less than about 100 pF. As another example, the isolation transformer may have a capacitance of less than about 30 to 100 pF. In some embodiments, the isolation transformer may provide voltage isolation up to 1 kV, 5 kV, 10 kV, 25 kV, 50 kV, etc.

[0141] In some embodiments, the isolation transformer may have low stray capacitance. For example, the isolation transformer may have stray capacitance of about 1,000 pF, 100 pF, less than 10 pF, etc. In some embodiments, low capacitance may minimize electrical coupling to low-voltage components (e.g., sources of input control power) and / or reduce EMI generation (e.g., generation of electrical noise). In some embodiments, the transformer stray capacitance of the isolation transformer may include the capacitance measured between the primary winding and the secondary winding.

[0142] In some embodiments, the isolation transformer may be a DC-DC converter or an AC-DC transformer. In some embodiments, the transformer may include, for example, a 110V AC transformer. In any case, the isolation transformer may provide power isolated from other components of the high-voltage switch (700). In some embodiments, the isolation is galvanic isolation so that no conductor on the primary side of the isolation transformer passes through or contacts any conductor on the secondary side of the isolation transformer.

[0143] In some embodiments, the transformer may include a primary winding that can be tightly wound or wrapped around a transformer core. In some embodiments, the primary winding may include a conductive sheet that wraps around the transformer core. In some embodiments, the primary winding may include one or more windings.

[0144] In some embodiments, the secondary winding may be wound around the core as far away from the core as possible. For example, the winding bundle containing the secondary winding may be wound through the center of a hole in the transformer core. In some embodiments, the secondary winding may include one or more windings. In some embodiments, the wire bundle containing the secondary winding may include a cross-section that is circular or square, for example, to minimize stray capacitance. In some embodiments, an insulator (e.g., oil or air) may be placed between the primary winding, the secondary winding, or the transformer core.

[0145] In some embodiments, keeping the secondary winding away from the transformer core may offer several advantages. For example, it can reduce stray capacitance between the primary side of the isolation transformer and the secondary side of the isolation transformer. As another example, it allows for a high-voltage standoff between the primary side of the isolation transformer and the secondary side of the isolation transformer, thereby preventing corona and / or breakdown from occurring during operation.

[0146] In some embodiments, the gap between the primary side of the isolation transformer (e.g., primary winding) and the secondary side of the isolation transformer (e.g., secondary winding) may be about 0.1", 0.5", 1", 5", or 10". In some embodiments, the typical gap between the core of the isolation transformer and the secondary side of the isolation transformer (e.g., secondary winding) may be about 0.1", 0.5", 1", 5", or 10". In some embodiments, the gap between the windings may be filled with the lowest possible dielectric material, such as vacuum, air, insulating gas or liquid, or a solid material with a relative dielectric constant of less than 3.

[0147] In some embodiments, the power supply (740) may include any type of power supply that can provide a high voltage standoff (isolation) or have a low capacitance (e.g., about 1,000 pF, 100 pF, less than 10 pF, etc.). In some embodiments, the control voltage power supply may supply 720 V AC or 240 V AC at 60 Hz.

[0148] In some embodiments, each power supply unit (740) may be electrically coupled to a single control voltage power supply unit by induction. For example, power supply unit (740A) may be electrically coupled to the power supply unit through a first transformer; power supply unit (740B) may be electrically coupled to the power supply unit through a second transformer; power supply unit (740C) may be electrically coupled to the power supply unit through a third transformer; and power supply unit (740D) may be electrically coupled to the power supply unit through a fourth transformer. For example, any type of transformer capable of providing voltage isolation between various power supplies may be used.

[0149] In some embodiments, the first transformer, the second transformer, the third transformer, and the fourth transformer may include different secondary windings around the core of a single transformer. For example, the first transformer may include a first secondary winding, the second transformer may include a second secondary winding, the third transformer may include a third secondary winding, and the fourth transformer may include a fourth secondary winding. Each of these secondary windings may be wound around the core of a single transformer. In some embodiments, the first secondary winding, the second secondary winding, the third secondary winding, the fourth secondary winding, or the primary winding may include a single winding or a plurality of windings wound around the transformer core.

[0150] In some embodiments, power supply unit (740A), power supply unit (740B), power supply unit (740C) and / or power supply unit (740D) may not share a return reference ground or local ground.

[0151] The isolated fiber trigger (745) may also be isolated from other components of the high voltage switch (700), for example. The isolated fiber trigger (745) may include a fiber receiver that allows each switch module (705) to float relative to other switch modules (705) and / or other components of the high voltage switch (700), for example, while allowing active control of the gate of each switch module (705).

[0152] In some embodiments, for example, the return reference ground, local ground, or common ground for each switch module (705) may be isolated from each other, for example, using an isolation transformer.

[0153] For example, common ground and electrical isolation of each switch module (705) enable multiple switches to be arranged in a series configuration for cumulative high-voltage switching. In some embodiments, some delay in switch module timing may be allowed or designed. For example, each switch module (705) may be configured or rated to switch 1 kV, each switch module may and / or be electrically isolated from one another, or the timing of closing each switch module (705) does not need to be perfectly aligned for a time defined by the capacitance of the snubber capacitor and / or the voltage rating of the switch.

[0154] In some embodiments, electrical insulation can provide many advantages. For example, one possible advantage may include minimizing switch jitter and / or allowing arbitrary switch timing. For example, each switch (710) may have switch switching jitter of about 500ns, 50ns, 20ns, less than 5ns, etc.

[0155] In some embodiments, electrical insulation between two components (or circuits) may mean very high resistance between the two components and / or small capacitance between the two components.

[0156] Each switch (710) may include any type of solid-state switching device, such as, for example, an IGBT, MOSFET, SiC MOSFET, SiC junction transistor, FET, SiC switch, GaN switch, photoconductive switch, etc. For example, the switch (710) may switch at a high frequency (e.g., greater than 1 kHz), at a high speed (e.g., a repetition rate greater than about 500 kHz), and / or with a fast rise time (e.g., a rise time of less than about 25 ns), and / or with a long pulse length (e.g., greater than about 10 ms), and a high voltage (e.g., a voltage greater than about 1 kV). In some embodiments, each switch may be individually rated to switch between 1,200 V and 1,700 V, but in another embodiment, it may switch beyond 4,800 V and 6,800 V (for four switches). Switches with various other rated voltages may be used.

[0157] Using a larger number of low-voltage switches than a few high-voltage switches can offer several advantages. For example, low-voltage switches generally provide better performance: they can switch faster, have quicker switching times, and switch more efficiently than high-voltage switches. However, as the number of switches increases, the issue of required time also becomes more significant.

[0158] The high voltage switch (700) illustrated in FIG. 7 includes four switch modules (705). Although four are shown in this figure, any number of switch modules (705), such as 2, 8, 12, 16, 20, 24, etc., may be used. For example, if the rating of each switch in each switch module (705) is 1200V and 16 switches are used, the high voltage switch can switch up to 19.2kV. As another example, if the rating of each switch in each switch module (705) is 1700V and 16 switches are used, the high voltage switch can switch up to 27.2kV.

[0159] In some embodiments, the high voltage switch (700) may include a high-speed capacitor (755). For example, the high-speed capacitor (755) may include one or more capacitors arranged in series and / or parallel. These capacitors may include, for example, one or more polypropylene capacitors. The high-speed capacitor (755) may store energy from a high voltage source (760).

[0160] In some embodiments, the high-speed capacitor (755) may have a low capacitance. In some embodiments, the high-speed capacitor (755) may have a capacitance value of about 1 μF, about 5 μF, about 1 μF to about 5 μF, about 100 nF to about 1,000 nF, etc.

[0161] In some embodiments, the high voltage switch (700) may or may not include a clover diode (750). The clover diode (750) may include a plurality of diodes arranged in series or parallel, which may be beneficial, for example, for driving an inductive load. In some embodiments, the clover diode (750) may include one or more Schottky diodes, for example, silicon carbide Schottky diodes. The clover diode (750) may detect, for example, whether the voltage from the switch of the high voltage switch is above a certain threshold value. If so, the clover diode (750) may short-circuit power from the switch module to ground. For example, the clover diode may allow the AC path to dissipate energy stored in the inductive load after switching. This may, for example, prevent large inductive voltage spikes. In some embodiments, the clover diode (750) may have a low inductance, such as 1 nH, 10 nH, 100 nH, etc. In some embodiments, the clover diode (750) may have a low capacitance such as, for example, 100pF, 1nF, 10nF, 100nF, etc.

[0162] In some embodiments, the clover diode (750) may not be used, for example, when the load (765) is primarily resistive.

[0163] In some embodiments, each gate driver circuit (730) may generate jitter of about 1000ns, 100ns, 10.0ns, 5.0ns, 3.0ns, less than 1.0ns, etc. In some embodiments, each switch (710) may have a minimum switch-on time (e.g., about 10 μs, 1 μs, 500 ns, 100 ns, 50 ns, 10, less than 5 ns, etc.) and a maximum switch-on time (e.g., 25 seconds, 10 seconds, 5 seconds, 1 second, greater than 500ms, etc.).

[0164] In some embodiments, during operation, each high voltage switch can be switched on and / or off within 1 ns of each other.

[0165] In some embodiments, each switch module (705) may have the same or substantially the same (±5%) stray inductance. The stray inductance may include all inductances within the switch module (705) that are not associated with an inductor, such as inductances of leads, diodes, resistors, switches (710) and / or circuit board traces, for example. The stray inductance within each switch module (705) may include low inductances, such as inductances of about 300 nH, 100 nH, 10 nH, less than 1 nH, for example. The stray inductance between each switch module (705) may include low inductances, such as inductances of about 300 nH, 100 nH, 10 nH, less than 1 nH, for example.

[0166] In some embodiments, each switch module (705) may have the same or substantially the same (±5%) stray capacitance. The stray capacitance may include all capacitance within the switch module (705) that is not associated with a capacitor, such as, for example, the capacitance of leads, diodes, resistors, switches (710) and / or circuit board traces. The stray capacitance within each switch module (705) may include low capacitances, for example, about 1,000 pF, 100 pF, less than 10 pF. The stray capacitance between each switch module (705) may include low capacitances, for example, about 1,000 pF, 100 pF, 10 pF.

[0167] The defect of voltage sharing can be resolved, for example, by using a passive snubber circuit (e.g., a snubber diode (715), a snubber capacitor (720), and / or a freewheeling diode (725)). For example, small differences in the timing of each switch (710) turning on or off, or differences in inductance or capacitance, can lead to voltage spikes. These spikes can be mitigated by various snubber circuits (e.g., a snubber diode (715), a snubber capacitor (720), and / or a freewheeling diode (725)).

[0168] For example, the snubber circuit may include a snubber diode (715), a snubber capacitor (720), a snubber resistor (716), and / or a freewheeling diode (725). In some embodiments, the snubber circuit may be arranged together in parallel with the switch (710). In some embodiments, the snubber capacitor (720) may have a low capacitance, such as a capacitance of less than about 100 pF.

[0169] In some embodiments, the high voltage switch (700) may be electrically coupled to or include a load (765) (e.g., a resistive, capacitive, or inductive load). For example, the load (765) may have a resistance from 50 ohms to 500 ohms. Alternatively or additionally, the load (765) may be an inductive load or a capacitive load.

[0170] FIG. 8 is a block diagram illustrating an ADC control system (800) for a nanosecond pulser system (100) (or a nanosecond pulser system (300)) according to some embodiments. In some embodiments, the ADC control system (800) may be electrically coupled to the nanosecond pulser system (100) at one or more locations. For example, a first HV signal (805A) may include a voltage signal at a point (120) of the nanosecond pulser system (100) located between the pulser and transformer terminal (101) and the bias compensation circuit (104). As another example, a second HV signal (805B) may include a voltage signal at a point (125) of the nanosecond pulser system (100) located between the load terminal (106) and the bias compensation circuit (104). In some embodiments, the first HV signal (805A) and the second HV signal (805B) may include voltage signals on each side of the capacitor (C12) of the bias compensation circuit (104). Any number of other signals may be received.

[0171] In some embodiments, the first HV signal (805A) or the second HV signal (805B) may include a voltage signal provided to the load terminal (106). In some embodiments, the first HV signal (805A) or the second HV signal (805B) may include a voltage signal provided to the bias compensation circuit (104). In some embodiments, the first HV signal (805A) or the second HV signal (805B) may include a voltage signal provided to the lead terminal (103). In some embodiments, the first HV signal (805A) or the second HV signal (805B) may include and may be measured a voltage signal provided to the pulser and transformer terminal (101). In some embodiments, the first HV signal (805A) or the second HV signal (805B) may include a voltage signal provided to the resistive output terminal (102).

[0172] The first HV signal (805A) and the second HV signal (805B) may be collectively or individually referred to as the HV input signal (805).

[0173] In some embodiments, the HV input signal (805) may be divided by a voltage divider (810). For example, the voltage divider (810) may include a high-value resistor or a low-value capacitor for dividing a high-voltage HV input signal (e.g., greater than 1 KV) into a low-voltage signal (e.g., less than 50 V). For example, the voltage divider (810) may divide the voltage at a ratio of 500:1. For example, the voltage divider (810) may divide an HV input signal (805) voltage of 0-10 kV into a voltage of 0-20 V. For example, the voltage divider (810) may divide the voltage with a minimum power loss, such as, for example, less than about 5 W.

[0174] In some embodiments, the voltage divider (810) may include a low-value capacitor, a high-value capacitor, a low-value resistor, and a high-value resistor. For example, the low-value capacitor may include a capacitor having a capacitance value of about 0.1, 0.5, 1.0, 2.5, 5.0, 10.0 pf, etc. For example, the large-value capacitor may include a capacitor having a capacitance value of about 500 pf. In some embodiments, the large-value capacitor may have a capacitance value of about 50, 100, 250, 500, 1,000, 2,500, 5,000 pF, etc., which is greater than the capacitance value of the low-value capacitor.

[0175] The low-value resistor may have a resistance value of approximately 1.0, 2.5, 5.0, 10, 25, 50, 100 kΩ, etc. The high-value resistor may have a resistance value of approximately 0.5, 1.0, 2.5, 5.0, 10, 25, 50, 100 MΩ, etc. In some embodiments, the high-value resistor may have a resistance value approximately 50, 100, 250, 500, 1,000, 2,500, 5,000 pF greater than the resistance value of the low-value resistor. In some embodiments, the ratio of the low-value capacitor to the high-value capacitor may be substantially the same as the ratio of the low-value resistor to the high-value resistor.

[0176] In some embodiments, the voltage divider (810) may receive an HV input signal and output a divided voltage signal. For example, the divided voltage signal may be 100 times, 250 times, 500 times, 750 times, or 1,000 times smaller than the HV input signal.

[0177] In some embodiments, a filter (815) may be included, for example, to filter any noise from the distributed voltage signal.

[0178] In some embodiments, the distributed voltage signal may be digitized by a first ADC (820). Any type of analog-to-digital converter may be used. The first ADC (820) may generate a digitized waveform signal. In some embodiments, the first ADC (820) may capture data at 100, 250, 500, 1,000, 2,000, 5,000 MSPS (mega-samples per second or millions of samples per second). In some embodiments, the digitized waveform signal may be transmitted to a controller (825) using any type of communication protocol, such as, for example, SPI, UART, RS-232, USB, I2C, etc.

[0179] In some embodiments, the controller (825) may include any type of controller, such as, for example, an FPGA, an ASIC, a complex programmable logic device, a microcontroller, a system-on-chip (SoC), or any combination thereof. In some embodiments, the controller (825) may include any or all components of the computing system (1600). In some embodiments, the controller (825) may include a standard microcontroller, such as, for example, a Broadcom Arm Cortex, an Intel ARM Cortex, a PIC32, etc.

[0180] In some embodiments, the controller (825) may receive a trigger signal from the trigger (830). In other embodiments, the first ADC (820) may receive a trigger signal from the trigger (830). The trigger signal may provide data acquisition timing in the first ADC (820). For example, the trigger signal may be a 5V TTL trigger. For example, the trigger signal may have a 50 ohm termination.

[0181] A digitized signal may be output from the controller (825) through one or more output ports, such as, for example, a first output (835A) or a second output (835B) (individually or collectively, output (835)). These outputs may be coupled to a nanosecond pulser controller. One or both of the outputs (835) may include electrical connectors, for example, LVDS, TTL, LVTTL connectors. One or both of the outputs (835) may provide data to the nanosecond pulser controller using any type of communication protocol, such as, for example, SPI, UART, RS-232, USB, I2C, EtherCat, Ethernet, Profibus, PROFINET.

[0182] In some embodiments, the ADC control system (800) may be coupled with the nanosecond pulser system (100) through an 8 mm multiram receptacle on the ADC control system (800).

[0183] In some embodiments, the second ADC (845) and the first ADC (820) may comprise a single ADC device. In some embodiments, one or both of the second ADC (845) or the first ADC (820) may be part of the controller (825). In some embodiments, the first ADC (820) may operate at a higher acquisition rate than the second ADC (845).

[0184] In some embodiments, the ADC control system (800) may include a second ADC (845) capable of receiving inputs from a first sensor (850A) and a second sensor (850B) (individually or collectively from the sensor (850)) (or any number of sensors). In some embodiments, the second ADC (845) may digitize analog signals from the sensor (850). The sensor (850) may include, for example, a sensor that detects inlet water temperature, dielectric fluid temperature, dielectric fluid pressure, chassis air temperature, voltage, fluid flow, fluid leak sensor, etc.

[0185] In some embodiments, the ADC control system (800) can monitor the voltage, frequency, pulse width, etc. of a given waveform and, in response, adjust the voltage, pulse repetition frequency, pulse width, burst repetition frequency (if the burst includes multiple pulses), etc. provided to the input of the nanosecond pulser system (100). For example, the first ADC (820) can monitor the voltage amplitude of the waveform. This voltage data can be provided to the nanosecond pulser controller. The nanosecond pulser controller can adjust the amplitude or frequency of the signal provided to the nanosecond pulser system (100).

[0186] In some embodiments, the ADC control system (800) may output any pulse signal to one or more nanosecond pulser systems (100) through an output (835). For example, the output (835) may include a fiber or electrical connection. In some embodiments, the ADC control system (800) may include a plurality of output pulse channels (e.g., 1, 2, 5, 8, 20, 50, 100, etc.) that may be independent of each other. The plurality of output pulse channels may output pulses having sub-nanosecond resolution, for example.

[0187] For example, if the waveform voltage is smaller than a predetermined voltage, the first ADC (820) can send a signal to the nanosecond pulser system (100) to generate a waveform with a higher voltage. If the waveform voltage is larger than a predetermined voltage, the first ADC (820) can send a signal to the nanosecond pulser system (100) to generate a waveform with a lower voltage.

[0188] As another example, if the pulse repetition frequency is greater than the expected pulse repetition frequency, the first ADC (820) can transmit a signal to the nanosecond pulser system (100) to generate a waveform having a lower frequency. If the burst repetition frequency is smaller than the expected burst frequency, the first ADC (820) can transmit a signal to the nanosecond pulser system (100) to generate a waveform having a higher pulse repetition frequency.

[0189] As another example, if the waveform pulse width is longer than the expected pulse width, the first ADC (820) can transmit a signal to the nanosecond pulser system (100) to generate a waveform having a shorter or longer pulse width. If the waveform duty cycle is shorter or longer than the expected duty cycle, the first ADC (820) can transmit a signal to the nanosecond pulser system (100) to generate a pulse having an appropriate duty cycle.

[0190] The ADC control system (800) can monitor other waveform characteristics and / or adjust these other characteristics.

[0191] In some embodiments, the ADC control system (800) may output any pulse signal to one or more nanosecond pulser systems (100) through an output (835). For example, the ADC control system may include any pulse generator. For example, the output (835) may include a fiber or electrical connection. In some embodiments, the ADC control system (800) may include a plurality of output pulse channels (e.g., 1, 2, 5, 8, 20, 50, 100, etc.) that may be independent of each other. The plurality of output pulse channels may output pulses having, for example, sub-nanosecond resolution. In some embodiments, the ADC control system (800) may output pulses having a resolution of less than about 0.1 ns. In some embodiments, the ADC control system (800) may output pulses having jitter of less than about 100 ps.

[0192] In some embodiments, each output pulse channel of the ADC control system (800) may output a pulse to the nanosecond pulser system (100) that triggers the nanosecond pulser system (100). For example, the ADC control system (800) may adjust parameters of the output pulse in real time or between pulses. These parameters may include pulse width, pulse repetition frequency, duty cycle, burst repetition frequency, voltage, number of pulses in a burst, number of bursts, etc. In some embodiments, one or more parameters may be adjusted or changed based on input to the ADC control system (800) or based on a recipe or program.

[0193] For example, the recipe may include alternating high bursts and low bursts. For example, the high burst may include multiple pulses having a long pulse width. For example, the low burst may include multiple pulses having a short pulse width. For example, the high burst and the low burst may include the same number of bursts or different numbers of bursts. For example, the short pulse width may be 20%, 30%, 80%, 50%, etc. of the long pulse width. The alternating high bursts and low bursts may include low bursts at 5%, 20%, 50%, 100%, 125%, 150%, etc. relative to the number of high bursts.

[0194] In some embodiments, the control system (800) may adjust the pulse width, duty cycle, or pulse repetition frequency in relation to different stages of the plasma processing recipe, wherein each stage of the recipe may correspond to a different ion current, chamber pressure, or different gas in the chamber. By adjusting the pulse width, duty cycle, or pulse repetition frequency, the electric field and / or voltage at the wafer surface may be adjusted to optimize the performance of each stage of the recipe.

[0195] In some embodiments, the ADC control system (800) includes an electrical shield. For example, the electrical shield may separate a high-voltage component from a low-voltage component. The electrical shield may be physically placed, for example, between a voltage divider (810) and a controller (825) or a first ADC (820). As another example, the electrical shield may be physically placed between a nanosecond pulser system (100) and a controller (825) or a first ADC (820).

[0196] In some embodiments, the electric shield may be physically placed between the resistors in the voltage divider (810). In some embodiments, the electric shield may be physically placed between the capacitors in the voltage divider (810).

[0197] In some embodiments, the electrical shield may include copper or nickel. In some embodiments, the electrical shield may include sheet metal, a metal screen, or a metal foam.

[0198] In some embodiments, the ADC control system (800) can monitor the sensor (850) and take action. Several examples are given below.

[0199] In some embodiments, the nanosecond pulser system may include a cooling subsystem. In some embodiments, the cooling subsystem may include a fluid (e.g., water or dielectric fluid) flowing through the cooling subsystem to remove heat from the nanosecond pulser system (100) (e.g., as illustrated in FIGS. 11 through 14). For example, one of the sensors (850) may include a flow sensor for the fluid in the cooling system. If the controller (825) determines that the flow rate is below a flow rate threshold, the ADC control system (800) will not allow the nanosecond pulser system (100) to be turned on. If the controller (825) determines that the flow rate is below a flow rate threshold, the ADC control system (800) will automatically turn off the nanosecond pulser system (100). In some embodiments, the flow sensor (in some cases together with the controller (825)) may be a flow interlock. For example, if the flow rate interlock is already turned on, if the flow rate is below the flow rate threshold value, it can prevent the nanosecond pulser system (100) from being turned on or turn off the nanosecond pulser system (100).

[0200] For example, one of the sensors (850) may include a thermometer combined with the cooling subsystem. If the controller (825) determines that the temperature of the cooling subsystem (e.g., the temperature of the fluid) is higher than the water temperature threshold, the ADC control system (800) will not allow the nanosecond pulser system (100) to be turned on. If the controller (825) determines that the temperature of the water is higher than the water temperature threshold, the ADC control system (800) will automatically turn off the nanosecond pulser system (100). For example, if the temperature interlock is already turned on, if the temperature is higher than the water temperature threshold, it may prevent the nanosecond pulser system (100) from being turned on or turn off the nanosecond pulser system (100).

[0201] For example, one of the sensors (850) may include a liquid level sensor for a fluid reservoir of the cooling system. If the controller (825) determines that the reservoir liquid level is higher than the liquid level threshold, the ADC control system (800) will not be turned on. If the controller (825) determines that the reservoir liquid level is higher than the liquid level threshold, the ADC control system (800) will automatically turn off the nanosecond pulser system (100). For example, if it is already turned on, when the liquid level is below the liquid level threshold, the liquid level interlock may prevent the nanosecond pulser system (100) from being turned on or turn off the nanosecond pulser system (100).

[0202] In some embodiments, the nanosecond pulser system (100) may include a nitrogen purge subsystem that pumps nitrogen into the nanosecond pulser system. For example, the nitrogen purge system may introduce dry nitrogen into an enclosure in which the high-voltage nanosecond pulser system is placed. For example, one of the sensors (850) may include a nitrogen pressure sensor. If the controller (825) determines that the nitrogen pressure level is below a pressure threshold, the ADC control system (800) will not be turned on. If the controller (825) determines that the nitrogen pressure level is below a pressure threshold, the ADC control system (800) will automatically turn off the nanosecond pulser system (100). For example, if the pressure interlock is already turned on, if the pressure is below the pressure threshold, the nanosecond pulser system (100) may be prevented from being turned on or the nanosecond pulser system (100) may be turned off.

[0203] In some embodiments, one of the sensors (850) may include a DC voltage sensor that can be coupled with a DC power supply in the nanosecond pulser system (100). For example, if multiple DC power supply systems are used in the nanosecond pulser system (100) and the voltage changes during operation by exceeding a set percentage (e.g., 1%, 5%, 10%, 20%, etc.) or by exceeding an absolute voltage (e.g., 5V, 10V, 50V, 100V, etc.), the ADC control system (800) may automatically turn off the nanosecond pulser system (100). As another example, when using a power system and during operation the voltage output differs from the set voltage by a certain percentage (e.g., 1%, 5%, 10%, 20%, etc.) or differs from the set voltage by an absolute voltage (e.g., 5V, 10V, 50V, 100V, etc.), the ADC control system (800) can automatically turn off the pulse.

[0204] In some embodiments, the output (835) may include an EtherCAT module capable of communicating with a third-party system (e.g., an external system). In some embodiments, the EtherCAT module may include any type of communication module. In some embodiments, the EtherCAT may include one or more components of the computing system (1600).

[0205] In some embodiments, the controller (825) may respond to the operation of one or more interlocks. The interlocks may include, for example, a 24V interlock, a dry N2 pressure interlock, a water flow rate interlock, a dielectric flow rate interlock, a water reservoir level interlock, a water temperature interlock, a dielectric temperature interlock, etc.

[0206] In some embodiments, the control system can control the operation of the pulsing system, such as, for example, pulse width, duty cycle, high voltage set point, on / off, current output voltage return, high voltage current set point, current output current return, high voltage output activation, high voltage activation state return, emergency termination, etc.

[0207] In some embodiments, the user can interface with the control system through an EtherCAT module. For example, the user can set the output pulse width by executing a PW command. As another example, the user can issue a DUTY command to set the duty cycle. As another example, the user can issue a PWR command to turn on the device to start operation and to turn off the device to stop operation. As another example, the device may continue to operate as set until another command is issued to change the duty cycle or pulse width, or another PWR command is issued to stop operation.

[0208] In some embodiments, the ADC control system (800) can receive commands from an external source in any type of communication protocol such as EtherCAT, LXI, Ethernet, Profibus, PROFINET, RS-232, ModBus, USB, UART, SPI, CC-Lin, etc.

[0209] FIG. 15 is a block diagram illustrating the flow of a process (1500) according to some embodiments. The process (500) includes a plurality of blocks. Additional blocks may be added or blocks may be removed. The process (1500) may be executed, for example, by one or more components of a computational system (600). The process (1500) may be executed, for example, by a control system (400).

[0210] In block 1505, the process (1500) can transmit a plurality of low-voltage pulses to a high-voltage pulser system (e.g., a nanosecond pulser (100) or a nanosecond pulser (300)) based on a recipe. For example, the low-voltage pulses may have a peak voltage of less than 20V, such as 5V. The low-voltage pulses may have a pulse repetition frequency, and each pulse may have a pulse width.

[0211] In some embodiments, the recipe may include alternating high bursts and low bursts as described above. In some embodiments, the recipe may be adjusted or changed in real time. In some embodiments, the recipe may depend on various parameters or characteristics of the plasma chamber.

[0212] In block 1510, the high voltage pulse can be measured in the high voltage pulser. For example, the high voltage pulser may have a peak voltage greater than 2 kV. In some embodiments, the high voltage pulse may have a peak voltage greater than 100 times the peak voltage of the low voltage pulse. In some embodiments, the high voltage pulse may be measured at an electrode in the plasma chamber. In some embodiments, the high voltage pulse may be measured across a resistor in the resistive output terminal or energy recovery terminal of the high voltage pulser. In some embodiments, the high voltage pulse may be measured at a bias capacitor in the high voltage pulser.

[0213] In some embodiments, the full width at half maximum of a high voltage pulse, peak voltage, DC bias, rise time, fall time, etc., can be measured.

[0214] In block 1515, the measured pulse can be compared to a desired (or expected) pulse. If the measured pulse matches the desired pulse (e.g., within some tolerance), the process (1500) proceeds to block 1505 and the process is repeated.

[0215] If the measured pulse does not match the desired pulse, process 1500 proceeds to block 1520. In block 1520, the pulse width or pulse repetition frequency of the low voltage pulse is adjusted. For example, if the voltage of the high voltage pulse is lower than desired, the pulse width of the low voltage pulse may be increased. As another example, if the voltage of the high voltage pulse is higher than desired, the pulse width of the low voltage pulse may be decreased.

[0216] For example, if the pulse repetition frequency (or pulse repetition period) of a high-voltage pulse is lower than desired, the pulse repetition frequency of a low-voltage pulse can be increased. As another example, if the pulse repetition frequency (or pulse repetition period) of a high-voltage pulse is higher than desired, the pulse repetition frequency of a low-voltage pulse can be decreased.

[0217] In some embodiments, the process (1500) may be executed in real time. For example, the process (1500) may be repeated for about 20 μs, 10 μs, 5 μs, less than 1 μs, etc. As another example, the process (1500) may control the accuracy of the inter-pulse period (e.g., pulse repetition period) with an accuracy of about 50 μs, 20 μs, 10 μs, 5 μs, less than 1 μs, etc.

[0218] FIG. 9 is a functional block diagram illustrating a nanosecond pulser system (900) according to some embodiments. In some embodiments, the nanosecond pulser system (900) may include all or part of the components illustrated or arranged in the nanosecond pulser system (100) and / or the nanosecond pulser system (150).

[0219] In some embodiments, the nanosecond pulser system (900) may include a chassis (905) surrounding some of the components. In some embodiments, the nanosecond pulser system (900) may include an ADC control module (912). The ADC control module (912) may include all or part of the components shown in the ADC control system (800).

[0220] In some embodiments, the nanosecond pulser system (900) may include a bias compensation module (965) (e.g., all or part of a component of a bias compensation circuit (104), a bias compensation circuit (514), or a bias compensation circuit (614)) and / or a bias capacitor (910) (e.g., a capacitor (C12)).

[0221] In some embodiments, the nanosecond pulser system (900) may include a heat exchanger subsystem (940).

[0222] In some embodiments, the nanosecond pulser system (900) may include a high-voltage DC power supply (950). The high-voltage DC power supply may supply DC power to the bias compensation module (965) or the nanosecond pulser (955).

[0223] In some embodiments, the nanosecond pulser system (900) may include a resistive output terminal (920) (e.g., a resistive output terminal (102)). In some embodiments, the nanosecond pulser system (900) may include any or all components, arrangements, functions, etc., shown and / or described in U.S. Patent Application Serial No. 15 / 941,931, filed March 30, 2018, titled “High Voltage Resistive Output Terminal Circuit,” which is incorporated herein by reference for all purposes.

[0224] In some embodiments, the nanosecond pulser system (900) may include an energy recovery circuit (165) as shown in FIG. 3.

[0225] In some embodiments, the nanosecond pulser system (900) may include an HVM module (915). In some embodiments, the HVM module (915) may include an EtherCAT slave module and / or a high-voltage DC power supply module. The HVM module (915) may include various connectors or ports for communication with an external system.

[0226] In some embodiments, the nanosecond pulser system (900) may include a control module (925). The control module (925) may include an EtherCAT slave module, a system-on-chip module, and / or an FPGA.

[0227] In some embodiments, the nanosecond pulser system (900) may include a second ADC module (930). The second ADC module (930) may include a microcontroller (e.g., all or part of the controller (825)) and / or an analog-to-digital converter (e.g., the second ADC (845)). For example, the microcontroller may include any or all components shown in the computing system (1600).

[0228] In some embodiments, the nanosecond pulser system (900) may have a modular design so that various modules can be easily replaced or repaired. For example, the nanosecond pulser system (900) may include a power input module, an AC heater filter module, a high-speed ADC module, a control module, and / or an HVM. For example, these modules may slide into the module. As another example, the nanosecond pulser system (900) may include other modules, such as, for example, a resistive output terminal resistor and / or inductor module, a thermal management system, and / or a nanosecond pulser. These modules may be accessed by removing or opening one or more covers from the system body.

[0229] In some embodiments, the nanosecond pulser system (900) may include a pulse bias generation (PBG) module. This module may generate output pulses at up to 8 kV and 900 kHz. For example, this module may include two or more nanosecond pulsers and / or resistive output stages.

[0230] In some embodiments, the nanosecond pulser system (900) may include a spatially variable wafer bias power system (e.g., some or all of the components of the spatially variable wafer bias power system (400)). In some embodiments, this module may be a smaller version of the pulse bias generation subsystem, such as scaled to about 25% power. In some embodiments, this module may drive the edges of the wafer separately from the central portion of the wafer. Various other implementations may be used in which different spatial regions of the wafer can be pulsed independently of each other.

[0231] In some embodiments, the nanosecond pulser system (900) may include an HVM module (e.g., a slide-in module). In some embodiments, this module may provide a DC chucking voltage.

[0232] In some embodiments, the nanosecond pulser system (900) may include an AC heater filter module (e.g., a slide-in module). In some embodiments, this module may filter AC power going to the heater element to minimize ground leakage current and prevent excessive power from being drawn from the PBG through the heater element to ground.

[0233] In some embodiments, the nanosecond pulser system (900) may include a control module and / or a second ADC (e.g., a slide-in module). In some embodiments, this module may allow the system to be controlled via EtherCAT. In some embodiments, this module may interface with an external DC power supply to control charging voltage and current. In some embodiments, this module may monitor internal sensors (e.g., temperature, flow, status, etc.) to check the system status.

[0234] In some embodiments, the nanosecond pulser system (900) may include a power distribution (e.g., a slide-in module). In some embodiments, this module may provide an interface to connect to an external power supply (e.g., HVDC and 3-phase 208V). In some embodiments, this module may include an ACDC power supply that generates the control voltage required for other modules inside the P1 chassis. In some embodiments, this module may provide a power distribution network to obtain the voltage required for the required modules of the system.

[0235] In some embodiments, the nanosecond pulser system (900) may include a chassis. In some embodiments, the chassis may include a mechanical assembly that secures all modules. In some embodiments, the chassis may provide RF sealing to prevent EMI from entering or leaking into the system. In some embodiments, the chassis may be modular to allow access to internal system components and / or may include a front removable cover. In some embodiments, the chassis may have side "slide-in" modules to allow for easy replacement as needed.

[0236] In some embodiments, the nanosecond pulser system (900) may include a thermal management subsystem (1000) that may include a heat exchanger, a plurality of fluid lines, and a plurality of cooling plates. In some embodiments, the thermal management subsystem may provide cooling to other system components. In some embodiments, the thermal management subsystem may include cooling water (e.g., 5 gpm or more). In some embodiments, the thermal management subsystem may include a heat exchanger to allow a dielectric coolant to circulate within the system, which may eliminate arc / capacitive coupling problems that may occur, for example, when water is used entirely. In some embodiments, the thermal management subsystem may include cooling plates for the switches and cores of the NSP and for the ROS and snubber resistors.

[0237] In some embodiments, the nanosecond pulser system (900) may include a sensor subsystem. In some embodiments, the sensor subsystem may provide all sensors necessary to monitor the state and operation of the system. In some embodiments, the sensor subsystem may include a temperature sensor that measures the temperature of key components (e.g., switches, cores, resistors, etc.) and / or dielectric fluid in the thermal management subsystem. In some embodiments, the sensor subsystem may include a flow / pressure sensor that can verify that the coolant is circulating properly and / or is not leaking. In some embodiments, the sensor subsystem may include a sensor for verifying nitrogen flow within the system, which may be necessary, for example, to prevent condensation.

[0238] FIG. 10 is a block diagram of a thermal management system (1000) according to some embodiments. In some embodiments, the thermal management system (1000) may include a main manifold (1005) and a heat exchanger (1010). The heat exchanger (1010) may exchange heat between the low-temperature side and the high-temperature side of the thermal management system. The high-temperature side may be fluidically coupled with any number of cooling plates so that the high-temperature system fluid returned from the cooling plates can be cooled by the facility fluid within the heat exchanger (1010). In some embodiments, the system fluid may include water, dielectric fluid, dielectric fluid Galden HT110, deionized water, glycol / water solution, aromatic dielectric fluid (e.g., DEB), silicate-ester-based dielectric fluid (e.g., Coolanol 25R), aliphatic dielectric fluid (e.g., PAO), silicon-based dielectric fluid (e.g., Syltherm XLT), fluorocarbon dielectric fluid (e.g., FC-77), ethylene glycol, propylene glycol, methanol / water, potassium formate / acetate solution, etc. In some embodiments, the facility fluid may include water, such as tap water.

[0239] In some embodiments, the facility side of the heat exchanger (1010) may receive facility fluid (e.g., water) from an external fluid source (1015). In some embodiments, the external fluid source (1015) may include a fluid inlet and a fluid outlet. In some embodiments, the external fluid source (1015) may include a facility fluid heat management system. In some embodiments, the external fluid source may include one or more pumps to ensure that facility fluid flows through the external fluid source including the heat exchanger (1010).

[0240] In some embodiments, the heat exchanger (1010) may exchange heat, for example, from a high-temperature side (e.g., various board components) to a low-temperature side (e.g., equipment). In some embodiments, the low-temperature side may include an equipment fluid (e.g., water) and the high-temperature side may include a system fluid (e.g., dielectric fluid). In some embodiments, the high-temperature side may include one or more switch cooling plates (1041, 1051), one or more core cooling plates (1046, 1047, 1056, 1057), one or more resistance cooling plates (1060, 1061, 1062, 1063), a snubber resistor cooling plate (1070, 1071), one or more liquid-to-air heat exchangers (1080, 1081), a pump (1025), and / or a reservoir (1020), etc. The high-temperature side may be a system that includes all of these. The cold side may be connected to an external fluid supply and / or thermal management system. In some embodiments, the system fluid may circulate faster than the facility fluid (e.g., twice as fast). In some embodiments, the system fluid may flow at a rate of about 1 to 100 gallons per minute, or the facility fluid may flow at a rate of about 1 to 100 gallons per minute. In some embodiments, the heat exchanger (1010) may facilitate heat exchange between the hot side and the cold side without transferring fluid between the hot side and the cold side.

[0241] In some embodiments, the high-temperature side of the heat exchanger (1010) may be connected to a cooling plate, a reservoir (1020), a pump (1025), or a main manifold (1030) through, for example, one or more pipes or tubes.

[0242] In some embodiments, the heat exchanger (1010) may include an expansion plate heat exchanger. In some embodiments, the heat exchanger (1010) may include a shell and tube heat exchanger. In some embodiments, the heat exchanger (1010) may include a double pipe heat exchanger.

[0243] In some embodiments, the reservoir (1020) may allow the system fluid to expand or contract as various components of the high-voltage nanosecond pulser system heat up during operation. In some embodiments, the reservoir (1020) may store excess system fluid to prevent the pump (1025) from operating dry. In some embodiments, the reservoir (1020) may be constructed in various ways, such as a welded steel container or a polymer container. In some embodiments, the reservoir (1020) may have a custom shape that can be sized or shaped to fit any configuration or space. In some embodiments, the reservoir (1020) may have an opening at the top of the reservoir (1020) so that the reservoir (1020) can be filled with additional system fluid. In some embodiments, the reservoir (1020) may include a pressure relief valve that can be automatically opened or closed to allow pressure within the reservoir to escape. In some embodiments, the reservoir (1020) may include multiple chambers or compartments that may be useful for separating bubbles or reducing obstructions to the flow of system fluid.

[0244] In some embodiments, the pump (1025) may pump system fluid through a heat exchanger (1010), a reservoir (1020), a main manifold (1030), tubes, pipes, or other components. For example, the pump (1025) may pump system fluid at a flow rate of about 10-30 gallons per minute or about 15-20 gallons per minute. In some embodiments, the pump may pump system fluid at a flow rate of about 18 gallons per hour. In some embodiments, the pump (1025) may include a self-driven pump, a centrifugal pump, a regenerative turbine pump, a mechanically sealed pump, etc. In some embodiments, the pump (1025) may include a variable frequency drive motor pump or a conventional single-speed centrifugal pump. In some embodiments, the pump may be wired so that the pump is automatically turned on when power is supplied to the entire system.

[0245] In some embodiments, the main manifold (1030) may distribute system fluid among any number of cooling plates. For example, the cooling plates may include one or more switch cooling plates (1041, 1051). An example of a switch cooling plate is shown in FIG. 11. For example, the cooling plates may include one or more core cooling plates (1046, 1047, 1056, 1057). Examples of core cooling plates are shown in FIG. 12, 13 and 14.

[0246] In some embodiments, the core cooling plate may interface with the toroidal transformer core to provide optimal cooling while minimizing the impact on transformer performance. In some embodiments, the core cooling plate may include an inner or outer insulating ring so that the transformer's continuous conductive sheet primary winding can be insulated from the core cooling plate. In some embodiments, the core cooling plate may be made of a tube pressed into an aluminum ring, or a larger diameter copper tube may be flattened into a ring shape to minimize the interaction of materials. As another example, the core cooling plate is made of a solid piece of copper with internally machined grooves to form an inner "tube," and then another piece of metal, such as copper, is soldered to the top.

[0247] For example, the cooling plate may include one or more resistor cooling plates (1060, 1061, 1062, 1063) and one or more snubber resistor cooling plates (1070, 1071). Examples of resistor cooling plates and snubber resistor cooling plates are shown in FIGS. 11 and 12. In some embodiments, the resistor cooling plate may include machined or soldered copper so that the resistor cooling plate can be made as thin as possible while handling high pressure / speed.

[0248] For example, the cooling plate may include one or more liquid-to-air heat exchangers (1080, 1081). One or more liquid-to-air heat exchangers (1080, 1081) can cool air circulating inside the nanosecond pulser system. A fan placed inside the nanosecond pulser system can circulate this cold air through parts to which the water-cooled cooling plate is not attached. For example, the heat exchangers can be used to cool diodes, gate driving circuits, switching regulators, etc.

[0249] In some embodiments, the main manifold (1030) may include a plurality of interconnected orifices coupled with a plurality of connectors. The plurality of connectors may be used to connect the tubes to various components. In some embodiments, each of the plurality of connectors may include a quick-connect connector for ease of assembly, disassembly, or maintenance. In some embodiments, each of the plurality of connectors may include a barb connector capable of generating less drag on the system fluid. In some embodiments, the manifold may have orifices of different sizes to allow different fluid flow rates for different components.

[0250] In some embodiments, the cooling plate may include various cooling plates that can be configured or modified to be combined with various components. In some embodiments, the cooling plate may be designed using computational fluid dynamics (CFD) to ensure proper cooling based on specific operating conditions (e.g., steady-state flow rate, pressure, temperature, etc.) or geometry of each component.

[0251] In some embodiments, the switch cooling plate and the core cooling plate may be designed and used to minimize size, stray capacitance, or stray inductance while removing as much heat as possible from each component in a uniform manner.

[0252] In some embodiments, the core cooling plate may introduce stray capacitance of about 10 pF, 1 pF, 100 nF, less than 10 nF, etc. For example, the stray capacitance measured between the secondary winding and ground with the core cooling plate in place is about 10 nF (or about 10 pF, 1 pF, 100 nF) greater than the stray capacitance between the secondary winding and ground without the core cooling plate.

[0253] In some embodiments, the core cooling plate may introduce stray inductances such as about 1 nH, 10 nH, 100 nH, 1 μH, or less than 10 μH as measured on the secondary side. For example, the stray inductance measured on the secondary side of a transformer with a core cooling plate may be less than 10 μH greater than the stray inductance on the secondary side of a transformer without a core cooling plate. As another example, the stray inductance measured on the primary side of a transformer with a core cooling plate may be less than 10 nH greater than the stray inductance on the secondary side of a transformer without a core cooling plate.

[0254] In some embodiments, the switch cooling plate may introduce a capacitance of less than about 10 nF. For example, the switch may include a heat sink. The switch cooling plate may be coupled with the heat sink. A first capacitance between the switch heat sink and ground may be determined without the switch cooling plate coupled with the heat sink. A second capacitance between the switch heat sink and ground may be determined by the switch cooling plate coupled with the heat sink. The difference between the first capacitance and the second capacitance may be a capacitance of less than 10 nF, such as a capacitance of less than about 5 nF, for example, between about 10 pF and 10 nF. As another example, when the switch cooling plate is coupled with the switch heat sink, the stray capacitance between the switch cooling plate and ground is less than 5 nF greater than the stray capacitance between the switch heat sink and ground when the first switch cooling plate is removed.

[0255] In some embodiments, the switch cooling plate may be coupled to the switch heat sink so that the switch cooling plate and the switch heat sink are at the same potential. This may also electrically connect the switch cooling plate to the collector (in the case of an IGBT) or the drain (in the case of a MOSFET) because the heat sink of the switch may be connected to the collector or the drain.

[0256] In some embodiments, a thermal (or electrical) insulating material may be placed between the switch and the switch cooling plate.

[0257] In some embodiments, the switch cooling plate and / or core cooling plate may have a minimized geometric structure.

[0258] In some embodiments, various cooling plates may be connected in series or in parallel to the main manifold (1030).

[0259] In this example, two circuit boards (1040, 1050) are included, each comprising a pulser and transformer terminal (e.g., pulser and transformer terminal (101)) and a transformer core. Each board may include one or more switch cooling plates capable of contacting one or more switches (e.g., switch (S1) in FIG. 1) and / or one or more core cooling plates capable of contacting one transformer core (e.g., transformer (T2) in FIG. 1). Multiple resistance cooling plates are coupled to a resistance output terminal resistor (e.g., resistor (R1) in FIG. 1) and a snubber resistor (e.g., resistor (R3) in FIG. 1). Each of these cooling plates may be fluidically connected to the main manifold via copper or plex piping. In some embodiments, the piping may have pipe sizes such as about 0.1", 0.2", 0.5".

[0260] In some embodiments, the heat transfer material may be used to bridge the gap between an electrical component (e.g., a switch, a resistor, a transformer core, etc.) and a cooling plate (e.g., one or more switch cooling plates (1041, 1051), one or more core cooling plates (1046, 1047, 1056, 1057), one or more resistance cooling plates (1060, 1061, 1062, 1063), a snubber resistance cooling plate (1070, 1071), or more liquid-to-air heat exchangers (1080, 1081). In some embodiments, the heat transfer material may be used to bridge the gap between a pipe and a cooling plate (e.g., one or more switch cooling plates (1041, 1051), one or more core cooling plates (1046, 1047, 1056, 1057), one or more resistance cooling plates (1060, 1061, 1062, 1063), A snubber resistance cooling plate (1070, 1071) can be placed between one or more liquid-to-air heat exchangers (1080, 1081).

[0261] In some embodiments, the heat transfer material may be very thin to minimize thermal resistance (e.g., as thin as 0.0005 inches and up to 0.1 inches thick). In some embodiments, the heat transfer material may have a thicker or uneven thickness to bridge gaps between objects with uneven surfaces or to provide structural rigidity. For example, the thermal interface material may be a solid, such as aluminum nitride, or deformable, such as conductive epoxy, thermal paste, or compressible thermal conductive pad. Depending on the application, the heat transfer material may be electrically insulating or electrically conductive.

[0262] In some embodiments, thermal epoxy may be used to mechanically and thermally attach the core cooling plate to the transformer core. For example, thermal epoxy has a higher thermal conductivity than standard RTV. In some embodiments, each switch may be bonded to the switch cooling plate using a thermally conductive adhesive pad that has higher thermal conductivity than thermal epoxy but is less structural. In some embodiments, clips may be attached to the switch cooling plate with screws. In some embodiments, a thin layer of thermally conductive paste, which may have higher thermal conductivity than the adhesive pad, may be used to bond the resistor and the resistor core cooling plate. In some embodiments, the resistor may be screwed onto the surface of the resistor cooling plate, which can provide a constant, uniform pressure to optimize heat transfer.

[0263] FIG. 11 illustrates an embodiment and / or arrangement of a switch cooling plate system (1100) (e.g., switch cooling plates (1041, 1051)). The switch cooling plate system (1100) may include a plurality of switch cooling plates (1105A, 1105B, 1105C, 1105D, 1105E, 1105F, 1105G, 1105H) (individually or collectively switch cooling plates (1105)) arranged in a circular or octagonal configuration (e.g., axially arranged around a center point) to be coupled with a switch (e.g., switch (S1) of FIG. 1) of a corresponding circular or octagonal configuration (e.g., axially arranged around a center point). The switch cooling plates (1105) may be coupled together via piping (1120, 1125). Piping (1120, 1125) can conduct system fluid, for example, through various switch cooling plates (1105). In some embodiments, two parallel piping lines can connect various switch cooling plates (1105) and conduct system fluid between the switch cooling plates (1105).

[0264] In some embodiments, each switch cooling plate (1105) may include a first surface and a second surface. Each switch cooling plate (1105) may include one or two channels (or grooves) cut through a second surface that is sized and configured to be rigidly bonded to the tubing (1120, 1125), such as having a channel diameter substantially similar to the tube diameter, for example. In some embodiments, the first surface may be substantially flat and may be bonded to the surface of the switch (e.g., the flat part of the switch) using a heat transfer material, such as a thermal conductive paste or adhesive (e.g., aluminum nitride). For example, the channels may be physically bonded to the tube using a heat transfer material, such as a thermal conductive paste or adhesive (e.g., aluminum nitride). In some embodiments, the piping (1120, 1125) forms an octagon that can be pressed into the channel of each switch cooling plate and / or then soldered to the inlet / outlet manifold (1110) or loopback manifold (1115) and screwed to the circuit board to which the switch is attached.

[0265] In some embodiments, the second surface of each switch cooling plate (1105) may be attached to one, two, four, eight, etc. switches, for example, through a thermally conductive paste or adhesive. In some embodiments, each switch cooling plate (1105) may include one or more mounting holes that can be coupled to switches.

[0266] In some embodiments, the system fluid may enter the inlet / outlet manifold (1110) through the inlet port (1140), enter the switch cooling plate system (1100) through the inlet / outlet manifold (1110), and exit the inlet / outlet manifold (1110) through the outlet port (1145). In some embodiments, the inlet port (1140) may include an inlet connector. In some embodiments, the outlet port may include an outlet connector. In some embodiments, the inlet / outlet manifold (1110) may include an aluminum material block. In some embodiments, the loopback manifold (1115) may include a metal material block such as, for example, aluminum, brass, bronze, or copper. In some embodiments, the loopback manifold (1115) may include plastic.

[0267] In some embodiments, the inlet / outlet manifold (1110) may divide the system fluid into two separate paths: the first path may conduct the system fluid through a pipe (1120) coupled to four switch cooling plates (1105G, 1105F, 1105E, 1105D) and again through a pipe (1125) coupled to these four switch cooling plates (1105G, 1105F, 1105E, 1105D); The second path allows the system fluid to pass through a pipe (1130) combined with four switch cooling plates (1105H, 1105A, 1105B, 1105C) and again through a pipe (1135) combined with these four switch cooling plates (1105H, 1105A, 1105B, 1105C).

[0268] In some embodiments, the loopback manifold (1115) may receive system fluid from pipe (1120) and return system fluid through pipe (1125). In some embodiments, the loopback manifold (1115) may receive system fluid from pipe (1130) and return system fluid through pipe (1135). For example, this arrangement may help keep the temperature difference between switches small and / or reduce the number of fittings.

[0269] In some embodiments, a heat transfer material may be placed between the pipe (1130) or pipe (1135) and each switch cooling plate (1105).

[0270] In some embodiments, the inlet / outlet manifold (1110) divides the system fluid into a first path that conducts the system fluid in one direction through various switch cooling plates (1105) from one pipe (e.g., pipe (1125)) and a second path that conducts the system fluid in the opposite direction through various switch cooling plates (1105) from another pipe (e.g., pipe (1120)) without a loopback manifold (1115).

[0271] In some embodiments, the switch cooling plate can maintain the surface temperature of various switches at a temperature of about 250 °C or less. In some embodiments, the switch cooling plate can remove more than about 1 W of heat from each switch.

[0272] FIGS. 12, 13, and 14 illustrate embodiments and / or configurations of a cooling plate (1200) (e.g., core cooling plate (1046, 1047, 1056, 1057)) according to some embodiments. In some embodiments, the core cooling plate (1200) may provide heat dissipation to one or more transformer cores, such as a toroidal transformer core. In some embodiments, the core cooling plate (1200) may be positioned between two transformer cores (1210, 1211), namely, one transformer core (1210) on one side of the core cooling plate (1200) and another transformer core (1211) on the other side of the core cooling plate (1200). In some embodiments, the core cooling plate may be positioned on the other side of the transformer cores (1210 and 1211).

[0273] In some embodiments, the system fluid may be pumped through the inner tube (1215) of the core cooling plate (1200) at a rate of 0.1 to 10 gallons per minute.

[0274] In some embodiments, as illustrated in FIGS. 13 and 14, the core cooling plate (1200) may be manufactured as a flat ring (1205) that may include an inner tube (1215). In some embodiments, the flat ring (1205) may have a toroidal or donut shape and may have an inner hole. In some embodiments, the flat ring may have an inner circumference or an outer circumference. The flat ring (1205) may include any metal, such as, for example, aluminum, brass, steel, bronze, copper, etc. In some embodiments, the inner tube (1215) may conduct system fluid between two transformer cores (1210, 1211). The inner tube (1215) may include, for example, copper tubing.

[0275] In some embodiments, the core cooling plate (1200) comprises a flat ring (1205), an inner tube (1215), an inner ring (1230), or an outer ring (1235). In some embodiments, the inner ring (1230) or the outer ring (1235) may comprise plastic or any other insulating material. In some embodiments, the inner ring (1230) may have an outer circumference substantially similar to the inner circumference of the flat ring (1205). In some embodiments, the inner ring (1230) may be placed within an inner opening of the flat ring (1205). In some embodiments, the outer ring (1235) may have an inner circumference substantially similar to the outer circumference of the flat ring (1205).

[0276] In some embodiments, the openings of the flat ring (1205), inner ring (1230), outer ring (1235), transformer core (1210), and transformer core (1211) may be substantially aligned along the axis through the center axis of each hole of the flat ring (1205), inner ring (1230), outer ring (1235), transformer core (1210), and transformer core (1211), for example.

[0277] In some embodiments, an inner ring (1230) or an outer ring (1235) may be attached to the inner and outer diameters of the transformer core to enable standoff from any primary transformer winding and / or secondary transformer winding that can be wound around the transformer core. In some embodiments, the inner ring (1230) or the outer ring (1235) may reduce capacitive or inductive coupling between the core cooling plate (1200) and any primary transformer winding and / or secondary transformer winding that can be wound around the transformer core.

[0278] In some embodiments, the inner tube (1215) may be coupled to an inlet connector (1220) and an outlet connector (1225). The inlet connector (1220) may be coupled to the inlet tube (1240) with, for example, a clamp (1260) (metal or plastic clamp) and a quick disconnect device, or soldered together. The inlet pipe (1240) may be coupled to the connector (1250) for example, through the clamp (1260). For example, the connector (1250) may be connected to the main manifold (1030). The outlet connector (1225) may be coupled to the outlet pipe (1241) for example, with the clamp (1260). The outlet pipe (1241) may be coupled to the connector (1251) for example, through the clamp (1260). For example, the connector (1251) may be connected to the main manifold (1030).

[0279] In some embodiments, the core cooling plate can maintain the surface temperature of the transformer core at a temperature of about 200°C or less. In some embodiments, the core cooling plate can remove more than about 1W of heat from the transformer core.

[0280] In some embodiments, the transformer core may include a ferrite core. In some embodiments, the transformer core may include a toroidal shape, a square shape, a rectangular shape, etc. In some embodiments, the transformer may include a cylindrical transformer.

[0281] In some embodiments, the thermal management system may include a number of sensors (e.g., sensors (850)), such as a pressure sensor in one or more system fluid lines, a thermal sensor (e.g., a thermometer, a thermistor, or a thermal cell), a liquid level sensor (e.g., inside a reservoir), or a flow meter. In some embodiments, the flow meter may be placed in or in line with one or more system fluid tubes. In some embodiments, the flow meter may be placed in or in line with one or more water tubes. In some embodiments, the thermal sensor may be placed in the system fluid tube at the inlet / outlet manifold or outlet port of the switch cooling plate system.

[0282] In some embodiments, these sensors may provide data to a controller or interlock system capable of adjusting the flow rate of one or both of the system fluid or facility fluid by, for example, changing the pump speed or opening and closing various valves throughout the system. In some embodiments, a high-voltage power supply may not turn on a specific sensor or may turn it off automatically.

[0283] In some embodiments, the temperature of the system fluid may be measured in the main manifold prior to the heat exchanger, pump output, resistor cooling plate, core cooling plate switch cooling plate, switch core cooling plate, or any other location. In some embodiments, the air temperature within the high-voltage power supply may be monitored using an air temperature sensor, such as a surface-mounted sensor, for example.

[0284] In some embodiments, the high-voltage power supply may not be turned on unless the water flow rate exceeds a flow threshold, for example, about 1, 2.5, 5, 7.5, or 10 gallons per minute. In some embodiments, the high-voltage power supply may not be turned on unless the water flow rate is below a flow threshold, for example, about 10, 20, 50, or 100 gallons per minute. For example, the water flow rate may be measured at or near the water inlet port.

[0285] In some embodiments, the high-voltage power supply may not be turned on unless the flow rate of the system fluid exceeds a flow threshold, for example, about 1, 2.5, 5, 7.5, or 10 gallons per minute. In some embodiments, the high-voltage power supply may not be turned on unless the flow rate of the system fluid is below a flow threshold, for example, about 10, 20, 50, or 100 gallons per minute. For example, the system fluid flow rate may be measured at or near the pump.

[0286] In some embodiments, when the input water temperature or system fluid temperature is greater than a temperature threshold, such as about 20 to 50°C, about 20 to 25°C, or about 20°C, the high voltage power supply may not be turned on.

[0287] In some embodiments, the high voltage power supply may be turned off when the input water temperature or system fluid temperature is greater than a temperature threshold value, such as, for example, about 50 to 70°C, about 50 to 60°C, or about 50°C.

[0288] In some embodiments, when the system fluid level of the reservoir is less than a certain amount or less than a pool ratio, such as about 30% to 75%, about 30% to 50%, or about 30% pool, the high voltage power supply may be turned off.

[0289] In some embodiments, when the temperature of the system fluid exiting one or more switch cooling plates is greater than a temperature threshold value, such as 50 to 75°C, about 50 to 55°C, or about 50°C, the high voltage power supply can be turned off.

[0290] In some embodiments, when the pressure of the system fluid system is below a pressure threshold, such as about 0 to 1.5 bar, about 0.5 to 1 bar, or about 1 bar, the high-voltage power supply may be turned off or not turned on. In some embodiments, when the pressure of the system fluid system is above a pressure threshold, such as about 1.7 to 3 bar, about 1.75 to 2 bar, or about 1.75 bar, the high-voltage power supply may be turned off or not turned on. For example, the pressure of the system fluid may be measured within any dielectric tube or pipe connected to the main manifold.

[0291] In some embodiments, when the pressure of the nitrogen sensor is below a pressure threshold value, such as below atmospheric pressure, for example, the high voltage power supply may be turned off or not turned on.

[0292] In some embodiments, when the leak sensor indicates that a fluid leak (system fluid or facility fluid) has occurred, the high-voltage power supply may be turned off or not turned on. For example, the leak sensor may include an optical sensor that indicates the presence of liquid when the optical sensor is obscured.

[0293] In some embodiments, any sensor may include a switch sensor. For example, the switch sensor may automatically close the switch when a detected threshold value is met. For example, the switch may open or close the circuit.

[0294] In some embodiments, multiple fans may be placed within a high-voltage nanosecond pulser system. For example, multiple fans may be used to circulate air within a high-voltage nanosecond pulser system. In this example, various fans are placed to create an airflow pattern that circulates cooled air upward from the bottom around the sides of various modules, for example, through a control interconnection board, to various heat exchangers that can be coupled to either or both of the system fluid system or the facility fluid system.

[0295] According to some embodiments, an inert gas purge subsystem may be included. In some embodiments, an inert gas (e.g., nitrogen, helium, argon, etc.) may flow through the system to reduce the possibility of condensation occurring in the cooling components. In some embodiments, nitrogen may enter through a nitrogen bulkhead (e.g., on the bottom surface of the chassis), pass through a filter and a nitrogen flow sensor, and move from an orifice limiter (e.g., limiting the nitrogen flow to 10 liters per minute) to a high-voltage nanosecond pulser system. In some embodiments, nitrogen may leave the chassis through another bulkhead, through a gap in the chassis or body, or at any other point of the chassis.

[0296] In some embodiments, the nanosecond pulser system may include an enclosure, and one or more nanosecond pulsers having various subsystems may be located within the enclosure. For example, two or more of the following may be within the enclosure: a thermal management system, a control system, a bias capacitor, a bias compensation power supply, a second nanosecond pulser, a resistive output stage, or an energy-reducing circuit. In some embodiments, the enclosure is about 1 m 3 It can have a volume of less than

[0297] In some embodiments, a plurality of resistive output stage resistors may be coupled to each nanosecond pulser. In some embodiments, a plurality of snubber resistors (R3) may be coupled to each nanosecond pulser. In some embodiments, various components may be slide-mounted within the chassis.

[0298] In some embodiments, internal and slide-in modules may be connected to an interconnection PCB. In some embodiments, the PCB may be designed to shield signals between ground layers to minimize EMI effects. In some embodiments, a rigid design may be used that is optimal for the placement / alignment of the slide-in modules. In some embodiments, the modules may be screwed together, and socket-style connections enable modularity compared to cable or solder connections.

[0299] In some embodiments, the peak electric field between any two components inside the enclosure may be less than about 20 MV / m.

[0300] Unless otherwise specified, the term “substantially” means within 5% or 10% of the stated value or within the manufacturing tolerance. Unless otherwise specified, the term “about” means within 5% or 10% of the stated value or within the manufacturing tolerance.

[0301] The computational system (1600) illustrated in FIG. 16 may be used to perform any embodiment of the present invention. As another example, the computational system (1600) may be used to perform any computation, identification, and / or decision described herein. The computational system (1600) includes hardware elements that can be electrically coupled (or appropriately communicated) via a bus (1605). The hardware elements may include one or more general-purpose processors and / or one or more special-purpose processors (such as digital signal processing chips, graphics acceleration chips, etc.); one or more input devices (1615) which may include, without limitation, a mouse, keyboard, etc.; and one or more output devices (1620) which may include, without limitation, a display device, printer, etc., and one or more processors (1610).

[0302] The computing system (1600) may further include one or more storage devices (1625) (and / or may communicate with them), which may include, without limitation, local and / or network-accessible storage and / or solid-state storage devices such as disk drives, drive arrays, optical storage devices, random access memory (“RAM”) and / or read-only memory (“ROM”), which may be programmable, flash-updatable and / or similar. The computing system (1600) may also include a communication subsystem (1630) which may, without limitation, include a modem, a network card (wireless or wired), an infrared communication device, a wireless communication device and / or a chipset (e.g., a Bluetooth device, an 802.6 device, a Wi-Fi device, a WiMAX device, a cellular communication facility, etc.) and / or similar. The communication subsystem (1630) may be capable of exchanging data with a network (e.g., a network described below) and / or any other device described herein. In many embodiments, the computing system (1600) may further include a working memory (1635) that may include a RAM or ROM device as described above.

[0303] The computing system (1600) may also include software elements depicted as being located within the current working memory (1635), including other code such as an operating system (1640) and / or one or more application programs (1645) that may be designed to implement the method of the present invention and / or constitute the system of the present invention as described herein. For example, one or more procedures described in relation to the method(s) discussed above may be implemented as code and / or instructions executable by a computer (and / or a processor within the computer). A set of these instructions and / or code may be stored in a computer-readable storage medium such as the storage device(s) (1625) described above.

[0304] In some cases, the storage medium may be integrated within the computing system (1600) or may communicate with the computing system (1600). In other embodiments, the storage medium may be detachable from the computing system (1600) (e.g., removable media such as a compact disk) or provided as an installation package, so that the storage medium may be used to program a general-purpose computer with instructions / code stored thereon. These instructions may take the form of executable code that can be executed by the computing system (1600) and / or take the form of source and / or installable code, which takes the form of executable code when compiled and / or installed on the computing system (1600) (e.g., using various commonly available compilers, installers, compression / decompression utilities, etc.).

[0305] Numerous specific details have been described in this specification to provide a thorough understanding of the subject matter claimed. However, those skilled in the art will understand that the subject matter claimed may be practiced without these specific details. In other examples, methods, apparatuses, or systems known to those skilled in the art have not been described in detail so as not to obscure the subject matter claimed.

[0307] Some parts are provided in terms of algorithms or symbolic representations of operations on data bits or binary digital signals stored within the memory of a computing system, such as computer memory. Such descriptions or representations of algorithms are examples of techniques used by a person of ordinary skill in data processing technology to convey the nature of the work to a person of the art. An algorithm is a coherent sequence of operations or similar processes leading to a desired result. In this context, operations or processes involve the physical manipulation of physical quantities. Generally, but not necessarily, these physical quantities may take the form of electrical or magnetic signals that can be stored, transmitted, combined, compared, or manipulated. It has proven convenient, primarily for general use, to refer to signals as bits, data, values, elements, symbols, characters, terms, numbers, numerical values, etc. However, it must be understood that these and similar terms are merely convenient labels and must be associated with the appropriate physical quantities. Unless otherwise specifically stated, descriptions using terms such as “processing,” “computing,” “calculation,” “decision,” and “identification” throughout this specification refer to the operation or process of a computing device, such as one or more computers or similar electronic computing devices or devices, which manipulates or transforms data represented as physical, electronic, or magnetic quantities within memory, registers, or other information storage devices, transmission devices, or display devices of a computing platform. The systems or systems described herein are not limited to a specific hardware architecture or configuration. A computing device may include any suitable arrangement of components that provide a coordinated result for one or more inputs. A suitable computing device includes a general-purpose microprocessor-based computer system that accesses stored software to program or configure a computing system from a general-purpose computing device to a specialized computing device that implements one or more embodiments of the subject matter.Any suitable programming, scripting, or other type of language or combination of languages ​​may be used to implement the instructions contained herein in software used to program or configure a computing device.

[0308] Embodiments of the method disclosed herein may be performed in the operation of such computing devices. The order of the blocks presented in the above examples may be changed. For example, blocks may be rearranged, combined, and / or divided into sub-blocks. Specific blocks or processes may be performed in parallel.

[0309] In this specification, the terms “adapted” or “configured” are used in an open and inclusive manner, not excluding devices adapted or configured to perform additional operations or steps. Furthermore, the use of “based” is used in an open and inclusive manner in that a process, step, calculation, or other operation “based” on one or more mentioned conditions or values ​​may actually be based on additional conditions or values ​​beyond those mentioned. Headings, lists, and numbering included in this specification are for convenience of description only and are not restrictive.

[0310] Although the gist of the invention has been described in detail with respect to specific embodiments, those skilled in the art will understand that modifications, variations, and equivalents to these embodiments can be easily achieved by understanding the foregoing. Accordingly, it should be understood that the present disclosure is presented for illustrative purposes rather than as a limitation, and does not exclude such modifications, changes, and / or additions to the subject matter as will be apparent to those skilled in the art.

Claims

Claim 1 A high-voltage pulsing power supply, comprising: a high-voltage pulser providing as output a plurality of pulses having an amplitude greater than 1 kV, a pulse width less than 1 μs, and a pulse repetition frequency greater than 20 kHz; a plasma chamber; an electrode disposed within the plasma chamber that is electrically coupled to the output of the high-voltage pulser to generate an electric field within the plasma chamber; and at least two of a thermal management system, a control system, a bias capacitor, a bias compensation power supply, and an energy recovery circuit disposed within an enclosure. Claim 2 A power supply device according to claim 1, wherein the inductance between the output of the high voltage pulser and the electrode is less than 10 μH. Claim 3 A power supply according to claim 1, wherein the capacitance between the output of the high voltage pulser and ground is less than 10nF. Claim 4 A power supply device according to claim 1, further comprising a control module for measuring the voltage of the plurality of pulses. Claim 5 A power supply according to claim 1, further comprising: a bias capacitor disposed between the high voltage pulser and the electrode; and a bias compensation power supply electrically coupled to the high voltage pulser and the electrode, wherein the bias compensation power supply generates a voltage across the bias capacitor. Claim 6 A power supply device according to claim 1, further comprising a high voltage pulser and a resistive output terminal electrically coupled to the electrode to remove charge from a load on a rapid time scale. Claim 7 A power supply according to claim 6, wherein the resistive output terminal comprises an inductor and a capacitor arranged in series, and the inductor has an inductance less than 200 μH. Claim 8 A power supply device according to claim 1, further comprising the high voltage pulser and an energy recovery circuit electrically coupled to the electrode to remove charge from the load on a rapid time scale. Claim 9 A power supply device according to claim 1, further comprising a control module electrically coupled to the high voltage pulser that generates a low voltage signal controlling the pulse width and pulse repetition frequency of the plurality of pulses. Claim 10 A power supply device according to claim 1, further comprising: a second high-voltage pulser providing as output a pulse having an amplitude greater than 1 kV, a pulse width less than 1 μs, and a pulse repetition frequency greater than 20 kHz; and the second electrode disposed within the plasma chamber, electrically coupled to the output of the second high-voltage pulser to generate a pulsing electric field within the plasma chamber near the second electrode. Claim 11 In claim 10, the power supply device wherein the pulse from the high voltage pulser and the pulse from the second high voltage pulser differ in at least one of the voltage, pulse width, and pulse repetition frequency. Claim 12 A power supply device according to claim 1, further comprising a thermal management subsystem including one or more switch cooling plates and one or more transformer core cooling plates, wherein the high voltage pulser includes a plurality of switches coupled to the one or more switch cooling plates and a transformer coupled to the one or more transformer core cooling plates. Claim 13 In claim 12, the thermal management subsystem comprises a fluid flowing through the switch cooling plate and the core cooling plate, a power device. Claim 14 In claim 1, the volume dimension is 1m 3 A power supply unit comprising a smaller enclosure, wherein the high voltage pulser is disposed within the enclosure; and at least three of a thermal management system, a control system, a bias capacitor, a bias compensation power supply, a second nanosecond pulser, a resistive output terminal, and an energy recovery circuit are disposed within the enclosure. Claim 15 A power supply according to claim 1, wherein the maximum electric field between any two components inside the enclosure is less than 20 MV / m. Claim 16 A high-voltage pulsing power supply, comprising: a high-voltage pulser providing as output a plurality of pulses having an amplitude greater than 1 kV, a pulse width less than 1 μs, and a pulse repetition frequency greater than 20 kHz—the high-voltage pulser comprising a plurality of switches and transformers; a plasma chamber; an electrode disposed within the plasma chamber and electrically coupled to the output of the high-voltage pulser to generate an electric field within the plasma chamber; and a control module electrically coupled to the high-voltage pulser—the control module measuring the voltage of the plurality of pulses at the electrode and the control module modifying at least one of the repetition frequency, pulse width, and voltage of the plurality of pulses in response to the measured voltage. A power device comprising - and further comprising, the high voltage pulser comprises a thermal management subsystem comprising a plurality of cooling plates coupled to the high voltage pulser, wherein the plurality of cooling plates comprises: one or more switch cooling plates coupled to the plurality of switches; and one or more transformer core cooling plates coupled to the transformer core, and the thermal management subsystem comprises a fluid flowing through at least one of the plurality of cooling plates. Claim 17 delete Claim 18 In claim 16, the power device comprising a thermal management subsystem including a fluid flowing through at least one of the plurality of cooling plates. Claim 19 A power supply device according to claim 16, wherein the control module measures one or more parameters of the thermal management subsystem and stops the high voltage pulser from outputting a plurality of pulses when one or more of the parameters is outside the tolerance. Claim 20 A high-voltage pulsing power supply comprises: a first high-voltage pulser providing a first plurality of pulses as a first output having a first amplitude greater than 1 kV, a first pulse width less than 1 μs, and a first pulse repetition frequency greater than 20 kHz; a second high-voltage pulser providing a second plurality of pulses as a second output having a second amplitude greater than 1 kV, a second pulse width less than 1 μs, and a second pulse repetition frequency greater than 20 kHz; a plasma chamber; a first electrode disposed within the plasma chamber and electrically coupled to the first output of the first high-voltage pulser; a second electrode disposed within the plasma chamber and electrically coupled to the second output of the second high-voltage pulser; and a first bias capacitor disposed between the first high-voltage pulser and the first electrode. A power supply device comprising a second bias capacitor disposed between the second high voltage pulser and the second electrode. Claim 21 A power supply according to claim 20, comprising: a first bias compensation power supply electrically coupled to the first high voltage pulser and the first electrode—the first bias compensation power supply generates a voltage across the first bias capacitor—; and a second bias compensation power supply electrically coupled to the second high voltage pulser and the second electrode—the second bias compensation power supply generates a voltage across the second bias capacitor. Claim 22 A power supply device according to claim 20, further comprising a thermal management subsystem including a plurality of cooling plates coupled to the first high-voltage pulser and the second high-voltage pulser. Claim 23 A power supply device according to claim 20, wherein one or both of the first bias capacitor or the second bias capacitor has a capacitance greater than 1 nF.

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