Method for manufacturing a standalone stress-free epitaxial layer starting from a disposable substrate patterned with an etched pillar array

Abstract

The method of the present invention provides the growth of an epitaxial layer (200) made of a first semiconductor material on a substrate (100) made of a second semiconductor material; said materials have different and different CTEs; said method A) A step of forming an array of pillars (110) by patterning the substrate (100) by an etching process, wherein the pillars (110) are laterally spaced from each other and have an upper section (112) that is larger than a lower section (114) and / or an intermediate section (116), B) a step of depositing the second semiconductor material on the upper part of the pillar (110) at a growth temperature to form an epitaxial layer (200) generated by vertical and lateral growth, and C) A step of inducing fracture of the pillar (110) by cooling the substrate (100) and the epitaxial layer (200) to a temperature below the growth temperature. Includes

Description

Technology Field

[0001] The present invention relates to a method for manufacturing a freestanding epitaxial layer starting from a disposable substrate; and a freestanding epitaxial layer formed by this method, in particular used as a substrate for manufacturing electrical or electronic or optoelectronic components, is also disclosed herein. Background Technology

[0002] The production of substrates for manufacturing electrical, electronic, or optoelectronic components is a critical step in microelectronics technology, as the quality of the functional films deposited on the substrate—that is, the core components—depends significantly on the characteristics of the substrate. Epitaxial growth of materials with different coefficients of thermal expansion (thermal mismatch) relative to the substrate leads to harmful warping of the wafer or extended cracks during the cooling process due to thermal stress generated by the accumulation of material on the film and subsequent shrinkage of the film compared to the substrate. Heteroepitaxy remains very popular because inexpensive substrates, such as silicon substrates, provide starting seeds for the epitaxial phases of functional materials, not only for economic reasons but also because it is the best method for inducing unique crystalline phases (e.g., cubic 3C-SiC on Si). It is necessary to properly orient the wafer surface to align the growth front of the film in a way that matches the crystalline phase of the epitaxial film or reduces the density of extension defects: for example, Si (111) appears suitable for reducing reverse phase domains and staking defects in cubic 3C-SiC. However, due to reasons related to the combination of elastic constants and low density of mobility extension defects in the mechanical properties of these materials, this orientation results in greater thermal stress, creating larger warping and extension cracks even at moderate film thicknesses. Cubic 3C-SiC cannot be deposited on planar Si (111) substrates with a film thickness exceeding 1 micron without creating extension cracks. Such thin thicknesses are not suitable for the manufacture of all power devices, not only for geometric reasons but also because the quality of the top functional part of the film, particularly the functional part of interest for electrical, electronic, and optoelectronic components, is known to generally improve with film thickness due to mutual defect annihilation.

[0003] In a prior patent application (WO2017186810A1 – currently granted in the U.S. as US 10,734,226 B2) and in the inventor's subsequent scientific paper, a method was discussed in which patterning of a substrate in a micrometer-sized pillar array within a defined area can accommodate different shrinkage of a film relative to the substrate by utilizing the lateral bending of the pillars. This adaptation mechanism is effective when the aspect ratio of the pillars is quantitatively adjusted with respect to the lateral size of the array, thereby creating a continuous film patch deposited on the pillars with reduced bending and no cracking. Thus, the substrate wafer can be patterned into multiple separated arrays through appropriate geometry, pillar pitch, and array separation, so that the entire wafer surface is covered with a film patch with a thickness of 10 to 20 micrometers, with reduced bending and no cracking. In the case of cubic 3C-SiC on Si (111), for example, the thickness of a film patch of about 500 micrometers can be as small as 20 micrometers, and the bending is significantly reduced and there are no cracks. This is particularly useful when the film is still integrated on a substrate and is suitable for all applications requiring both SiC and Si, such as power devices in 3C-SiC that are connected and driven by logic transistors on the Si side.

[0004] However, the inventors considered that when a standalone wafer of a deposited film is required for any standalone application, or when a standalone layer of a deposited film with a lateral size of several centimeters is required, the film thickness should be several hundred micrometers and a substrate can be placed thereon.

[0005] In a recent patent (US 10,153,207) granted to STMicroelectronics, this is achieved by epitaxially growing, for example, a SiC film on a planar, for example, Si substrate at a sufficiently high temperature, such that the substrate melts before growth is complete. This process works when the melting temperature of the substrate is significantly lower than the temperature of the film and the growth kinetics of the deposited film are suitable for this elevated temperature. This appears to be the case for SiC on Si. Still, apart from the aforementioned limitations in substrate and film properties, the melting of the substrate in the growth chamber requires a unique design of a susceptor and additional systems to capture the molten silicon.

[0006] In recent scientific literature, methods for providing lift-off of ultrathin films from a substrate (particularly those dealing with the production of multi-junction solar cells) can be classified into two main categories: one involves depositing a sacrificial layer between the film and the substrate, which is ultimately removed by wet etching, possibly in combination with additional process conditions (see e.g., Journal of Electronic Materials, vol. 24, No. 6, (1995) 757-760, and Applied Physics Letters, vol. 111, (2017) 233509); the other involves creating a porous silicon layer on top of the substrate, possibly with heat treatment, and ultimately removing the film deposited thereon by mechanical action such as rolling (see e.g., Solar Energy Materials and Solar Cells vol. 135, (2015) 113–123, and Solar Energy Materials and Solar Cells, vol. 203). (2019) 110108, or Joule, vol. 3, (2019) 1782-1793).

[0007] Still, apart from the complexity of the method and different objectives (including substrate reuse), the inventor considered that none of these rely solely on the spontaneous action of thermal stress during the inevitable cooling phase in the case of the lift-off process, and that there is no chemical action at all and no (or almost no) mechanical action, as described below, which is highly advantageous.

[0008] Therefore, there is a need to improve conventional technical methods for manufacturing substrates used in the manufacture of electrical, electronic, or optoelectronic components.

[0009] The general objective of the present invention is to satisfy these requirements.

[0010] These general and more specific purposes are achieved thanks to what is set forth in the appended claims, which form an essential part of this specification.

[0011] The first basic idea of ​​the present invention is to manufacture an independent epitaxial layer starting from a substrate to be placed.

[0012] The second basic idea of ​​the present invention is to use different semiconductor materials for the substrate and the epitaxial layer.

[0013] A third basic idea of ​​the present invention is to separate an epitaxial layer from a substrate without (or substantially without) mechanical and / or chemical post-processing steps. According to the present invention, separation is induced by (only or mainly) cooling of the produced structure; in particular, such cooling induces breaking due to different shrinkage of distinct parts of the produced structure.

[0014] The fourth basic idea of ​​the present invention is to grow an epitaxial layer on an array of pillars, particularly pillars derived from patterning a substrate.

[0015] Advantageously, the pillars are shaped and sized so that they break at the same (or approximately the same) location, particularly at the same (or approximately the same) depth from the upper surface of the substrate on which the pillars are etched.

[0016] Advantageously, the manufacturing method ensures that the deposited epitaxial layer is not laterally bonded (or substantially bonded) so that the layer becomes free from the substrate when the pillar breaks. In particular, this can be achieved in two ways: the deposited layer is surrounded by free space, or the deposited layer is surrounded by members or members of different materials that are not attached to the material of the epitaxial layer. Brief explanation of the drawing

[0017] The present invention will become more clear from the following detailed description, which should be considered together with the attached drawings, and in the drawings FIG. 1 schematically illustrates a vertical cross-section of one embodiment of a structure according to the present invention before and after cooling, and FIG. 2 schematically illustrates a series of steps of one embodiment of the method according to the present invention, and FIG. 3 schematically illustrates columns of one embodiment of a structure manufactured according to the present invention, and FIG. 4 schematically illustrates a cross-section of a first exemplary detailed structure of one embodiment of a structure manufactured according to the present invention, and FIG. 5 schematically illustrates a cross-section of a second exemplary detailed structure of one embodiment of a structure manufactured according to the present invention, and FIG. 6 schematically illustrates a top view of a first exemplary seed of one embodiment of a structure manufactured according to the present invention, and FIG. 7 schematically illustrates a top view of a first exemplary patch of one embodiment of a structure manufactured according to the present invention, and FIG. 8 schematically illustrates a top view of a second exemplary seed of one embodiment of a structure manufactured according to the present invention, and FIG. 9 schematically illustrates a top view of a second exemplary patch of one embodiment of a structure manufactured according to the present invention. As will be readily understood, there are various methods for substantially carrying out the present invention, which are defined in their most advantageous aspects by the appended claims and are not limited by the specific details for carrying out the invention below or the attached drawings. Specific details for implementing the invention

[0018] A structure manufactured according to the present invention essentially comprises a manufactured semiconductor substrate (e.g., a substrate labeled 100 in FIGS. 1 and 2), and a semiconductor epitaxial layer (e.g., a layer labeled 200 in FIGS. 1 and 2) formed on top of the substrate through a high-temperature epitaxial growth process performed in the reaction chamber of an epitaxial reactor.

[0019] The growth temperature depends on various elements, particularly semiconductor materials, precursor materials, growth pressure, and the type of epitaxial reactor. For example, and without any intent to limit the invention, single-crystal silicon can be epitaxially grown on single-crystal silicon at 1150 °C and 100 kPa, single-crystal hexagonal silicon carbide can be epitaxially grown on single-crystal hexagonal silicon carbide at 1650 °C and 10 kPa, and single-crystal cubic silicon carbide can be epitaxially grown on single-crystal silicon at 1370 °C and 13 kPa.

[0020] Once the high-temperature epitaxial growth process is completed, the structure is extracted from the reaction chamber and cooled to, for example, room temperature (e.g., 20 to 30°C).

[0021] Structures manufactured according to the present invention typically undergo many other processing steps in addition to the high-temperature epitaxial growth process.

[0022] FIG. 1a schematically illustrates one embodiment of a structure according to the present invention before cooling the inside of a reaction chamber, and FIG. 1b illustrates the same structure after cooling the outside of the reaction chamber.

[0023] In FIG. 1, for example, a substrate (100) made of silicon is patterned and a plurality of pillars (110) are formed, and for example, an epitaxial layer (200) of silicon carbide is positioned on the substrate (100), particularly on the pillars (110); both the substrate and the layer continue, for example, from the right, and are shown in a pointed shape.

[0024] According to the embodiment of FIG. 1, the column (110) has a suitable shape; there is a large upper section (112) (adjacent to the floor (200)) and a small lower section (114); the cross-sectional area of ​​the column (110) gradually increases as it moves from the lower section (114) to the middle section (116) and then from the middle section (116) to the upper section (112); thus, there is a necking (118) on the column (110) in this middle section.

[0025] During the cooling phase, the silicon carbide epitaxial layer (200) shrinks more than the silicon substrate (100) due to the different CTE (=coefficient of thermal expansion) of the two materials; the white arrow in FIG. 1b indicates thermal stress within the epitaxial layer (100). Due to this thermal stress within the layer (200), shear stress is generated within the columns (110). If the columns (110) are (sufficiently) thin, this thermal stress can lead to their fracture; it should be noted that in FIG. 1b, all the columns (110) have fractured; and the columns (110) have fractured at their necking (118), that is, where their cross-sectional area is minimal. FIG. 1b illustrates that after fracture, a portion of the columns (110) (i.e., their upper portions) may remain bonded to the layer (200), and a portion of the columns (110) (i.e., their lower portions) may remain integral with the substrate (100).

[0026] When all the pillars (110) are broken, the layer (200) is completely free from the substrate (100). If some pillars (110) are not broken and / or if any mechanical connection remains between the substrate (100) and the layer (200), a (small) force or (small) torque may be applied to the substrate (100) and / or the layer (200) to free the layer (200) from the substrate (100).

[0027] In this stage, a substrate (100) of FIG. 1b including any portion of the pillars (110) may be disposed, and a layer (200) of FIG. 1b including any portion of the pillars (110) is a standalone epitaxial layer (where its thickness is sufficiently high, for example, 50 to 500 microns, preferably 150 to 300 microns) and may be used as a substrate for manufacturing electrical or electronic or optoelectronic components or as a substrate for further epitaxial growth.

[0028] After separating the layer (200) from the substrate (100), especially when the upper part of the pillar (110) remains bonded to the layer (200), it may be advantageous to lap the back surface of the layer (200) so that the independent epitaxial layer is flat on both sides.

[0029] According to the embodiment of FIG. 1, it should be noted that due to cooling, the epitaxial layer shrinks more than the substrate. However, alternatively, according to the present invention, it may be preferable for the substrate to shrink more than the epitaxial layer. What happens depends on the CTE of the material of the substrate and the material of the layer.

[0030] A possible process for providing the structure of Fig. 1a is described below with the help of Fig. 2.

[0031] The starting point of this process is a substrate (100) made of single-crystal silicon, as shown in FIG. 2a.

[0032] A substrate (100) is appropriately masked to be etched; FIG. 2a illustrates the substrate (100), and a plurality of mask members (150) are placed on its flat upper surface. Subsequently, a first etching step is performed and a plurality of deep, narrow vertical grooves (122) are formed as shown in FIG. 2c; this may be referred to as a "vertical" etching step. In this way, an array of vertical columns is formed on the upper surface of the substrate (100). This first etching step may be performed through a dry etching process, for example, a Bosch process (well known to experts) or a cryo process.

[0033] Subsequently, a second etching step is performed and the groove (122) is enlarged to create a number of deep, shaped vertical grooves (124) as shown in FIG. 2d. In this way, the array of columns is transformed into an array of columns (110) spaced laterally apart from each other as shown in FIG. 1a. This second etching step can be performed through an isotropic dry etching process or a wet etching process (well known to experts).

[0034] Subsequently, the mask member (150) is removed from the upper section of the pillar (110) through a third etching step, such as illustrated in FIG. 2e, leaving a flat and smooth “epitaxy-ready” surface (119) on the upper part of the pillar (110); as is known, “epitaxy-ready” means preparation for subsequent epitaxy forming a single-crystal material. This third etching step may be performed through a dry etching process or a wet etching process (well known to experts) and may include surface oxidation and oxide wet stripping.

[0035] In this stage, the epitaxial deposition process of silicon carbide is carried out at a high temperature. For this purpose, the structure shown in FIG. 2e is introduced, for example, into the reaction chamber of an epitaxial reactor.

[0036] In the following, the epitaxial deposition process is divided into three consecutive deposition sub-steps for simple exemplary explanation; however, this should not be interpreted as a limitation of the invention; in fact, as is known to experts, the actual deposition step (corresponding to step B described above) is very complex and progresses through several sub-steps. FIGS. 2f, 2g, and 2h may correspond to different moments of a single deposition step B.

[0037] After the first deposition sub-step, single-crystal silicon carbide seeds (210) are formed on each surface (119) of the pillar (110) as shown in FIG. 2f. The seeds (210) are laterally spaced from each other. During this first deposition, it can be assumed that growth is mainly in the vertical direction.

[0038] After the second deposition sub-step, the seed (210) grows in both the vertical and lateral directions, so that an array of adjacent silicon carbide seeds (220) is formed as shown in FIG. 2g - the merging of multiple seeds into a single patch begins.

[0039] After the third deposition sub-step, a (suitably thick) layer (200) of silicon carbide is formed on the pillar (110) as shown in FIG. 2h.

[0040] At this stage, the structure can be extracted from the reaction chamber of the epitaxial reactor; typically, the structure may still be at a relatively high temperature at the time of extraction.

[0041] Generally, a method for manufacturing a standalone epitaxial layer according to the present invention is based on the use of two different semiconductor materials having different CTEs.

[0042] According to embodiments of the present invention, the substrate may belong to a first series (allowing for easy patterning), for example, Si, Ge, or SiGe, a second series, including GaAs, GaP, ZnSe, ZnS, SiC, and GaN, or a third series (i.e., oxides), such as ZnO, Al2O3, and MgAlO4.

[0043] According to embodiments of the present invention, the epitaxial layer may comprise Si, Ge, GaN (hexagonal and cubic) and SiC (hexagonal and cubic), which are attractive as semiconductor materials for power electronics and / or optoelectronics, for example.

[0044] Generally, a method for manufacturing a standalone epitaxial layer according to the present invention comprises the following steps (referencing FIGS. 1 and FIGS. 2, but not limited to):

[0045] A) (refer particularly to FIG. 2) a step of patterning a substrate (100) of a first semiconductor material by an etching process to form an array of pillars (110), wherein the pillars (110) are appropriately spaced laterally from each other and have an upper section (112) that is larger than a bottom section (114) and / or an intermediate section (116),

[0046] B) (Refer particularly to FIG. 2) a step of depositing a second semiconductor material at a growth temperature on the upper part of a pillar (110) so as to form an epitaxial layer (200) generated by vertical and lateral growth of the second semiconductor material, and

[0047] C) (Refer particularly to FIG. 1) A step of cooling the substrate (100) and the epitaxial layer (200) to a growth temperature below the growth temperature to induce fracture of the pillar (110).

[0048] The upper section of the column must be able to allow for the subsequent growth of single-crystal material (in particular, it must be flat and smooth). The lower and / or middle sections are preferably very narrow so that they fracture relatively easily. More details regarding the shape and size of the column will be provided later; typically, the columns are identical or very similar.

[0049] A method for controlling the ratio between vertical and lateral growth in step B is known to those skilled in the art; typically, this is achieved by controlling the deposition conditions.

[0050] Step B may include one or more consecutive deposition steps.

[0051] In step C, it may be typical to cool the structure to room temperature, but this is not strictly necessary. In other processing steps after step C, if the column (preferably all or most of the column, for example, more than 80 to 90%) is fractured, it may be desirable to lower the temperature to, for example, only 10 to 40% of the growth temperature.

[0052] As is already evident from the description of the embodiments of FIGS. 1 and 2, it is advantageous for the pillars to be manufactured by a multi-step etching process of the substrate.

[0053] This multi-stage etching process may include at least two dry etching steps to suitably shape the pillars, particularly to form a necking (118 in FIG. 1) in the middle section of the pillars; the necking is arranged to fracture under thermal stress according to step C. Preferably, the necking is formed at the same (or nearly the same) depth from the top surface of the substrate so that the pillars fracture at the same (or nearly the same) location.

[0054] This multi-stage etching process may include a wet etching process to form an epitaxially prepared surface (119 in FIG. 2) on the upper section of the pillar (112 in FIG. 1).

[0055] The steps of the method according to the present invention are typically designed so that the epitaxial layer deposited in step B extends only in the area corresponding to the array of columns. For example, it should be noted that due to lateral growth, the area of ​​the epitaxial layer may not exactly correspond to the area occupied by the array of columns.

[0056] Now, refer to Fig. 3, where three columns (300) correspond to the columns (110) of Fig. 1 and Fig. 2. The shape of the cross-section of the columns will be considered later; for simplification, it is now assumed to be circular.

[0057] The column (300) can be considered to have a “T-shaped” geometric shape having a wide upper section (302) supported by a narrow stem (304); an intermediate section (116 in FIG. 1A) is located between the upper section (302) and the stem (304), and a necking exists in the column of this intermediate section; in fact, there are multiple intermediate sections (306) between the upper section (112 in FIG. 1A) and the lower section (114 in FIG. 1A). In particular, the cross-sectional area of ​​the stem (304) gradually decreases as it moves from the bottom to this intermediate section, and the cross-sectional area of ​​the upper section (302) gradually increases as it moves from this intermediate section to the top.

[0058] The size (312) of the upper section may be, for example, in the range of 3 microns to 20 microns, preferably in the range of 5 microns to 10 microns.

[0059] The size of the distance (314) between the upper sections of two consecutive columns may be, for example, in the range of 1 micron to 5 microns, preferably in the range of 1.5 microns to 3 microns.

[0060] The size (322) of the middle section in the necking may be, for example, in the range of 0.2 microns to 2 microns, preferably in the range of 0.7 microns to 1.5 microns.

[0061] The size (332) of the bottom section may be, for example, in the range of 1.5 microns to 5 microns, preferably in the range of 2 microns to 3.5 microns.

[0062] The height (342) of the upper part (302) may be, for example, in the range of 1 micron to 10 microns, preferably in the range of 1.2 microns to 5 microns.

[0063] The height (344) of the stem (304) may be, for example, in the range of 7 microns to 30 microns, preferably in the range of 9 microns to 15 microns.

[0064] Accordingly, the height of the column may be, for example, in the range of 8 microns to 40 microns, preferably in the range of 10 microns to 20 microns.

[0065] Accordingly, the distance (334) between the vertical axes of two consecutive columns may be, for example, in the range of 2.5 microns to 15 microns, preferably in the range of 4 microns to 8 microns.

[0066] The shape of the cross-section of the column can be, for example, square (see Fig. 8), rectangular, pentagonal, hexagonal (see Fig. 6), circular, or elliptical. Typically, the column maintains the same or nearly the same shape along its length, but preferably, its cross-sectional area differs.

[0067] In the above description, it was assumed that the epitaxial layer is not laterally bonded (or is not substantially bonded), so the layer becomes free from the substrate when the pillar breaks.

[0068] According to a first possibility, which can be better understood by referring to FIG. 4, a trench (400 in FIG. 4) is formed around an array of pillars (100 in FIG. 4) on the substrate so that the epitaxial layer (200 in FIG. 4) is not laterally bonded. Typically, the trench is around the entire perimeter of the pillar array. For example, during step B, the semiconductor material is not deposited only on the pillars but also around the pillars (see 230 in FIG. 4) and inside the trench (see 240 in FIG. 4); however, due to the depth of the trench, a void remains around the epitaxial layer (200 in FIG. 4).

[0069] According to a second possibility, which may be better understood by referring to FIG. 5, a frame of a third material (500 in FIG. 5) is formed around an array of pillars (110 in FIG. 5) on a substrate (100 in FIG. 5), and an epitaxial layer (200 in FIG. 5) is loosely laterally bonded to the frame (500 in FIG. 5). Typically, the frame is around the entire perimeter of the pillar array. If the material of the layer is single-crystal silicon carbide, the material of the frame (different from the material of the layer) may be, for example, amorphous or polycrystalline silicon carbide. For example, during step B, the semiconductor material is not deposited only on the pillars but also around the pillars (see 500 in FIG. 4). According to an embodiment of FIG. 5, the deposited material, for example, silicon carbide, is the same, but the grown material is different; This is due to, for example, a layer (450) of silicon nitride or silicon oxide formed before the frame around the column array.

[0070] FIG. 6 illustrates an embodiment in which the cross-sectional shape of the column is hexagonal; in particular, reference 600 corresponds to a very thin (e.g., less than 1 micron) seed on the column that has not yet been merged together to form a patch or layer (e.g., refer to FIG. 2f). The distance (602) between consecutive seeds may be in the range of 1 micron to 5 microns, preferably in the range of 1.5 microns to 3 microns.

[0071] FIG. 8 illustrates an embodiment in which the cross-sectional shape of the column is square; in particular, reference 800 corresponds to a very thin (e.g., less than 1 micron) seed on the column that has not yet been merged together to form a patch or layer (e.g., refer to FIG. 2f). The distance (802) between consecutive seeds may be in the range of 1 micron to 5 microns, preferably in the range of 1.5 microns to 3 microns.

[0072] The conceptual similarity between Fig. 6 and Fig. 8 is evident.

[0073] FIGS. 6 and FIGS. 8 illustrate an embodiment in which a set of distinct individual arrays of pillars is formed on a substrate in step A to form a corresponding set of epitaxial layer patches in step B (see FIG. 7, where each patch is labeled 700, and FIG. 9, where each patch is labeled 900). FIG. 6 illustrates three sets of pillars (610, 620, and 630); they are laterally spaced further apart from the seed; and this distance (604) may be in the range of 3 microns to 10 microns, preferably in the range of 5 microns to 8 microns. FIG. 8 illustrates four sets of pillars (810, 820, 830, and 840); they are laterally spaced further apart from the seed; These distances (804) may be in the range of 3 microns to 10 microns, preferably in the range of 5 microns to 8 microns. In particular, if these patches are considered as separate, independent epitaxial layers, much longer distances should not be excluded.

[0074] Each of these patches (e.g., 700 in FIG. 7 and 900 in FIG. 9) may be a standalone epitaxial layer and may be used as a substrate for manufacturing electrical or electronic or optoelectronic components; in this case, their size must be relatively large, for example, the size (702) of patch (700) and the size (902) of patch (900) may be in the range of 100 microns to 1000 microns (e.g., corresponding to the size of a single electrical or electronic or optoelectronic component). However, handling small patches may be difficult; therefore, the aforementioned sizes may be increased for handling purposes.

[0075] The conceptual similarity between Fig. 7 and Fig. 9 is evident.

[0076] Patches, for example, the patch (700) of FIG. 7 and the patch (900) of FIG. 9 can be used as starting building blocks or starting points to form a larger epitaxial layer; in this case, their size should be relatively small, for example, the size (702) of the patch (700) and the size (902) of the patch (900) can be smaller than several hundred microns.

[0077] In this case, a set of consecutive thin patches is formed through Step 1 B as illustrated in FIGS. 7 and 9 (since these patches do not need to be "standalone," their thickness may be relatively small, for example, in the range of 5 to 50 microns); then, Step 1 C can be used to break most of the pillars for each patch. Subsequently, Step 2 B is performed to merge the patches and grow a thick (for example, in the range of 50 to 500 microns, preferably in the range of 150 to 300 microns) wide (for example, in the range of 1,000 to 10,000 microns, but roughly the size of the entire wafer or, for example, roughly 1 / 2, 1 / 3, 1 / 4, or 1 / 5 of the entire wafer or less) standalone epitaxial layer. Finally, Step 2 C can be used to break the remaining pillars.

[0078] As previously indicated, a standalone epitaxial layer can be formed through the method of the present invention and can be arranged to be used as a substrate for manufacturing electrical or electronic or optoelectronic components or as a substrate for further epitaxial growth. Such a layer can be considered as the final product of the method of the present invention.

[0079] Generally, the standalone epitaxial layer can be of any size nearly equal to the size of the starting single-use substrate (which must be slightly smaller) and of any shape (in particular, circular or square).

[0080] It should be noted that the method of the present invention forms an intermediate product if, for example, the method is stopped immediately after step A, immediately after step B, or immediately after step C (particularly if the epitaxial layer is not completely separated from the disposable substrate).

Claims

Claim 1 A method for manufacturing a freestanding epitaxial layer (200) starting from a substrate (100) that can be disposed thereon, wherein the epitaxial layer (200) is made of a first semiconductor material, the substrate (100) is made of a second semiconductor material, the first semiconductor material is different from the second semiconductor material, and the CTE of the first semiconductor material is different from the CTE of the second semiconductor material; A) a step of patterning the substrate (100) by an etching process to form an array of pillars (110), wherein the pillars (110) are laterally spaced from each other and have an upper section (112) that is larger than a lower section (114) and / or an intermediate section (116); B) a step of depositing the second semiconductor material on the upper portion of the pillars (110) at a growth temperature to generate by vertical and lateral growth of the second semiconductor material The method comprises the steps of: forming an epitaxial layer (200); and C) inducing breaking of the pillars (110) by cooling the substrate (100) and the epitaxial layer (200) to a temperature below the growth temperature, wherein (i) the pillars (110) are manufactured by a multi-step etching process of the substrate (100), the multi-step etching process comprises at least two dry etching steps to form a necking (118) at an intermediate section of the pillars (110) or at the same depth from the upper surface of the substrate (100), and the necking (118) is arranged to break under thermal stress according to step C; or (ii) the method is such that the epitaxial layer (200) extends only in an area corresponding to an array of the pillars (110). or (iii) a trench around the array of pillars (110) on the substrate (100);A method comprising: (400) being formed so that the epitaxial layer (200) is not laterally bonded; or (iv) a frame (500) of a third material being formed around an array of pillars (110) on the substrate (100) so that the epitaxial layer (200) is laterally loosely bonded to the frame (500); or (v) a set of separate individual arrays of pillars being formed on the substrate in step A to form a set of epitaxial layer patches in step B. Claim 2 In claim 1, the method wherein the pillar (110) is manufactured by a multi-stage etching process of the substrate (100). Claim 3 In paragraph 2, the multi-stage etching process comprises at least two dry etching steps to form a necking (118) at the same depth from the upper surface of the substrate (100) or in the middle section of the column (110), and the necking (118) is arranged to break under thermal stress according to step C. Claim 4 A method according to claim 2 or 3, wherein the multi-stage etching process comprises a wet etching step to form an epi-ready surface in the upper section (112). Claim 5 A method according to any one of claims 1 to 3, wherein the epitaxial layer (200) is extended only in the region corresponding to the array of the columns (110). Claim 6 A method according to any one of claims 1 to 3, wherein a trench (400) is formed around the array of pillars (110) on the substrate (100) so as not to cause the epitaxial layer (200) to be joined laterally. Claim 7 A method according to any one of claims 1 to 3, wherein a frame (500) of a third material is formed around an array of pillars (110) on the substrate (100), and the epitaxial layer (200) is loosely coupled laterally to the frame (500). Claim 8 A method according to any one of claims 1 to 3, wherein step B comprises two or more consecutive deposition steps. Claim 9 A method according to any one of claims 1 to 3, wherein a set of separate individual arrays of pillars is formed on the substrate in step A and a set of epitaxial layer patches is formed in step B. Claim 10 In claim 9, steps B and C are repeated to merge the set of epitaxial layer patches and form a single independent epitaxial layer. Claim 11 A method according to claim 1, further comprising the step of D) applying force or torque to free the epitaxial layer (200) from the substrate (100) after step C. Claim 12 A method according to claim 1 or 11, further comprising the step of E) lapping the back surface of the epitaxial layer (200) after step C or step D.

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