Semiconductor device and electronic device

Abstract

The present invention provides a novel shift register. The transistor (101), transistor (102), transistor (103), and transistor (104) are included. The transistor (101) has a first terminal connected to wiring (111) and a second terminal connected to wiring (112). The transistor (102) has a first terminal connected to wiring (113) and a second terminal connected to wiring (112). The transistor (103) has a first terminal connected to wiring (113) and a gate connected to wiring (111) or wiring (119). The transistor (104) has a first terminal connected to the second terminal of transistor (103), a second terminal connected to the gate of transistor (101), and a gate connected to the gate of transistor (102).

Description

Technology Field

[0001] One embodiment of the present invention relates to a semiconductor device, a display device, a display module, and an electronic device.

[0002] However, one embodiment of the present invention is not limited to the technical field described above. The technical field of the invention disclosed in this specification, etc., relates to objects, methods, or manufacturing methods. Alternatively, one embodiment of the present invention relates to processes, machines, products, or compositions of matter. Therefore, examples of more specific technical fields of one embodiment of the invention disclosed in this specification include semiconductor devices, display devices, light-emitting devices, capacitor devices, memory devices, methods for driving or manufacturing the same. Background Technology

[0003] In recent years, the development of shift registers composed of transistors with the same polarity has been underway. Patent Documents 1 and 2 disclose technology regarding such shift registers. Prior art literature

[0004] Japanese Patent Publication No. 2004-103226 and Japanese Patent Publication No. 2005-050502 The problem to be solved

[0005] In the shift register illustrated in Fig. 7 of Patent Document 1, voltage VOFF is output when the transistor (M2) is turned on. However, since the transistor (M2) is turned off during the period when GOUT[N-1] is at a high level, the period during which voltage VOFF is output is short. Additionally, since the gate of the transistor (M2) is connected to the gate of the transistor (M4), when the transistor (M2) is turned on, the transistor (M4) is also turned on. Therefore, if the transistor (M2) is turned on during the period when GOUT[N-1] is at a high level, the shift register does not function.

[0006] In the shift register illustrated in Fig. 7 of Patent Document 2, voltage VOFF is output when either transistor (Q53) or transistor (Q56) is turned on. During the period when signal IN1 is at a high level, transistor (Q53) is in the off state, but since transistor (Q56) is in the on state, voltage VOFF is output. However, to realize this, two transistors, transistor (Q53) and transistor (Q56), are required, so the number of transistors increases.

[0007] One embodiment of the present invention has as its objective to provide a novel circuit configuration. In particular, it has as its objective to provide a novel circuit configuration applicable to a part of a shift register or to a part of a sequence circuit having said shift register. One embodiment of the present invention has as its objective to extend the period for outputting voltage, or to provide a circuit configuration capable of realizing this. One embodiment of the present invention has as its objective to extend the period during which a transistor for outputting voltage is in the ON state, or to provide a circuit configuration capable of realizing this. One embodiment of the present invention has as its objective to reduce the number of transistors. One embodiment of the present invention has as its objective to reduce power consumption. One embodiment of the present invention has as its objective to reduce the layout area. One embodiment of the present invention has as its objective to reduce the manufacturing process. One embodiment of the present invention has as its objective to reduce manufacturing costs.

[0008] Furthermore, the description of these problems does not prevent the existence of other problems. Also, one embodiment of the present invention is not required to solve all of these problems. Furthermore, problems other than these become naturally apparent from the description in the specification, drawings, claims, etc., and problems other than these can be derived from the description in the specification, drawings, claims, etc. means of solving the problem

[0009] One embodiment of the present invention is a semiconductor device comprising first to fourth transistors. One of the source and drain of the first transistor is electrically connected to a first wiring. The other of the source and drain of the first transistor is electrically connected to a second wiring. One of the source and drain of the second transistor is electrically connected to a third wiring. The other of the source and drain of the second transistor is electrically connected to the second wiring. One of the source and drain of the third transistor is electrically connected to the third wiring. One of the source and drain of the fourth transistor is electrically connected to the other of the source and drain of the third transistor. The other of the source and drain of the fourth transistor is electrically connected to the gate of the first transistor. The gate of the fourth transistor is electrically connected to the gate of the second transistor.

[0010] In the semiconductor device above, the gate of the third transistor may be electrically connected to the first wiring.

[0011] In the above semiconductor device, the gate of the third transistor may be electrically connected to the fourth wiring.

[0012] In the above semiconductor device, the W (channel width) / L (channel length) of the fourth transistor may be higher than the W / L of the third transistor.

[0013] In the above semiconductor device, the area where the semiconductor layer and the gate electrode of the fourth transistor overlap may be larger than the area where the semiconductor layer and the gate electrode of the third transistor overlap.

[0014] In the semiconductor device above, at least one of the first to fourth transistors may have a channel forming region in the oxide semiconductor. Effects of the invention

[0015] One embodiment of the present invention may provide a novel circuit configuration. Brief explanation of the drawing

[0016] Figure 1 is a circuit diagram of a sequence circuit. Figure 2 is a timing chart of a sequence circuit. Figure 3 is a circuit diagram of a sequence circuit. Figure 4 is a circuit diagram of a sequence circuit. Figure 5 is a circuit diagram of a sequence circuit. Figure 6 is a circuit diagram of a sequence circuit. Figure 7 is a circuit diagram of a sequence circuit. Figure 8 is a circuit diagram of a sequence circuit. Figure 9 is a circuit diagram of a sequence circuit. Figure 10 is a circuit diagram of a sequence circuit. Figure 11 is a circuit diagram of a shift register. Figure 12 is a timing chart of a shift register. FIG. 13 is a diagram illustrating the configuration of a semiconductor display device. Fig. 14 is a top view of a pixel. Fig. 15 is a cross-sectional view of a pixel. FIG. 16 is a diagram illustrating the cross-sectional structure of a transistor. FIG. 17 is a top view of a liquid crystal display device. FIG. 18 is a cross-sectional view of a liquid crystal display device. FIG. 19 is a drawing illustrating an electronic device. Specific details for implementing the invention

[0017] In the following, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the description below, and those skilled in the art will readily understand that various changes to its form and details can be made without departing from the spirit and scope of the present invention. Accordingly, the present invention is not to be interpreted as being limited to the contents of the embodiments described below.

[0018] One embodiment of the present invention includes various semiconductor devices using transistors, such as integrated circuits, RF tags, and semiconductor display devices. Additionally, integrated circuits include microprocessors, image processing circuits, Digital Signal Processors (DSPs), Large Scale Integrated Circuits (LSIs) including microcontrollers, and Programmable Logic Devices (PLDs) such as Field Programmable Gate Arrays (FPGAs) or Complex PLDs (CPLDs). Furthermore, semiconductor display devices include liquid crystal display devices, light-emitting devices comprising light-emitting elements represented by organic light-emitting diodes (OLEDs) in each pixel, electronic paper, Digital Micromirror Devices (DMDs), Plasma Display Panels (PDPs), and Field Emission Displays (FEDs), as well as semiconductor display devices having circuit elements using semiconductor films in their driving circuits.

[0019] In this specification, the term "semiconductor display device" includes within its scope a panel in which display elements, such as liquid crystal elements or light-emitting elements, are formed in each pixel, and a module in which an IC including a controller is mounted on the panel.

[0020] For example, where it is explicitly stated in the present specification, etc. that "X and Y are connected," this includes cases where X and Y are electrically connected, cases where X and Y are functionally connected, and cases where X and Y are directly connected. Accordingly, the connection relationship is not limited to a predetermined connection relationship, for example, a connection relationship shown in drawings or text, but is also considered to include connections other than those shown in drawings or text.

[0021] Here, X and Y are objects (e.g., devices, components, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0022] An example of a case where X and Y are electrically connected is when one or more components (e.g., switches, transistors, capacitive elements, inductors, resistors, diodes, display elements, light-emitting elements, loads, etc.) that enable the electrical connection between X and Y are connected between X and Y. Additionally, the switch is controlled to be in an ON state and an OFF state. That is, the switch has the function of controlling whether current flows by becoming in a conducting state (ON state) or a non-conducting state (OFF state). Alternatively, the switch has the function of selecting and switching the path through which current flows.

[0023] An example of a case where X and Y are functionally connected is when one or more circuits that enable the functional connection between X and Y are connected between X and Y (e.g., logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boost circuits, step-down circuits, etc.), level shifter circuits that change the potential level of a signal, etc.), voltage sources, current sources, switching circuits, amplifier circuits (circuits capable of increasing signal amplitude or current amount, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc.). Additionally, as an example, even if other circuits exist between X and Y, X and Y are considered to be functionally connected if a signal output from X is transmitted to Y.

[0024] In addition, where it is explicitly stated that "X and Y are connected," it includes cases where X and Y are electrically connected (i.e., X and Y are connected via other components or circuits), cases where X and Y are functionally connected (i.e., X and Y are functionally connected via other components or circuits), and cases where X and Y are directly connected (i.e., X and Y are connected without other components or circuits interposing them). That is, cases where it is explicitly stated that "they are electrically connected" are equivalent to cases where it is explicitly stated that "they are connected."

[0025] In addition, for example, if the source (or first terminal, etc.) of a transistor is electrically connected to X through (or without) Z1 and the drain (or second terminal, etc.) of a transistor is electrically connected to Y through (or without) Z2, or if the source (or first terminal, etc.) of a transistor is directly connected to a part of Z1 and another part of Z1 is directly connected to X, and the drain (or second terminal, etc.) of a transistor is directly connected to a part of Z2 and another part of Z2 is directly connected to Y, it can be expressed as follows.

[0026] For example, it can be expressed as, "X, Y, the source (or first terminal, etc.) of a transistor, and the drain (or second terminal, etc.) of a transistor are electrically connected to each other, and are electrically connected in the order of X, the source (or first terminal, etc.) of a transistor, the drain (or second terminal, etc.) of a transistor, and Y." Or, it can be expressed as, "The source (or first terminal, etc.) of a transistor is electrically connected to X, and the drain (or second terminal, etc.) of a transistor is electrically connected to Y, and X, the source (or first terminal, etc.) of a transistor, the drain (or second terminal, etc.) of a transistor, and Y are electrically connected in this order." Alternatively, it may be expressed as, "X is electrically connected to Y through the source (or first terminal, etc.) of the transistor and the drain (or second terminal, etc.) of the transistor, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are provided in this order of connection." By defining the order of connection in the circuit configuration using the expression method described above, the source (or first terminal, etc.) of the transistor and the drain (or second terminal, etc.) of the transistor can be distinguished to determine the technical scope. However, these expression methods are merely examples and are not limited thereto. Here, X, Y, Z1, and Z2 are objects (e.g., devices, components, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0027] The source of a transistor refers to a source region, which is part of a semiconductor film functioning as an active layer, or a source electrode electrically connected to said semiconductor film. Similarly, the drain of a transistor refers to a drain region, which is part of a semiconductor film functioning as an active layer, or a drain electrode electrically connected to said semiconductor film. Additionally, the gate refers to the gate electrode.

[0028] The names of the source and drain of a transistor change depending on the channel type of the transistor and the level of potential supplied to each terminal. Generally, in the case of an n-channel transistor, the terminal supplied with a low potential is called the source, and the terminal supplied with a high potential is called the drain. In addition, in the case of a p-channel transistor, the terminal supplied with a low potential is called the drain, and the terminal supplied with a high potential is called the source. In this specification, for convenience, the connection relationships of the transistor are sometimes described by assuming that the source and drain are fixed, but in reality, the names of the source and drain change according to the relationship of the potential.

[0029] (Embodiment 1)

[0030] In this embodiment, a sequence circuit (also called a semiconductor device) is described.

[0031] An example of the configuration of a sequence circuit is described with reference to FIG. 1. FIG. 1 is an example of a circuit diagram of a sequence circuit. The sequence circuit shown in FIG. 1 has transistors (101) to transistors (107) and wiring (111) to wiring (115).

[0032] Additionally, the transistors (101) to (107) illustrated as examples in FIG. 1 are n-channel type transistors. However, they are not limited to this, and the transistors (101) to (107) may be p-channel type transistors. If the conductivity types of the transistors (101) to (107) are all the same, the manufacturing process can be simplified compared to a CMOS circuit, thereby reducing manufacturing costs.

[0033] In addition, when transistors (101) to (107) are n-channel type transistors, an oxide semiconductor, amorphous silicon, or microcrystalline silicon can be used in the channel forming region. This simplifies the manufacturing process compared to when polycrystalline silicon is used in the channel forming region, thereby reducing manufacturing costs. In particular, if an oxide semiconductor is used in the channel forming region, the off-current of transistors (101) to (107) can be made very small, thus allowing for a reduction in power consumption.

[0034] The connection relationships of each transistor are described. Transistor (101) has a first terminal connected to wiring (111) and a second terminal connected to wiring (112). Transistor (102) has a first terminal connected to wiring (113) and a second terminal connected to wiring (112). Transistor (103) has a first terminal connected to wiring (113) and a gate connected to wiring (111). Transistor (104) has a first terminal connected to the second terminal of transistor (103), a second terminal connected to the gate of transistor (101), and a gate connected to the gate of transistor (102). Transistor (105) has a first terminal connected to wiring (114), a second terminal connected to the gate of transistor (101), and a gate connected to wiring (115). A transistor (106) has a first terminal connected to the wiring (115), a second terminal connected to the gate of the transistor (102), and the gate connected to the wiring (115). A transistor (107) has a first terminal connected to the wiring (113), a second terminal connected to the gate of the transistor (102), and the gate connected to the gate of the transistor (101). In this way, a new circuit configuration can be provided.

[0035] In addition, the gate of the transistor (101) is labeled as node (N1), and the gate of the transistor (102) is labeled as node (N2).

[0036] An example of a signal or voltage input to each wire is described. Signal CK1 is input to wire (111), voltage VSS is input to wire (113), signal SP is input to wire (114), and signal CK2 is input to wire (115). Then, signal OUT is output to wire (112) according to signals CK1, CK2, and SP. Signals CK1 and CK2 are clock signals. Signals CK1 and CK2 have different phases. Signal SP is a start pulse (also called a set signal). Voltage VSS is a power supply voltage or ground voltage. Signal OUT is the output signal of the sequence circuit.

[0037] Also, for convenience, the high level potential of signals CK1, CK2, and SP is set to VDD (VDD > VSS), and the low level potential is set to VSS.

[0038] In addition, one embodiment of the present invention includes within its scope a state in which a signal or voltage, etc., is not input to each wiring. For example, each wiring may be capable of receiving the signal or voltage.

[0039] Explain the function of each transistor.

[0040] The transistor (101) controls the conduction or non-conduction state between the wiring (111) and the wiring (112) according to the potential of the node (N1). Then, the transistor (101) supplies signal CK1 to the wiring (112) according to the potential of the node (N1) to make signal OUT a high level.

[0041] The transistor (102) controls the conduction or non-conduction state between the wiring (113) and the wiring (112) according to the potential of the node (N2). Then, the transistor (102) supplies voltage VSS to the wiring (112) according to the potential of the node (N2) to set the signal OUT to a low level.

[0042] The transistor (103) controls the conduction or non-conduction state between the wiring (113) and the first terminal of the transistor (104) according to the signal CK1. Additionally, the transistor (104) controls the conduction or non-conduction state between the second terminal of the transistor (103) and the node (N1) according to the potential of the node (N2). That is, the circuit having the transistor (103) and the transistor (104) controls the conduction or non-conduction state between the wiring (113) and the node (N1) according to the signal CK1 and the potential of the node (N2). Furthermore, the circuit having the transistor (103) and the transistor (104) supplies voltage VSS to the node (N1) according to the signal CK1 and the potential of the node (N2) to set the potential of the node (N1) to a value at which the transistor (101) becomes off.

[0043] The transistor (105) controls the conduction or non-conduction state between the wiring (114) and the node (N1) according to the signal CK2. Then, the transistor (105) supplies the signal SP to the node (N1) according to the signal CK2 to set the potential of the node (N1) to a value that turns the transistor (101) on. After that, the transistor (105) stops supplying the signal SP to the node (N1) to make the node (N1) a floating state.

[0044] The transistor (106) controls the conduction or non-conduction state between the wiring (115) and the node (N2) according to the signal CK2. Then, the transistor (106) supplies the signal CK2 to the node (N2) according to the signal CK2, thereby setting the potential of the node (N2) to a value that turns on the transistor (102) and the transistor (104).

[0045] The transistor (107) controls the conduction or non-conduction state between the wiring (113) and the node (N2) according to the potential of the node (N1). Then, the transistor (107) supplies voltage VSS to the node (N2) according to the potential of the node (N1) to set the potential of the node (N2) to a value in which the transistor (102) and the transistor (104) become off.

[0046] An example of the operation of the sequential circuit illustrated in FIG. 1 will be explained with reference to FIG. 2 to 4. FIG. 2 shows signals CK1, CK2, signal SP, and the potential (V) of node (N1). N1 ), potential of node (N2) (V N2 This is a timing chart showing an example of the signal OUT, and the ), and signal OUT. Fig. 3 (A) is a schematic diagram of the operation from time t1 to time t2 (also called period T1), and Fig. 3 (B) is a schematic diagram of the operation from time t2 to time t3 (also called period T2). Fig. 4 (A) is a schematic diagram of the operation from time t3 to time t4 (also called period T3), and Fig. 4 (B) is a schematic diagram of the operation from time t4 to time t5 (also called period T4).

[0047] In addition, signals CK1 and CK2, shown as examples in FIG. 2, have equal lengths for the high-level period and the low-level period in one cycle, and a phase difference of 180°. That is, signal CK1 is the inverted signal of signal CK2. Also, signal SP, shown as an example in FIG. 2, has a pulse width that is half the period of signal CK1 or signal CK2.

[0048] First, at time t1, signal SP becomes high level, signal CK1 becomes low level, and signal CK2 becomes high level.

[0049] The potential of node (N1) is as follows. When signal CK2 becomes high level, transistor (105) turns on. Also, when signal CK1 becomes low level, transistor (103) turns off. Additionally, as described later, the potential of node (N2) becomes high value, and transistor (104) turns on. Accordingly, since the high-level signal SP is supplied to node (N1) through transistor (105), the potential of node (N1) rises. After that, when the potential of node (N1) rises to the value obtained by subtracting the threshold voltage of transistor (105) from the potential of the gate of transistor (105), that is, the value obtained by subtracting the threshold voltage of transistor (105) from the high-level potential of signal CK2 (VDD-Vth105), transistor (105) turns off. Then, node (N1) becomes floating, and the potential of node (N1) is maintained at VDD-Vth105.

[0050] The potential of node (N2) is as follows. When the signal CK2 becomes high level, the transistor (106) turns on. Also, when the potential of node (N1) becomes high, the transistor (107) turns on. Accordingly, the signal CK2, which is at a high level, is supplied to node (N1) through the transistor (106), and the voltage VSS is supplied through the transistor (107). Therefore, the potential of node (N2) is determined according to the resistance ratio of the transistor (106) and the transistor (107). Here, the resistance value between the source and drain of the transistor (106) is made sufficiently smaller than that of the transistor (107). And, the potential of node (N2) is made to be a value sufficiently higher than VSS. Specifically, the potential of the node (N2) is higher than the sum of the potential of the first terminal of the transistor (102) and the threshold voltage of the transistor (102), and also higher than the sum of the potential of the first terminal of the transistor (104) and the threshold voltage of the transistor (104), that is, higher than the sum of the voltage VSS and the threshold voltage of the transistor (102) (VSS+Vth102), and also higher than the sum of the voltage VSS and the threshold voltage of the transistor (104) (VSS+Vth104).

[0051] The potential of the wiring (112) is as follows. The potential of node (N1) becomes a high value, and the transistor (101) turns on. Also, the potential of node (N2) becomes a high value, and the transistor (102) turns on. Accordingly, a low-level signal CK1 is supplied to the wiring (112) through the transistor (101), and a voltage VSS is supplied through the transistor (102), so that the potential of the wiring (112) becomes VSS. That is, the signal OUT becomes a low level.

[0052] Next, at time t2, signal SP becomes low level, signal CK1 becomes high level, and signal CK2 becomes low level.

[0053] The potential of node (N1) is as follows. When signal CK2 becomes low level, transistor (105) is kept off. When signal CK1 becomes high level, transistor (103) is turned on. As described later, when the potential of node (N2) becomes VSS, transistor (104) is turned off. Therefore, node (N1) is kept in a floating state, and the potential of node (N1) is maintained at VDD-Vth105. However, as described later, as the potential of the wiring (112) rises, the potential of node (N1) rises further.

[0054] The potential of node (N2) is as follows. When the signal CK2 becomes low level, the transistor (106) is turned off. Also, when the potential of node (N1) becomes high, the transistor (107) is kept off. Accordingly, voltage VSS is supplied to node (N2) through the transistor (107), and the potential of node (N2) becomes VSS.

[0055] The potential of the wiring (112) is as follows. The potential of the node (N1) is maintained at a high value, so that the transistor (101) remains in the ON state. Also, the potential of the node (N2) becomes VSS, so that the transistor (102) becomes OFF. Accordingly, a high-level signal CK1 is supplied to the wiring (112) through the transistor (101), and the potential of the wiring (112) rises. At this time, the potential difference between the node (N1) and the wiring (112) is maintained by the parasitic capacitance between the gate of the transistor (101) and the second terminal. Also, the node (N1) is in a floating state. Therefore, as the potential of the wiring (112) rises, the potential of the node (N1) also rises. Here, the potential of the node (N1) is set to be higher than the sum of the potential of the first terminal of the transistor (101) and the threshold voltage of the transistor (101), that is, the sum of the high level potential of signal CK1 and the threshold voltage of the transistor (101) (VDD+Vth101). Therefore, the potential of the wiring (112) rises until it reaches VDD. That is, the signal OUT becomes a high level.

[0056] Next, at time t3, signal SP is maintained at a low level, signal CK1 becomes low level, and signal CK2 becomes high level.

[0057] The potential of node (N1) is as follows. When signal CK2 becomes high level, transistor (105) turns on. When signal CK1 becomes low level, transistor (103) turns off. Also, as described later, when the potential of node (N2) becomes high value, transistor (104) turns on. Accordingly, signal SP, which is at a low level, is input to node (N1), and the potential of node (N1) becomes VSS.

[0058] The potential of node (N2) is as follows. When signal CK2 becomes high level, transistor (106) turns on. Also, when the potential of node (N1) becomes VSS, transistor (107) turns off. Accordingly, since the high-level signal CK2 is supplied to node (N2) through transistor (106), the potential of node (N2) rises. Then, when the potential of node (N2) rises to the value obtained by subtracting the threshold voltage of transistor (106) from the potential of the gate of transistor (106), that is, the value obtained by subtracting the threshold voltage of transistor (106) from the high-level potential of signal CK2 (VDD-Vth106), transistor (106) turns off. Then, node (N2) becomes floating and the potential of node (N2) is maintained at VDD-Vth106.

[0059] The potential of the wiring (112) is as follows. When the potential of node (N1) becomes VSS, the transistor (101) is turned off. Also, when the potential of node (N2) becomes a high value, the transistor (102) is turned on. Accordingly, voltage VSS is supplied to the wiring (112) through the transistor (102), and the potential of the wiring (112) becomes VSS. That is, the signal OUT becomes a low level.

[0060] Next, at time t4, signal SP is maintained at a low level, signal CK1 becomes high level, and signal CK2 becomes low level.

[0061] The potential of node (N1) is as follows. When signal CK2 becomes low level, transistor (105) is turned off. Also, when signal CK1 becomes high level, transistor (103) is turned on. Additionally, as described later, the potential of node (N2) is maintained at a high value, so transistor (104) is turned on. Accordingly, voltage VSS is supplied to node (N1) through transistor (103) and transistor (104), and the potential of node (N1) is maintained at VSS.

[0062] The potential of node (N2) is as follows. When signal CK2 becomes low level, transistor (106) is turned off. Also, when the potential of node (N1) becomes VSS, transistor (107) is turned off. Therefore, node (N2) becomes floating and the potential of node (N2) is maintained at VDD-Vth106.

[0063] The potential of the wiring (112) is as follows. The potential of node (N1) is maintained at VSS, so that the transistor (101) is kept in the off state. Also, the potential of node (N2) is maintained at a high value, so that the transistor (102) is kept in the on state. Accordingly, voltage VSS is continuously supplied to the wiring (112) through the transistor (102), so that the potential of the wiring (112) is maintained at VSS. That is, the signal OUT is maintained at a low level.

[0064] After time t5, until signal SP becomes high level again, the operation at time t3 to time t4 and the operation at time t4 to time t5 are repeated whenever signal CK1 and signal CK2 are inverted.

[0065] An example of the effect exhibited by the sequence circuit shown in Fig. 1 will be explained.

[0066] It can provide a new circuit configuration.

[0067] By turning off the transistor (103) during period T1, the gate of the transistor (102) can be connected to the gate of the transistor (104), and the transistor (102) can be turned on during periods T1, T3, and T4. Thus, the period during which the transistor (102) is turned on can be extended, thereby extending the period during which the voltage VSS is supplied to the wiring (112). Additionally, since there is no need to provide a transistor that alternately turns on with the transistor (102), the number of transistors can be reduced. Furthermore, the on / off of the transistor (102) and the transistor (104) can be controlled by a common signal or a common circuit, thereby reducing the number of signals or reducing the circuit size.

[0068] By connecting a transistor (104) between the transistor (103) and the node (N1), it is possible to make it difficult for potential fluctuations of the gate of the transistor (103) to be transmitted to the node (N1). By doing so, the potential of the node (N1) can be stabilized and malfunctions can be suppressed.

[0069] A circuit configuration capable of producing the aforementioned effects can be provided.

[0070] An example of W (channel width) and L (channel length) of transistors (101) to transistors (107) will be described.

[0071] The load of the wiring (112) is often greater than the load of the node (N1) and the node (N2). Therefore, it is desirable that the W / L of the transistor (101) be higher than the W / L of the transistor (103). It is desirable that the W / L of the transistor (101) be higher than the W / L of the transistor (104). It is desirable that the W / L of the transistor (101) be higher than the W / L of the transistor (105). It is desirable that the W / L of the transistor (101) be higher than the W / L of the transistor (106). It is desirable that the W / L of the transistor (101) be higher than the W / L of the transistor (107). Additionally, it is desirable that the W / L of the transistor (102) be higher than the W / L of the transistor (103). It is desirable that the W / L of the transistor (102) be higher than the W / L of the transistor (104). It is desirable that the W / L of the transistor (102) be higher than the W / L of the transistor (105). It is preferable that the W / L of the transistor (102) be higher than the W / L of the transistor (106). It is also preferable that the W / L of the transistor (102) be higher than the W / L of the transistor (107). This allows the current supply capability of the transistor (101) and the transistor (102) to be increased, thereby allowing the change in signal OUT to be rapid. In addition, the load of the wiring (112) can be increased. Meanwhile, since the size of the transistors (103) to the transistor (107) can be reduced, the layout area of ​​the sequential circuit can be reduced.

[0072] The load of node (N1) is often greater than the load of node (N2). Therefore, it is desirable that the W / L of transistor (105) be higher than the W / L of transistor (106). It is also desirable that the W / L of transistor (105) be higher than the W / L of transistor (107). This increases the current supply capability of transistor (105), thereby allowing the potential of node (N1) to change quickly and increasing the operating speed of the sequential circuit. Meanwhile, since the size of transistor (106) and transistor (107) can be reduced, the layout area of ​​the sequential circuit can be reduced.

[0073] The transistor (105) is turned on to change the potential of the node (N1), while the transistors (103) and (104) are turned on to maintain the potential of the node (N1). Therefore, it is desirable that the W / L of the transistor (105) be higher than the W / L of the transistor (103). It is also desirable that the W / L of the transistor (105) be higher than the W / L of the transistor (104). This increases the current supply capability of the transistor (105), allowing the potential of the node (N1) to be changed quickly and the operation speed of the sequential circuit to be increased. Meanwhile, since the size of the transistors (103) and (104) can be reduced, the layout area of ​​the sequential circuit can be reduced.

[0074] Transistors (103) and (104) are connected in series between the wiring (113) and the node (N1), and a transistor (107) is connected between the wiring (113) and the node (N2). Additionally, the load of the node (N1) is often greater than the load of the node (N2). Therefore, it is desirable that the W / L of the transistor (103) be higher than the W / L of the transistor (107). Additionally, it is desirable that the W / L of the transistor (104) be higher than the W / L of the transistor (107). This increases the current supply capability of the transistors (103) and (104), allowing the potential of the node (N1) to be lowered quickly and improving the operating speed of the sequential circuit. Furthermore, the potential of the node (N1) can be reliably maintained at VSS, thereby suppressing malfunctions. Meanwhile, since the size of the transistor (107) can be reduced, the layout area of ​​the sequential circuit can be reduced.

[0075] The smaller the area where the semiconductor layer and the gate electrode overlap in the transistor (103), the more difficult it is for the potential of the gate of the transistor (103) to be transferred to the node (N1). However, if the area where the semiconductor layer and the gate electrode overlap in the transistor (103) is made small, there is a concern that the current supply capability of the transistor (103) will be low, so it is desirable to increase the current supply capability of the transistor (104). Therefore, it is desirable that the area where the semiconductor layer and the gate electrode overlap in the transistor (104) is larger than the area where the semiconductor layer and the gate electrode overlap in the transistor (103). Alternatively, it is desirable that the W / L of the transistor (104) is higher than the W / L of the transistor (103). Alternatively, it is desirable that the W×L of the transistor (104) is higher than the W×L of the transistor (103).

[0076] In order to make the resistance value between the source and drain of the transistor (106) sufficiently smaller than that of the transistor (107), it is desirable that the W / L of the transistor (106) be higher than that of the transistor (107).

[0077] A modified example of the sequence circuit shown in FIG. 1 will be described. However, for parts common to FIG. 1, the same reference numerals will be used, or they will not be shown and their descriptions will be omitted.

[0078] As shown in FIG. 5 (A), the gate of the transistor (105) may be connected to the wiring (114). The transistor (105) shown in FIG. 5 (A) supplies the signal SP to the node (N1) according to the signal SP. Thus, malfunction caused by a timing mismatch between the signal SP and the signal CK2 can be prevented.

[0079] As shown in FIG. 5 (B), the first terminal of the transistor (105) may be connected to the wiring (115), and the gate of the transistor (105) may be connected to the wiring (114). The transistor (105) shown in FIG. 5 (B) supplies signal CK2 to the node (N1) according to signal SP. Therefore, the potential change of the node (N1) can be made rapid, thereby improving the operating speed of the sequence circuit.

[0080] As shown in (C) of FIG. 5, the first terminal of the transistor (105) may be connected to the wiring (117), and the gate of the transistor (105) may be connected to the wiring (114). Voltage VDD is supplied to the wiring (117). The transistor (105) shown in (C) of FIG. 5 supplies voltage VDD to the node (N1) according to the signal SP. Thus, the potential change of the node (N1) can be made rapid, thereby improving the operating speed of the sequential circuit.

[0081] Additionally, two or more of the transistors (105) shown in (A), (B), and (C) of FIG. 1 and FIG. 5 may be provided in the sequence circuit. For example, as shown in (D) of FIG. 5, a transistor (105A) corresponding to the transistor (105) shown in (A) of FIG. 5 and a transistor (105B) corresponding to the transistor (105) shown in FIG. 1 may be provided.

[0082] As shown in FIG. 6 (A), the first terminal of the transistor (107) may be connected to the wiring (115). The transistor (107) shown in FIG. 6 (A) supplies signal CK2 to node (N2) according to the potential of node (N1). Since signal CK2 becomes high level during period T1, it is possible to prevent through current from occurring in transistor (106) and transistor (107) during period T1. This allows for a reduction in power consumption. Additionally, since there is no need to increase the W / L of the transistor (106), the layout area of ​​the sequential circuit can be reduced.

[0083] As shown in FIG. 6 (B), the first terminal of the transistor (107) may be connected to the wiring (114). The transistor (107) shown in FIG. 6 (B) supplies a signal SP to the node (N2) according to the potential of the node (N1). Since the signal SP becomes high level during period T1, it is possible to prevent through current from occurring in the transistor (106) and transistor (107) during period T1. This allows for a reduction in power consumption. Additionally, since there is no need to increase the W / L of the transistor (106), the layout area of ​​the sequential circuit can be reduced.

[0084] As shown in (C) of FIG. 6, the gate of the transistor (107) may be connected to the wiring (112). The transistor (107) shown in (C) of FIG. 6 supplies voltage VSS to the node (N2) according to the signal OUT. Since the signal OUT becomes low level during period T1, the transistor (107) can be turned off during period T1. By doing so, through-currents can be prevented from occurring in the transistor (106) and transistor (107) during period T1, thereby reducing power consumption. In addition, since there is no need to increase the W / L of the transistor (106), the layout area of ​​the sequential circuit can be reduced.

[0085] As shown in FIG. 6 (D), the first terminal of the transistor (107) may be connected to the wiring (115), and the gate of the transistor (107) may be connected to the wiring (112). The transistor (107) shown in FIG. 6 (D) supplies signal CK2 to the node (N2) according to signal OUT. Since signal OUT becomes low level during period T1, the transistor (107) can be turned off during period T1. By doing so, it is possible to prevent through-current from occurring in the transistor (106) and transistor (107) during period T1, thereby reducing power consumption. In addition, since there is no need to increase the W / L of the transistor (106), the layout area of ​​the sequential circuit can be reduced.

[0086] As shown in (E) of FIG. 6, the first terminal of the transistor (107) may be connected to the wiring (114), and the gate of the transistor (107) may be connected to the wiring (112). The transistor (107) shown in (E) of FIG. 6 supplies signal SP to the node (N2) according to signal OUT. Since signal OUT becomes low level during period T1, the transistor (107) can be turned off during period T1. By doing so, through current can be prevented from occurring in the transistor (106) and transistor (107) during period T1, thereby allowing for a reduction in power consumption. Additionally, since there is no need to increase the W / L of the transistor (106), the layout area of ​​the sequential circuit can be reduced.

[0087] As shown in FIG. 7 (A), the first terminal of the transistor (106) may be connected to the wiring (117). The transistor (106) shown in FIG. 7 (A) supplies voltage VDD to the node (N2) according to the signal CK2. This prevents a low-level signal from being supplied to the node (N2) due to timing misalignment or the like.

[0088] As shown in FIG. 7 (B), the first terminal of the transistor (106) may be connected to the wiring (118), and the gate of the transistor (106) may be connected to the wiring (118). A signal CK3 is input to the wiring (118). The signal CK3 is a clock signal. However, the signal CK3 is different in phase from the signals CK1 and CK2. The transistor (106) shown in FIG. 7 (B) supplies the signal CK3 to the node (N2) according to the signal CK3.

[0089] As shown in (C) of FIG. 7, the first terminal of the transistor (106) may be connected to the wiring (117), and the gate of the transistor (107) may be connected to the wiring (118). The transistor (106) shown in (C) of FIG. 7 supplies voltage VDD to the node (N2) according to the signal CK3. By doing so, it is possible to prevent a low-level signal from being supplied to the node (N2) due to timing misalignment, etc.

[0090] As shown in (A) of FIG. 8, the first terminal of the transistor (104) may be connected to the wiring (113), the first terminal of the transistor (103) may be connected to the second terminal of the transistor (104), and the second terminal of the transistor (103) may be connected to the node (N1).

[0091] As shown in FIG. 8 (B), the gate of the transistor (103) may be connected to the wiring (119). Signal CK4 is input to the wiring (119), and signal CK4 is supplied to the gate of the transistor (103) through the wiring (119). Signal CK4 is a clock signal. However, signal CK4 has a different phase from signals CK1 and CK2.

[0092] Although not shown, the gate of the transistor (103) may be connected to the wiring (118).

[0093] Although not shown, a capacitive element may be provided in which the first terminal is connected to the node (N1) and the second terminal is connected to the wiring (112).

[0094] Although not shown, the first terminal of the transistor (102) may be connected to a wiring different from the wiring (113). For example, by supplying a voltage higher than VSS to the wiring, the current generated in the transistor (101) and the transistor (102) can be reduced.

[0095] Although not shown, the gate of the transistor (102) may be connected to the wiring (115), wiring (118), or wiring (119).

[0096] Additionally, the sequence circuits described above, illustrated in FIG. 1, FIG. 5 to FIG. 8, etc., may be freely combined. For example, as shown in FIG. 7 (A), the first terminal of the transistor (106) may be connected to the wiring (117), and as shown in FIG. 6 (A), the first terminal of the transistor (107) may be connected to the wiring (115) (see FIG. 9 (A)). As another example, as shown in FIG. 7 (A), the first terminal of the transistor (106) may be connected to the wiring (117), and as shown in FIG. 8 (B), the gate of the transistor (103) may be connected to the wiring (119) (see FIG. 9 (B)).

[0097] One embodiment of the present invention includes the following configurations within its scope.

[0098] One embodiment of the present invention has a transistor (101), a transistor (102), a transistor (103), and a transistor (104). A transistor (101) has a first terminal connected to a wire (111) and a second terminal connected to a wire (112). A transistor (102) has a first terminal connected to a wire (113) and a second terminal connected to a wire (112). A transistor (103) has a first terminal connected to a wire (113) and a gate connected to a wire (111). A transistor (104) has a first terminal connected to a second terminal of a transistor (103), a second terminal connected to a gate of a transistor (101), and a gate connected to a gate of a transistor (102) (see (A) in FIG. 10).

[0099] One embodiment of the present invention has a transistor (101), a transistor (102), a transistor (103), and a transistor (104). A transistor (101) has a first terminal connected to a wire (111) and a second terminal connected to a wire (112). A transistor (102) has a first terminal connected to a wire (113) and a second terminal connected to a wire (112). A transistor (103) has a first terminal connected to a wire (113) and a gate connected to a wire (119). A transistor (104) has a first terminal connected to a second terminal of a transistor (103), a second terminal connected to a gate of a transistor (101), and a gate connected to a gate of a transistor (102) (see (B) of FIG. 10).

[0100] This embodiment may be implemented in appropriate combination with other embodiments disclosed in this specification, etc.

[0101] (Embodiment 2)

[0102] In this embodiment, a shift register (also called a semiconductor device) using the sequence circuit described in Embodiment 1 is described.

[0103] An example of the configuration of a shift register will be explained with reference to FIG. 11. FIG. 11 is an example of a circuit diagram of a shift register.

[0104] The shift register illustrated in FIG. 11 has a sequence circuit (100[1]) to a sequence circuit (100[N]) (N is a natural number greater than or equal to 2). However, FIG. 11 only illustrates the sequence circuit (100[1]) to a sequence circuit (100[3]). The sequence circuit (100[1]) to a sequence circuit (100[N]) is the sequence circuit illustrated in FIG. 1. However, the sequence circuit (100[1]) to a sequence circuit (100[N]) is not limited to the sequence circuit illustrated in FIG. 11 and may be other sequence circuits disclosed in Embodiment 1, etc., etc., in this specification.

[0105] The shift register illustrated in FIG. 11 is connected to wiring (121[1]) to wiring (121[N]), wiring (122), wiring (123), wiring (124), and wiring (125). In the sequence circuit (100[i]) (i is any one of 2 to N), wiring (111) is connected to one of wiring (123) and wiring (124), wiring (112) is connected to wiring (121[i]), wiring (113) is connected to wiring (125), wiring (114) is connected to wiring (121[i-1]), and wiring (115) is connected to the other of wiring (123) and wiring (124). The sequence circuit (100[1]) differs from the sequence circuit (100[i]) in that wiring (114) is connected to wiring (122). Additionally, in the odd-numbered sequence circuit and the even-numbered sequence circuit, the connection points of the wiring (111) and wiring (115) are opposite to each other. For example, in the odd-numbered sequence circuit, wiring (111) is connected to wiring (123) and wiring (115) is connected to wiring (124), whereas in the even-numbered sequence circuit, wiring (111) is connected to wiring (124) and wiring (115) is connected to wiring (123).

[0106] Signals SOUT[1] to SOUT[N] are output from wiring (121[1]) to wiring (121[N]), respectively. Wiring (121[1]) to wiring (121[N]) correspond to wiring (112), and signals SOUT[1] to SOUT[N] correspond to signal OUT. Signal SSP is input to wiring (122). Wiring (122) corresponds to wiring (114), and signal SSP corresponds to signal SP. In particular, in the sequence circuit (100[i]), wiring (121[i-1]) corresponds to wiring (114), and signal SOUT[i-1] corresponds to signal SP. Signal SCK1 is input to wiring (123), and signal SCK2 is input to wiring (124). Wiring (123) corresponds to one of wiring (111) and wiring (115), and signal SCK1 corresponds to one of signal CK1 and signal CK2. Additionally, wiring (124) corresponds to the other of wiring (111) and wiring (115), and signal SCK2 corresponds to the other of signal CK1 and signal CK2. Voltage VSS is supplied to wiring (125). Wiring (125) corresponds to wiring (113).

[0107] An example of the operation of the shift register illustrated in FIG. 11 will be explained with reference to FIG. 12. FIG. 12 shows signals SCK1, SCK2, SSP, and the potential (V) of node (N1) of the sequence circuit (100[1]). N1 ), potential (V) of node (N2) of sequential circuit (100[1]) N2 This is a timing chart showing an example of the signal SOUT[1], signal SOUT[2], and signal SOUT[3].

[0108] First, at time t1, signal SCK1 becomes low level, signal SCK2 becomes high level, and signal SSP becomes high level. Since the sequence circuit (100[1]) operates during period T1 as described in Embodiment 1, signal SOUT[1] becomes low level. Since the sequence circuit (100[2]) operates during period T4 as described in Embodiment 1, signal SOUT[2] becomes low level. Since the sequence circuit (100[3]) operates during period T3 as described in Embodiment 1, signal SOUT[3] becomes low level.

[0109] Next, at time t2, signal SCK1 becomes high level, signal SCK2 becomes low level, and signal SSP becomes low level. Since the sequence circuit (100[1]) operates during period T2 as described in Embodiment 1, signal SOUT[1] becomes high level. Since the sequence circuit (100[2]) operates during period T1 as described in Embodiment 1, signal SOUT[2] becomes low level. Since the sequence circuit (100[3]) operates during period T4 as described in Embodiment 1, signal SOUT[3] becomes low level.

[0110] Next, at time t3, signal SCK1 becomes low level, signal SCK2 becomes high level, and signal SSP becomes low level. Since the sequence circuit (100[1]) operates during period T3 as described in Embodiment 1, signal SOUT[1] becomes low level. Since the sequence circuit (100[2]) operates during period T2 as described in Embodiment 1, signal SOUT[2] becomes high level. Since the sequence circuit (100[3]) operates during period T1 as described in Embodiment 1, signal SOUT[3] becomes low level.

[0111] Next, at time t4, signal SCK1 becomes high level, signal SCK2 becomes low level, and signal SSP becomes low level. Since the sequence circuit (100[1]) operates during period T4 as described in Embodiment 1, signal SOUT[1] becomes low level. Since the sequence circuit (100[2]) operates during period T3 as described in Embodiment 1, signal SOUT[2] becomes low level. Since the sequence circuit (100[3]) operates during period T2 as described in Embodiment 1, signal SOUT[3] becomes high level.

[0112] This embodiment may be implemented in appropriate combination with other embodiments disclosed in this specification, etc.

[0113] (Embodiment 3)

[0114] <Configuration Example of a Semiconductor Display Device>

[0115] Next, an example of the configuration of a semiconductor display device according to one embodiment of the present invention will be described.

[0116] In the semiconductor display device (70) illustrated in (A) of FIG. 13, a plurality of pixels (55), wiring (GL) corresponding to a bus line for selecting pixels (55) row by row (represented as wiring (GL1) to wiring (GLy) (y is a natural number), and wiring (SL) for supplying an image signal to the selected pixels (55) (represented as wiring (SL1) to wiring (SLx) (x is a natural number)) are provided in the pixel section (71). The input of a signal to the wiring (GL) is controlled by a driving circuit (72). The input of an image signal to the wiring (SL) is controlled by a driving circuit (73). Each of the plurality of pixels (55) is connected to at least one of the wiring (GL) and at least one of the wiring (SL).

[0117] Specifically, the driving circuit (72) has a shift register (75) that generates a signal for sequentially selecting wiring (GL1) to wiring (GLy). Additionally, specifically, the driving circuit (73) has a shift register (76) that sequentially generates a signal having pulses, and a switch circuit (77) that controls the supply of an image signal for wiring (SL1) to wiring (SLx) according to the signal generated by the shift register (76).

[0118] A sequence circuit or shift register according to one embodiment of the present invention may be used as a shift register (75) or a shift register (76). In this case, for example, each of the wiring (GL1) to wiring (GLy) corresponds to wiring (112).

[0119] Additionally, the type and number of wires provided to the pixel section (71) can be determined according to the configuration, number, and arrangement of the pixels (55). Specifically, (A) of FIG. 13 illustrates an example in which pixels (55) are arranged in a matrix form of x columns × y rows in the pixel section (71), and wires (SL1) to wires (SLx) and wires (GL1) to wires (GLy) are arranged within the pixel section (71).

[0120] Additionally, Figure 13 (A) illustrates an example in which the driving circuit (72) and the driving circuit (73) are formed on a single substrate together with the pixel portion (71), but the driving circuit (72) and the driving circuit (73) may be formed on a different substrate from the pixel portion (71).

[0121] Additionally, the configuration of a pixel (55) is illustrated as an example in (B) of FIG. 13. Each pixel (55) has a liquid crystal element (60), a transistor (56) that controls the supply of an image signal to the liquid crystal element (60), and a capacitance element (57) for maintaining a voltage between the pixel electrode and the common electrode of the liquid crystal element (60). The liquid crystal element (60) has a liquid crystal layer comprising a pixel electrode, a common electrode, and a liquid crystal material to which a voltage between the pixel electrode and the common electrode is applied.

[0122] The transistor (56) controls whether to supply the potential of the wiring (SL) to the pixel electrode of the liquid crystal element (60). A predetermined potential is supplied to the common electrode of the liquid crystal element (60).

[0123] In the following, the specific connection configuration of the transistor (56) and the liquid crystal element (60) will be described. In (B) of FIG. 13, the gate of the transistor (56) is connected to any one of the wires (GL1) to the wire (GLy). One of the source and drain of the transistor (56) is connected to any one of the wires (SL1) to the wire (SLx), and the other of the source and drain of the transistor (56) is connected to the pixel electrode of the liquid crystal element (60).

[0124] In the liquid crystal element (60), the orientation of liquid crystal molecules included in the liquid crystal layer changes according to the value of the voltage applied between the pixel electrode and the common electrode, thereby changing the transmittance. Accordingly, the liquid crystal element (60) can display a grayscale by controlling its transmittance by the potential of the image signal supplied to the pixel electrode. And, as the grayscale of the liquid crystal element (60) is adjusted according to the image signal having image information in each of the plurality of pixels (55) of the pixel unit (71), an image is displayed in the pixel unit (71).

[0125] Figure 13 (B) illustrates an example in which a single transistor (56) is used as a switch to control the input of an image signal to the pixel (55). However, multiple transistors functioning as a single switch may be used in the pixel (55).

[0126] In one embodiment of the present invention, it is preferable to use a transistor (56) with a significantly small off-current as a switch for controlling the input of an image signal to a pixel (55). If the off-current of the transistor (56) is small, it is possible to prevent charge leakage through the transistor (56). Therefore, since the potential of the image signal supplied to the liquid crystal element (60) and the capacitive element (57) can be maintained more reliably, the transmittance of the liquid crystal element (60) can be prevented from changing due to charge leakage during one frame period, thereby improving the quality of the displayed image. In addition, since the off-current of the transistor (56) is small, it is possible to prevent charge leakage through the transistor (56), so the supply of power potential or signal to the driving circuit (72) and the driving circuit (73) may be stopped during the period of displaying a still image. With this configuration, the number of times the image signal is recorded for the pixel part (71) can be reduced, thereby reducing the power consumption of the semiconductor display device.

[0127] For example, a transistor containing an oxide semiconductor in the semiconductor film has a significantly smaller off-current, so it is suitable to use this as a transistor (56).

[0128] In addition, the transistor (56) in (B) of FIG. 13 may have a pair of gate electrodes that overlap with a semiconductor film. The pair of gate electrodes are electrically connected. In one embodiment of the present invention, this configuration can increase the on-current of the transistor (56) and also increase the reliability of the transistor (56).

[0129] Next, another example of a pixel (55) is shown in (C) of FIG. 13. The pixel (55) has a transistor (95) that controls the input of an image signal to the pixel (55), a light-emitting element (98), a transistor (96) that controls the current value supplied to the light-emitting element (98) according to the image signal, and a capacitance element (97) for maintaining the potential of the image signal.

[0130] As the light-emitting element (98), for example, an element whose brightness is controlled by current or voltage, such as an LED (Light Emitting Diode) or an OLED (Organic Light Emitting Diode), may be used. For example, an OLED has at least an EL layer, an anode, and a cathode. The EL layer is composed of a single layer or a plurality of layers provided between the anode and the cathode, and at least includes a light-emitting layer containing a light-emitting material among these layers.

[0131] In addition, in the EL layer, electroluminescence can be obtained by the current supplied when the potential difference between the anode and the cathode becomes greater than or equal to the threshold voltage of the light-emitting element (98). Electroluminescence includes light emission (fluorescence) when returning from a singlet excited state to a ground state and light emission (phosphorescence) when returning from a triplet excited state to a ground state.

[0132] One of the positive and negative electrodes of the light-emitting element (98) has its potential controlled according to an image signal input to the pixel (55). Among the positive and negative electrodes, the one whose potential is controlled according to the image signal is designated as the pixel electrode, and the other as the common electrode. A predetermined potential is supplied to the common electrode of the light-emitting element (98), and the brightness of the light-emitting element (98) is determined by the potential difference between the pixel electrode and the common electrode. Accordingly, the light-emitting element (98) can display a grayscale by controlling its brightness according to the potential of the image signal. And, as the grayscale of the light-emitting element (98) is adjusted according to the image signal containing image information in each of the plurality of pixels (55) of the pixel section, an image is displayed in the pixel section (71).

[0133] Next, the connection configuration of the transistor (95), transistor (96), capacitive element (97), and light-emitting element (98) of the pixel (55) will be explained.

[0134] One of the source and drain of the transistor (95) is connected to the wiring (SL), and the other of the source and drain is connected to the gate of the transistor (96). The gate of the transistor (95) is connected to the wiring (GL). One of the source and drain of the transistor (96) is connected to the power line (VL), and the other of the source and drain is connected to the light-emitting element (98). Specifically, the other of the source and drain of the transistor (96) is connected to one of the positive and negative electrodes of the light-emitting element (98). A predetermined potential is supplied to the other of the positive and negative electrodes of the light-emitting element (98).

[0135] In (C) of FIG. 13, the transistor (96) may have a pair of gate electrodes that overlap with a semiconductor film. The pair of gate electrodes are electrically connected. In one embodiment of the present invention, this configuration can increase the on-current of the transistor (96) and also increase the reliability of the transistor (96).

[0136] For example, in the present specification, etc., a display element, a display device having a display element, a light-emitting element, and a light-emitting device having a light-emitting element may have various forms and may also include various elements. The display element, the display device, the light-emitting element, or the light-emitting device may have at least one of, for example, an EL (electroluminescence) element (an EL element including organic and inorganic materials, an organic EL element, an inorganic EL element), an LED (a white LED, a red LED, a green LED, a blue LED, etc.), a transistor (a transistor that emits light by current), an electron emission element, a liquid crystal element, electronic ink, an electrophoretic element, a diffraction light valve (GLV), a plasma display (PDP), a display element using a microelectromechanical system (MEMS), a digital micromirror device (DMD), a digital micro shutter (DMS), an interference modulation (IMOD) element, a shutter-type MEMS display element, an optical interference-type MEMS display element, an electrowetting element, a piezoelectric ceramic display, a display element using carbon nanotubes, etc. In addition to these, there may be display media in which contrast, brightness, reflectance, transmittance, etc. are changed by electrical or magnetic action. An example of a display device using an EL element is an EL display. An example of a display device using an electron emission element is a field emission display (FED) or a flat panel display using the SED method (SED: Surface-conduction Electron-emitter Display). An example of a display device using a liquid crystal element is a liquid crystal display (transmissive liquid crystal display, transmissive liquid crystal display, reflective liquid crystal display, direct-view liquid crystal display, projection liquid crystal display). An example of a display device using electronic ink, electronic liquid powder (registered trademark), or electrophoretic element is electronic paper.In addition, when implementing a transflective liquid crystal display or a reflective liquid crystal display, it is preferable that some or all of the pixel electrodes function as reflective electrodes. For example, it is preferable that some or all of the pixel electrodes include aluminum or silver. In this case, it is also possible to provide a memory circuit such as SRAM under the reflective electrodes. This allows for further reduction in power consumption.

[0137] In addition, the present specification and others may form transistors using various substrates. The type of substrate is not limited to specific types. Examples of substrates include semiconductor substrates (e.g., single-crystal substrates or silicon substrates), SOI substrates, glass substrates, quartz substrates, plastic substrates, metal substrates, stainless steel substrates, substrates having stainless steel foil, tungsten substrates, substrates having tungsten foil, flexible substrates, bonding films, paper containing fiber-shaped materials, or base material films. Examples of glass substrates include barium borosilicate glass, aluminoborosilicate glass, or soda-lime glass. Examples of flexible substrates, bonding films, base films, etc. include the following. For example, there are plastics represented by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), and polyethersulfone (PES). Or, as an example, there are synthetic resins such as acrylic. Alternatively, examples include polypropylene, polyester, polyvinyl fluoride, or polyvinyl chloride. Alternatively, examples include polyamide, polyimide, aramid, epoxy, inorganic deposited film, or paper. In particular, when fabricating transistors using semiconductor substrates, single-crystal substrates, or SOI substrates, it is possible to produce transistors with low variation in characteristics, size, or shape, high current capability, and small size. By constructing circuits with such transistors, it is possible to achieve low power consumption or high integration of the circuit.

[0138] In addition, a flexible substrate may be used as the substrate, and a transistor may be formed directly on this flexible substrate. Alternatively, a release layer may be provided between the substrate and the transistor. The release layer can be used to separate from the substrate and transfer to another substrate after forming part or all of the semiconductor device thereon. At this time, the transistor may be transferred to a substrate with poor heat resistance or a flexible substrate. In addition, this release layer may have a configuration in which an inorganic film, such as a tungsten film and a silicon oxide film, is laminated, for example, or a configuration in which an organic resin film, such as polyimide, is formed on the substrate.

[0139] That is, after forming a transistor using one substrate, the transistor may be transferred to another substrate to place the transistor on that other substrate. Examples of substrates on which the transistor is transferred include, in addition to the aforementioned substrates capable of forming a transistor, paper substrates, cellophane substrates, aramid film substrates, polyimide film substrates, stone substrates, wood substrates, fabric substrates (including natural fibers (silk, cotton, hemp), synthetic fibers (nylon, polyurethane, polyester), or recycled fibers (acetate, cupro, rayon, recycled polyester), leather substrates, or rubber substrates. By using such substrates, it is possible to form transistors with good characteristics, form transistors with low power consumption, manufacture devices that are difficult to destroy, impart heat resistance, reduce weight, or make them thin.

[0140] This embodiment may be implemented in appropriate combination with other embodiments disclosed in this specification, etc.

[0141] (Embodiment 4)

[0142] <Composition of Pixels>

[0143] Next, an example configuration of a pixel (55) of a liquid crystal display device, which is an example of a semiconductor display device (70) shown in (A) of FIG. 13, will be described. FIG. 14 shows a top view of a pixel (55) as an example. Also, in FIG. 14, various insulating films have been omitted to clearly show the layout of the pixel (55). FIG. 15 shows a cross-sectional view of a liquid crystal display device formed using a device substrate having the pixel (55) shown in FIG. 14. In the liquid crystal display device shown in FIG. 15, the device substrate including the substrate (31) corresponds to the cross-sectional view along dashed line B1-B2 of FIG. 14.

[0144] The pixel (55) shown in FIGS. 14 and 15 has a transistor (56) and a capacitive element (57). Also, the pixel (55) shown in FIG. 15 has a liquid crystal element (60).

[0145] A transistor (56) has a conductive film (40) that functions as a gate electrode on a substrate (31) having an insulating surface, an insulating film (22) that functions as a gate insulating film on the conductive film (40), an oxide semiconductor film (41) that functions as an oxide semiconductor film (41) that functions as an insulating film (22) and overlaps with the conductive film (40), a conductive film (43) that is electrically connected to the oxide semiconductor film (41) and functions as a source electrode or a drain electrode, and a conductive film (44). The conductive film (40) functions as a wiring (GL) as shown in (B) of FIG. 13. Additionally, the conductive film (43) functions as a wiring (SL) as shown in (B) of FIG. 13.

[0146] Additionally, the pixel (55) has a metal oxide film (42) on an insulating film (22). The metal oxide film (42) is a conductive film that is transparent to visible light. Furthermore, a conductive film (61) electrically connected to the metal oxide film (42) is provided on the metal oxide film (42). The conductive film (61) functions as a wiring that supplies a predetermined potential to the metal oxide film (42).

[0147] The insulating film (22) may be a single-layer or multilayer structure of an insulating film comprising one or more of aluminum oxide, magnesium oxide, silicon oxide, silicon nitride oxide, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. In addition, in this specification, nitride oxide refers to a material having a higher oxygen content than nitrogen in its composition, and nitride oxide refers to a material having a higher nitrogen content than oxygen in its composition.

[0148] Additionally, in FIG. 15, an insulating film (26) and an insulating film (27) are sequentially stacked on an oxide semiconductor film (41), a conductive film (43), and a conductive film (44), and also on a metal oxide film (42) and a conductive film (61). The transistor (56) may include the insulating film (26) and the insulating film (27) as its components. Although FIG. 15 illustrates a case where the insulating film (26) and the insulating film (27) are sequentially stacked, a single-layer insulating film may be used instead of the insulating film (26) and the insulating film (27), or a stacked insulating film of three or more layers may be used.

[0149] And, insulating films (26) and insulating films (27) have an opening (58) at a position overlapping with the metal oxide film (42). The opening (58) is provided in an area overlapping with the metal oxide film (42), and the oxide semiconductor film (41), conductive film (43), and conductive film (44) are not provided in said area.

[0150] In addition, in FIG. 15, a nitride insulating film (28) and an insulating film (29) are sequentially laminated on the insulating film (26) and the insulating film (27), and also on the metal oxide film (42) at the opening (58).

[0151] Additionally, by forming an oxide semiconductor film on the insulating film (22) and forming a nitride insulating film (28) in contact with the oxide semiconductor film, the conductivity of the oxide semiconductor film can be increased. Furthermore, the oxide semiconductor film with high conductivity can be used as a metal oxide film (42). It is believed that the increased conductivity of the oxide semiconductor film is due to the formation of oxygen vacancies within the oxide semiconductor film when the opening (58) is formed or when the nitride insulating film (28) is formed, and the hydrogen diffused from the nitride insulating film (28) bonds to the oxygen vacancies, thereby generating donors. Specifically, the resistivity of the metal oxide film (42) is typically 1×10⁻⁶. -3 Ωcm or more 1×10 4 Less than Ωcm, more preferably resistivity of 1×10⁻⁶ -3 Ωcm or more 1×10 -1 It is good if it is less than Ωcm.

[0152] It is preferable that the metal oxide film (42) has a higher hydrogen concentration than the oxide semiconductor film (41). The hydrogen concentration of the metal oxide film (42) obtained by secondary ion mass spectrometry (SIMS) is 8×10 19 atoms / cm 3 Ideally, 1×10 20 atoms / cm 3 Ideally, 5×10 20 atoms / cm 3 The hydrogen concentration of the oxide semiconductor film (41) obtained by secondary ion mass spectrometry is 5×10 19 atoms / cm 3 Less than, preferably 5×10 18 atoms / cm 3 Less than, more preferably 1×10 18 atoms / cm 3 Below, more preferably 5×10 17 atoms / cm 3Below, more preferably 1×10 16 atoms / cm 3 The following applies.

[0153] For example, silicon nitride, silicon nitride oxide, aluminum nitride, aluminum nitride oxide, etc. can be used for the nitride insulating film (28). Compared to an oxide insulating film using silicon oxide or aluminum oxide, the nitride insulating film (28) using the above-described materials can prevent impurities from the outside, such as water, alkali metals, alkaline earth metals, etc., from diffusing into the oxide semiconductor film (41).

[0154] Additionally, an opening (62) is provided in the nitride insulating film (28) and insulating film (29) at a position overlapping with the conductive film (44). Furthermore, a conductive film (45) is provided on the nitride insulating film (28) and insulating film (29) to have transparency to visible light and function as a pixel electrode. The conductive film (45) is electrically connected to the conductive film (44) at the opening (62). Additionally, the conductive film (45) overlaps with the metal oxide film (42) at the opening (58). The portion where the conductive film (45) and the metal oxide film (42) overlap with the nitride insulating film (28) and insulating film (29) functions as a capacitive element (57).

[0155] The metal oxide film (42) and the conductive film (45), which function as a pair of electrodes in the capacitive element (57), and the nitride insulating film (28) and the insulating film (29), which function as dielectric films, have light transmittance to visible light. Because of this, the capacitive element (57) has light transmittance to visible light, so the aperture ratio of the pixel (55) can be increased compared to a pixel with low light transmittance to visible light of the capacitive element. Therefore, the power consumption of the semiconductor device can be reduced by securing the capacitance value necessary to obtain high image quality while suppressing light loss within the panel to a small extent.

[0156] In addition, as described above, although it is not necessary to form an insulating film (29), by using an insulating film (29) with an insulating material having a lower dielectric constant than that of the nitride insulating film (28) as a dielectric film together with the nitride insulating film (28), the dielectric constant of the dielectric film of the capacitive element (57) can be adjusted to a desired value without increasing the thickness of the nitride insulating film (28).

[0157] An orientation film (52) is provided on top of the conductive film (45).

[0158] Additionally, a substrate (46) is provided to face the substrate (31). On the substrate (46), a shielding film (47) having the function of blocking visible light and a coloring layer (48) transmitting visible light within a specific wavelength range are provided. A resin film (50) is provided on the shielding film (47) and the coloring layer (48), and a conductive film (59) functioning as a common electrode is provided on the resin film (50). Additionally, an alignment film (51) is provided on the conductive film (59).

[0159] Additionally, a liquid crystal layer (53) containing a liquid crystal material is provided between the substrate (31) and the substrate (46) so as to be fitted between the alignment layer (52) and the alignment layer (51). The liquid crystal element (60) has a conductive film (45), a conductive film (59), and a liquid crystal layer (53).

[0160] In addition, while FIGS. 14 and 15 illustrate the case where a TN (Twisted Nematic) mode is adopted as a driving method for the liquid crystal, FFS (Fringe Field Switching) mode, STN (Super Twisted Nematic) mode, VA (Vertical Alignment) mode, MVA (Multi-domain Vertical Alignment) mode, IPS (In-Plane Switching) mode, OCB (Optically Compensated Birefringence) mode, Blue phase mode, TBA (Transverse Bend Alignment) mode, VA-IPS mode, ECB (Electrically Controlled Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (Anti-Ferroelectric Liquid Crystal) mode, PDLC (Polymer Dispersed Liquid Crystal) mode, PNLC (Polymer Network Liquid Crystal) mode, guest host mode, ASV (Advanced Super View) mode, etc. may also be applied.

[0161] In addition, in a liquid crystal display device according to one embodiment of the present invention, a liquid crystal material classified as, for example, a thermotropic liquid crystal or a lyotropic liquid crystal may be used in the liquid crystal layer. Alternatively, a liquid crystal material classified as, for example, a nematic liquid crystal, a smetic liquid crystal, a cholesteric liquid crystal, or a discotic liquid crystal may be used in the liquid crystal layer. Alternatively, a liquid crystal material classified as, for example, a ferroelectric liquid crystal or an antiferroelectric liquid crystal may be used in the liquid crystal layer. Alternatively, a liquid crystal material classified as a polymer liquid crystal, such as a main chain polymer liquid crystal, a side chain polymer liquid crystal, or a composite polymer liquid crystal, or a low-molecular-weight liquid crystal may be used in the liquid crystal layer. Alternatively, a liquid crystal material classified as a polymer dispersed liquid crystal (PDLC) may be used in the liquid crystal layer.

[0162] In addition, a liquid crystal exhibiting a blue phase that does not require an alignment layer may be used in the liquid crystal layer. The blue phase is one of the liquid crystal phases and is manifested just before the cholesteric phase transitions to the isotropic phase as the temperature of the cholesteric liquid crystal is increased. Since the blue phase is manifested only within a narrow temperature range, a chiral agent or a UV-curing resin is added to improve the temperature range. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent is desirable because it has a response speed of 1 msec or less, is optically isotropic, eliminates the need for alignment treatment, and has low dependence on the viewing angle.

[0163] In addition, although a liquid crystal display device that displays a color image using a color filter is illustrated in FIG. 15 as an example, a liquid crystal display device according to one embodiment of the present invention may have a configuration that displays a color image by sequentially illuminating a plurality of light sources that emit light of different colors.

[0164] Additionally, the oxide semiconductor film (41) of the transistor (56) is not limited to a single oxide semiconductor film, but may be composed of a plurality of stacked oxide semiconductor films. Figure 16 (A) illustrates a case in which the oxide semiconductor film (41) is composed of three stacked oxide semiconductor films. Specifically, in the transistor (56) shown in Figure 16 (A), the oxide semiconductor film (41a), the oxide semiconductor film (41b), and the oxide semiconductor film (41c) are sequentially stacked from the insulating film (22) side as the oxide semiconductor film (41).

[0165] And, the oxide semiconductor film (41a) and the oxide semiconductor film (41c) include at least one of the metal elements constituting the oxide semiconductor film (41b) as a component, and are oxide films in which the energy of the conduction band bottom is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0.15 eV or more, and is close to the vacuum level by 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less than that of the oxide semiconductor film (41b). In addition, it is preferable for the oxide semiconductor film (41b) to include at least indium, as this increases carrier mobility.

[0166] Additionally, as shown in (B) of FIG. 16, an oxide semiconductor film (41c) may be provided on the conductive film (43) and the conductive film (44) so ​​as to overlap with the insulating film (22).

[0167] This embodiment may be implemented in appropriate combination with other embodiments disclosed in this specification, etc.

[0168] (Embodiment 5)

[0169] Top view and cross-sectional view of a semiconductor display device

[0170] Next, using FIG. 17, the appearance of a semiconductor display device according to one embodiment of the present invention will be described with reference to a liquid crystal display device. FIG. 17 is a top view of a liquid crystal display device in which a substrate (4001) and a substrate (4006) are bonded together with a sealant (4005). FIG. 18 corresponds to a cross-sectional view along the dashed line C1-C2 of FIG. 17.

[0171] A sealing material (4005) is provided to surround a pixel portion (4002) and a pair of driving circuits (4004) provided on a substrate (4001). Additionally, a substrate (4006) is provided on the pixel portion (4002) and the driving circuits (4004). Thus, the pixel portion (4002) and the driving circuits (4004) are sealed with the substrate (4001), the sealing material (4005), and the substrate (4006).

[0172] Additionally, a driving circuit (4003) is provided in an area different from the area surrounded by the sealant (4005) on the substrate (4001).

[0173] Additionally, the pixel portion (4002) and the driving circuit (4004) provided on the substrate (4001) have a plurality of transistors. FIG. 18 illustrates a transistor (4010) included in the pixel portion (4002). An insulating film (4020) composed of various insulating films, including a nitride insulating film, is provided on the transistor (4010), and the transistor (4010) is connected to a pixel electrode (4021) on the insulating film (4020) at an opening formed in the insulating film (4020).

[0174] Additionally, a resin film (4059) is provided on the substrate (4006), and a common electrode (4060) is provided on the resin film (4059). Furthermore, a liquid crystal layer (4028) is provided to be interposed between the pixel electrode (4021) and the common electrode (4060) between the substrate (4001) and the substrate (4006). The liquid crystal element (4023) has the pixel electrode (4021), the common electrode (4060), and the liquid crystal layer (4028).

[0175] In the liquid crystal element (4023), the orientation of liquid crystal molecules included in the liquid crystal layer (4028) changes according to the value of the voltage applied between the pixel electrode (4021) and the common electrode (4060), thereby changing the transmittance. Accordingly, the liquid crystal element (4023) can display a grayscale by controlling its transmittance by the potential of the image signal supplied to the pixel electrode (4021).

[0176] Additionally, as illustrated in FIG. 18, in one embodiment of the present invention, the insulating film (4020) is removed from the panel end. Then, a conductive film (4050) is formed in the area where the insulating film (4020) has been removed. The conductive film (4050) and the conductive film functioning as the source or drain of the transistor (4010) can be formed by etching one conductive film.

[0177] Additionally, a resin film (4062) in which conductive particles (4061) having conductivity are dispersed is provided between the substrate (4001) and the substrate (4006). The conductive film (4050) is electrically connected to the common electrode (4060) through the conductive particles (4061). That is, the common electrode (4060) and the conductive film (4050) are electrically connected at the panel end through the conductive particles (4061). A thermosetting resin or a UV-curing resin may be used for the resin film (4062). Furthermore, as the conductive particles (4061), for example, particles in which spherical organic resin is coated with a metal such as Au, Ni, or Co in the form of a thin film may be used.

[0178] In addition, although the alignment layer is not shown in FIG. 18, when an alignment layer is provided on the pixel electrode (4021) and the common electrode (4060) respectively, in order to electrically connect the common electrode (4060), the conductive particle (4061), and the conductive film (4050), it is preferable to partially remove the portion of the alignment layer that overlaps with the common electrode (4060) and also partially remove the portion of the alignment layer that overlaps with the conductive film (4050).

[0179] In addition, in a liquid crystal display device according to one embodiment of the present invention, a color image may be displayed using a color filter, or a color image may be displayed by sequentially illuminating a plurality of light sources emitting light of different colors.

[0180] Additionally, image signals from the driving circuit (4003) and various control signals and potentials from the FPC (4018) are supplied to the driving circuit (4004) or pixel unit (4002) through the lead wiring (4030) and lead wiring (4031).

[0181] This embodiment may be implemented in appropriate combination with other embodiments disclosed in this specification, etc.

[0182] (Embodiment 6)

[0183] In this embodiment, an oxide semiconductor layer that can be used in the semiconductor layer of the transistor described in the above embodiment is described.

[0184] The oxide semiconductor used in the channel-forming region of the semiconductor layer of the transistor preferably includes at least indium (In) or zinc (Zn). In particular, it is preferable to include both In and Zn. In addition to these, it is preferable to include a stabilizer that strongly binds oxygen. As the stabilizer, it is preferable to include at least one of gallium (Ga), tin (Sn), zirconium (Zr), hafnium (Hf), and aluminum (Al).

[0185] In addition, as another stabilizer, any one or more of the lanthanoids lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu) may be included.

[0186] Examples of oxide semiconductors that can be used in the semiconductor layer of a transistor include indium oxide, tin oxide, zinc oxide, In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Sn-Mg oxide, In-Mg oxide, In-Ga oxide, In-Ga-Zn oxide (also denoted as IGZO), In-Al-Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn-Al-Zn oxide, In-Hf-Zn oxide, In-Zr-Zn oxide, In-Ti-Zn oxide, In-Sc-Zn oxide, In-Y-Zn oxide, In-La-Zn oxide, In-Ce-Zn oxide, In-Pr-Zn oxide, In-Nd-Zn oxide, In-Sm-Zn oxide, and In-Eu-Zn oxide. There are In-Gd-Zn oxides, In-Tb-Zn oxides, In-Dy-Zn oxides, In-Ho-Zn oxides, In-Er-Zn oxides, In-Tm-Zn oxides, In-Yb-Zn oxides, In-Lu-Zn ​​oxides, In-Sn-Ga-Zn oxides, In-Hf-Ga-Zn oxides, In-Al-Ga-Zn oxides, In-Sn-Al-Zn oxides, In-Sn-Hf-Zn oxides, In-Hf-Al-Zn oxides, and others.

[0187] For example, it is preferable to use an In-Ga-Zn oxide with an atomic ratio of In:Ga:Zn=1:1:1, In:Ga:Zn=3:1:2, or In:Ga:Zn=2:1:3, or an oxide having a composition close to that.

[0188] If the oxide semiconductor film constituting the semiconductor layer contains a large amount of hydrogen, some of the hydrogen becomes a donor through bonding with the oxide semiconductor, generating electrons that act as carriers. Consequently, the threshold voltage of the transistor shifts in the negative direction. Therefore, it is desirable to achieve high purity by removing hydrogen or moisture from the oxide semiconductor film through a dehydration process after forming the film, thereby ensuring that impurities are contained as little as possible.

[0189] In addition, oxygen may be reduced in the oxide semiconductor film due to the dehydration treatment (dehydrogenation treatment) of the oxide semiconductor film. Therefore, it is desirable to perform a treatment to add oxygen to the oxide semiconductor film in order to preserve the oxygen vacancies increased by the dehydration treatment (dehydrogenation treatment). In this specification and other documents, the act of supplying oxygen to the oxide semiconductor film may be described as an oxygenation treatment. Alternatively, the act of making the oxygen contained in the oxide semiconductor film greater than the stoichiometric composition may be described as an over-oxygenation treatment.

[0190] In this way, by removing hydrogen or moisture from the oxide semiconductor film through dehydration treatment and preserving oxygen vacancies through oxygenation treatment, it can become an i-type (intrinsic) or substantially i-type (intrinsic) oxide semiconductor film that is infinitely close to i-type. Furthermore, being substantially intrinsic means that there are very few carriers originating from donors within the oxide semiconductor film (close to zero) and the carrier density is 1×10⁻⁶. 17 / cm 3 Below, 1×10 16 / cm 3 Below, 1×10 15 / cm 3 Below, 1×10 14 / cm 3 Below, 1×10 13 / cm 3 It refers to the following.

[0191] Furthermore, transistors using such type i or substantially type i oxide semiconductor films can have excellent off-current characteristics. For example, the drain current in the off state of a transistor using an oxide semiconductor film is 1 × 10⁻⁶ at room temperature (approximately 25°C). -18 A or less, preferably 1×10 -21 A or less, more preferably 1×10 -24 A or less, or 1×10⁻⁶ at 85℃ -15 A or less, preferably 1×10 -18 A or less, more preferably 1×10 -21 It can be less than or equal to A. In addition, the transistor being in the off state refers to a state in which, for an n-channel transistor, the gate voltage is sufficiently smaller than the threshold voltage. Specifically, if the gate voltage is 1V or more, 2V or more, or 3V or more less than the threshold voltage, the transistor is in the off state.

[0192] The structure of the oxide semiconductor film is described below.

[0193] Oxide semiconductor films are divided into non-silver oxide semiconductor films and single-crystal oxide semiconductor films. Alternatively, oxide semiconductors are divided, for example, into crystalline oxide semiconductors and amorphous oxide semiconductors.

[0194] In addition, non-monocrystalline oxide semiconductors include CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor), polycrystalline oxide semiconductors, microcrystalline oxide semiconductors, and amorphous oxide semiconductors. Furthermore, crystalline oxide semiconductors include single-crystal oxide semiconductors, CAAC-OS, polycrystalline oxide semiconductors, and microcrystalline oxide semiconductors.

[0195] First, I will explain the CAAC-OS membrane.

[0196] The CAAC-OS film is one of the oxide semiconductor films having multiple c-axis oriented crystal regions.

[0197] When observing the combined image of the bright-field and diffraction patterns of the CAAC-OS film (also known as a high-resolution TEM image) using a transmission electron microscope (TEM), multiple crystal regions are identified. However, even in the high-resolution TEM image, clear boundaries between the crystal regions, namely grain boundaries, are not identified. Therefore, it can be said that a decrease in electron mobility caused by grain boundaries is unlikely to occur in the CAAC-OS film.

[0198] In high-resolution TEM images observing a cross-section of the CAAC-OS film from a direction substantially parallel to the sample surface, it is confirmed that metal atoms are arranged in layers within the crystal region. Each layer of metal atoms has a shape that reflects the irregularities of the surface on which the CAAC-OS film is formed (also called the surface to be formed) or the upper surface of the CAAC-OS film, and is arranged parallel to the surface to be formed or the upper surface of the CAAC-OS film.

[0199] Meanwhile, in high-resolution TEM images of the plane of the CAAC-OS film observed from a direction substantially perpendicular to the sample surface, it is confirmed that metal atoms are arranged in triangular or hexagonal shapes in the crystal regions. However, no regularity is observed in the arrangement of metal atoms between different crystal regions.

[0200] When performing structural analysis of the CAAC-OS film using an X-ray diffraction (XRD) device, for example, in the out-of-plane analysis of a CAAC-OS film having an InGaZnO4 crystal, a peak may appear when the diffraction angle (2θ) is around 31°. Since this peak is attributed to the (009) plane of the InGaZnO4 crystal, it can be confirmed that the crystal of the CAAC-OS film has c-axis orientation and that the c-axis is oriented in a direction substantially perpendicular to the surface to be formed or the upper surface.

[0201] In addition, when analyzing a CAAC-OS film having InGaZnO4 crystals using the out-of-plane method, in addition to the peak appearing when 2θ is around 31°, a peak may also appear when 2θ is around 36°. The peak appearing when 2θ is around 36° indicates that some parts of the CAAC-OS film contain crystals that do not have c-axis orientation. It is desirable for the CAAC-OS film to have a peak when 2θ is around 31° and not a peak when 2θ is around 36°.

[0202] CAAC-OS films are oxide semiconductor films with low impurity concentrations. Impurities refer to elements other than the main components of the oxide semiconductor film, such as hydrogen, carbon, silicon, and transition metals. In particular, elements such as silicon, which have a stronger bonding affinity with oxygen than the metal elements constituting the oxide semiconductor film, disrupt the atomic arrangement of the film by depriving it of oxygen, thereby becoming a factor that degrades crystallinity. Furthermore, heavy metals such as iron and nickel, as well as argon and carbon dioxide, have large atomic radii (or molecular radii); therefore, when included in the oxide semiconductor film, they disrupt the atomic arrangement and contribute to a decrease in crystallinity. Additionally, impurities contained in the oxide semiconductor film can act as carrier traps or carrier generators.

[0203] In addition, the CAAC-OS film is an oxide semiconductor film with a low defect level density. For example, oxygen vacancies within the oxide semiconductor film can become carrier traps or carrier sources by capturing hydrogen.

[0204] Oxide semiconductor films with low impurity concentration and low defect level density (low oxygen vacancies) are referred to as high-purity intrinsic or substantially high-purity intrinsic. Oxide semiconductor films that are high-purity intrinsic or substantially high-purity intrinsic have fewer carrier sources, allowing for a lower carrier density. Consequently, transistors using such oxide semiconductor films rarely have a negative threshold voltage (also known as a normaly-on). Furthermore, oxide semiconductor films that are high-purity intrinsic or substantially high-purity intrinsic have fewer carrier traps. Therefore, transistors using such oxide semiconductor films exhibit minimal variation in electrical characteristics and are highly reliable. Additionally, charges trapped in the carrier traps of the oxide semiconductor film take a long time to be released, sometimes behaving like fixed charges. Consequently, transistors using oxide semiconductor films with high impurity concentration and high defect level density may experience unstable electrical characteristics.

[0205] In addition, transistors using CAAC-OS films exhibit small fluctuations in electrical characteristics due to irradiation with visible or ultraviolet light.

[0206] Next, microcrystalline oxide semiconductor films will be described.

[0207] Microcrystalline oxide semiconductor films have regions where crystal regions are visible in high-resolution TEM images and regions where crystal regions are not clearly visible. The size of the crystal regions included in microcrystalline oxide semiconductor films is often between 1 nm and 100 nm, or between 1 nm and 10 nm. In particular, oxide semiconductor films containing nanocrystals (nc) that are microcrystalline between 1 nm and 10 nm, or between 1 nm and 3 nm, are called nc-OS (nanocrystalline oxide semiconductor) films. Furthermore, in nc-OS films, crystal grain boundaries may not be clearly visible in high-resolution TEM images, for example.

[0208] nc-OS films exhibit periodicity in their atomic arrangement in minute regions (e.g., regions from 1 nm to 10 nm, particularly from 1 nm to 3 nm). Additionally, nc-OS films do not show regularity in crystal orientation between different crystal regions. Consequently, orientation is not confirmed throughout the film. Therefore, depending on the analysis method, it may be impossible to distinguish between nc-OS films and amorphous oxide semiconductor films. For example, when the structure of an nc-OS film is analyzed using the out-of-plane method with an XRD device that uses X-rays with a diameter larger than that of the crystal region, peaks representing crystal planes are not detected. Furthermore, when observing the electron diffraction pattern of an nc-OS film using an electron beam with a probe diameter larger than that of the crystal region (e.g., 50 nm or more) (also known as a limited-field electron diffraction pattern), diffraction patterns such as halo patterns are observed. Meanwhile, spots are observed in the nanobeam electron diffraction pattern of an nc-OS film when using an electron beam with a probe diameter that is close to or smaller than the size of the crystal region. In addition, in the nanobeam electron diffraction pattern of an nc-OS film, a ring-shaped region with high brightness is observed. In addition, multiple spots are observed in the ring-shaped region of the nanobeam electron diffraction pattern of an nc-OS film.

[0209] nc-OS films are oxide semiconductor films with higher regularity than amorphous oxide semiconductor films. Therefore, nc-OS films have a lower defect level density than amorphous oxide semiconductor films. However, nc-OS films do not exhibit regularity in crystal orientation between different crystal regions. Consequently, nc-OS films have a higher defect level density compared to CAAC-OS films.

[0210] Next, amorphous oxide semiconductor films will be described.

[0211] An amorphous oxide semiconductor film is an oxide semiconductor film in which the atomic arrangement within the film is irregular and it does not possess crystalline regions. An example is an oxide semiconductor film having an amorphous state, such as quartz.

[0212] Crystalline regions are not identified in high-resolution TEM images of amorphous oxide semiconductor films.

[0213] When structural analysis of an amorphous oxide semiconductor film is performed using an XRD device, peaks representing crystal planes are not detected in the analysis by the out-of-plane method. Additionally, a halo pattern is observed in the electron diffraction pattern of the amorphous oxide semiconductor film. Furthermore, no spots are observed in the nanobeam electron diffraction pattern of the amorphous oxide semiconductor film, and a halo pattern is observed.

[0214] In addition, oxide semiconductor films may have a structure that exhibits properties between those of nc-OS films and amorphous oxide semiconductor films. Oxide semiconductor films having such a structure are specifically called a-like OS (amorphous-like Oxide Semiconductor) films.

[0215] In high-resolution TEM images of α-like OS films, voids (also called cavities) may be observed. Additionally, high-resolution TEM images contain regions where crystallization is clearly visible and regions where it is not. In α-like OS films, crystallization may occur and crystallization may grow due to minute amounts of electron irradiation, which is comparable to that observed by TEM. On the other hand, in high-quality nc-OS films, crystallization caused by minute amounts of electron irradiation, such as that observed by TEM, rarely occurs.

[0216] In addition, the size of the crystal regions of a-like OS films and nc-OS films can be measured in high-resolution TEM images. For example, the crystal of InGaZnO4 has a layered structure and has two Ga-Zn-O layers between the In-O layers. The unit cell of the InGaZnO4 crystal has a structure in which a total of nine layers—three In-O layers and six Ga-Zn-O layers—are superimposed layered in the c-axis direction. Therefore, the spacing between these adjacent layers is approximately equal to the lattice plane spacing (also called the d value) of the (009) plane, and this value is calculated to be 0.29 nm from the analysis of the crystal structure. Therefore, based on the lattice fringes in the high-resolution TEM image, in the region where the spacing of the lattice fringes is between 0.28 nm and 0.30 nm, each lattice fringe corresponds to the ab plane of the InGaZnO4 crystal.

[0217] Furthermore, oxide semiconductor films may have different densities depending on their structure. For example, if the composition of an oxide semiconductor film is known, its structure can be estimated by comparing it with the density of a single-crystal oxide semiconductor film having the same composition. For example, with respect to the density of a single-crystal oxide semiconductor film, the density of an a-like OS film is 78.6% or higher and less than 92.3%. Also, for example, with respect to the density of a single-crystal oxide semiconductor film, the densities of an nc-OS film and a CAAC-OS film are 92.3% or higher and less than 100%. Furthermore, oxide semiconductor films with a density of less than 78% with respect to the density of a single-crystal oxide semiconductor film are difficult to form.

[0218] The above is explained with a specific example. For instance, regarding an oxide semiconductor film satisfying In:Ga:Zn = 1:1:1 [atomic ratio], the density of a single-crystal InGaZnO4 having a rhombohedral crystal structure is 6.357 g / cm³. 3.... Therefore, for example, in an oxide semiconductor film satisfying In:Ga:Zn = 1:1:1 [atomic ratio], the density of the a-like OS film is 5.0 g / cm³ 3 Above 5.9 g / cm² 3 It is less than. In addition, for example, in an oxide semiconductor film satisfying In:Ga:Zn = 1:1:1 [atomic ratio], the density of the nc-OS film and the density of the CAAC-OS film are 5.9 g / cm³. 3 Above 6.3g / cm² 3 It is less than.

[0219] Furthermore, there are cases where single crystals with the same composition do not exist. In such cases, a density equivalent to that of a single crystal with a desired composition can be calculated by combining single crystals with different compositions in arbitrary proportions. The density equivalent to that of a single crystal with a desired composition is preferably calculated using a weighted average of the proportions in which single crystals with different compositions are combined. However, when calculating the density, it is desirable to combine as few types of single crystals as possible.

[0220] In addition, the oxide semiconductor film may be a stacked film having two or more types among, for example, an amorphous oxide semiconductor film, an α-like OS film, a microcrystalline oxide semiconductor film, and a CAAC-OS film.

[0221] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or greater and 10° or less. Accordingly, cases ranging from -5° to 5° are also included in this category. Additionally, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -30° or greater and 30° or less. Additionally, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or greater and 100° or less. Accordingly, cases ranging from 85° to 95° or less are also included in this category. Additionally, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or greater and 120° or less.

[0222] Additionally, in this specification, trigonal or rhombohedral crystals are included in the hexagonal crystal system.

[0223] This embodiment may be implemented in appropriate combination with other embodiments disclosed in this specification, etc.

[0224] (Embodiment 7)

[0225] <Example of configuration of an electronic device using a semiconductor device>

[0226] A semiconductor device according to one embodiment of the present invention can be used in a display device, a personal computer, and an image playback device equipped with a recording medium (typically, a device having a display capable of displaying an image by playing a recording medium such as a DVD: Digital Versatile Disc). In addition, electronic devices for which a semiconductor device according to one embodiment of the present invention can be used include mobile phones, game consoles (including portable game consoles), portable information terminals, electronic books, cameras such as video cameras or digital still cameras, goggle-type displays (head-mounted displays), navigation systems, audio playback devices (car audio, digital audio players, etc.), photocopiers, fax machines, printers, multifunction printers, automated teller machines (ATMs), vending machines, etc. Specific examples of these electronic devices are illustrated in FIG. 19.

[0227] The portable game device illustrated in FIG. 19 (A) has a housing (5001), a housing (5002), a display unit (5003), a display unit (5004), a microphone (5005), a speaker (5006), an operation key (5007), a stylus (5008), etc. A semiconductor device according to one embodiment of the present invention may be used in the display unit (5003) or the display unit (5004), or in other integrated circuits. The portable game device illustrated in FIG. 19 (A) has two display units (5003 and 5004), but the number of display units in the portable game device is not limited thereto.

[0228] The portable information terminal illustrated in (B) of FIG. 19 has a first housing (5601), a second housing (5602), a first display unit (5603), a second display unit (5604), a connection unit (5605), an operation key (5606), etc. The first display unit (5603) is provided in the first housing (5601), and the second display unit (5604) is provided in the second housing (5602). In addition, the first housing (5601) and the second housing (5602) are connected by the connection unit (5605), and the angle between the first housing (5601) and the second housing (5602) can be adjusted by the connection unit (5605). The image displayed on the first display unit (5603) may be configured to switch according to the angle between the first housing (5601) and the second housing (5602) in the connection unit (5605). A semiconductor device according to one embodiment of the present invention may be used in the first display unit (5603) or the second display unit (5604), or in other integrated circuits.

[0229] The notebook-type personal computer illustrated in (C) of FIG. 19 has a housing (5401), a display unit (5402), a keyboard (5403), a pointing device (5404), etc. A semiconductor device according to one embodiment of the present invention may be used in the display unit (5402) or other integrated circuits.

[0230] The wristwatch illustrated in (D) of FIG. 19 has a housing (5201), a display unit (5202), an operating button (5203), a band (5204), etc. A semiconductor device according to one embodiment of the present invention may be used for the display unit (5202) or other integrated circuits.

[0231] The video camera illustrated in (E) of FIG. 19 has a first housing (5801), a second housing (5802), a display unit (5803), an operation key (5804), a lens (5805), a connection unit (5806), etc. The operation key (5804) and the lens (5805) are provided in the first housing (5801), and the display unit (5803) is provided in the second housing (5802). In addition, the first housing (5801) and the second housing (5802) are connected by the connection unit (5806), and the angle between the first housing (5801) and the second housing (5802) can be adjusted by the connection unit (5806). The image displayed on the display unit (5803) may be configured to switch according to the angle between the first housing (5801) and the second housing (5802) in the connection unit (5806). A semiconductor device according to one embodiment of the present invention may be used in the display unit (5803) or other integrated circuits.

[0232] The mobile phone illustrated in (F) of FIG. 19 is provided with a display unit (5902), a microphone (5907), a speaker (5904), a camera (5903), an external connection unit (5906), and an operation button (5905) in the housing (5901). A semiconductor device according to one embodiment of the present invention may be used in the display unit (5902) or other integrated circuits. Additionally, by forming the semiconductor device according to one embodiment of the present invention on a flexible substrate, the semiconductor device may be applied to a display unit (5902) having a curved surface as illustrated in (F) of FIG. 19.

[0233] Additionally, the contents (or parts thereof) described in any one embodiment may be applied, combined, or substituted with other contents (or parts thereof) described in that embodiment and / or contents (or parts thereof) described in one or more other embodiments.

[0234] In addition, the content described in the embodiments refers to the content described using various drawings in each embodiment, or the content described using sentences described in the specification.

[0235] In addition, more drawings may be formed by combining a drawing (or part thereof) referenced in one embodiment with another part of that drawing, another drawing (or part thereof) referenced in that embodiment, and / or a drawing (or part thereof) referenced in one or more other embodiments.

[0236] Furthermore, regarding content not defined by drawings or text in the specification, an embodiment of the invention may be constructed that excludes such content. Alternatively, if a numerical range, such as upper and lower limits, is described regarding a certain value, an embodiment of the invention may be constructed that excludes a part of the range by arbitrarily narrowing the range or excluding a point within the range. By doing so, it may be determined that, for example, prior art does not fall within the technical scope of an embodiment of the present invention.

[0237] As a specific example, if a circuit diagram using first to fifth transistors is described regarding a certain circuit, the invention may be constructed by specifying that the circuit does not have a sixth transistor. Alternatively, the invention may be constructed by specifying that the circuit does not have a capacitive element. Furthermore, the invention may be constructed by specifying that the circuit does not have a sixth transistor having a certain specific connection structure. Alternatively, the invention may be constructed by specifying that the circuit does not have a capacitive element having a certain specific connection structure. For example, the invention may be constructed by specifying that the sixth transistor does not have a gate connected to the gate of the third transistor. Or, for example, the invention may be constructed by specifying that the first electrode does not have a capacitive element connected to the gate of the third transistor.

[0238] As another specific example, if it is stated regarding a certain value that "it is suitable for a certain voltage to be 3V or higher and 10V or lower," one form of the invention may be constructed by specifying, for example, that the case where the certain voltage is -2V or higher and 1V or lower is excluded. Or, for example, one form of the invention may be constructed by specifying that the case where the certain voltage is 13V or higher is excluded. Furthermore, the invention may be constructed by specifying, for example, that the voltage is 5V or higher and 8V or lower. Also, the invention may be constructed by specifying, for example, that the voltage is approximately 9V. Furthermore, the invention may be constructed by specifying, for example, that the voltage is 3V or higher and 10V or lower, but the case where it is 9V is excluded. Additionally, even if it is stated regarding a certain value that "it is desirable to be within such a range" or "it is desirable to satisfy these," the certain value is not limited to these descriptions. That is, even if it is stated as "desirable" or "suitable," it is not necessarily limited to these descriptions.

[0239] As another specific example, in the case where it is stated regarding a certain value that "a certain voltage is suitable to be 10V," one form of the invention may be constructed by specifying, for example, that the case where a certain voltage is -2V or higher and 1V or lower is excluded. Or, for example, one form of the invention may be constructed by specifying that the case where a certain voltage is 13V or higher is excluded.

[0240] As another specific example, if it is stated regarding the properties of a certain material that "a certain film is an insulating film," one form of the invention may be constructed by stipulating, for example, that the case where the insulating film is an organic insulating film is excluded. Alternatively, one form of the invention may be constructed by stipulating, for example, that the case where the insulating film is an inorganic insulating film is excluded. Alternatively, one form of the invention may be constructed by stipulating, for example, that the case where the film is a conductive film is excluded. Alternatively, one form of the invention may be constructed by stipulating, for example, that the case where the film is a semiconductor film is excluded.

[0241] As another specific example, regarding a certain laminated structure, if it is stated that "a certain film is provided between film A and film B," the invention may be constructed by stipulating, for example, that the film is a laminated film of four or more layers. Or, for example, the invention may be constructed by stipulating that a conductive film is provided between film A and the film.

[0242] Furthermore, regarding all terminals of active components (transistors, diodes, etc.) and passive components (capacitive elements, resistive elements, etc.), a person skilled in the art may be able to constitute an embodiment of the invention even if the connection points are not specified. In other words, it can be said that an embodiment of the invention is clear even if the connection points are not specified. Moreover, if the content regarding the specified connection points is described in the present specification, etc., it may be determined that an embodiment of the invention without specified connection points is described in the present specification, etc. In particular, if several connection points can be conceived for a single terminal, there is no need to limit the connection points of that terminal to specific locations. Therefore, there are cases where an embodiment of the invention can be constituted by specifying the connection points for only some of the terminals of active components (transistors, diodes, etc.) and passive components (capacitive elements, resistive elements, etc.).

[0243] Furthermore, regarding the present specification, etc., there are cases where a person skilled in the art can identify the invention if at least the connection point is specified with respect to a circuit. Alternatively, regarding the circuit, there are cases where a person skilled in the art can identify the invention if at least the function is specified. In other words, if the function is specified, it can be said that one form of the invention is clear. Moreover, there are cases where it can be determined that one form of the invention with a specified function is described in the present specification, etc. Therefore, even if the function is not specified with respect to a circuit, if the connection point is specified, one form of the invention can be constituted as disclosed as one form of the invention. Alternatively, even if the connection point is not specified with respect to a circuit, if the function is specified, one form of the invention can be constituted as disclosed as one form of the invention.

[0244] Furthermore, in the present specification and the like, a part of a drawing or text from any embodiment may be extracted to constitute a form of the invention. Therefore, when there is a drawing or text intended to explain a certain part, the content extracted from that drawing or text is also disclosed as a form of the invention, and thus a form of the invention may be constructed from these. And, such a form of the invention can be considered clear. Therefore, for example, when there is a drawing or text describing one or more active elements (transistors, diodes, etc.), wiring, passive elements (capacitive elements, resistive elements, etc.), conductive layer, insulating layer, semiconductor layer, organic material, inorganic material, component, device, method of operation, manufacturing method, etc., a part thereof may be extracted to constitute a form of the invention. For example, in a circuit diagram comprising N (N is an integer) circuit elements (transistors, capacitive elements, etc.), M (M is an integer and M <N)의 회로 소자(트랜지스터, 용량 소자 등)를 추출하여 발명의 일 형태를 구성할 수 있다. 다른 예로서는, N개(N은 정수)의 층을 포함하여 구성된 단면도에서 M개(M은 정수이며 M<N)의 층을 추출하여 발명의 일 형태를 구성할 수 있다. 또 다른 예로서는, N개(N은 정수)의 요소를 포함하여 구성된 흐름도에서 M개(M은 정수이며 M<N)의 요소를 추출하여 발명의 일 형태를 구성할 수 있다. 또 다른 예로서는, "A는 B, C, D, E, 또는 F를 가진다"라는 문장에서 일부의 요소를 임의로 추출하여, "A는 B와 E를 가진다", "A는 E와 F를 가진다", "A는 C와 E와 F를 가진다", 또는 "A는 B와 C와 D와 E를 가진다" 등으로 발명의 일 형태를 구성할 수 있다.

[0245] Furthermore, in the present specification and the like, where at least one specific example is described in drawings or text in any embodiment, it is easy for those skilled in the art to derive the higher-level concept of that specific example. Therefore, where at least one specific example is described in drawings or text in any embodiment, the higher-level concept of that specific example can also be disclosed as a form of invention and thus constitute a form of invention. And, it can be said that such a form of invention is clear.

[0246] Furthermore, in this specification and the like, at least the contents (or parts thereof) described in the drawings may constitute a form of the invention as disclosed as a form of the invention. Accordingly, regarding any content, if it is described in the drawings, even if it is not written in text, such content may constitute a form of the invention as disclosed as a form of the invention. Likewise, regarding drawings from which a part of the drawings has been extracted, such content may constitute a form of the invention as disclosed as a form of the invention. And, such a form of the invention may be considered clear. Explanation of the symbols

[0247] 13: Transistor 22: Insulating film 26: Insulating film 27: Insulating film 28: Nitride insulating film 29: Insulating film 31: Substrate 40: Challenge Screen 41: Oxide semiconductor film 41a: Oxide semiconductor film 41b: Oxide semiconductor film 41c: Oxide semiconductor film 42: Metal oxide film 43: Challenge Match 44: Challenge Match 45: Challenge Screen 46: Substrate 47: Shielding 48: Colored layer 50: Sujimak 51: Orientation membrane 52: Orientation membrane 53: Liquid crystal layer 55: Pixel 56: Transistor 57: Capacitive element 58: Opening 59: Challenge Match 60: Liquid crystal element 61: Challenge Match 62: Opening 70: Semiconductor display device 71: Pixel section 72: Driving circuit 73: Driving circuit 75: Shift Register 76: Shift Register 77: Switch circuit 95: Transistor 96: Transistor 97: Capacitive element 98: Light-emitting element 100: Sequential circuit 101: Transistor 102: Transistor 103: Transistor 104: Transistor 105: Transistor 105A: Transistor 105B: Transistor 106: Transistor 107: Transistor 111: Wiring 112: Wiring 113: Wiring 114: Wiring 115: Wiring 117: Wiring 118: Wiring 119: Wiring 121: Wiring 122: Wiring 123: Wiring 124: Wiring 125: Wiring 4001: Board 4002: Pixel section 4003: Driving circuit 4004: Driving circuit 4005: Sealant 4006: Board 4010: Transistor 4018: FPC 4020: Insulating film 4021: Pixel electrode 4023: Liquid crystal element 4028: Liquid crystal layer 4030: Wiring 4050: Challenge Screen 4059: Sujimak 4060: Common electrode 4061: Conductive particle 4062: Sujimak 5001: Housing 5002: Housing 5003: Display unit 5004: Display unit 5005: Microphone 5006: Speaker 5007: Control Keys 5008: Stylus 5201: Housing 5202: Display unit 5203: Operation button 5204: Band 5401: Housing 5402: Display unit 5403: Keyboard 5404: Pointing device 5601: Housing 5602: Housing 5603: Display unit 5604: Display unit 5605: Connection section 5606: Control Keys 5801: Housing 5802: Housing 5803: Display unit 5804: Control Keys 5805: Lens 5806: Connection section 5901: Housing 5902: Display unit 5903: Camera 5904: Speaker 5905: Button 5906: External Connection 5907: Microphone

Claims

Claim 1 A circuit having multiple stages, each of the multiple stages having a first to seventh transistor, wherein in any one of the multiple stages, in the first transistor, one of the source and drain is always in a conductive state with the first wiring, and the other of the source and drain is always in a conductive state with the second wiring, in the second transistor, one of the source and drain is always in a conductive state with the first wiring, and the other of the source and drain is always in a conductive state with the third wiring, in the third transistor, one of the source and drain is always in a conductive state with the gate of the first transistor, and the other of the source and drain is always in a conductive state with one of the source and drain of the fourth transistor, in the fourth transistor, a power supply voltage having a first polarity is input to the other of the source and drain, so that the gate is always in a conductive state with the gate of the second transistor, in the fifth transistor, one of the source and drain is always in a conductive state with the fourth wiring, and the gate is always in a conductive state with the fifth wiring. In the sixth transistor, one of the source and drain is always in a conducting state with the gate of the second transistor, the other of the source and drain is always in a conducting state with the fourth wiring, and the gate is always in a conducting state with the sixth wiring; in the seventh transistor, one of the source and drain is always in a conducting state with the gate of the second transistor, and the other of the source and drain is always in a conducting state with the third wiring; the first wiring has the function of outputting a first signal to the gate of the pixel transistor; the second wiring has the function of inputting a first clock signal; the third wiring has the function of a power line of the first polarity; the fourth wiring has the function of a power line of the second polarity; the fifth wiring has the function of inputting a second signal output from a circuit different from the one circuit among the multiple stages of the circuit to the one circuit; and the sixth wiring,It has a function of inputting a second clock signal, and when the fourth wiring is in a conducting state with the gate of the first transistor and the gate of the seventh transistor through at least the channel forming region of the fifth transistor, the potential of the fourth wiring is input to the gate of the first transistor and the gate of the seventh transistor through at least the channel forming region of the fifth transistor, and when the other side of the source and drain of the fourth transistor is in a conducting state with the gate of the first transistor and the gate of the seventh transistor through at least the channel forming region of the fourth transistor and the channel forming region of the third transistor, the power supply voltage having the first polarity is input to the gate of the first transistor and the gate of the seventh transistor through at least the channel forming region of the fourth transistor and the channel forming region of the third transistor, and when the other side of the source and drain of the fourth transistor is not in a conducting state with the gate of the first transistor and the gate of the seventh transistor through at least the channel forming region of the fourth transistor and the channel forming region of the third transistor, the power supply voltage having the first polarity is input to at least the fourth A semiconductor device that is not input to the gate of the first transistor and the gate of the seventh transistor through the channel forming region of the transistor and the channel forming region of the third transistor. Claim 2 A circuit having multiple stages, each of the multiple stages having a first to seventh transistor, and in any one of the multiple stages, in the first transistor, one of the source and drain is electrically connected to a first wire and the other of the source and drain is electrically connected to a second wire; in the second transistor, one of the source and drain is electrically connected to the first wire and the other of the source and drain is electrically connected to a third wire; in the third transistor, one of the source and drain is electrically connected to the gate of the first transistor and the other of the source and drain is electrically connected to one of the source and drain of the fourth transistor; in the fourth transistor, a power supply voltage having a first polarity is input to the other of the source and drain, so that the gate is electrically connected to the gate of the second transistor; in the fifth transistor, one of the source and drain is electrically connected to a fourth wire and the gate is electrically connected to a fifth wire; and in the sixth transistor, the source and drain One of them is electrically connected to the gate of the second transistor, and the other of the source and drain is electrically connected to the fourth wiring, and the gate is electrically connected to the sixth wiring, and in the seventh transistor, one of the source and drain is electrically connected to the gate of the second transistor, and the other of the source and drain is electrically connected to the third wiring, the first wiring has the function of outputting a first signal to the gate of the pixel transistor, the second wiring has the function of inputting a first clock signal, the third wiring has the function of a power line of the first polarity, the fourth wiring has the function of a power line of the second polarity, the fifth wiring has the function of inputting a second signal output from a circuit different from the one circuit among the multiple stages of the circuit to the one circuit, and the sixth wiring isIt has a function of inputting a second clock signal, and when the fourth wiring is in a conducting state with the gate of the first transistor and the gate of the seventh transistor through at least the channel forming region of the fifth transistor, the potential of the fourth wiring is input to the gate of the first transistor and the gate of the seventh transistor through at least the channel forming region of the fifth transistor, and when the other side of the source and drain of the fourth transistor is in a conducting state with the gate of the first transistor and the gate of the seventh transistor through at least the channel forming region of the fourth transistor and the channel forming region of the third transistor, the power supply voltage having the first polarity is input to the gate of the first transistor and the gate of the seventh transistor through at least the channel forming region of the fourth transistor and the channel forming region of the third transistor, and when the other side of the source and drain of the fourth transistor is not in a conducting state with the gate of the first transistor and the gate of the seventh transistor through at least the channel forming region of the fourth transistor and the channel forming region of the third transistor, the power supply voltage having the first polarity is input to at least the fourth A semiconductor device that is not input to the gate of the first transistor and the gate of the seventh transistor through the channel forming region of the transistor and the channel forming region of the third transistor. Claim 3 A semiconductor device according to claim 1 or 2, wherein the third transistor has a larger W / L than the seventh transistor, where W is the channel width and L is the channel length. Claim 4 A semiconductor device according to claim 1 or 2, wherein the fourth transistor has a larger W / L than the seventh transistor, where W is the channel width and L is the channel length. Claim 5 A semiconductor device according to claim 1 or 2, wherein the third transistor and the fourth transistor each have a W / L greater than that of the seventh transistor, where W is the channel width and L is the channel length. Claim 6 A semiconductor device according to claim 1 or 2, wherein the fourth transistor has a larger overlapping area between the semiconductor layer and the gate electrode than the third transistor. Claim 7 A semiconductor device according to claim 1 or 2, wherein the first to seventh transistors have the same polarity. Claim 8 A semiconductor device according to claim 1 or 2, wherein when the fourth wiring is in a conducting state with the gate of the first transistor and the gate of the seventh transistor through at least the channel forming region of the fifth transistor, the potential of the fourth wiring is input to the gate of the first transistor and the gate of the seventh transistor through at least the channel forming region of the fifth transistor, thereby causing the first transistor and the seventh transistor to be in a conducting state, and when the other side of the source and drain of the fourth transistor is in a conducting state with the gate of the first transistor and the gate of the seventh transistor through at least the channel forming region of the fourth transistor and the channel forming region of the third transistor, the power supply voltage having the first polarity is input to the gate of the first transistor and the gate of the seventh transistor through at least the channel forming region of the fourth transistor and the channel forming region of the third transistor, thereby causing the first transistor and the seventh transistor to be in a non-conducting state. Claim 9 A circuit having multiple stages, each of the multiple stages having a first to seventh transistor, wherein in any one of the multiple stages, in the first transistor, one of the source and drain is always in a conductive state with the first wiring, and the other of the source and drain is always in a conductive state with the second wiring, in the second transistor, one of the source and drain is always in a conductive state with the first wiring, and the other of the source and drain is always in a conductive state with the third wiring, in the third transistor, one of the source and drain is always in a conductive state with the gate of the first transistor, and the other of the source and drain is always in a conductive state with one of the source and drain of the fourth transistor, in the fourth transistor, a power supply voltage having a first polarity is input to the other of the source and drain, so that the gate is always in a conductive state with the gate of the second transistor, in the fifth transistor, one of the source and drain is always in a conductive state with the fourth wiring, and the gate is always in a conductive state with the fifth wiring. A semiconductor device in which, in the sixth transistor, one of the source and drain is always in a conducting state with the gate of the second transistor, the other of the source and drain is always in a conducting state with the fourth wiring, and the gate is always in a conducting state with the sixth wiring, and in the seventh transistor, one of the source and drain is always in a conducting state with the gate of the second transistor, and the other of the source and drain is always in a conducting state with the third wiring. Claim 10 The apparatus has first to seventh transistors and first to sixth wirings, wherein one of the source and drain of the first transistor is electrically connected to the first wiring, the other of the source and drain of the first transistor is electrically connected to the second wiring, one of the source and drain of the second transistor is electrically connected to the third wiring, the other of the source and drain of the second transistor is electrically connected to the first wiring, one of the source and drain of the third transistor is electrically connected to the third wiring, the other of the source and drain of the third transistor is electrically connected to one of the source and drain of the fourth transistor, the gate of the third transistor is electrically connected to the second wiring, the other of the source and drain of the fourth transistor is electrically connected to the gate of the seventh transistor, the gate of the fourth transistor is electrically connected to the gate of the second transistor, and the source of the fifth transistor One of the source and drain is electrically connected to the gate of the seventh transistor, the other of the source and drain of the fifth transistor is electrically connected to the fourth wiring, the gate of the fifth transistor is electrically connected to the fifth wiring, one of the source and drain of the sixth transistor is electrically connected to the sixth wiring, the other of the source and drain of the sixth transistor is electrically connected to the gate of the second transistor, the gate of the sixth transistor is electrically connected to the fifth wiring, one of the source and drain of the seventh transistor is electrically connected to the gate of the second transistor, the other of the source and drain of the seventh transistor is electrically connected to the fifth wiring, and the gate of the seventh transistor isA semiconductor device electrically connected to the gate of the first transistor. Claim 11 The apparatus has first to seventh transistors and first to sixth wirings, wherein one of the source and drain of the first transistor is electrically connected to the first wiring, the other of the source and drain of the first transistor is electrically connected to the second wiring, one of the source and drain of the second transistor is electrically connected to the third wiring, the other of the source and drain of the second transistor is electrically connected to the first wiring, one of the source and drain of the third transistor is electrically connected to the third wiring, the other of the source and drain of the third transistor is electrically connected to one of the source and drain of the fourth transistor, the gate of the third transistor is electrically connected to the second wiring, the other of the source and drain of the fourth transistor is electrically connected to the gate of the seventh transistor, the gate of the fourth transistor is electrically connected to the gate of the second transistor, and the source of the fifth transistor One of the source and drain is electrically connected to the gate of the seventh transistor, the other of the source and drain of the fifth transistor is electrically connected to the fourth wiring, the gate of the fifth transistor is electrically connected to the fifth wiring, one of the source and drain of the sixth transistor is electrically connected to the sixth wiring, the other of the source and drain of the sixth transistor is electrically connected to the gate of the second transistor, the gate of the sixth transistor is electrically connected to the fifth wiring, one of the source and drain of the seventh transistor is electrically connected to the gate of the second transistor, the other of the source and drain of the seventh transistor is electrically connected to the fifth wiring, and the gate of the seventh transistor isA semiconductor device having a first wire electrically connected to the gate of the first transistor, a first wire electrically connected to the gate of the transistor of the first pixel, a first clock signal input to the second wire, a first power supply voltage input to the third wire, a fourth wire electrically connected to the gate of the transistor of the second pixel, a second clock signal input to the fifth wire, and a second power supply voltage input to the sixth wire. Claim 12 The apparatus has first to seventh transistors and first to sixth wirings, wherein one of the source and drain of the first transistor is electrically connected to the first wiring, the other of the source and drain of the first transistor is electrically connected to the second wiring, one of the source and drain of the second transistor is electrically connected to the third wiring, the other of the source and drain of the second transistor is electrically connected to the first wiring, one of the source and drain of the third transistor is electrically connected to the third wiring, the other of the source and drain of the third transistor is electrically connected to one of the source and drain of the fourth transistor, the gate of the third transistor is electrically connected to the second wiring, the other of the source and drain of the fourth transistor is electrically connected to the gate of the seventh transistor, the gate of the fourth transistor is electrically connected to the gate of the second transistor, and the source of the fifth transistor One of the source and drain is electrically connected to the gate of the seventh transistor, the other of the source and drain of the fifth transistor is electrically connected to the fourth wiring, the gate of the fifth transistor is electrically connected to the fifth wiring, one of the source and drain of the sixth transistor is electrically connected to the sixth wiring, the other of the source and drain of the sixth transistor is electrically connected to the gate of the second transistor, the gate of the sixth transistor is electrically connected to the fifth wiring, one of the source and drain of the seventh transistor is electrically connected to the gate of the second transistor, the other of the source and drain of the seventh transistor is electrically connected to the fifth wiring, and the gate of the seventh transistor isA semiconductor device electrically connected to the gate of the first transistor, wherein the fifth transistor has a greater ratio of channel width to channel length than the sixth transistor. Claim 13 The apparatus has first to seventh transistors and first to sixth wirings, wherein one of the source and drain of the first transistor is electrically connected to the first wiring, the other of the source and drain of the first transistor is electrically connected to the second wiring, one of the source and drain of the second transistor is electrically connected to the third wiring, the other of the source and drain of the second transistor is electrically connected to the first wiring, one of the source and drain of the third transistor is electrically connected to the third wiring, the other of the source and drain of the third transistor is electrically connected to one of the source and drain of the fourth transistor, the gate of the third transistor is electrically connected to the second wiring, the other of the source and drain of the fourth transistor is electrically connected to the gate of the seventh transistor, the gate of the fourth transistor is electrically connected to the gate of the second transistor, and the source of the fifth transistor One of the source and drain is electrically connected to the gate of the seventh transistor, the other of the source and drain of the fifth transistor is electrically connected to the fourth wiring, the gate of the fifth transistor is electrically connected to the fifth wiring, one of the source and drain of the sixth transistor is electrically connected to the sixth wiring, the other of the source and drain of the sixth transistor is electrically connected to the gate of the second transistor, the gate of the sixth transistor is electrically connected to the fifth wiring, one of the source and drain of the seventh transistor is electrically connected to the gate of the second transistor, the other of the source and drain of the seventh transistor is electrically connected to the fifth wiring, and the gate of the seventh transistor isA semiconductor device having a first wire electrically connected to the gate of the first transistor, a first wire electrically connected to the gate of the transistor of the first pixel, a first clock signal input to the second wire, a first power supply voltage input to the third wire, a fourth wire electrically connected to the gate of the transistor of the second pixel, a second clock signal input to the fifth wire, a second power supply voltage input to the sixth wire, and the fifth transistor having a greater ratio of channel width to channel length than the sixth transistor. Claim 14 A semiconductor device according to any one of claims 10 to 13, wherein the first to seventh transistors all have the same polarity.

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