Semiconductor package and method of manufacturing the same

Abstract

A semiconductor package according to some embodiments comprises: a base substrate; an interposer substrate comprising a plurality of interposer redistribution structures sequentially stacked along a vertical direction, each comprising a plurality of conductive interposer patterns and a plurality of conductive interposer vias, and an interposer insulating layer; a semiconductor chip interposed between the base substrate and the interposer substrate and attached to the base substrate; and a plurality of conductive connection pads each disposed on a plurality of uppermost conductive interposer patterns of an uppermost interposer redistribution structure among the plurality of interposer redistribution structures; wherein the interposer insulating layer has a plurality of pad holes that expose at least a portion of the upper surface of the plurality of conductive connection pads and the upper surface of the plurality of uppermost conductive interposer patterns, the side of the plurality of conductive connection pads is perpendicular to the upper surface of the interposer insulating layer, the side of the plurality of uppermost conductive interposer patterns is perpendicular to the upper surface of the interposer insulating layer, and the inner wall of the plurality of pad holes is inclined with respect to the upper surface of the interposer insulating layer.

Description

Technology Field

[0001] The technical concept of the present invention relates to a semiconductor package and a method for manufacturing the same, and more specifically, to a fan-out semiconductor package and a method for manufacturing the same. Background Technology

[0002] Driven by the rapid advancement of the electronics industry and user demands, electronic devices are becoming increasingly smaller and lighter; consequently, there is a demand for high integration of semiconductor chips, which are the core components of electronic devices. To address this trend, semiconductor package structures are being proposed that stack multiple semiconductor chips on a single package substrate or insert an interposer substrate between semiconductor chips. Furthermore, stacked semiconductor package structures are being proposed in which a second semiconductor package structure is stacked on top of a semiconductor package structure. The problem to be solved

[0003] The problem that the technical concept of the present invention aims to solve is to provide a semiconductor package with improved reliability.

[0004] The problem that the technical concept of the present invention aims to solve is to provide a method for manufacturing a semiconductor package with improved reliability. means of solving the problem

[0005] According to some embodiments for solving the above-described technical problem, a semiconductor package is provided. The semiconductor package comprises: a base substrate; an interposer substrate comprising a plurality of interposer redistribution structures sequentially stacked along a vertical direction, each comprising a plurality of conductive interposer patterns and a plurality of conductive interposer vias, and an interposer insulating layer; and a semiconductor chip interposed between the base substrate and the interposer substrate and attached on the base substrate. The apparatus comprises a plurality of conductive connection pads each disposed on a plurality of uppermost conductive interposer patterns of an uppermost interposer redistribution structure among the plurality of interposer redistribution structures, wherein the interposer insulating layer has a plurality of pad holes that expose at least a portion of the upper surface of the plurality of conductive connection pads and the upper surface of the plurality of uppermost conductive interposer patterns, the side of the plurality of conductive connection pads is perpendicular to the upper surface of the interposer insulating layer, the side of the plurality of uppermost conductive interposer patterns is perpendicular to the upper surface of the interposer insulating layer, and the inner wall of the plurality of pad holes is inclined with respect to the upper surface of the interposer insulating layer.

[0006] According to some embodiments for solving the technical problem described above, a semiconductor package is provided. The semiconductor package comprises: a base substrate including a plurality of base redistribution structures sequentially stacked along a vertical direction, each comprising a plurality of conductive base patterns and a plurality of conductive base vias, and a base insulating layer; a semiconductor chip attached to the base substrate through a plurality of chip connecting members; an interposer substrate disposed on the semiconductor chip, comprising a plurality of interposer redistribution structures sequentially stacked along a vertical direction, each comprising a plurality of conductive interposer patterns and a plurality of conductive interposer vias, and an interposer insulating layer having a plurality of pad holes on its upper surface; a plurality of conductive posts disposed around the semiconductor chip and extending in the vertical direction to connect the base substrate and the interposer substrate; a molding layer surrounding the semiconductor chip and the plurality of conductive posts between the base substrate and the interposer substrate; and a plurality of conductive connection pads disposed respectively on a plurality of uppermost conductive interposer patterns of an uppermost interposer redistribution structure among the plurality of interposer redistribution structures and disposed within a plurality of pad holes. and a plurality of conductive pad seed layers each interposed between the plurality of uppermost conductive interposer patterns and the plurality of conductive connection pads, and covering the lower surface of the plurality of conductive connection pads; wherein the side and upper surfaces of each of the plurality of uppermost conductive interposer patterns and the side and upper surfaces of each of the plurality of conductive connection pads are not covered by the interposer insulating layer.

[0007] According to some embodiments for solving the technical problem described above, a semiconductor package is provided. The semiconductor package comprises: a first base substrate; a first semiconductor chip attached to the first base substrate; a plurality of conductive posts disposed around the first semiconductor chip on the first base substrate; an interposer insulating layer comprising an interposer redistribution structure including a conductive interposer pattern and a conductive interposer via, and a pad hole exposing the interposer pattern on its upper surface, and an interposer substrate electrically connected to the first base substrate through the plurality of conductive posts on the first semiconductor chip; a second base substrate on the interposer substrate; a second semiconductor chip attached to the second base substrate; and a conductive connection pad disposed on the conductive interposer pattern within the pad hole. and an external connection terminal disposed on the conductive connection pad and electrically connecting the interposer substrate and the second base substrate; wherein the inner wall of the pad hole is inclined with respect to the upper surface of the interposer insulating layer and is spaced apart in a first horizontal direction from the conductive connection pad and the conductive interposer pattern. Effects of the invention

[0008] A semiconductor package according to the technical concept of the present invention includes an interposer substrate having a pad hole on its upper surface, and an uppermost connection terminal and an uppermost interposer rewiring pattern are exposed through the pad hole. Accordingly, the mechanical stability of the interposer substrate can be improved, and the reliability of the semiconductor package can be improved. Brief explanation of the drawing

[0009] FIG. 1 is a cross-sectional view showing a semiconductor package according to embodiments of the technical concept of the present invention. Figure 2 is an enlarged view of the part labeled "EX1" in Figure 1. Figure 3 is an enlarged view of the part labeled "EX2" in Figure 1. FIGS. 4 and 5 are schematic plan views for illustrating some components of the portion labeled "EX2" in a semiconductor package according to exemplary embodiments. FIG. 6 is an enlarged view of a portion corresponding to the portion labeled "EX2" in FIG. 1 in a semiconductor package according to some other embodiments of the present invention. FIG. 7 is a cross-sectional view showing a package-on-package type semiconductor package according to another embodiment of the technical concept of the present invention, in which an upper package is stacked on a lower package. Figure 8 is an enlarged view of the part labeled "EX3" in Figure 7. FIG. 9 is an enlarged view of a portion corresponding to the portion labeled "EX3" in FIG. 7 in a package-on-package type semiconductor package according to some other embodiments of the present invention. FIGS. 10a to 10l are cross-sectional views illustrating, in order, a method for manufacturing a semiconductor package according to exemplary embodiments of the present invention. Specific details for implementing the invention

[0010] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Identical components in the drawings are denoted by the same reference numerals, and redundant descriptions thereof are omitted.

[0011] FIG. 1 is a cross-sectional view showing a semiconductor package (1a) according to embodiments of the technical concept of the present invention. FIG. 2 is an enlarged view of the portion labeled "EX1" in FIG. 1. FIG. 3 is an enlarged view of the portion labeled "EX2" in FIG. 1. FIG. 4 and FIG. 5 are schematic plan views for explaining some components of the portion labeled "EX2" in a semiconductor package (1a) according to exemplary embodiments.

[0012] Referring to FIGS. 1 to 3, a semiconductor package (1a) may include a base substrate (100), a semiconductor chip (10) on the base substrate (100), and an interposer substrate (200) covering the semiconductor chip (10).

[0013] As the semiconductor chip becomes smaller or the number of input / output terminals increases, there are limitations to accommodating all input / output terminals within the main surface of the semiconductor chip. A semiconductor package (1a) according to exemplary embodiments may be a fan-out package in which the input / output terminals are arranged extending to an area outside the outer surface of the semiconductor chip (10). Additionally, the semiconductor package (1a) may have a structure that is a Fan Out Wafer Level Package (FOWLP) or a Fan Out Panel Level Package (FOPLP) manufactured at the wafer level or panel level.

[0014] According to exemplary embodiments, the base substrate (100) may include a first lower insulating layer (102), a base insulating layer (110), and a plurality of base redistribution structures (120, 130, 140, 150, 160) disposed at different levels in the vertical direction (Z direction).

[0015] According to exemplary embodiments, the base insulating layer (110) may include first to fourth sub-base insulating layers (112, 114, 116, 118) sequentially stacked on the first lower insulating layer (102). Although FIG. 1 illustrates the base insulating layer (110) as including four sub-base insulating layers, it is not limited thereto. For example, the base insulating layer (110) may include one, two, or three sub-base insulating layers, or it may include five or more sub-base insulating layers. According to exemplary embodiments, the base insulating layer (110) may be formed as a single structure. For example, the first to fourth sub-base insulating layers (112, 114, 116, 118) may be formed as a single structure. For example, the upper surface of the fourth sub-base insulating layer (118) may refer to the upper surface of the base insulating layer (110). According to exemplary embodiments, the base insulating layer (110) and the first lower insulating layer (102) may be formed as a single structure.

[0016] According to exemplary embodiments, the first lower insulating layer (102) and the first to fourth sub-base insulating layers (112, 114, 116, 118) may each be made of an organic polymer material. According to exemplary embodiments, the first lower insulating layer (102) and the first to fourth sub-base insulating layers (112, 114, 116, 118) may each be made of a PID (Photo Imageable Dielectric) capable of photoresist processing.

[0017] According to exemplary embodiments, the first to fifth base rewiring structures (120, 130, 140, 150, 160) may be sequentially stacked along a vertical direction (Z direction) on the first lower insulating layer (102) and may be at least partially surrounded by the first lower insulating layer (102) and the first to fourth sub-base insulating layers (112, 114, 116, 118).

[0018] Although FIG. 1 is illustrated as having a base substrate (100) comprising five base rewiring structures, it is not limited thereto. For example, the base substrate (100) may include two, three, or four base rewiring structures stacked sequentially, and may include six or more base rewiring structures stacked sequentially.

[0019] According to exemplary embodiments, the first base rewiring structure (120) may be the lowest base rewiring structure of the base substrate (100). According to exemplary embodiments, the first base rewiring structure (120) may include a plurality of first conductive base seed layers (122), a plurality of first conductive base pads (124), and a plurality of first conductive base patterns (126). According to exemplary embodiments, the plurality of first conductive base patterns (126) may be disposed on the upper surface of the first lower insulating layer (102) and may extend in a horizontal direction (X direction and / or Y direction) and may be connected to a plurality of first conductive base pads (124) that penetrate the first lower insulating layer (102) in a vertical direction (Z direction). In this case, the lower surface of the plurality of first conductive base pads (124) may be exposed to the lower surface of the first lower insulating layer (102).

[0020] According to exemplary embodiments, the first sub-base insulating layer (112) may surround a plurality of first conductive base patterns (126) on the first lower insulating layer (102). According to exemplary embodiments, a plurality of first conductive base seed layers (122) may include a portion disposed between a plurality of first conductive base patterns (126) and the first lower insulating layer (102), and a portion disposed between a plurality of first conductive base pads (124) and the first lower insulating layer (102). In some embodiments, each first conductive base pattern (126) and each first conductive base pad (124) connected thereto may be formed as a single structure.

[0021] In some embodiments, the lower surface of a plurality of first conductive base pads (124) may be located at the same level in the vertical direction (Z direction) as the lower surface of the first lower insulating layer (102). In other embodiments, the lower surface of a plurality of first conductive base pads (124) may not be located at the same level in the vertical direction (Z direction) as the lower surface of the first lower insulating layer (102). For example, the lower surface of a plurality of first conductive base pads (124) may be located at a higher level in the vertical direction (Z direction) than the lower surface of the first lower insulating layer (102). For example, the lower surface of a plurality of first conductive base pads (124) may be located at a lower level in the vertical direction (Z direction) than the lower surface of the first lower insulating layer (102).

[0022] According to exemplary embodiments, a plurality of external connection terminals (182) may be disposed on the lower surface of a plurality of first conductive base pads (124). According to exemplary embodiments, the semiconductor package (1a) may be configured to electrically connect to a motherboard or other external device. For example, the plurality of first conductive base pads (124) may function as Under Bump Metallurgy (UBM). For example, the plurality of external connection terminals (182) may be solder balls or bumps.

[0023] According to exemplary embodiments, a second base rewiring structure (130) may be disposed on a first base rewiring structure (120). According to exemplary embodiments, the second base rewiring structure (130) may include a plurality of second conductive base seed layers (132), a plurality of second conductive base vias (134), and a plurality of second conductive base patterns (136). According to exemplary embodiments, the plurality of second conductive base patterns (136) may extend horizontally (in the X direction and / or Y direction) from the upper surface of the first sub-base insulating layer (112) and may be surrounded by the second sub-base insulating layer (114). According to exemplary embodiments, a plurality of second conductive base vias (134) may each penetrate the first sub-base insulating layer (112) on the first conductive base pattern (126) in a vertical direction (Z direction) and connect the first conductive base pattern (126) and the second conductive base pattern (136). According to exemplary embodiments, a plurality of second conductive base seed layers (132) may each include a portion disposed between the second conductive base pattern (136) and the first sub-base insulating layer (112), a portion disposed between a plurality of second conductive base vias (134) and the first sub-base insulating layer (112), and a portion disposed between a plurality of second conductive base vias (134) and a plurality of first conductive base patterns (126). According to exemplary embodiments, each second conductive base pattern (136) and each second conductive base via (134) connected thereto may be formed as a single structure.

[0024] According to exemplary embodiments, a third base rewiring structure (140) may be disposed on a second base rewiring structure (130). According to exemplary embodiments, the third base rewiring structure (140) may include a plurality of third conductive base seed layers (142), a plurality of third conductive base vias (144), and a plurality of third conductive base patterns (146). According to exemplary embodiments, the plurality of third conductive base patterns (146) may extend horizontally (in the X direction and / or Y direction) from the upper surface of the second sub-base insulating layer (114) and may be surrounded by the third sub-base insulating layer (116). According to exemplary embodiments, a plurality of third conductive base vias (144) may each penetrate the second sub-base insulating layer (114) on the second conductive base pattern (136) in a vertical direction (Z direction) and connect the second conductive base pattern (136) and the third conductive base pattern (146). According to exemplary embodiments, a plurality of third conductive base seed layers (142) may each include a portion disposed between the third conductive base pattern (146) and the second sub-base insulating layer (114), a portion disposed between the plurality of third conductive base vias (144) and the second sub-base insulating layer (114), and a portion disposed between the plurality of third conductive base vias (144) and the plurality of second conductive base patterns (136). According to exemplary embodiments, each third conductive base pattern (146) and each third conductive base via (144) connected thereto may be formed as a single structure.

[0025] According to exemplary embodiments, a fourth base rewiring structure (150) may be disposed on a third base rewiring structure (140). According to exemplary embodiments, the fourth base rewiring structure (150) may include a plurality of fourth conductive base seed layers (152), a plurality of fourth conductive base vias (154), and a plurality of fourth conductive base patterns (156). According to exemplary embodiments, the plurality of fourth conductive base patterns (156) may extend horizontally (in the X direction and / or Y direction) from the upper surface of the third sub-base insulating layer (116) and may be surrounded by the fourth sub-base insulating layer (118). According to exemplary embodiments, a plurality of fourth conductive base vias (154) may each penetrate the third sub-base insulating layer (116) on the third conductive base pattern (146) in a vertical direction (Z direction) and connect the third conductive base pattern (146) and the fourth conductive base pattern (156). According to exemplary embodiments, a plurality of fourth conductive base seed layers (152) may each include a portion disposed between the fourth conductive base pattern (156) and the third sub-base insulating layer (116), a portion disposed between the plurality of fourth conductive base vias (154) and the third sub-base insulating layer (116), and a portion disposed between the plurality of fourth conductive base vias (154) and the plurality of third conductive base patterns (146). According to exemplary embodiments, each fourth conductive base pattern (156) and each fourth conductive base via (154) connected thereto may be formed as a single structure.

[0026] According to exemplary embodiments, a fifth base rewiring structure (160) may be disposed on a fourth base rewiring structure (150). According to exemplary embodiments, the fifth base rewiring structure (160) may correspond to a base rewiring structure disposed at the top in the vertical direction (Z direction) among a plurality of base rewiring structures (120, 130, 140, 150, 160). For example, the fifth base rewiring structure (160) may be a top base rewiring structure (UBRD).

[0027] According to exemplary embodiments, the fifth base rewiring structure (160) may include a plurality of fifth conductive base seed layers (162), a plurality of fifth conductive base vias (164), and a plurality of fifth conductive base patterns (166). According to exemplary embodiments, the plurality of fifth conductive base patterns (166) may include a base rewiring line extending in a horizontal direction (X direction and / or Y direction) on the upper surface of the fourth sub-base insulating layer (118), and a base rewiring pad configured to connect the base substrate (100) to the semiconductor chip (10). According to exemplary embodiments, the plurality of fifth conductive base vias (164) may each penetrate the fourth sub-base insulating layer (118) in a vertical direction (Z direction) on the fourth conductive base pattern (156) and connect the fourth conductive base pattern (156) and the fifth conductive base pattern (166). According to exemplary embodiments, a plurality of fifth conductive base seed layers (162) may each include a portion disposed between a fifth conductive base pattern (166) and a fourth sub-base insulating layer (118), a portion disposed between a plurality of fifth conductive base vias (164) and a fourth sub-base insulating layer (118), and a portion disposed between a plurality of fifth conductive base vias (164) and a plurality of fourth conductive base patterns (156). According to exemplary embodiments, each fifth conductive base pattern (166) and each fifth conductive base via (164) connected thereto may be formed as a single structure.

[0028] According to exemplary embodiments, a plurality of first to fifth conductive base seed layers (122, 132, 142, 152, 162) may each comprise copper (Cu), titanium (Ti), titanium tungsten (TiW), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), chromium (Cr), aluminum (Al), or a combination thereof, but are not limited thereto. According to exemplary embodiments, a plurality of first to fifth conductive base seed layers (122, 132, 142, 152, 162) may each be Cu / Ti, in which copper is deposited on titanium, or Cu / TiW, in which copper is deposited on titanium tungsten.

[0029] According to exemplary embodiments, a plurality of first conductive base pads (124) may comprise metals such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), ruthenium (Ru), or alloys thereof.

[0030] According to exemplary embodiments, a plurality of second to fifth conductive base vias (134, 144, 154, 164) and a plurality of first to fifth conductive base patterns (126, 136, 146, 156, 166) may each comprise a metal or an alloy thereof such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), ruthenium (Ru), etc.

[0031] According to exemplary embodiments, the semiconductor chip (10) may include a semiconductor substrate (12) having an active surface (14) and an inactive surface (13) that are opposite to each other. The semiconductor chip (10) may be understood as a concept including a semiconductor device having an integrated circuit. According to exemplary embodiments, a circuit portion for implementing the integrated circuit function of the semiconductor chip (10) may be formed on the active surface (14) of the semiconductor substrate (12). According to exemplary embodiments, a plurality of chip pads (16) may be disposed on the lower surface of the semiconductor chip (10) adjacent to the active surface (14) of the semiconductor substrate (12). Since the active surface (14) of the semiconductor substrate (12) is very close to the lower surface of the semiconductor chip (10), the illustration of separately distinguishing the active surface (14) of the semiconductor substrate (12) and the lower surface of the semiconductor chip (10) is omitted. For example, the lower surface of the semiconductor chip (10) may be referred to as the active surface (14) of the semiconductor substrate (12), and the upper surface of the semiconductor chip (10) may be referred to as the inactive surface (13) of the semiconductor substrate (12).

[0032] According to exemplary embodiments, the semiconductor chip (10) may be disposed on the base substrate (100) in a face-down arrangement where the active surface (14) of the semiconductor substrate (12) faces the base substrate (100).

[0033] According to exemplary embodiments, a semiconductor chip (10) may include a plurality of chip pads (16) and may be connected to a base substrate (100) through a plurality of chip connecting members (18) between some of the plurality of fifth conductive base patterns (166) and the plurality of chip pads (16). In this case, the plurality of fifth conductive base patterns (166) connected to the plurality of chip connecting members (18) may perform the function of conductive pads. For example, the plurality of chip connecting members may be solder balls or microbumps.

[0034] According to exemplary embodiments, the semiconductor substrate (12) may include a semiconductor material such as silicon (Si) or germanium (Ge). According to exemplary embodiments, the semiconductor substrate (12) may include a compound semiconductor material such as SiC (silicon carbide), GaAs (gallium arsenide), InAs (indium arsenide), and InP (indium phosphide). For example, the semiconductor substrate (12) may include a conductive region, for example, an impurity-doped well, and may have various device isolation structures such as a shallow trench isolation (STI) structure.

[0035] In some embodiments, the semiconductor chip (10) may be a logic chip. For example, the semiconductor chip (10) may be a central processing unit (CPU) chip, a graphic processing unit (GPU) chip, or an application processor (AP) chip. In some other embodiments, the semiconductor chip (10) may be a memory semiconductor chip. For example, the semiconductor chip (10) may be a non-volatile memory semiconductor chip such as Flash Memory, Phase-change Random Access Memory (PRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FeRAM), or Resistive Random Access Memory (RRAM). The Flash Memory may be, for example, NAND Flash Memory or V-NAND Flash Memory. For example, the semiconductor chip (10) may be a volatile memory semiconductor chip such as Dynamic Random Access Memory (DRAM) or Static Random Access Memory (SRAM).

[0036] According to exemplary embodiments, a plurality of conductive posts (172) may be disposed around a semiconductor chip (10). According to exemplary embodiments, the plurality of conductive posts (172) may be disposed on some of a plurality of fifth conductive base patterns (166) and configured to electrically connect the base substrate (100) and the interposer substrate (200). In this case, the plurality of fifth conductive base patterns (166) connected to the plurality of conductive posts (172) may function as conductive pads. According to exemplary embodiments, the plurality of conductive posts (172) may be made of copper (Cu), copper-tin (CuSn), copper-manganese (CuMg), copper-nickel (CuNi), copper-zinc (CuZn), copper-lead (CuPd), copper-gold (CuAu), copper-tungsten (CuW), tungsten (W), or an alloy thereof.

[0037] According to exemplary embodiments, a molding layer (174) may be interposed in the space between the base substrate (100) and the interposer substrate (200). The molding layer (174) may surround a semiconductor chip (10), a plurality of conductive posts (172), a plurality of fifth conductive base patterns (166), and a plurality of chip connecting members (18). For example, the top conductive base pattern of the top base redistribution structure (UBRD) (e.g., the fifth conductive base pattern (166)) may be placed on the upper surface of the base insulating layer (110), and the side and top surfaces may be covered by the molding layer (174). According to exemplary embodiments, it may be made of an epoxy-based molding resin, a polyimide-based molding resin, etc. For example, it may be a molding member comprising an epoxy mold compound (EMC).

[0038] According to exemplary embodiments, the interposer substrate (200) may include a second lower insulating layer (202), an interposer insulating layer (210), and a plurality of interposer redistribution structures (220, 230, 240) disposed at different levels in the vertical direction (Z direction).

[0039] According to exemplary embodiments, the interposer insulating layer (210) may include first to third sub-interposer insulating layers (212, 214, 216) sequentially stacked on the second lower insulating layer (202). Although FIG. 1 illustrates the interposer insulating layer (210) as including three sub-interposer insulating layers, it is not limited thereto. For example, the interposer insulating layer (210) may include one or two sub-interposer insulating layers, or four or more sub-interposer insulating layers. According to exemplary embodiments, the interposer insulating layer (210) may be formed as a single structure. For example, the first to third sub-interposer insulating layers (212, 214, 216) may be formed as a single structure. For example, the upper surface (210U) of the interposer insulating layer (210) may refer to the upper surface of the uppermost sub-interposer insulating layer (USI) (e.g., the third interposer insulating layer (216)) among the plurality of sub-interposer insulating layers. According to exemplary embodiments, the interposer insulating layer (210) and the second lower insulating layer (202) may be formed as a single structure.

[0040] According to exemplary embodiments, the second lower insulating layer (202) and the first to third sub-interposer insulating layers (212, 214, 216) may each be made of an organic polymer material. According to exemplary embodiments, the second lower insulating layer (202) and the first to third sub-interposer insulating layers (212, 214, 216) may each be made of a PID (Photo Imageable Dielectric) capable of photoresist processing.

[0041] According to exemplary embodiments, the interposer insulating layer (210) may have a plurality of pad holes (PH) that partially penetrate the interposer insulating layer (210) on the upper surface (210U). According to exemplary embodiments, the plurality of pad holes (PH) may have an inlet on the upper surface (210U) of the interposer insulating layer (210) and may have a bottom surface (PHU) and an inner wall (PHS) within the interposer insulating layer (210). According to exemplary embodiments, the plurality of pad holes (PH) may have a tapered shape in which the horizontal cross-sectional area gradually narrows as it extends from the inlet toward the bottom surface (PHU). In this case, the inner wall (PHS) of the plurality of pad holes (PH) may be inclined with respect to the upper surface (210U) of the interposer insulating layer (210). For example, the first width (a1), which is the width along the first horizontal direction (X direction) of the entrance of the plurality of pad holes (PH), may be larger than the second width (a2), which is the width along the first horizontal direction (X direction) of the bottom surface (PHU). In this specification, the width along the first horizontal direction (X direction) of the plurality of pad holes (PH) may refer to the second width (a2), which is the width along the first horizontal direction (X direction) of the bottom surface (PHU) of the plurality of pad holes (PH).

[0042] According to exemplary embodiments, a plurality of pad holes (PH) may penetrate the uppermost sub-interposer insulating layer (USI) (e.g., the third interposer insulating layer (216)). For example, the plurality of pad holes (PH) may be defined by the inner wall of the third sub-interposer insulating layer (216) and the upper surface of the second sub-interposer insulating layer (214). For example, the inner wall (PHS) of the plurality of pad holes (PH) may be the inner wall of the third sub-interposer insulating layer (216), and the bottom surface (PHU) of the plurality of pad holes (PG) may be the upper surface of the second sub-interposer insulating layer (214).

[0043] According to exemplary embodiments, the first to third interposer redistribution structures (220, 230, 240) may be sequentially stacked along a vertical direction (Z direction) on the second lower insulating layer (202). According to exemplary embodiments, the first to third interposer redistribution structures (220, 230, 240) may be at least partially surrounded by the second lower insulating layer (202) and the first to third sub-interposer insulating layers (212, 214, 216).

[0044] In FIG. 1, the interposer substrate (200) is illustrated as including three interposer redistribution structures, but is not limited thereto. For example, the interposer substrate (200) may include two interposer redistribution structures stacked sequentially, and may include four or more interposer redistribution structures stacked sequentially.

[0045] According to exemplary embodiments, the first interposer redistribution structure (220) may be the lowest interposer redistribution structure of the interposer substrate (200). According to exemplary embodiments, the first interposer redistribution structure (220) may include a plurality of first conductive interposer seed layers (222), a plurality of first conductive interposer pads (224), and a plurality of first conductive interposer patterns (226).

[0046] According to exemplary embodiments, a plurality of first conductive interposer patterns (226) may extend in a horizontal direction (X direction and / or Y direction) on the second lower insulating layer (202). According to exemplary embodiments, a first sub-interposer insulating layer (212) may surround a plurality of first conductive interposer patterns (226) on the second lower insulating layer (202). According to exemplary embodiments, a plurality of first conductive interposer pads (224) penetrate the second lower insulating layer (202) in a vertical direction (Z direction) on a plurality of conductive posts (172) and may each contact a plurality of first conductive interposer patterns (226). In some embodiments, each first conductive interposer pattern (226) and each first conductive interposer pad (224) contacting it may be formed as a single structure.

[0047] According to exemplary embodiments, a plurality of first conductive interposer seed layers (222) may include a portion disposed between a plurality of first conductive interposer patterns (226) and a second lower insulating layer (202), a portion disposed between a plurality of first conductive interposer pads (224) and a second lower insulating layer (202), and a portion disposed between a plurality of first conductive interposer pads (224) and a plurality of conductive posts (172). For example, the lower surface of each of the plurality of first conductive interposer pads (224) may face the upper surface of a conductive post (172) with the first conductive interposer seed layer (222) in between.

[0048] In some embodiments, the lower surface of a plurality of first conductive interposer pads (224) may be located at the same level in the vertical direction (Z direction) as the lower surface of the second lower insulating layer (202). In other embodiments, the lower surface of a plurality of first conductive interposer pads (224) may not be located at the same level in the vertical direction (Z direction) as the lower surface of the second lower insulating layer (202). For example, the lower surface of a plurality of first conductive interposer pads (224) may be located at a higher level in the vertical direction (Z direction) than the lower surface of the second lower insulating layer (202). For example, the lower surface of a plurality of first conductive interposer pads (224) may be located at a lower level in the vertical direction (Z direction) than the lower surface of the second lower insulating layer (202).

[0049] According to exemplary embodiments, a second interposer redistribution structure (230) may be disposed on a first interposer redistribution structure (220). According to exemplary embodiments, the second interposer redistribution structure (230) may include a plurality of second conductive interposer seed layers (232), a plurality of second conductive interposer vias (234), and a plurality of second conductive interposer patterns (236). According to exemplary embodiments, the plurality of second conductive interposer patterns (236) may extend horizontally (in the X direction and / or Y direction) from the upper surface of the first sub-interposer insulating layer (212) and may be surrounded by the second sub-interposer insulating layer (214). According to exemplary embodiments, a plurality of second conductive interposer vias (234) may each penetrate the first sub-interposer insulating layer (212) on the first conductive interposer pattern (226) in a vertical direction (Z direction) and connect the first conductive interposer pattern (226) and the second conductive interposer pattern (236). According to exemplary embodiments, a plurality of second conductive interposer seed layers (232) may each include a portion disposed between the second conductive interposer pattern (236) and the first sub-interposer insulating layer (212), a portion disposed between the plurality of second conductive interposer vias (234) and the first sub-interposer insulating layer (212), and a portion disposed between the plurality of second conductive interposer vias (234) and the plurality of first conductive interposer patterns (226). According to exemplary embodiments, each second conductive interposer pattern (236) and each second conductive interposer via (234) connected thereto may be formed as a single structure.

[0050] According to exemplary embodiments, a third interposer redistribution structure (240) may be disposed on a second interposer redistribution structure (230). According to exemplary embodiments, the third interposer redistribution structure (240) may correspond to the interposer redistribution structure disposed at the top in the vertical direction (Z direction) among a plurality of interposer redistribution structures (220, 230, 240). For example, the third interposer redistribution structure (240) may correspond to the top interposer redistribution structure (UIRD).

[0051] According to exemplary embodiments, the third interposer rewiring structure (240) may include a plurality of third conductive interposer seed layers (242), a plurality of third conductive interposer vias (244), and a plurality of third conductive interposer patterns (246). For example, the plurality of third conductive interposer patterns (246) may correspond to a plurality of uppermost conductive interposer patterns (UIP).

[0052] Referring to FIGS. 4 and 5, a plurality of third conductive interposer patterns (246) may be disposed on the upper surface of the second sub-interposer insulating layer (214). According to exemplary embodiments, the plurality of third conductive interposer patterns (246) may include a plurality of conductive pad patterns (246a) having a dot shape and a plurality of conductive line patterns (246b) having a line shape extending in a horizontal direction (X direction and / or Y direction). For example, the plurality of conductive pad patterns (246a) may have an independent island shape in a planar view. According to exemplary embodiments, the side (246S) of the plurality of third conductive interposer patterns (246) may be perpendicular to the upper surface (210U) of the interposer insulating layer (210).

[0053] According to exemplary embodiments, a plurality of third conductive interposer vias (244) may each penetrate the second sub-interposer insulating layer (214) on the second conductive interposer pattern (236) in a vertical direction (Z direction) and connect the second conductive interposer pattern (236) and the third conductive interposer pattern (246). According to exemplary embodiments, a plurality of third conductive interposer seed layers (242) may each include a portion disposed between the third conductive interposer pattern (246) and the second sub-interposer insulating layer (214), a portion disposed between the plurality of third conductive interposer vias (244) and the second sub-interposer insulating layer (214), and a portion disposed between the plurality of third conductive interposer vias (244) and the plurality of second conductive interposer patterns (236). According to exemplary embodiments, each third conductive interposer pattern (246) and each third conductive interposer via (244) connected thereto may be formed as a single structure.

[0054] According to exemplary embodiments, a plurality of first to third conductive interposer seed layers (222, 232, 242) may each comprise copper (Cu), titanium (Ti), titanium tungsten (TiW), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), chromium (Cr), aluminum (Al), or a combination thereof, but are not limited thereto. According to exemplary embodiments, a plurality of first to third conductive interposer seed layers (222, 232, 242) may each be Cu / Ti, in which copper is stacked on titanium, or Cu / TiW, in which copper is stacked on titanium tungsten.

[0055] According to exemplary embodiments, a plurality of first conductive interposer pads (224) may comprise metals such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), ruthenium (Ru), or alloys thereof.

[0056] According to exemplary embodiments, a plurality of second and third conductive interposer vias (234, 344) and a plurality of first to third conductive interposer patterns (226, 236, 246) may each comprise a metal or an alloy thereof such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), ruthenium (Ru), etc.

[0057] According to exemplary embodiments, a plurality of third conductive interposer patterns (246) may be at least partially exposed through a plurality of pad holes (PH). Referring to FIGS. 4 and 5, in a planar view, a conductive pad pattern (246a) may be placed within a pad hole (PH), and a conductive line pattern (246b) may cross a pad hole (PH).

[0058] According to exemplary embodiments, a plurality of third conductive interposer patterns (246) may have a third width (b1) which is a width along a first horizontal direction (X direction). For example, the third width (b1) may be the width along the first horizontal direction (X direction) of a conductive pad pattern (246a) having a dot shape. For example, a conductive line pattern (246b) may traverse a pad hole (PH) in a second horizontal direction (Y direction) from a planar perspective, and in this case, the third width (b1) may be the width along the first horizontal direction (X direction) of the conductive line pattern (246b).

[0059] According to exemplary embodiments, a second width (a2), which is the width along the first horizontal direction (X direction) of a plurality of pad holes (PH), may be equal to or greater than a third width (b1), which is the width along the first horizontal direction (X direction) of a plurality of third interposer patterns (246). In FIGS. 1 and 3, the second width (a2) of the plurality of pad holes (PH) is depicted as being greater than the third width (b1) of the plurality of third interposer patterns (246), but is not limited thereto. For example, the second width (a2) of the plurality of pad holes (PH) may be equal to the third width (b1) of the plurality of third interposer patterns (245).

[0060] According to exemplary embodiments, the side (246S) of each third interposer pattern (246) may include a portion spaced apart from the inner wall (PHS) of each pad hole (PH). For example, the side of each conductive pad pattern (246a) may be spaced apart from the inner wall (PHS) of each pad hole (PH). For example, the side of each conductive line pattern (246b) may include a portion spaced apart from the inner wall (PHS) of each pad hole (PH) in the first horizontal direction (X direction).

[0061] According to exemplary embodiments, the sides (246S) of a plurality of third interposer patterns (246) may be exposed through a plurality of pad holes (PH) and may not be covered by the interposer insulating layer (210). For example, the sides (246S) of a plurality of third interposer patterns (246) may not be covered by the third sub-interposer insulating layer (216). According to exemplary embodiments, a plurality of third conductive interposer seed layers (242) may include a portion exposed by a plurality of pad holes (PH).

[0062] According to exemplary embodiments, a plurality of conductive connection pads (252) may be disposed on a plurality of third interposer patterns (246) within a plurality of pad holes (PH). According to exemplary embodiments, the plurality of conductive connection pads (252) may have a dot shape and may overlap with the plurality of third conductive interposer patterns (246) in a vertical direction (Z direction). For example, in a planar view, the plurality of conductive connection pads (252) may have an independent island shape. According to exemplary embodiments, a fourth width (b2), which is the width of the plurality of conductive connection pads (252) along the first horizontal direction (X direction), may be smaller than a third width (b1), which is the width of the plurality of third conductive interposer patterns (246) along the first horizontal direction (X direction).

[0063] A semiconductor package (1a) according to exemplary embodiments of the present invention may not include a separate conductive via structure connecting each conductive connection pad (252) and each third conductive interposer pattern (246) to each other. For example, each conductive connection pad (252) and each third conductive interposer pattern (246) may come into contact with each other directly or through a conductive pad seed layer (254) described later, thereby improving the electrical reliability of the semiconductor package (1a).

[0064] According to exemplary embodiments, the upper surface (252U) of a plurality of third conductive connection pads (252) may be located at a level equal to or lower than the upper surface (210U) of the interposer insulating layer (210) in the vertical direction (Z direction). According to exemplary embodiments, the upper surface (252U) of a plurality of third conductive connection pads (252) may be located at a level lower than the upper surface (210U) of the interposer insulating layer (210) by a first length (c1) in the vertical direction (Z direction). According to exemplary embodiments, the first length (c1) may be 0.1 μm to 5 μm.

[0065] According to exemplary embodiments, a plurality of conductive connection pads (252) may each be spaced apart from the inner wall (PHS) of the pad hole (PH). According to exemplary embodiments, the upper surface (252U) and side surface of the conductive connection pad (252) may not be covered by the interposer insulating layer (210). For example, the upper surface (252U) and side surface of the conductive connection pad (252) may be exposed through the pad hole (PH). According to exemplary embodiments, the side surface of the plurality of conductive connection pads (252) may be perpendicular to the upper surface (210U) of the interposer insulating layer (210).

[0066] According to exemplary embodiments, the upper surface (246U) of a plurality of third interposer patterns (246) may be partially exposed through a plurality of pad holes (PH). For example, a portion of the upper surface (246U) of each third interposer pattern (246) that does not overlap in a vertical direction with each conductive connection pad (252) may not be covered by the interposer insulating layer (210) and may be exposed through the pad holes (PH).

[0067] According to exemplary embodiments of the present invention, the interposer insulating layer (210) of the semiconductor package (1a) may not cover the sides of the plurality of uppermost conductive interposer patterns (UIP) and the plurality of conductive connection pads (252) exposed through the plurality of pad holes (PH). Accordingly, cracks in the interposer insulating layer (210) due to expansion or contraction of the plurality of uppermost conductive interposer patterns (UIP) and the plurality of conductive connection pads (252) can be prevented, and the structural and electrical reliability of the semiconductor package (1a) can be improved.

[0068] According to exemplary embodiments, the semiconductor package (1a) may further include a conductive pad seed layer (254) that is interposed between a plurality of conductive connection pads (252) and a plurality of third conductive interposer patterns (246) and covers the lower surface of the plurality of conductive connection pads (252). For example, the plurality of conductive pad seed layers (254) may overlap with the conductive connection pads (252) in a vertical direction (Z direction). For example, the width of the plurality of conductive pad seed layers (254) in a first horizontal direction (X direction) may be equal to the fourth width (b2), which is the width of the plurality of conductive pad seed layers (254) in a first horizontal direction.

[0069] According to exemplary embodiments, a plurality of conductive connection pads (252) may comprise copper (Cu), nickel (Ni), aluminum (Al), silver (Ag), gold (Au), chromium (Cr), titanium (Ti), palladium (Pd), or an alloy thereof. According to exemplary embodiments, a plurality of conductive connection pads (252) may be Ni / Au, in which gold (Au) is laminated on nickel (Ni).

[0070] According to exemplary embodiments, a plurality of pad seed layers may comprise metals such as copper (Cu), titanium (Ti), titanium tungsten (TiW), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), chromium (Cr), aluminum (Al), nickel (Ni), or alloys thereof.

[0071] FIG. 6 is an enlarged view of a portion corresponding to the portion labeled "EX2" in FIG. 1 in a semiconductor package (1b) according to some other embodiments of the present invention. The difference between FIG. 6 and FIG. 3 is whether the semiconductor package (1b) further includes a conductive barrier layer (256).

[0072] Referring to FIG. 6, the semiconductor package (1b) may include a plurality of conductive barrier layers (256) that are interposed between a plurality of conductive connection pads (252) and a plurality of third conductive interposer patterns (246), and cover the upper surface (246U) of each third conductive interposer pattern (246). For example, the width of the plurality of conductive barrier layers (256) along the first horizontal direction (X direction) may be equal to the third width (b1), which is the width of the plurality of third interposer patterns (246) along the first horizontal direction (X direction). According to exemplary embodiments, the plurality of conductive barrier layers (256) may each face the conductive connection pad (252) with a conductive pad seed layer (254) in between. According to exemplary embodiments, a plurality of conductive barrier layers (256) may each overlap a third conductive interposer pattern (246) in a vertical direction (Z direction), and the upper surface (256U) of the plurality of conductive barrier layers (256) may be partially exposed through a plurality of pad holes (PH). In this case, the upper surface (246U) of the plurality of third conductive interposer patterns (246) may not be exposed. Accordingly, the third conductive interposer pattern (246) may be prevented from being deformed or damaged by external contamination or stress.

[0073] According to exemplary embodiments, a plurality of conductive barrier layers (256) may be made of a metal with high corrosion resistance. According to exemplary embodiments, they may include chromium (Cr), aluminum (Al), titanium (Ti), and nickel (Ni).

[0074] According to exemplary embodiments, a first thickness, which is the thickness along the vertical direction (Z direction) of a plurality of conductive barrier layers (256), may be smaller than a second thickness, which is the thickness along the vertical direction (Z direction) of a plurality of third conductive interposer patterns (246). According to exemplary embodiments, the ratio of the second thickness of a plurality of third conductive interposer patterns (246) to the first thickness of a plurality of conductive barrier layers (256) may be 1 to 6, and preferably 1 to 3. Within the above-described range, electrical reliability of the semiconductor package (1b) can be ensured.

[0075] FIG. 7 is a cross-sectional view showing a semiconductor package (2a) according to another embodiment of the technical concept of the present invention, which is a package-on-package type semiconductor package in which an upper package (400U) is stacked on a lower package (400L). FIG. 8 is an enlarged view of the portion labeled "EX2" in FIG. 7.

[0076] In FIG. 7, a lower package (400L) including an interposer substrate (200) is illustrated as corresponding to the semiconductor package (1a) described above with reference to FIG. 1 to 5, but the lower package (400L) may correspond to the semiconductor package (1b) described with reference to FIG. 6. In the semiconductor packages (1a, 1b) described above with reference to FIG. 1 to 6, the base substrate (100) may be referred to as the first base substrate, the semiconductor chip (10) as the first semiconductor chip, the chip pad (16) as the first chip pad, the chip connection member (18) as the first chip connection terminal, the molding layer (174) as the first molding layer, and the external connection terminal (182) as the first external connection terminal.

[0077] Referring to FIGS. 7 and 8, the upper package (400U) may include a second base substrate (300), a second semiconductor chip (20), and a second molding layer (374). According to exemplary embodiments, the second base substrate (300) may be, for example, a printed circuit board. The second base substrate (300) may include a second base insulating layer (312) made of at least one material selected from phenolic resin, epoxy resin, and polyimide. Additionally, the second base substrate (300) may include a plurality of lower substrate pads (314) disposed on the lower surface of the second base insulating layer (312) and a plurality of upper substrate pads (316) disposed on the upper surface of the second base insulating layer (312). Internal wiring configured to electrically connect the plurality of lower substrate pads (314) and the plurality of upper substrate pads (316) may be formed within the second base insulating layer (312).

[0078] According to exemplary embodiments, the semiconductor package (2a) may include a plurality of second external connection terminals (282), each of which is disposed between a lower substrate pad (314) and a conductive connection pad (252) and configured to electrically connect a second base substrate (300) and an interposer substrate (200). According to exemplary embodiments, a plurality of second external connection terminals (282) may each be attached to an upper surface (252U) of a plurality of conductive connection pads (252). For example, a plurality of second external connection terminals (282) may not cover an upper surface (246U) and a side surface (246S) of a plurality of third conductive interposer patterns (246). According to exemplary embodiments, a side surface (246S) of a plurality of third conductive interposer patterns (246) may each be spaced apart from an inner wall (PHS) of a pad hole (PH). According to exemplary embodiments, a plurality of second external connection terminals (282) may be solder balls or bumps.

[0079] According to exemplary embodiments, the second semiconductor chip (20) may be attached to the second base substrate (300). For example, a plurality of second chip pads (26) of the second semiconductor chip (20) may be electrically connected to the upper substrate pad (316) of the second base substrate (300) through a plurality of second chip connecting members (28).

[0080] According to exemplary embodiments, a second molding layer (374) may be interposed on a second base substrate (300) to at least partially surround a second semiconductor chip (20) and a plurality of second chip connecting members (28). According to exemplary embodiments, the second molding layer (374) may include an epoxy-based molding resin or a polyimide-based molding resin, etc. For example, it may be a molding member including an epoxy mold compound (EMC).

[0081] According to exemplary embodiments, the first semiconductor chip (10) and the second semiconductor chip (20) may be semiconductor chips of the same type. In exemplary embodiments, the first semiconductor chip (10) and the second semiconductor chip (20) may be semiconductor chips of different types. For example, when the first semiconductor chip (10) is a logic chip, the second semiconductor chip (20) may be a memory chip. According to exemplary embodiments, the second semiconductor chip (20) may be implemented as a High Bandwidth Memory (HBM) chip. In some embodiments, the upper package (400U) may include a plurality of second semiconductor chips (20). According to exemplary embodiments, the semiconductor package (2a) may be configured such that components such as different types of semiconductor chips and passive components are electrically connected to each other to operate as a single system.

[0082] FIG. 9 is an enlarged view of a portion corresponding to the part labeled "EX3" in FIG. 7 in a package-on-package type semiconductor package (2b) according to some other embodiments of the present invention. The difference between FIG. 9 and FIG. 8 is whether the semiconductor package (2b) further includes a conductive barrier layer (256). Content that overlaps with what was previously explained with reference to FIG. 6 is omitted.

[0083] Referring to FIG. 9, the semiconductor package (2b) may include a plurality of conductive barrier layers (256) each covering the upper surface (246U) of a plurality of third conductive interposer patterns (246). According to exemplary embodiments, a plurality of second external connection terminals (282) may cover a plurality of conductive connection pads (252). In this case, the plurality of second external connection terminals (282) may contact the upper surface (256U) of a plurality of conductive barrier layers (256), and the plurality of third conductive interposer patterns (246) may be spaced apart from the second external connection terminals (282) with the conductive barrier layers (256) in between. Accordingly, contamination or damage to the third conductive interposer patterns (246) by the second external connection terminals (282) may be prevented, and the structural stability and electrical reliability of the semiconductor package (2b) may be improved.

[0084] FIGS. 10a to 10m are cross-sectional views illustrating, in sequence, a method for manufacturing a semiconductor package according to exemplary embodiments of the present invention, and FIGS. 8i to 8l are enlarged cross-sectional views of a portion corresponding to the portion labeled "EX2" in FIG. 1. Hereinafter, with reference to FIGS. 10a to 10m, a method for manufacturing a semiconductor package (1a) described with reference to FIGS. 1 to 5 will be described.

[0085] Referring to FIG. 10a, a release layer (94), an etch stop layer (96), and a first lower insulating layer (102) can be sequentially formed on a carrier substrate (92). According to exemplary embodiments, the carrier substrate (92) may be a glass substrate, but is not limited thereto. For example, the carrier substrate (92) may include a heat-resistant organic polymer material such as polyimide (PI), poly(etheretherketone) (PEEK), poly(ethersulfone) (PES), poly(phenylene sulfide) (PPS), etc. According to exemplary embodiments, it may comprise, but is not limited to, a spin-on hardmask (SOH) which is an amorphous carbon layer (ACL) or a film made of a hydrocarbon compound or a derivative thereof having a relatively high carbon content of about 85% by weight to about 99% by weight based on total weight. For example, the release layer (94) may be made of a PID (Photo Imageable Dielectric). According to exemplary embodiments, the etch stop layer (96) may be made of a material having an etch selectivity ratio with the first lower insulating layer (102). For example, the etch stop layer (96) may be made of a metal such as titanium (Ti).

[0086] According to exemplary embodiments, a first base opening (bo1) can be formed that penetrates the first lower insulating layer (102) and exposes the etch stop layer (96). For example, the first base opening (bo1) can be formed by a photoresist process. According to exemplary embodiments, the shape may have a horizontal cross-section width that narrows as it extends from the upper surface to the lower surface of the first lower insulating layer (102).

[0087] Referring to FIG. 10b, in the result of FIG. 10a, a conductive material film is formed conformally covering the upper surface of the first lower insulating layer (102), the inner surface of the first base opening (bo1), and the bottom surface, and then a mask pattern (not shown) is placed to expose the first base opening (bo1), and a first conductive base pad (124) and a first conductive base pattern (126) can be formed through a plating process in the exposed area. After that, the mask pattern (not shown) is removed, and a portion of the conductive material film is removed to form a first conductive base seed layer (122), thereby forming a first base rewiring structure (120).

[0088] Referring to FIGS. 10c and 10d, in the result of FIG. 10b, a first sub-base insulating layer (112) covering a first base rewiring structure (120) can be formed on a first lower insulating layer (102). Then, a second base opening (bo2) can be formed through a photoresist process to expose a first conductive base pattern (126) by penetrating the first sub-base insulating layer (112).

[0089] After that, a conductive material film can be formed conformally covering the upper surface of the first sub-base insulating layer (112), the inner surface and the bottom surface of the second base opening (bo2). According to exemplary embodiments, a mask pattern (not shown) that exposes the second base opening (bo2) can be placed, and a second conductive base via (134) and a second conductive base pattern (136) can be formed through a plating process using the conductive material film in the exposed area. After that, after removing the mask pattern, a portion of the conductive material film can be removed to form a second conductive base seed layer (132), thereby forming a second base redistribution structure (130) that contacts the first base redistribution structure (120).

[0090] Referring to FIG. 10e, second to fourth sub-base insulating layers (114, 116, 118) and third to fifth base redistribution structures (140, 150, 160) can be formed on the result of FIG. 10d through substantially the same process as described in FIG. 10c and 10d. For example, after forming a second sub-base insulating layer (114) covering a second base redistribution structure (130), a third base redistribution structure (140) in contact with the second base redistribution structure (130) can be formed on the second sub-base insulating layer (114). Then, after forming a third sub-base insulating layer (116) covering the third base redistribution structure (140), a fourth base redistribution structure (150) in contact with the third base redistribution structure (140) can be formed on the third sub-base insulating layer (116). After that, a fourth sub-base insulating layer (118) covering the fourth base redistribution structure (150) can be formed, and then a fifth base redistribution structure (160) in contact with the fourth base redistribution structure (150) can be formed on the fourth sub-base insulating layer (118).

[0091] Referring to FIG. 10f, in the result of FIG. 10e, a plurality of conductive posts (172) can be formed that contact some of the plurality of fifth conductive base patterns (166) of the fifth base rewiring structure (160). For example, the plurality of conductive posts (172) can be formed using a mask that utilizes a photoresist process. After that, a semiconductor chip (10) can be attached to the base substrate (100). For example, a plurality of chip pads (16) and some of the plurality of fifth conductive base patterns (166) can be connected through a plurality of chip connecting members (18). After that, an underfill layer (not shown) can be formed under the semiconductor chip (10) that surrounds the plurality of chip connecting members (18) and some of the plurality of fifth conductive base patterns (166) connected to the plurality of chip connecting members (18). After that, a molding layer (174) is formed that covers the upper surface of the base substrate (100) and surrounds a plurality of conductive posts (172), a semiconductor chip (10), and a plurality of fifth conductive base patterns (166), and a flattening process can be performed.

[0092] Referring to FIG. 10g, after forming a second lower insulating layer (202) on the result of FIG. 10f, a mask pattern (not shown) is placed on the second lower insulating layer (202) to form a first interposer opening (io1) that exposes the upper surface of a plurality of conductive posts (172).

[0093] Referring to FIG. 10h, on the result of FIG. 10g, first and second sub-interposer insulating layers (212, 214) and first to third interposer redistribution structures (220, 230, 240) can be formed through substantially the same process as described in FIG. 10b to 10d. For example, in the result of FIG. 10g, a conductive material layer can be formed conformally covering the upper surface of the second lower insulating layer (202) and the inner wall and bottom surface of the first interposer opening (io1).

[0094] After that, a mask pattern (not shown) that exposes the first interposer opening (io1) can be formed, and a plating process can be performed on the exposed conductive material layer to form a plurality of first conductive interposer pads (224) and a plurality of first conductive interposer patterns (226). After that, the mask pattern (not shown) can be removed, and a portion of the conductive material layer can be removed to form a plurality of first conductive interposer seed layers (222) to form a first interposer redistribution structure (220).

[0095] After that, a first sub-interposer insulating layer (212) covering the first interposer redistribution structure (220) can be formed, and then a second interposer redistribution structure (230) in contact with the first interposer redistribution structure (220) can be formed on the first sub-interposer insulating layer (212). After that, a second sub-interposer insulating layer (214) covering the second interposer redistribution structure (230) can be formed, and then a third interposer redistribution structure (240) in contact with the second interposer redistribution structure can be formed on the second sub-interposer insulating layer (214).

[0096] FIGS. 10i to 10k are enlarged cross-sectional views of a portion corresponding to the portion marked "EX2" in FIG. 1, for explaining a method of manufacturing a semiconductor package (1a) after FIG. 10h.

[0097] Referring together to FIGS. 10h, FIGS. 10i, and FIGS. 10j, in the result of FIGS. 10h and FIGS. 10i, a preliminary pad seed layer (p254) can be formed conformally covering the upper surface of the second sub-interposer insulating layer (214), the upper surface (246U) and side surface (246S) of the third interposer redistribution pattern (246), and the side surface of a portion of the third conductive interposer seed layer (242). Then, a first photomask pattern (MP1) can be formed on the preliminary pad seed layer (p254) to form a plurality of first pad openings (po1) that partially expose the preliminary pad seed layer (p254) on a plurality of third interposer redistribution patterns (246).

[0098] Referring to FIG. 10k, in the result of FIG. 10j, a plurality of conductive connection pads (252) that fill a plurality of first pad openings (po1) can be formed through a plating process. Then, after removing the first photomask pattern (MP1), a portion of the preliminary pad seed layer (p254) can be removed through an etching process to form a plurality of conductive pad seed layers (254). In this case, the upper surface (246U) and the side surface (246S) of a plurality of third interposer redistribution patterns (246) can be exposed, respectively.

[0099] Referring to FIG. 10k and FIG. 10l together, in the result of FIG. 10k, an insulating layer (not shown) can be formed on a second sub-interposer insulating layer (214) that covers a plurality of third interposer redistribution patterns (246) and a plurality of conductive connection pads (252). For example, the upper surface of the insulating layer (not shown) may be located at a higher level than the upper surface (252U) of the plurality of conductive connection pads (252) in the vertical direction (Z direction). Then, a plurality of pad holes (PH) that expose the plurality of conductive connection pads (252) can be formed through a photoresist process. In this case, the upper surface and side surface of the plurality of third interposer redistribution patterns (246) may be exposed within the plurality of pad holes (PH).

[0100] Referring to FIG. 10L and FIG. 1 together, the carrier substrate (92) attached to the lower surface of the release layer (94) in the result of FIG. 10L can be separated. For example, to separate the carrier substrate (92), a laser may be irradiated or heat may be applied to the release layer (94). In some other embodiments, a photolithography process may be performed. According to exemplary embodiments, after the carrier substrate (92) and the release layer (94) are removed, the etch stop layer (96) may be removed to expose the lower surface of a plurality of first conductive base pads (124). For example, during the process of removing the etch stop layer (96), a portion of the plurality of first conductive base seed layers (122) formed between the etch stop layer (96) and the plurality of first conductive base pads (124) may be removed. After that, a plurality of external connection terminals (182) may be attached to the lower surface of the exposed plurality of first conductive base pads (124).

[0101] Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications and changes are possible by those skilled in the art within the technical spirit and scope of the present invention. Explanation of the symbols

[0102] 10: Semiconductor chip, 100: Base substrate, 110: Base insulating layer, 172: Conductive post, 174: Molding layer, 200: Interposer substrate, 210: Interposer insulating layer, 252: Conductive connection pad, UIP: Multiple uppermost conductive interposer patterns, UIRD: Uppermost interposer rewiring structure.

Claims

Claim 1 A semiconductor package comprising: a base substrate; a plurality of interposer redistribution structures sequentially stacked along a vertical direction, each comprising a plurality of conductive interposer patterns and a plurality of conductive interposer vias, and an interposer insulating layer; a semiconductor chip interposed between the base substrate and the interposer substrate and attached to the base substrate; and a plurality of conductive connection pads each disposed on a plurality of uppermost conductive interposer patterns of an uppermost interposer redistribution structure among the plurality of interposer redistribution structures; wherein the interposer insulating layer has a plurality of pad holes that expose a portion of the upper surface of the plurality of conductive connection pads and the upper surface of the plurality of uppermost conductive interposer patterns, the side of the plurality of conductive connection pads is perpendicular to the upper surface of the interposer insulating layer, the side of the plurality of uppermost conductive interposer patterns is perpendicular to the upper surface of the interposer insulating layer, and the inner wall of the plurality of pad holes is inclined with respect to the upper surface of the interposer insulating layer. Claim 2 A semiconductor package according to claim 1, wherein the inner wall of each of the plurality of pad holes is spaced apart from the side of each of the plurality of uppermost conductive interposer patterns. Claim 3 A semiconductor package according to claim 1, characterized in that the width of the plurality of conductive connection pads along the first horizontal direction is smaller than the width of the plurality of uppermost conductive interposer patterns along the first horizontal direction. Claim 4 A semiconductor package according to claim 1, characterized in that the width of the plurality of pad holes along the first horizontal direction is greater than the width of the plurality of uppermost conductive interposer patterns along the first horizontal direction. Claim 5 A semiconductor package according to claim 1, characterized in that the uppermost surface of the interposer insulating layer is located at a level equal to or higher than the upper surface of the plurality of conductive connection pads in the vertical direction. Claim 6 A semiconductor package according to claim 1, wherein the plurality of uppermost conductive interposer patterns include a conductive line pattern extending in a horizontal direction and a conductive pad pattern having an independent island shape in a planar view. Claim 7 A semiconductor package according to claim 1, further comprising a plurality of conductive pad seed layers disposed between the plurality of uppermost conductive interposer patterns and the plurality of conductive connection pads, each covering the lower surface of the plurality of conductive connection pads. Claim 8 A semiconductor package according to claim 1, further comprising a plurality of conductive barrier layers disposed between the plurality of uppermost conductive interposer patterns and the plurality of conductive connection pads, each covering the upper surface of the plurality of uppermost conductive interposer patterns and partially exposed through the plurality of pad holes. Claim 9 A base substrate comprising a plurality of base redistribution structures sequentially stacked along a vertical direction, each including a plurality of conductive base patterns and a plurality of conductive base vias, and a base insulating layer; a semiconductor chip attached to the base substrate through a plurality of chip connecting members; an interposer substrate disposed on the semiconductor chip, comprising a plurality of interposer redistribution structures sequentially stacked along a vertical direction, each including a plurality of conductive interposer patterns and a plurality of conductive interposer vias, and an interposer insulating layer having a plurality of pad holes on its upper surface; a plurality of conductive posts disposed around the semiconductor chip and extending in the vertical direction to connect the base substrate and the interposer substrate; a molding layer surrounding the semiconductor chip and the plurality of conductive posts between the base substrate and the interposer substrate; and a plurality of conductive connection pads disposed respectively on a plurality of uppermost conductive interposer patterns of an uppermost interposer redistribution structure among the plurality of interposer redistribution structures, and disposed within a plurality of pad holes. A semiconductor package comprising: a plurality of conductive pad seed layers each interposed between the plurality of uppermost conductive interposer patterns and the plurality of conductive connection pads, and covering the lower surface of the plurality of conductive connection pads, wherein the side and upper surfaces of each of the plurality of uppermost conductive interposer patterns and the side and upper surfaces of each of the plurality of conductive connection pads are not covered by the interposer insulating layer. Claim 10 A semiconductor package according to claim 9, wherein the plurality of pad holes have a tapered shape in which the horizontal cross-sectional area gradually narrows from the entrance of the pad hole toward the bottom surface of the pad hole, and the plurality of uppermost conductive interposer patterns are disposed on the bottom surface of the pad hole.

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