Display device and tiled dipslay device

Abstract

A display device and a tile-type display device are provided. The display device comprises a substrate including a first surface, a second surface facing the first surface, a first chamfered surface extending from one side of the first surface, a second chamfered surface extending from one side of the second surface, and a first side connecting the first chamfered surface and the second chamfered surface; a pixel including a light-emitting element disposed on the first surface of the substrate and emitting light; a first driving pad disposed at the edge of the first surface of the substrate and electrically connected to the pixel; and side wiring disposed on the first surface of the substrate, the first chamfered surface, the first side, the second chamfered surface, and the second surface, wherein the first driving pad comprises a flat portion connected to the side wiring and a partition portion surrounding three sides of the flat portion.

Description

Technology Field

[0001] The present invention relates to a display device and a tile-type display device. Background Technology

[0002] As the information society develops, the demand for display devices for displaying images is increasing in various forms. Display devices may be flat panel display devices such as Liquid Crystal Displays, Field Emission Displays, and Light Emitting Displays. Light Emitting Displays may include organic light-emitting display devices comprising organic light-emitting diode elements as light-emitting elements, or light-emitting diode display devices comprising inorganic light-emitting diode elements such as LEDs as light-emitting elements.

[0003] A display device includes a display area that operates in pixel units to display an image, and a non-display area (or bezel area) that is arranged around the display area and where wiring for driving the pixels is arranged. Recently, bezel-less display devices are being released to maximize the area of ​​the display area. Accordingly, there is an increasing demand for display devices in which the non-display area is reduced or the non-display area is omitted by forming wiring on the side of the substrate. The problem to be solved

[0004] The problem that the present invention aims to solve is to provide a display device capable of improving image quality defects or electrical short circuits by changing the design of the pad.

[0005] The problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0006] A display device according to one embodiment for solving the above problem comprises: a substrate including a first surface, a second surface facing the first surface, a first chamfered surface extending from one side of the first surface, a second chamfered surface extending from one side of the second surface, and a first side connecting the first chamfered surface and the second chamfered surface; a pixel including a light-emitting element disposed on the first surface of the substrate and emitting light; a first driving pad disposed at the edge of the first surface of the substrate and electrically connected to the pixel; and side wiring disposed on the first surface of the substrate, the first chamfered surface, the first side, the second chamfered surface, and the second surface, wherein the first driving pad comprises a flat portion connected to the side wiring and a partition portion surrounding three sides of the flat portion.

[0007] A display device according to one embodiment for solving the above other problems comprises: a substrate including a first surface, a second surface facing the first surface, a first chamfered surface extending from one side of the first surface, a second chamfered surface extending from one side of the second surface, and a first side connecting the first chamfered surface and the second chamfered surface; a thin film transistor layer including a plurality of thin film transistors disposed on the first surface of the substrate, and a plurality of data metal layers and a plurality of planarization films disposed on the plurality of thin film transistors; a first driving pad spaced apart from the planarization films on the first surface of the substrate; and a side wiring disposed on the first surface of the substrate, the first chamfered surface, the first side, the second chamfered surface, and the second surface, wherein the first driving pad includes a flat portion having a surface parallel to the first surface of the substrate that contacts the side wiring, and a partition portion on which the plurality of data metal layers are stacked.

[0008] A display device according to another embodiment for solving the above other problems comprises: a substrate including a first surface, a second surface facing the first surface, a first chamfered surface extending from one side of the first surface, a second chamfered surface extending from one side of the second surface, and a first side connecting the first chamfered surface and the second chamfered surface; a pixel including a light-emitting element disposed on the first surface of the substrate and emitting light; a first driving pad disposed at the edge of the first surface of the substrate and electrically connected to the pixel; a first inspection pad connected to the first driving pad on the first surface of the substrate; and side wiring connected to the first driving pad on the first surface of the substrate, the first chamfered surface, the first side, the second chamfered surface, and the second surface, wherein the inspection pad comprises a flat portion and a partition portion having an upper surface at a position higher than the upper surface of the flat portion. Effects of the invention

[0009] According to a display device according to one embodiment, a driving pad in contact with a side wiring may include two regions with different heights on their upper surfaces. Accordingly, the driving pad and the side wiring can be stably brought into contact.

[0010] According to one embodiment, a display device may include an inspection pad for inspecting contact failure between a driving pad and a side wiring. By including two regions with different heights on their upper surfaces, the inspection pad can improve the occurrence of an electrical short circuit by an inspection probe.

[0011] The effects according to the embodiments are not limited to those exemplified above, and a wider variety of effects are included in this specification. Brief explanation of the drawing

[0012] FIG. 1 is a perspective view showing the front of a display device according to one embodiment. FIG. 2 is a perspective view showing the back side of a display device according to one embodiment. FIG. 3 is an exemplary drawing showing an example of a pixel of a display device according to one embodiment. FIG. 4 is an exemplary drawing showing another example of a pixel of a display device according to one embodiment. Figure 5 is an example of a cross-sectional structure of a pixel cut along the AA' line of Figure 3. FIG. 6 is a perspective view illustrating the arrangement relationship between pixels and side wiring of a display device according to one embodiment. FIG. 7 is a plan view illustrating the arrangement relationship between pixels and side wiring of a display device according to one embodiment. FIG. 8 is a rear view illustrating the arrangement relationship between pixels and side wiring of a display device according to one embodiment. FIG. 9a is a plan view showing one side edge of a display device according to one embodiment. FIGS. 9b to 9f are plan views of the lamination of a transparent metal material and sub-pads of a first driving pad and a first inspection pad according to one embodiment. FIG. 10 is a perspective view showing one side edge of a display device according to one embodiment. Figure 11 is an example of a cross-sectional structure of a pixel cut along the BB' line of Figure 8. FIG. 12 is an enlarged cross-sectional view of the first driving pad of FIG. 11. FIG. 13 is an example of the cross-sectional structure of the first driving pad cut along the CC' line of FIG. 9a. Figure 14 is an example of the cross-sectional structure of the first inspection pad cut along the DD' line of Figure 9a. Figure 15 shows images of a confinement microscope of the first driving pad. FIGS. 16a to 16c are plan views showing one side edge of a display device according to another embodiment. FIG. 17 is a perspective view showing one side edge of a display device according to another embodiment. Figure 18 is an example of a cross-sectional structure of a pixel cut along the EE' line of Figure 16a. FIG. 19 is a schematic diagram of a side wiring inspection using an inspection pad according to one embodiment. Figure 20 is a conceptual diagram of a side wiring inspection method using an inspection pad. FIG. 21 is a perspective view showing a tile-type display device including a plurality of display devices according to one embodiment. Figure 22 is an enlarged view of area E of Figure 21. FIG. 23 is a cross-sectional view showing an example of a tile-type display device cut along X1-X1' of FIG. 22. FIG. 24 is a block diagram showing a tile-type display device according to one embodiment. Specific details for implementing the invention

[0013] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims.

[0014] When elements or layers are referred to as being "on" another element or layer, this includes cases where another layer or element is interposed directly on or in the middle of another element. Throughout the specification, the same reference numerals refer to the same components. Shapes, sizes, ratios, angles, numbers, etc., disclosed in the drawings for describing embodiments are exemplary and therefore the invention is not limited to the depicted details.

[0015] Although terms such as "first," "second," etc., are used to describe various components, it goes without saying that these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, it goes without saying that the first component mentioned below may also be the second component within the technical scope of the present invention.

[0016] The features of each of the various embodiments of the present invention may be combined or combined with one another, either partially or wholly, and may technically enable various interlocking and operation. Each embodiment may be implemented independently of one another or may be implemented together in an associated relationship.

[0017] Specific embodiments will be described below with reference to the attached drawings.

[0018] FIG. 1 is a perspective view showing the front of a display device according to one embodiment. FIG. 2 is a perspective view showing the back of a display device according to one embodiment.

[0019] FIGS. 1 and 2 show a first direction (DR1), a second direction (DR2), and a third direction (DR3). The first direction (DR1) indicates the horizontal direction of the display device (10), the second direction (DR2) indicates the vertical direction of the display device (10), and the third direction (DR3) indicates the thickness direction of the display device (10). In this case, “left,” “right,” “up,” and “down” indicate the direction when viewing the display device (10) from a plane. For example, “right” indicates one side of the first direction (DR1), “left” indicates the other side of the first direction (DR1), “up” indicates one side of the second direction (DR2), and “down” indicates the other side of the second direction (DR2). Additionally, “up” indicates one side of the third direction (DR3), and “down” indicates the other side of the third direction (DR3). "Upper" may be referred to as one side, front, or first side of the display device (10), and "lower" may be referred to as the other side, back, or second side of the display device (10).

[0020] Referring to FIGS. 1 and 2, a display device (10) according to one embodiment is a device for displaying video or still images, and can be used as a display screen for various products such as televisions, laptops, monitors, billboards, and the Internet of Things (IOT), as well as portable electronic devices such as mobile phones, smartphones, tablet PCs, smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, PMPs (portable multimedia players), navigation systems, and UMPCs (Ultra Mobile PCs).

[0021] The display device (10) may be formed in a planar shape similar to a rectangle. For example, the display device (10) may have a planar shape similar to a rectangle having a long side in the first direction (DR1) and a short side in the second direction (DR2), as shown in FIG. 1. The corner where the long side in the first direction (DR1) and the short side in the second direction (DR2) meet may be formed rounded to have a predetermined curvature or formed at a right angle. The planar shape of the display device (10) is not limited to a rectangle and may be formed similarly to other polygons, circles, or ellipses.

[0022] A display device (10) according to one embodiment may include a substrate (100), a plurality of pixels (PX), a plurality of side wirings (SIL), a circuit board (200), and a display driving circuit (300).

[0023] A substrate (100) can serve as the base of a display device (10). The substrate (100) has a three-dimensional shape similar to a rectangular prism and may include a front surface, a side surface, and a back surface. The substrate (100) may have a shape in which the edges formed by the front surface and the side surfaces, and the edges formed by the back surface and the side surfaces, are bent. For example, the substrate (100) may include chamfered surfaces formed by bending the edges.

[0024] The substrate (100) may include a first surface (FS), a second surface (BS), a plurality of sides, and a plurality of chamfered surfaces.

[0025] The first surface (FS) may be the front surface of the substrate (100). The first surface (FS) may have a rectangular shape having a long side in the first direction (DR1) and a short side in the second direction (DR2).

[0026] The second surface (BS) may be a surface facing the first surface (FS) in the third direction (DR3). The second surface (BS) may be the back surface of the substrate (100). The second surface (BS) may have a rectangular shape having a long side in the first direction (DR1) and a short side in the second direction (DR2).

[0027] A plurality of sides are sides positioned between the first side (FS) and the second side (BS), and may be side surfaces of the substrate (100). The first side (SS1) may be a side extending from the lower side (the other side of the second direction (DR2)) of the first side (FS) among the plurality of sides. The second side (SS2) may be a side extending from the left side (the other side of the first direction (DR1)) of the first side (FS) among the plurality of sides. Meanwhile, among the plurality of sides, a side extending from the upper side (one side of the second direction (DR2)) of the first side (FS) may be referred to as the "third side," and a side extending from the right side (one side of the first direction (DR1)) of the first side (FS) may be referred to as the "fourth side."

[0028] Multiple chamfered surfaces refer to surfaces that are beveled and positioned between a first surface (FS) and multiple sides, and between a second surface (BS) and multiple sides, to prevent chipping defects from occurring in multiple side wires (SIL). Due to the multiple chamfered surfaces, chipping or cracking can be prevented in the multiple side wires (SIL).

[0029] A first chamfered surface (CS1) may be positioned between a first surface (FS) and a first side (SS1). A second chamfered surface (CS2) may be positioned between a first surface (FS) and a second side (SS2). A third chamfered surface may be positioned between a first surface (FS) and a third side. A fourth chamfered surface may be positioned between a first surface (FS) and a fourth side. The interior angle formed by the first surface (FS) and the first chamfered surface (CS1), the interior angle formed by the first surface (FS) and the second chamfered surface (CS2), the interior angle formed by the first surface (FS) and the third chamfered surface, and the interior angle formed by the first surface (FS) and the fourth chamfered surface may each be greater than 90 degrees.

[0030] A fifth chamfered surface (CS5) may be placed between the second surface (BS) and the first side (SS1). A sixth chamfered surface (CS6) may be placed between the second surface (BS) and the second side (SS2). A seventh chamfered surface may be placed between the second surface (BS) and the third side. An eighth chamfered surface may be placed between the second surface (BS) and the fourth side. The interior angle formed by the second surface (BS) and the fifth chamfered surface (CS5), the interior angle formed by the second surface (BS) and the sixth chamfered surface (CS6), the interior angle formed by the second surface (BS) and the seventh chamfered surface, and the interior angle formed by the second surface (BS) and the eighth chamfered surface may each be greater than 90 degrees.

[0031] A plurality of pixels (PX) can be arranged on a first surface (FS) of a substrate (100) to display an image. The plurality of pixels (PX) can be arranged in a matrix form in a first direction (DR1) and a second direction (DR2). A detailed description of the plurality of pixels (PX) will be provided later in conjunction with FIG. 3.

[0032] Each of the multiple side wires (SIL) serves to connect a first driving pad (PD1 in FIG. 7), e.g., a front driving pad, which is placed on a first surface (FS), and a second driving pad (PD2 in FIG. 8), e.g., a back driving pad, which is placed on a second surface (BS). The first driving pads (PD1) can be connected to data wires that are connected to pixels (PX) of the substrate (100).

[0033] A plurality of side wirings (SIL) may be disposed on at least two of a first surface (FS), a second surface (BS), a plurality of chamfered surfaces, and at least one of a plurality of sides. For example, a plurality of side wirings (SIL) may be disposed on a first surface (FS), a second surface (BS), a first chamfered surface (CS1), a fifth chamfered surface (CS5), and a first side (SS1) to connect a first driving pad (PD1) disposed on a first side of the first surface (FS) (the other side of the second direction (DR2) in FIG. 1) and a second driving pad (PD2) disposed on a first side of the second surface (BS) (one side of the second direction (DR2) in FIG. 2).

[0034] In some embodiments, when additionally including first driving pads (PD1) disposed on the second side of the first surface (FS) (the other side of the first direction (DR1) in FIG. 1) and second driving pads (PD2) disposed on the second side of the second surface (BS) (one side of the first direction (DR1) in FIG. 2), a plurality of side wirings (SIL) may be additionally disposed on the first surface (FS), the second surface (BS), the second chamfered surface (CS2), the sixth chamfered surface (CS6), and the second side (SS2).

[0035] Circuit boards (200) may be placed on a second surface (BS) of the substrate (100). Each of the circuit boards (200) may be connected to third driving pads (PD3 in FIG. 8) placed on the second surface (BS) of the substrate (100) using a conductive adhesive member such as an anisotropic conductive film (ACF). As will be described later in FIG. 8, since the third driving pads (PD3) are each electrically connected to the second driving pads (PD2), the circuit boards (200) may be electrically connected to the first driving pads (PD1) through side wiring (SIL). The circuit boards (200) may be flexible printed circuit boards, printed circuit boards, or flexible films such as chip-on-film.

[0036] The display driving circuit (300) can generate data voltages and supply them to the data lines through the circuit board (200), third driving pads (PD3), second driving pads (PD2), a plurality of side lines (SIL), and first driving pads (PD1). The display driving circuit (300) can be formed as an integrated circuit (IC) and attached to the circuit board (200). Alternatively, the display driving circuit (300) can be directly attached to the second side (BS) of the substrate (100) in a chip-on-glass (COG) manner.

[0037] As shown in FIG. 1, by connecting the first driving pads (PD1) placed on the first surface (FS) and the second driving pads (PD2) placed on the second surface (BS) using a plurality of side wires (SIL), the flexible film that is folded along the side of the substrate (100) can be eliminated. As a result, a bezel-less display device can be realized.

[0038] Hereinafter, the structure of a pixel (PX) of a display device (10) according to one embodiment will be described.

[0039] FIG. 3 is an exemplary drawing showing one example of a pixel of a display device according to one embodiment. FIG. 4 is an exemplary drawing showing another example of a pixel of a display device according to one embodiment.

[0040] Referring to FIGS. 3 and FIGS. 4, each of the pixels (PX) may include a plurality of subpixels (SPX1, SPX2, SPX3). FIGS. 2 and FIGS. 3 illustrate that each of the pixels (PX) includes three subpixels (SPX1, SPX2, SPX3), namely, a first subpixel (SPX1), a second subpixel (SPX2), and a third subpixel (SPX3), but the embodiments of the present specification are not limited thereto. Each of the first subpixel (SPX1), the second subpixel (SPX2), and the third subpixel (SPX3) may be connected to any one of the data lines and at least one scan line among the scan lines.

[0041] Each of the first subpixel (SPX1), the second subpixel (SPX2), and the third subpixel (SPX3) may have a planar shape of a rectangle, a square, or a rhombus. For example, each of the first subpixel (SPX1), the second subpixel (SPX2), and the third subpixel (SPX3) may have a planar shape of a rectangle having a short side in the first direction (DR1) and a long side in the second direction (DR2), as shown in FIG. 3. Alternatively, each of the first subpixel (SPX1), the second subpixel (SPX2), and the third subpixel (SPX3) may have a planar shape of a square or a rhombus including sides having the same length in the first direction (DR1) and the second direction (DR2), as shown in FIG. 4.

[0042] As shown in FIG. 3, the first subpixel (SPX1), the second subpixel (SPX2), and the third subpixel (SPX3) may be arranged in a first direction (DR1). Alternatively, either one of the second subpixel (SPX2) and the third subpixel (SPX3) may be arranged with the first subpixel (SPX1) in the first direction (DR1), and the other one with the first subpixel (SPX1) may be arranged in a second direction (DR2). For example, as shown in FIG. 4, the first subpixel (SPX1) and the second subpixel (SPX2) may be arranged in the first direction (DR1), and the first subpixel (SPX1) and the third subpixel (SPX3) may be arranged in the second direction (DR2).

[0043] Alternatively, either one of the first subpixel (SPX1) and the third subpixel (SPX3) and the second subpixel (SPX2) may be arranged in the first direction (DR1), and the other one and the second subpixel (SPX2) may be arranged in the second direction (DR2). Alternatively, either one of the first subpixel (SPX1) and the second subpixel (SPX2) and the third subpixel (SPX3) may be arranged in the first direction (DR1), and the other one and the third subpixel (SPX3) may be arranged in the second direction (DR2).

[0044] A first subpixel (SPX1) may emit a first light, a second subpixel (SPX2) may emit a second light, and a third subpixel (SPX3) may emit a third light. Here, the first light may be light in the red wavelength band, the second light may be light in the green wavelength band, and the third light may be light in the blue wavelength band. The red wavelength band may be a wavelength band of approximately 600 nm to 750 nm, the green wavelength band may be a wavelength band of approximately 480 nm to 560 nm, and the blue wavelength band may be a wavelength band of approximately 370 nm to 460 nm, but the embodiments of this specification are not limited thereto.

[0045] Each of the first subpixel (SPX1), the second subpixel (SPX2), and the third subpixel (SPX3) may include an inorganic light-emitting element having an inorganic semiconductor as a light-emitting element. For example, the inorganic light-emitting element may be a flip-chip type micro LED (Light Emitting Diode), but the embodiments of this specification are not limited thereto.

[0046] As shown in FIGS. 3 and 4, the area of ​​the first subpixel (SPX1), the area of ​​the second subpixel (SPX2), and the area of ​​the third subpixel (SPX3) may be substantially the same, but the embodiments of the present specification are not limited thereto. At least one of the area of ​​the first subpixel (SPX1), the area of ​​the second subpixel (SPX2), and the area of ​​the third subpixel (SPX3) may be different from the other. Alternatively, any two of the area of ​​the first subpixel (SPX1), the area of ​​the second subpixel (SPX2), and the area of ​​the third subpixel (SPX3) may be substantially the same, and the remaining one may be different from the two. Alternatively, the area of ​​the first subpixel (SPX1), the area of ​​the second subpixel (SPX2), and the area of ​​the third subpixel (SPX3) may be different from each other.

[0047] Figure 5 is an example of a cross-sectional structure of a pixel cut along the AA' line of Figure 3.

[0048] Referring to FIG. 5, each of the plurality of sub-pixels (SPX1, SPX2, SPX3) forming a pixel (PX) may include a thin film transistor layer (TFTL) and light-emitting elements (LE) disposed on a substrate (100). The thin film transistor layer (TFTL) may be a layer on which thin film transistors (TFTs) that transmit electrical signals of light-emitting elements (LE) are formed, comprising a plurality of conductive layers and a plurality of insulating layers.

[0049] The thin-film transistor layer (TFTL) includes, as conductive layers, an active layer (ACT), a first gate layer (GTL1), a second gate layer (GTL2), a first data metal layer (DTL1), a second data metal layer (DTL2), a third data metal layer (DTL3), and a fourth data metal layer (DTL4). Additionally, the thin-film transistor layer (TFTL) includes, as insulating layers, a buffer film (BF), a gate insulating film (130), a first interlayer insulating film (141), a second interlayer insulating film (142), a first planarization film (160), a first insulating film (161), a second planarization film (180), a second insulating film (181), a third planarization film (190), and a third insulating film (191). Furthermore, the thin-film transistor layer (TFTL) includes a first protective film (PVX1) formed on the third insulating film (191).

[0050] The substrate (100) may be a base substrate or base member for supporting a display device (10). The substrate (100) may be a rigid substrate made of glass material, but the embodiments of the present specification are not limited thereto. The substrate (100) may be a flexible substrate capable of bending, folding, rolling, etc. In this case, the substrate (100) may include an insulating material such as a polymer resin such as polyimide (PI).

[0051] A buffer film (BF) may be disposed on one side of the substrate (100). The buffer film (BF) may be a film for preventing the penetration of air or moisture. The buffer film (BF) may be composed of a plurality of inorganic films that are alternately stacked. For example, the buffer film (BF) may be formed as a multilayer film in which one or more inorganic films selected from a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately stacked. The buffer film (BF) may be omitted.

[0052] An active layer (ACT) may be disposed on the buffer film (BF). The active layer (ACT) may include a silicon semiconductor such as polycrystalline silicon, single-crystal silicon, low-temperature polycrystalline silicon, and amorphous silicon, or may include an oxide semiconductor.

[0053] The active layer (ACT) may include a channel (TCH), a first electrode (TS), and a second electrode (TD) of the thin-film transistor (TFT). The channel (TCH) of the thin-film transistor (TFT) may be a region that overlaps with the gate electrode (TG) of the thin-film transistor (TFT) in a third direction (DR3), which is the thickness direction of the substrate (100). The first electrode (TS) of the thin-film transistor (TFT) may be disposed on one side of the channel (TCH), and the second electrode (TD) may be disposed on the other side of the channel (TCH). The first electrode (TS) and the second electrode (TD) of the thin-film transistor (TFT) may be regions that do not overlap with the gate electrode (TG) in the third direction (DR3). The first electrode (TS) and the second electrode (TD) of the thin-film transistor (TFT) may be regions that have conductivity by doping ions into a silicon semiconductor or an oxide semiconductor.

[0054] A gate insulating film (130) may be disposed on the active layer (ACT). The gate insulating film (130) may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0055] A first gate layer (GTL1) may be disposed on the gate insulating film (130). The first gate layer (GTL1) may include a gate electrode (TG) of a thin-film transistor (TFT) and a first capacitor electrode (CAE1). The first gate layer (GTL1) may be formed as a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0056] A first interlayer insulating film (141) may be disposed on the first gate layer (GTL1). The first interlayer insulating film (141) may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0057] A second gate layer (GTL2) may be disposed on the first interlayer insulating film (141). The second gate layer (GTL2) may include a second capacitor electrode (CAE2). The second capacitor electrode (CAE2) may form a capacitor (Cst) with the first capacitor electrode (CAE1) by using the first interlayer insulating film (141) as a dielectric. The second gate layer (GTL2) may be formed as a single layer or a multilayer composed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0058] A second interlayer insulating film (142) may be disposed on the second gate layer (GTL2). The second interlayer insulating film (142) may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0059] A first data metal layer (DTL1) may be disposed on the second interlayer insulating film (142). The first data metal layer (DTL1) may include a first connection electrode (CE1). The first connection electrode (CE1) may be connected to the second electrode (TD) of the thin-film transistor (TFT) through a first contact hole (CT1) penetrating the gate insulating film (130), the first interlayer insulating film (141), and the second interlayer insulating film (142). Not limited thereto, the first connection electrode (CE1) may also be connected to the first electrode (TS).

[0060] The first data metal layer (DTL1) may be formed as a single layer or a multilayer composed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. Meanwhile, as will be described later, the first data metal layer (DTL1) may further include a first sub-pad (SPD1 in FIG. 11) and a data wiring (DL in FIG. 11). The data wiring (DL) may be formed integrally with the first sub-pad (SPD1), but the embodiments of this specification are not limited thereto.

[0061] A first planarization film (160) for flattening the step difference caused by the active layer (ACT), the first gate layer (GTL1), the second gate layer (GTL2), and the first data metal layer (DTL1) may be disposed on the first data metal layer (DTL1). The first planarization film (160) may be formed from an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0062] A second data metal layer (DTL2) may be disposed on the first planarization film (160). The second data metal layer (DTL2) may include a second connection electrode (CE2). The second connection electrode (CE2) may be connected to the first connection electrode (CE1) through a second contact hole (CT2) that penetrates the first insulating film (161) and the first planarization film (160). The second data metal layer (DTL2) may be formed as a single layer or a multilayer composed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. Meanwhile, as will be described later, the second data metal layer (DTL2) may further include a second sub-pad (SPD2 in FIG. 11).

[0063] In one embodiment, a first insulating film (161) may be formed between the first planarization film (160) and the second data metal layer (DTL2). The first insulating film (161) may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The first insulating film (161) may be omitted.

[0064] A second planarization film (180) may be disposed on the second data metal layer (DTL2). The second planarization film (180) may be formed from an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0065] A third data metal layer (DTL3) may be disposed on the second planarization film (180). The third data metal layer (DTL3) may include a third connecting electrode (CE3). The third connecting electrode (CE3) may be connected to the second connecting electrode (CE2) through a third contact hole (CT3) that penetrates the second insulating film (181) and the second planarization film (180). The third data metal layer (DTL3) may be formed as a single layer or a multilayer composed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. Meanwhile, the third data metal layer (DTL3) may further include a third sub-pad (SPD3 of FIG. 11).

[0066] In one embodiment, a second insulating film (181) may be formed between the second planarization film (180) and the third data metal layer (DTL3). The second insulating film (181) may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The second insulating film (181) may be omitted.

[0067] A third planarization film (190) may be disposed on the third data metal layer (DTL3). The third planarization film (190) may be formed from an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0068] A fourth data metal layer (DTL4) may be disposed on the third planarization film (190). The fourth data metal layer (DTL4) may include pad electrodes, for example, an anode pad electrode (APD) and a cathode pad electrode (CPD). The anode pad electrode (APD) may be connected to a third connecting electrode (CE3) through a fourth contact hole (CT4) penetrating the third insulating film (191) and the third planarization film (190). The cathode pad electrode (CPD) may be supplied with a low potential voltage. The fourth data metal layer (DTL4) may be formed as a single layer or a multilayer composed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. Meanwhile, the fourth data metal layer (DTL4) may further include a fourth sub-pad (SPD4 of FIG. 11).

[0069] A transparent metal material (TCO) may be disposed on the pad electrodes to increase adhesion between the first contact electrode (CTE1) and the second contact electrode (CTE2) of the light-emitting element (LE). For example, the transparent metal material (TCO) can increase the adhesion between the anode pad electrode (APD) and the first contact electrode (CTE1), and the adhesion between the cathode pad electrode (CPD) and the second contact electrode (CTE2). The transparent metal material (TCO) may be formed from a transparent conductive oxide such as ITO (Indium Tin Oxide) and IZO (Indium Zinc Oxide). Meanwhile, a transparent metal material (TCO) may be disposed on the top of the first driving pad (PD1) of FIG. 11.

[0070] In one embodiment, a third insulating film (191) may be formed between the third planarization film (190) and the fourth data metal layer (DTL4). The third insulating film (191) may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The third insulating film (191) may be omitted.

[0071] A first protective film (PVX1) may be disposed on the anode pad electrode (APD) and the cathode pad electrode (CPD). The first protective film (PVX1) may be disposed to cover the edges of the anode pad electrode (APD) and the cathode pad electrode (CPD). The first protective film (PVX1) may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0072] A light-emitting element (LE) may be disposed on the anode pad electrode (APD) and the cathode pad electrode (CPD) that are not covered by the first protective film (PVX1). The light-emitting element (LE) is exemplified as a flip-chip type micro LED in which the first contact electrode (CTE1) faces the anode pad electrode (APD) and the second contact electrode (CTE2) faces the cathode pad electrode (CPD). The light-emitting element (LE) may include an inorganic material such as GaN. The length of the light-emitting element (LE) in the horizontal direction (i.e., the first direction (DR1) or the second direction (DR2)) and the length of the third direction (DR3) may each be several to several hundred μm.

[0073] A light-emitting element (LE) can be formed by growing on a semiconductor substrate such as a silicon wafer. The light-emitting element (LE) can be transferred directly from the silicon wafer onto the anode pad electrode (APD) and cathode pad electrode (CPD) of the substrate (100). Alternatively, the light-emitting element (LE) can be transferred onto the anode pad electrode (APD) and cathode pad electrode (CPD) of the substrate (100) via an electrostatic method using an electrostatic head or a stamping method using an elastic polymer material such as PDMS or silicon as a transfer substrate.

[0074] The light-emitting element (LE) may be a light-emitting structure comprising a base substrate (SPUB), an n-type semiconductor (NSEM), an active layer (MQW), a p-type semiconductor (PSEM), a first contact electrode (CTE1), and a second contact electrode (CTE2).

[0075] The base substrate (SPUB) may be a sapphire substrate, but the embodiments of this specification are not limited thereto.

[0076] The n-type semiconductor (NSEM) can be placed on one side of the base substrate (SPUB). For example, the n-type semiconductor (NSEM) can be placed on the lower side of the base substrate (SPUB). The n-type semiconductor (NSEM) can be made of GaN doped with n-type conductive dopants such as Si, Ge, Sn, Se, etc.

[0077] The active layer (MQW) may be disposed on a portion of one surface of an n-type semiconductor (NSEM). The active layer (MQW) can form electron-hole pair combinations according to an electrical signal through electrons of the n-type semiconductor (NSEM) and holes of the p-type semiconductor (PSEM), and emit light. The active layer (MQW) may include a material having a single or multiple quantum well structure. When the active layer (MQW) includes a material having a multiple quantum well structure, it may have a structure in which multiple well layers and barrier layers are alternately stacked. In this case, the well layers may be formed of InGaN, and the barrier layers may be formed of GaN or AlGaN, but are not limited thereto. Alternatively, the active layer (MQW) may have a structure in which semiconductor materials with large band gap energy and semiconductor materials with small band gap energy are alternately stacked, or it may include different Group 3 to Group 5 semiconductor materials depending on the wavelength range of the emitted light.

[0078] A p-type semiconductor (PSEM) can be disposed on one side of an active layer (MQW). The p-type semiconductor (PSEM) can be made of GaN doped with p-type conductive dopants such as Mg, Zn, Ca, Ba, etc.

[0079] A first contact electrode (CTE1) is disposed on a p-type semiconductor (PSEM), and a second contact electrode (CTE2) may be disposed on another part of one side of an n-type semiconductor (NSEM). The other part of the side of the n-type semiconductor (NSEM) on which the second contact electrode (CTE2) is disposed may be disposed apart from the part of the side of the n-type semiconductor (NSEM) on which the active layer (MQW) is disposed.

[0080] The first contact electrode (CTE1) and the anode pad electrode (APD) can be bonded to each other through a conductive adhesive member. Alternatively, the first contact electrode (CTE1) and the anode pad electrode (APD) can be bonded to each other through a soldering process.

[0081] The second contact electrode (CTE2) and the cathode pad electrode (CPD) can be bonded to each other through a conductive adhesive member. Alternatively, the second contact electrode (CTE2) and the common pad electrode (CPD) can be bonded to each other through a soldering process.

[0082] FIG. 6 is a perspective view illustrating the arrangement relationship between pixels and side wiring of a display device according to one embodiment. FIG. 7 is a plan view illustrating the arrangement relationship between pixels and side wiring of a display device according to one embodiment. FIG. 8 is a rear view illustrating the arrangement relationship between pixels and side wiring of a display device according to one embodiment.

[0083] Referring to FIGS. 6 to 8, a display device (10) according to one embodiment includes first driving pads (PD1), second driving pads (PD2), third driving pads (PD3), and back connection wiring (BCL). Additionally, the display device (10) includes first inspection pads (IPD1) and second inspection pads (IPD2).

[0084] The first driving pads (PD1) may be front pads disposed on a first surface (FS) corresponding to the front surface of the substrate (100). The first driving pads (PD1) may be disposed on the edge of the first side of the first surface (FS) of the substrate (100). The first driving pads (PD1) may be arranged in a first direction (DR1).

[0085] The second driving pads (PD2) may be back pads disposed on a second surface (BS) corresponding to the back surface of the substrate (100). The second driving pads (PD2) may be disposed on the edge of the first side of the second surface (BS) of the substrate (100). The second driving pads (PD2) may be arranged in a first direction (DR1).

[0086] The third driving pads (PD3) may be back pads placed on the second surface (BS) of the substrate (100). The third driving pads (PD3) may be placed adjacent to the center of the second surface (BS) of the substrate (100) relative to the second driving pads (PD2). The third driving pads (PD3) may be arranged in a first direction (DR1). To connect more third driving pads (PD3) to the circuit board (200), the spacing between adjacent third driving pads (PD3) in the first direction (DR1) may be smaller than the spacing between adjacent second driving pads (PD2) in the first direction (DR1).

[0087] The back connecting wire (BCL) serves to connect the second driving pad (PD2) and the third driving pads (PD3). Since the spacing between adjacent second driving pads (PD2) in the first direction (DR1) and the spacing between adjacent third driving pads (PD3) in the first direction (DR1) are different, the back connecting wire (BCL) may be bent at least once. The back connecting wire (BCL) may be formed integrally with the second driving pad (PD2) and the third driving pad (PD3). The second driving pad (PD2), the third driving pad (PD3), and the back connecting wire (BCL) may be formed as a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0088] The side wiring (SIL) may include a front section (FSP), a first inclined section (CSP1), a side section (SSP), a second inclined section (CSP2), and a back section (BSP).

[0089] The front portion (FSP) corresponds to a portion disposed on the first surface (FS) of the substrate (100). The front portion (FSP) is disposed on the first driving pad (PD1) and can be disposed to completely cover the first driving pad (PD1). The front portion (FSP) can be connected to the first driving pad (PD1).

[0090] The first inclined portion (CSP1) corresponds to a first chamfered portion disposed on the first chamfered surface (CS1) of the substrate (100). The first inclined portion (CSP1) may be disposed between the front portion (FSP) and the side portion (SSP).

[0091] The side portion (SSP) corresponds to a side portion disposed on the first side portion (SS1) of the substrate (100). The side portion (SSP) may be disposed between the first inclined portion (CSP1) and the second inclined portion (CSP2).

[0092] The second bevel portion (CSP2) corresponds to a second bevel portion disposed on the fifth bevel surface (CS5) of the substrate (100). The second bevel portion (CSP2) may be disposed between the side portion (SSP) and the back portion (BSP).

[0093] The back portion (BSP) corresponds to a portion disposed on the second side (BS) of the substrate (100). The back portion (BSP) is disposed on the second driving pad (PD2) and may be disposed to completely cover the second driving pad (PD2). The back portion (BSP) may be connected to the second driving pad (PD2).

[0094] The side wiring (SIL) may include a metal powder containing metal particles such as silver (Ag) and copper (Cu) and a polymer such as acrylic resin or epoxy resin. The metal powder enables the side wiring (SIL) to be conductive, and the polymer may act as a binder to connect the metal particles.

[0095] Specifically, the side wiring (SIL) can be formed by printing a metal paste containing metal particles, monomers, and a solvent onto a substrate (100) using a silicon pad, and then sintering it using a laser. The resistivity of the side wiring (SIL) can be lowered as the monomers react into polymers due to heat from the laser during the sintering process, causing the metal particles to adhere to each other and aggregate. The side wiring (SIL) can be formed in a wrap-around manner around the front surface (FSP), the first sloped surface (CSP1), the side surface (SSP), the second sloped surface (CSP2), and the back surface (BSP).

[0096] The first inspection pads (IPD1) and the second inspection pads (IPD2) may each be inspection pads for inspecting whether there is a disconnection between the first driving pad (PD1) and the side wiring (SIL), and whether there is a disconnection between the second driving pad (PD2) and the side wiring (SIL). Each of the first inspection pads (PD1) may be formed integrally with the first driving pad (PD1). Each of the second inspection pads (PD2) may be formed integrally with the second driving pad (PD20).

[0097] The first inspection pad (IPD1) may be a front inspection pad placed on the first side (FS) of the substrate (100). The first inspection pads (IPD1) may be placed adjacent to the first driving pad (PD1) at the edge of the first side of the first side (FS) of the substrate (100). The first inspection pads (IPD1) may be arranged in a first direction (DR1). Since the first inspection pad (IPD1) is directly connected to the first driving pad (PD1), the first inspection pad (IPD1) can be used to inspect whether the side wiring (SIL) attached to the first driving pad (PD1) is shorted or open.

[0098] The second inspection pad (IPD2) may be a front inspection pad placed on the second side (BS) of the substrate (100). The second inspection pads (IPD2) may be placed adjacent to the second driving pad (PD2) at the edge of the first side of the second side (BS) of the substrate (100). The second inspection pads (IPD2) may be arranged in a first direction (DR1). Since the second inspection pad (IPD2) is directly connected to the second driving pad (PD2), the second inspection pad (IPD2) can be used to inspect whether the side wiring (SIL) attached to the second driving pad (PD2) is shorted or open.

[0099] The method for inspecting side wiring (SIL) through the first inspection pad (IPD1) and the second inspection pad (IPD2) will be described later in FIG. 19.

[0100] Meanwhile, in this embodiment, one pixel (PX) is exemplified as being connected to one first driving pad (PD1) and one first inspection pad (IPD1), but is not limited thereto.

[0101] FIG. 9a is a plan view showing one side edge of a display device according to one embodiment. FIG. 9b to 9f are plan views of the lamination of a transparent metal material and sub-pads of a first driving pad and a first inspection pad according to one embodiment. FIG. 10 is a perspective view showing one side edge of a display device according to one embodiment.

[0102] For convenience of explanation, FIG. 9b illustrates the first sub-pad (SPD1), FIG. 9c illustrates the first sub-pad (SPD1) and the second sub-pad (SPD2). FIG. 9d illustrates the first to third sub-pads (SPD1, SPD2, SPD3), FIG. 9e illustrates the first to fourth sub-pads (SPD1, SPD2, SPD3, SPD4), and FIG. 9f illustrates the first to fourth sub-pads (SPD1, SPD2, SPD3, SPD4) and a transparent metal material (TCO).

[0103] Referring to FIGS. 9a through 9f and FIG. 10, a display device (10_1) according to one embodiment may include a first driving pad (PD1), a side wiring (SIL), and a first inspection pad (IPD1) disposed at the lower edge of a first surface (FS).

[0104] The first driving pad (PD1) may include a flat portion (PD1a) connected to a side wiring (SIL), and a partition portion (PD1b) surrounding three sides of the flat portion (PD1a). The partition portion (PD1b) may have a cage structure surrounding three sides of the flat portion (PD1a). The partition portion (PD1b) may be located between a pixel (PX) and the flat portion (PD1a).

[0105] The flat portion (PD1a) may form the bottom surface of the first driving pad (PD1). The flat portion (PD1a) is an area where the side wiring (SIL) comes into direct contact, and may have a flat surface that is parallel to the first surface (FS) of the substrate (100). The flat portion (PD1a) may be composed of a fourth sub-pad (SPD4) formed by a fourth data metal layer (DTL4) and a transparent metal material (TCO). Additionally, since the flat portion (PD1a) does not include a contact portion connected to the lower wiring, it may have a flat surface without a step. The flat portion (PD1a) may have a rectangular shape in which the length of the first direction (DR1) is longer than the length of the second direction (DR2), but is not limited thereto.

[0106] The partition portion (PD1b) may be formed to surround three sides of the flat portion (PD1a). When printing side wiring (SIL), the partition portion (PD1b) may act as a barrier or enclosure to confine the side wiring (SIL) so that the side wiring (SIL) is not printed beyond the partition portion (PD1b). Accordingly, the side wiring (SIL) may not overlap with the partition portion (PD1b) and may overlap with the flat portion (PD1a), but is not limited thereto.

[0107] The partition section (PD1b) may include a first part (PD1b1) extended in a first direction (DR1), a second part (PD1b2) connected to one end of the first part (PD1b1) and extended in a second direction (DR2), and a third part (PD1b3) connected to the other end of the first part (PD1b1) and extended in a second direction (DR2). The first part (PD1b1), the second part (PD1b2), and the third part (PD1b3) of the partition section (PD1b) may be formed to surround three sides of the flat section (PD1a). The first part (PD1b1) may be positioned between the pixel (PX) and the flat section (PD1a). By acting as a partition positioned between the pixel (PX) and the flat section (PD1a), the first part (PD1b1) can prevent the side wiring (SIL) from overflowing toward the pixel (PX). The partition portion (PD1b) may have a structure in which a plurality of data metal layers, for example, second to fourth sub-pads (SPD2, SPD3, SPD4), are stacked. The partition portion (PD1b) may include a plurality of first contact portions (CNT1) in which a first sub-pad (SPD1) is connected to a lower wiring (BL in FIG. 13).

[0108] The flat portion (PD1a) includes a fourth sub-pad (SPD4), whereas the partition portion (PD1b) may have a step difference between the flat portion (PD1a) and the partition portion (PD1b) as the second to fourth sub-pads (SPD2, SPD3, SPD4) are stacked. The thickness of the partition portion (PD1b) may be greater than the thickness of the flat portion (PD1a). The upper surface of the partition portion (PD1b) may be located at a higher position than the upper surface of the flat portion (PD1a).

[0109] In summary, by forming a step through the flat portion (PD1a) and the bulkhead portion (PD1b) of the first driving pad (PD1), a cage structure that encloses the side wiring (SIL) can be completed.

[0110] Meanwhile, if the side wiring (SIL) is printed to wrap around an area of ​​the first driving pad (PD1) that has a step difference due to a contact portion or a data metal layer without a fence structure, the side wiring (SIL) may lift up due to the step difference and fail to make proper contact with the first driving pad (PD1). If the side wiring (SIL) does not make proper contact with the first driving pad (PD1), the shape of the side wiring (SIL) may be deformed, the length of the side wiring (SIL) may change, and the contact resistance between the side wiring (SIL) and the first driving pad (PD1) may increase.

[0111] In contrast, the first driving pad (PD1) can be formed into a cage structure that encloses the side wiring (SIL) by forming a step through the flat portion (PD1a) and the partition portion (PD1b). In this case, when printing the side wiring (SIL), the side wiring (SIL) may not be positioned beyond the partition portion (PD1b) due to the cage function of the partition portion (PD1b). Accordingly, when the side wiring (SIL) made of silver (Ag) is printed to surround the first driving pad (PD1), it is possible to prevent the shape of the side wiring (SIL) from being deformed or the length of the side wiring (SIL) from changing. In addition, since the contact resistance between the side wiring (SIL) and the first driving pad (PD1) can be stably maintained, the image quality of the display device (10) caused by the contact resistance deviation can be improved.

[0112] The first inspection pad (IPD1) may include a first sub-pad (SPD1) and a transparent metal material (TCO). The first driving pad (PD1) and the first inspection pad (IPD1) may share the first sub-pad (SPD1) and the transparent metal material (TCO).

[0113] FIG. 11 is an example of a cross-sectional structure of a pixel cut along the BB' line of FIG. 8. FIG. 12 is an enlarged cross-sectional view of the first driving pad of FIG. 11. Descriptions that overlap with the embodiment of FIG. 5 are omitted in FIG. 11 and FIG. 12.

[0114] FIG. 11 shows a first driving pad (PD1) and light-emitting elements (LE) of a pixel (PX) placed on the first surface (FS) which is the upper side of the display device (10_1). Also, a second driving pad (PD2) and a third driving pad (PD3) placed on the second surface (BS) which is the lower side of the display device (10_1) are shown.

[0115] First driving pads (PD1) may be disposed on the upper edge of the display device (10_1). When the data wiring (DL) of the display device (10_1) extends in a second direction (DR2), the first driving pads (PD1) may be disposed on the upper and lower edges of the display device (10_1). Alternatively, when the data wiring (DL) of the display device (10_1) extends in a first direction (DR1), the first driving pads (PD1) may be disposed on the left and right edges of the display device (10_1). Meanwhile, the data wiring (DL) is wiring that applies a signal to drive a pixel (PX), and the first driving pad (PD1) is exemplified as being substantially identical to the data wiring (DL), but is not limited thereto. For example, the first driving pad (PD1) may be substantially identical to other wiring that applies a signal to the pixel (PX) or power wiring that applies a power voltage.

[0116] Each of the first driving pads (PD1) can be connected to a data fan-out wiring (DFL) through a first contact portion (CNT1) penetrating the first interlayer insulating film (141) and the second interlayer insulating film (142). The data fan-out wiring (DFL) can be connected to a data wiring (DL) through a contact portion penetrating the first interlayer insulating film (141) and the second interlayer insulating film (142). Although the data fan-out wiring (DFL) has been exemplified as being included in the first gate metal layer (GTL1), embodiments of this specification are not limited thereto. The data fan-out wiring (DFL) may be included in the second gate metal layer (GTL2).

[0117] Additionally, each of the first driving pads (PD1) can be connected to a side wiring (SIL). The side wiring (SIL) can be placed on the first surface (FS), the first chamfered surface (CS1), the first side (SS1), the fifth chamfered surface (CS5), and the second surface (BS) of the substrate (100). The side wiring (SIL) can be connected to a back connection wiring (BCL) on the lower surface of the substrate (100).

[0118] The first driving pads (PD1) may be placed on the second interlayer insulating film (142). The first driving pads (PD1) may be exposed without being covered by the first flattening film (160), the second flattening film (180), and the third flattening film (190). The edges of the first driving pad (PD1) may be covered by the first protective film (PVX1). The first driving pad (PD1) may have an exposed upper surface without being covered by the first protective film (PXV1).

[0119] The first driving pad (PD1) may include first to fourth sub-pads (SPD1, SPD2, SPD3, SPD4) and a transparent metal material (TCO). The first sub-pad (SPD1) may be placed on the second interlayer insulating film (142). The second sub-pad (SPD2) may be placed on the first sub-pad (SPD1) to cover the upper surface and sides of the first sub-pad (SPD1). The third sub-pad (SPD3) may be placed on the second sub-pad (SPD2) to cover the upper surface and sides of the second sub-pad (SPD2). The fourth sub-pad (SPD4) may be placed on the third sub-pad (SPD3) to cover the upper surface and sides of the third sub-pad (SPD3). The transparent metal material (TCO) may be placed on the fourth sub-pad (SPD4) to cover the upper surface and sides of the fourth sub-pad (SPD4). Although the first sub-pad (SPD1) is exemplified as being included in the first data metal layer (DTL1), the second sub-pad (SPD2) as being included in the second data metal layer (DTL2), the third sub-pad (SPD3) as being included in the third data metal layer (DTL3), and the fourth sub-pad (SPD4) as being included in the fourth data metal layer (DTL4), the embodiments of the present specification are not limited thereto.

[0120] The first driving pad (PD1) may include a flat portion (PD1a) and a partition portion (PD1b). In a cross-sectional view, the first driving pad (PD1) has an L-shape, the flat portion (PD1a) may form the bottom surface of the first driving pad (PD1), and the partition portion (PD1b) may form the partition of the first driving pad (PD1). The partition portion (PD1b) may be disposed between the flat portion (PD1a) and the first to third flattening films (160, 180, 190).

[0121] The maximum and minimum heights of the upper surface of the first driving pad (PD1) may differ. For example, the height of the upper surface of the flat portion (PD1a) of the first driving pad (PD1) may be lower than the height of the upper surface of the partition portion (PD1b). The upper surface of the flat portion (PD1a) and the upper surface of the partition portion (PD1b) may have a height difference of a first distance (D1). For example, the first distance (D1) may be 1 μm to 3 μm.

[0122] In one embodiment, only the fourth sub-pad (SPD4) and the transparent metal material (TCO) may be disposed in the flat portion (PD1a). The first to third sub-pads (SPD1, SPD2, SPD3) are not disposed in the flat portion (PD1a), and the fourth sub-pad (SPD4) in the flat portion (PD1a) may not overlap with the first to third sub-pads (SPD1, SPD2, SPD3). Since the flat portion (PD1a) is composed of the fourth sub-pad (SPD4) and the transparent metal material (TCO), there may be no step difference caused by multiple data metal layers. Since the flat portion (PD1a) has a flat surface, the side wiring (SIL) can be stably bonded.

[0123] In the partition section (PD1b), the first to fourth sub-pads (SPD1, SPD2, SPD3, SPD4) and a transparent metal material (TCO) may be laminated. In the partition section (PD1b), the first to fourth sub-pads (SPD1, SPD2, SPD3, SPD4) and the transparent metal material (TCO) may overlap in the thickness direction of the substrate (100). Since a plurality of data metal layers, for example, a first data metal layer (DTL1), a second data metal layer (DTL2), a third data metal layer (DTL3), and a fourth data metal layer (DTL4), are arranged in the partition section (PD1b), a step difference may exist due to the plurality of data metal layers. Referring to FIG. 12, in the partition section (PD1b), a step may exist due to one end of the first sub-pad (SPD1), one end of the second sub-pad (SPD2) and one end of the third sub-pad (SPD3), and a fourth sub-pad (SPD4) covering a portion of the upper surface and side of the first to third sub-pads (SPD1, SPD2, SPD3).

[0124] The fourth sub-pad (SPD4) may be made of the same material and same layer as the anode pad electrode (APD) and the cathode pad electrode (CPD). The fourth sub-pad (SPD4) may not overlap with the first to third sub-pads (SPD1, SPD2, SPD3) in the flat portion (PD1a) and may overlap with the first to third sub-pads (SPD1, SPD2, SPD3) in the partition portion (PD1b).

[0125] A second driving pad (PD2) may be placed at one end of the back connection wiring (BCL), and a third driving pad (PD3) may be placed at the other end of the back connection wiring (BCL). The second driving pad (PD2) and the third driving pad (PD3) may be formed of a transparent conductive oxide such as ITO (Indium Tin Oxide) and IZO (Indium Zinc Oxide).

[0126] The fourth planarization film (170) may be disposed on the back surface of the back surface connecting wiring (BCL) and the substrate (100). The fourth planarization film (170) may be formed from an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0127] The second protective layer (PVX2) may be disposed on the fourth planarization layer (170). The second protective layer (PVX2) may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0128] Side wiring (SIL) may be placed on the first surface (FS), second surface (BS), first side surface (SS1), first chamfered surface (CS1), and fifth chamfered surface (CS5) of the substrate (100). Side wiring (SIL) may be placed on a first driving pad (PD1) located at the edge of the first surface (FS) of the substrate (100) and connected to the first driving pad (PD1). Side wiring (SIL) may be placed on a second driving pad (PD2) located at the edge of the second surface (BS) of the substrate (100) and connected to the second driving pad (PD2). Side wiring (SIL) may come into contact with the first chamfered surface (CS1), first side surface (SS1), and fifth chamfered surface (CS5) of the substrate (100).

[0129] An overcoat layer (OC) may be disposed on a first surface (FS), a first chamfered surface (CS1), a first side surface (SS1), a fifth chamfered surface (CS5), and a second surface (BS) of a substrate (100). The overcoat layer (OC) may be disposed to cover a side wiring (SIL). The overcoat layer (OC) may be formed from an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0130] A circuit board (FPCB) may be placed on the back surface of a substrate (100). The circuit board (FPCB) may be connected to a third driving pad (PD3) that is exposed and not covered by the fourth planarization film (170) and the second protective film (PVX2) using a conductive adhesive member (CAM). The circuit board (FPCB) may be connected to the third driving pad (PD3) through the conductive adhesive member (CAM). The conductive adhesive member (CAM) may be an anisotropic conductive film or an anisotropic conductive paste.

[0131] FIG. 13 is an example of a cross-sectional structure of a first driving pad cut along the CC' line of FIG. 9a. FIG. 13 additionally illustrates a lower wiring (BL) that applies a signal or power voltage to a pixel (PX), and a first contact portion (CNT1) that connects the lower wiring (BL).

[0132] The lower wiring (BL) may overlap with the first driving pad (PD1). Although the lower wiring (BL) is exemplified as being included in the second gate metal layer (GTL2), the embodiments of this specification are not limited thereto. The lower wiring (BL) may be a wiring that applies signals or power voltage for driving the pixel (PX). The first contact portion (CNT1) may penetrate the second interlayer insulating film (142) to expose the lower wiring (BL). The lower wiring (BL) may be connected to the first sub-pad (SPD1) of the first driving pad (PD1) through the first contact portion (CNT1).

[0133] In the display device (10_1) according to the present embodiment, the side wiring (SIL) may be printed to wrap around a flat portion (PD1a) where no step exists, and may not be positioned beyond the partition portion (PD1b). Accordingly, when the side wiring (SIL) made of silver (Ag) is printed to wrap around the first driving pad (PD1), it is possible to prevent the shape of the side wiring (SIL) from being deformed or the length of the side wiring (SIL) from changing.

[0134] FIG. 14 is an example of a cross-sectional structure of a first inspection pad cut along the DD' line of FIG. 9a. FIG. 14 shows a first inspection pad (IPD1) and a second inspection pad (IPD2).

[0135] The first inspection pad (IPD1) may include a first sub-pad (SPD1) and a transparent metal material (TCO).

[0136] The first sub-pad (SPD1) may be placed on the second interlayer insulating film (142). The first sub-pad (SPD1) may be exposed without being covered by the first flattening film (160), the second flattening film (180), and the third flattening film (190). The edges of the first sub-pad (SPD1) may be covered by the first protective film (PVX1). The first sub-pad (SPD1) may have an exposed upper surface without being covered by the first protective film (PXV1).

[0137] The first sub-pad (SPD1) may be included in the first data metal layer (DTL1). A transparent metal material (TCO) may be disposed on the first sub-pad (SPD1).

[0138] The second inspection pad (IPD2) is disposed on the second surface (BS) of the substrate (100) and may include an electrode layer made of the same layer and the same material as the back connection wiring (BCL). The second inspection pad (IPD2) may include a transparent conductive oxide, such as ITO (Indium Tin Oxide) and IZO (Indium Zinc Oxide), disposed on the electrode side.

[0139] Figure 15 shows images of a confinement microscope of the first driving pad.

[0140] Referring to FIG. 15, the shape of the first driving pad (PD1) can be determined by analyzing a confocal microscope image. The first driving pad (PD1) may have a flat portion in contact with the side wiring (SIL) and a portion facing the pixel (PX) side, which may have a cage structure.

[0141] Hereinafter, a display device (10_2) according to another embodiment will be described.

[0142] FIGS. 16a to 16c are plan views showing one side edge of a display device according to another embodiment. FIG. 17 is a perspective view showing one side edge of a display device according to another embodiment.

[0143] Referring to FIG. 16a and FIG. 17, a display device (10_2) according to the present embodiment may include a first driving pad (PD1_2), a side wiring (SIL), a first inspection pad (IPD1_2), and a first connection line (CL1) disposed at the lower edge of a first surface (FS).

[0144] The first driving pad (PD1_2) may have a stacked structure in which the first to fourth sub-pads (SPD1, SPD2, SPD3, SPD4 of FIG. 11) are stacked. However, the present embodiment is not limited thereto, and the first driving pad (PD1_2) may have a cage structure including a flat section and a partition section as in the previous embodiment.

[0145] The first inspection pad (IPD1_2) differs from the first inspection pad (IPD1 of FIG. 11) of a display device (10_1 of FIG. 11) made of a single data metal layer in that it includes a flat portion (IPD1a) and a partition portion (IPD1b) surrounding three sides of the flat portion (IPD1a). The partition portion (IPD1b) may have a cage structure surrounding three sides of the flat portion (IPD1a). The partition portion (IPD1b) may be located between the pixel (PX) and the flat portion (IPD1a).

[0146] The flat portion (IPD1a) may form the bottom surface of the first driving pad (PD1). The flat portion (IPD1a) may have a flat surface, that is, a surface parallel to the first surface (FS) of the substrate (100). The flat portion (IPD1a) is formed by the fourth data metal layer (DTL4) and may not have a step by including a single data metal layer. Additionally, the flat portion (IPD1a) may not have a step and may have a flat surface, as it does not include a contact portion connected to the lower wiring. The flat portion (IPD1a) may have a rectangular shape in which the length of the first direction (DR1) is longer than the length of the second direction (DR2), but is not limited thereto.

[0147] The partition portion (IPD1b) may be formed to surround three sides of the flat portion (IPD1a). The partition portion (IPD1b) may serve as a partition or a fence to prevent the inspection probe (400 in FIG. 20) from advancing toward the upper side (one side of the second direction (DR2)) of the display device (10) where pixels (PX) are arranged, even if the inspection probe (400) touches the first inspection pad (PD1_2).

[0148] The bulkhead portion (IPD1b) may include a first portion extending in a first direction (DR1), a second portion connected to one end of the first portion and extending in a second direction (DR2), and a third portion connected to the other end of the first portion and extending in a second direction (DR2). The first, second, and third portions of the bulkhead portion (IPD1b) may be formed to surround three sides of the flat portion (IPD1a).

[0149] The partition portion (IPD1b) of the first inspection pad (IPD1_2) may be thicker than the flat portion (IPD1a). Since the partition portion (IPD1b) includes a plurality of data metal layers and the flat portion (IPD1a) includes a single data metal layer, the upper surface of the partition portion (IPD1b) may be located at a higher position than the upper surface of the flat portion (IPD1a).

[0150] The first inspection pad (IPD1_2) can be connected to the first driving pad (PD1_2) through the first connection line (CL1).

[0151] Referring to FIG. 16b, the display device (10_2) according to the present embodiment may include a first driving pad (PD1_3), a side wiring (SIL), and a first inspection pad (IPD1_2) disposed at the lower edge of the first surface (FS). The embodiment of FIG. 16b differs from the embodiment of FIG. 16a in that the first connection line (CL1) is omitted and the first driving pad (PD1_3) and the first inspection pad (IPD1_2) are formed integrally. That is, in the case of FIG. 16b, as in FIG. 9a to 9f, the first driving pad (PD1_3) and the first inspection pad (IPD1_2) may share a transparent metal material (TCO) with the first sub-pad (SPD1).

[0152] Referring to FIG. 16c, the display device (10_2) according to the present embodiment may include a first driving pad (PD1), a side wiring (SIL), and a first inspection pad (IPD1_2) disposed at the lower edge of the first surface (FS). The embodiment of FIG. 16c differs from the embodiment of FIG. 16a in that the first connection line (CL1) is omitted, the first driving pad (PD1) and the first inspection pad (IPD1_2) are formed integrally, and the first driving pad (PD1) includes a flat portion (PD1a) and a partition portion (PD1b). That is, in the case of FIG. 16c, both the first driving pad (PD1) and the first inspection pad (IPD1_2) may have a cage structure.

[0153] FIG. 18 is an example of a cross-sectional structure of a pixel cut along the EE' line of FIG. 16a. FIG. 18 shows a first inspection pad (IPD1_2) placed on the first surface (FS) which is the upper side of the display device (10_2) and a second inspection pad (IPD2) placed on the second surface (BS) which is the lower side of the display device (10_2).

[0154] A first inspection pad (IPD1_2) may be disposed on the upper edge of the display device (10_2). The first inspection pad (IPD1_2) may be disposed on the second interlayer insulating film (142). The first inspection pads (IPD1_2) may be exposed without being covered by the first flattening film (160), the second flattening film (180), and the third flattening film (190). The edge of the first inspection pad (IPD1_2) may be covered by the first protective film (PVX1). The first inspection pad (IPD1_2) may have an exposed upper surface without being covered by the first protective film (PXV1).

[0155] The first inspection pad (IPD1_2) may include first to fourth sub-pads (ISPD1~ISPD4) and a transparent metal material (TCO). The first sub-pad (ISPD1) may be placed on the second interlayer insulating film (142). The second sub-pad (ISPD2) may be placed on the first sub-pad (ISPD1) to cover the upper surface and sides of the first sub-pad (ISPD1). The third sub-pad (ISPD3) may be placed on the second sub-pad (ISPD2) to cover the upper surface and sides of the second sub-pad (ISPD2). The fourth sub-pad (ISPD4) may be placed on the third sub-pad (ISPD3) to cover the upper surface and sides of the third sub-pad (ISPD3). The transparent metal material (TCO) may be placed on the fourth sub-pad (ISPD4) to cover the upper surface and sides of the fourth sub-pad (ISPD4). Although the first sub-pad (ISPD1) is exemplified as being included in the first data metal layer (DTL1), the second sub-pad (ISPD2) as being included in the second data metal layer (DTL2), the third sub-pad (ISPD3) as being included in the third data metal layer (DTL3), and the fourth sub-pad (ISPD4) as being included in the fourth data metal layer (DTL4), the embodiments of the present specification are not limited thereto.

[0156] The first inspection pad (IPD1_2) may include a flat portion (IPD1a) and a partition portion (IPD1b). In a cross-sectional view, the first inspection pad (IPD1_2) has an L-shape, the flat portion (IPD1a) may form the bottom surface of the first inspection pad (IPD1_2), and the partition portion (IPD1b) may form the partition of the first inspection pad (IPD1_2). The partition portion (IPD1b) may be disposed between the flat portion (IPD1a) and the first to third flattening films (160, 180, 190).

[0157] The maximum and minimum heights of the upper surface of the first inspection pad (IPD1_2) may differ. For example, the height of the upper surface of the flat portion (IPD1a) of the first inspection pad (IPD1_2) may be lower than the height of the upper surface of the partition portion (IPD1b). The upper surface of the flat portion (IPD1a) and the upper surface of the partition portion (IPD1b) may have a height difference of 1 μm to 3 μm, but are not limited thereto.

[0158] In one embodiment, only the fourth sub-pad (ISPD4) and the transparent metal material (TCO) may be disposed in the flat portion (IPD1a). The first to third sub-pads (ISPD1, ISPD2, ISPD3) are not disposed in the flat portion (IPD1a), and the fourth sub-pad (ISPD4) may not overlap with the first to third sub-pads (ISPD1, ISPD2, ISPD3) in the flat portion (IPD1a). Since the flat portion (IPD1a) is composed of the fourth sub-pad (ISPD4) and the transparent metal material (TCO), there may be no step difference caused by multiple data metal layers.

[0159] In the partition section (IPD1b), the first to fourth sub-pads (ISPD1~ISPD4) and a transparent metal material (TCO) may be laminated. In the partition section (IPD1b), the first to fourth sub-pads (ISPD1~ISPD4) and the transparent metal material (TCO) may overlap in the thickness direction of the substrate (100). Since a plurality of sub-pads (ISPD1~ISPD4) are arranged in the partition section (IPD1b), a step difference may exist due to the plurality of sub-pads (ISPD1~ISPD4).

[0160] The second inspection pad (IPD2) is placed on the second surface (BS) of the substrate (100) and can be formed of a transparent conductive oxide such as ITO (Indium Tin Oxide) and IZO (Indium Zinc Oxide).

[0161] Meanwhile, a plurality of power lines are illustrated in FIG. 18. The plurality of power lines may be lines that apply a power voltage to drive a pixel (PX). A first power line (VDL) may be included in a second data metal layer (DTL2). The first power line (VDL) may be placed on a first planarization film (160). The first power line (VDL) may be a line that applies a high potential voltage to the pixel (PX). A second power line (VSL) may be placed on a second planarization film (180). The second power line (VSL) may be a line that applies a low potential voltage to the pixel (PX).

[0162] Hereinafter, with reference to FIGS. 19 and 20, a side wiring inspection process using the first inspection pad (IPD1_2) will be described.

[0163] FIG. 19 is a schematic diagram of a side wiring inspection using an inspection pad according to one embodiment. FIG. 20 is a conceptual diagram of a side wiring inspection method using an inspection pad.

[0164] First, a first driving pad (PD1_2), a second driving pad (PD2), a first inspection pad (IPD1_2), and a second inspection pad (IPD2) are formed on a substrate (100) (S110).

[0165] Then, a side wiring (SIL) connecting the first driving pad (PD1_2) and the second driving pad (PD2) is printed (S120). The side wiring (SIL) can be formed by printing a metal paste containing metal particles, monomers, and a solvent onto a substrate (100) using a silicon pad, and then sintering it using a laser. The side wiring (SIL) can be formed in a wrap-around manner around the front portion (FSP), the first inclined portion (CSP1), the side portion (SSP), the second inclined portion (CSP2), and the back portion (BSP).

[0166] Next, the inspection probe (400) is brought into contact with the first inspection pad (IPD1_2) and the second inspection pad (IPD2) to inspect for poor contact between the first driving pad (PD1_2) and the side wiring (SIL) and poor contact between the second driving pad (PD2) and the side wiring (SIL) (S130).

[0167] Referring to FIGS. 17 and 20, after contacting a test probe (400) (or pogo pin) to a first test pad (IPD1_2) connected to a first driving pad (PD1_2) and a second test pad (IPD2) connected to a second driving pad (PD2), the resistance can be measured to check whether the side wiring (SIL) is shorted or open.

[0168] In this case, when the inspection probe (400) rubs the inspection pad, if the inspection pad is formed flat, the inspection probe (400) may pass over the inspection pad and enter the interior of the first to third flattening films (160, 180, 190). For example, if the inspection probe (400) is pushed on the inspection pad and enters the interior of the second flattening film (180), a short circuit may occur between the first power line (VDL) and the second power line (VSL).

[0169] According to the present embodiment, the first inspection pad (IPD1_2) may have a height difference on its upper surface through a flat portion (IPD1a) and a partition portion (IPD1b). Since the upper surface of the partition portion (IPD1b), which is closer to the center of the substrate (100), is higher than the upper surface of the flat portion (IPD1a) located at the edge of the substrate (100), the inspection probe (400) may not be able to pass over the partition portion (IPD1b) even if it is pushed on the first inspection pad (IPD1_2). As the bezel area of ​​the display device (10_2) is minimized, the length of the second direction (DR2) of the first inspection pad (IPD1_2) and the second inspection pad (IPD2) may be reduced. Even if the length of the second direction (DR2) of the first inspection pad (IPD1_2) and the second inspection pad (IPD2) is reduced, the inspection probe (400) may not proceed toward the first to third flattening films (160, 180, 190) by getting caught on the partition (IPD1b) of the first inspection pad (IPD1_2). Accordingly, as the inspection probe (400) is pushed on the inspection pad and enters the interior of the second flattening film (180), a short circuit between the first power line (VDL) and the second power line (VSL) can be prevented.

[0170] FIG. 21 is a perspective view showing a tile-type display device including a plurality of display devices according to one embodiment.

[0171] Referring to FIG. 21, the tile-type display device (TD) may include a plurality of display devices (11, 12, 13, 14) and a joint (SM). For example, the tile-type display device (TD) may include a first display device (11), a second display device (12), a third display device (13), and a fourth display device (14).

[0172] Multiple display devices (11, 12, 13, 14) may be arranged in a grid form. Multiple display devices (11, 12, 13, 14) may be arranged in a matrix form with M (M is a positive integer) rows and N (N is a positive integer) columns. For example, the first display device (11) and the second display device (12) may be adjacent to each other in the first direction (DR1). The first display device (11) and the third display device (13) may be adjacent to each other in the second direction (DR2). The third display device (13) and the fourth display device (14) may be adjacent to each other in the first direction (DR1). The second display device (12) and the fourth display device (14) may be adjacent to each other in the second direction (DR2).

[0173] However, the number and arrangement of multiple display devices (11, 12, 13, 14) in the tile-type display device (TD) are not limited to those shown in FIG. 25. The number and arrangement of display devices (11, 12, 13, 14) in the tile-type display device (TD) may be determined according to the size of each of the display device (10) and the tile-type display device (TD) and the shape of the tile-type display device (TD).

[0174] Multiple display devices (11, 12, 13, 14) may have the same size as each other, but are not limited thereto. For example, multiple display devices (11, 12, 13, 14) may have different sizes.

[0175] Each of the plurality of display devices (11, 12, 13, 14) may have a rectangular shape including a long side and a short side. The plurality of display devices (11, 12, 13, 14) may be arranged such that their long sides or short sides are connected to one another. Some or all of the plurality of display devices (11, 12, 13, 14) may be placed at the edge of the tile-type display device (TD) and may form one side of the tile-type display device (TD). At least one of the plurality of display devices (11, 12, 13, 14) may be placed at at least one corner of the tile-type display device (TD) and may form two adjacent sides of the tile-type display device (TD). At least one of the plurality of display devices (11, 12, 13, 14) may be surrounded by other display devices.

[0176] Each of the plurality of display devices (11, 12, 13, 14) may be substantially identical to the display device (10) described in conjunction with FIG. 1. Therefore, a description of each of the plurality of display devices (11, 12, 13, 14) is omitted.

[0177] The joint (SM) may include a connecting member or an adhesive member. In this case, a plurality of display devices (11, 12, 13, 14) may be connected to each other through the connecting member or adhesive member of the joint (SM). The joint (SM) may be positioned between the first display device (11) and the second display device (12), between the first display device (11) and the third display device (13), between the second display device (12) and the fourth display device (14), and between the third display device (13) and the fourth display device (14).

[0178] Figure 22 is an enlarged view of area E of Figure 21.

[0179] Referring to FIG. 22, the joint (SM) may have a planar shape of a column cross, a cross, or an addition sign in the central area of ​​a tiled display device (TD) where the first display device (11), the second display device (12), the third display device (13), and the fourth display device (14) are adjacent. The joint (SM) may be positioned between the first display device (11) and the second display device (12), between the first display device (11) and the third display device (13), between the second display device (12) and the fourth display device (14), and between the third display device (13) and the fourth display device (14).

[0180] The first display device (11) may include first pixels (PX1) arranged in a matrix form in a first direction (DR1) and a second direction (DR2) to display an image. The second display device (12) may include second pixels (PX2) arranged in a matrix form in a first direction (DR1) and a second direction (DR2) to display an image. The third display device (13) may include third pixels (PX3) arranged in a matrix form in a first direction (DR1) and a second direction (DR2) to display an image. The fourth display device (14) may include fourth pixels (PX4) arranged in a matrix form in a first direction (DR1) and a second direction (DR2) to display an image.

[0181] The minimum distance between adjacent first pixels (PX1) in the first direction (DR1) is defined as the first horizontal separation distance (GH1), and the minimum distance between adjacent second pixels (PX2) in the first direction (DR1) can be defined as the second horizontal separation distance (GH2). The first horizontal separation distance (GH1) and the second horizontal separation distance (GH2) may be substantially the same.

[0182] A joint (SM) may be disposed between adjacent first pixel (PX1) and second pixel (PX2) in the first direction (DR1). The minimum distance (GA12) between adjacent first pixel (PX1) and second pixel (PX2) in the first direction (DR1) may be the sum of the minimum distance (GHS1) between the first pixel (PX1) and the joint (SM) in the first direction (DR1), the minimum distance (GHS2) between the second pixel (PX2) and the joint (SM) in the first direction (DR1), and the width (GSM1) of the joint (SM) in the first direction (DR1).

[0183] In the first direction (DR1), the minimum distance (GA12), the first horizontal separation distance (GH1), and the second horizontal separation distance (GH2) between adjacent first pixels (PX1) and second pixels (PX2) may be substantially the same. To this end, in the first direction (DR1), the minimum distance (GHS1) between the first pixel (PX1) and the joint (SM) may be smaller than the first horizontal separation distance (GH1), and the minimum distance (GHS2) between the second pixel (PX2) and the joint (SM) in the first direction (DR1) may be smaller than the second horizontal separation distance (GH2). Additionally, in the first direction (DR1), the width (GSM1) of the joint (SM) may be smaller than the first horizontal separation distance (GH1) or the second horizontal separation distance (GH2).

[0184] The minimum distance between adjacent third pixels (PX3) in the first direction (DR1) is defined as the third horizontal separation distance (GH3), and the minimum distance between adjacent fourth pixels (PX4) in the first direction (DR1) can be defined as the fourth horizontal separation distance (GH4). The third horizontal separation distance (GH3) and the fourth horizontal separation distance (GH4) may be substantially the same.

[0185] A joint (SM) may be disposed between adjacent third pixels (PX3) and fourth pixels (PX4) in the first direction (DR1). The minimum distance (GA34) between adjacent third pixels (PX3) and fourth pixels (PX4) in the first direction (DR1) may be the sum of the minimum distance (GHS3) between the third pixel (PX3) and the joint (SM) in the first direction (DR1), the minimum distance (GHS4) between the fourth pixel (PX4) and the joint (SM) in the first direction (DR1), and the width (GSM1) of the joint (SM) in the first direction (DR1).

[0186] In the first direction (DR1), the minimum distance (GA34), the third horizontal separation distance (GH3), and the fourth horizontal separation distance (GH4) between adjacent third pixels (PX3) and fourth pixels (PX4) may be substantially the same. To this end, in the first direction (DR1), the minimum distance (GHS3) between the third pixel (PX3) and the joint (SM) may be smaller than the third horizontal separation distance (GH3), and the minimum distance (GHS4) between the fourth pixel (PX4) and the joint (SM) in the first direction (DR1) may be smaller than the fourth horizontal separation distance (GH4). Additionally, in the first direction (DR1), the width (GSM1) of the joint (SM) may be smaller than the third horizontal separation distance (GH3) or the fourth horizontal separation distance (GH4).

[0187] The minimum distance between neighboring first pixels (PX1) in the second direction (DR2) is defined as the first vertical separation distance (GV1), and the minimum distance between neighboring third pixels (PX3) in the second direction (DR2) can be defined as the third vertical separation distance (GV3). The first vertical separation distance (GV1) and the third vertical separation distance (GV3) may be substantially the same.

[0188] A joint (SM) may be disposed between adjacent first pixel (PX1) and third pixel (PX3) in the second direction (DR2). The minimum distance (GA13) between adjacent first pixel (PX1) and third pixel (PX3) in the second direction (DR2) may be the sum of the minimum distance (GVS1) between the first pixel (PX1) and the joint (SM) in the second direction (DR2), the minimum distance (GVS3) between the third pixel (PX3) and the joint (SM) in the second direction (DR2), and the width (GSM2) of the joint (SM) in the second direction (DR2).

[0189] In the second direction (DR2), the minimum distance (GA13), the first vertical separation distance (GV1), and the third vertical separation distance (GV3) between adjacent first pixel (PX1) and third pixel (PX3) may be substantially the same. To this end, in the second direction (DR2), the minimum distance (GVS1) between the first pixel (PX1) and the joint (SM) may be smaller than the first vertical separation distance (GV1), and the minimum distance (GVS3) between the third pixel (PX3) and the joint (SM) in the second direction (DR2) may be smaller than the third vertical separation distance (GV3). Additionally, in the second direction (DR2), the width (GSM2) of the joint (SM) may be smaller than the first vertical separation distance (GV1) or the third vertical separation distance (GV3).

[0190] The minimum distance between adjacent second pixels (PX2) in the second direction (DR2) is defined as the second vertical separation distance (GV2), and the minimum distance between adjacent fourth pixels (PX4) in the second direction (DR2) can be defined as the fourth vertical separation distance (GV4). The second vertical separation distance (GV2) and the fourth vertical separation distance (GV4) may be substantially the same.

[0191] A joint (SM) may be disposed between adjacent second pixels (PX2) and fourth pixels (PX4) in the second direction (DR2). The minimum distance (GA24) between adjacent second pixels (PX2) and fourth pixels (PX4) in the second direction (DR2) may be the sum of the minimum distance (GVS2) between the second pixel (PX2) and the joint (SM) in the second direction (DR2), the minimum distance (GVS4) between the fourth pixel (PX4) and the joint (SM) in the second direction (DR2), and the distance (GSM4) of the joint (SM) in the second direction (DR2).

[0192] In the second direction (DR2), the minimum distance (GA24), the second vertical separation distance (GV2), and the fourth vertical separation distance (GV4) between adjacent second pixels (PX2) and fourth pixels (PX4) may be substantially the same. To this end, in the second direction (DR2), the minimum distance (GVS2) between the second pixel (PX2) and the joint (SM) may be smaller than the second vertical separation distance (GV2), and the minimum distance (GVS4) between the fourth pixel (PX4) and the joint (SM) in the second direction (DR2) may be smaller than the fourth vertical separation distance (GV4). Additionally, in the second direction (DR2), the width (GSM2) of the joint (SM) may be smaller than the second vertical separation distance (GV2) or the fourth vertical separation distance (GV4).

[0193] As shown in FIG. 22, in order to prevent a seam (SM) from being visible between images displayed by a plurality of display devices (11, 12, 13, 14), the minimum distance between pixels of adjacent display devices may be substantially the same as the minimum distance between pixels of each display device.

[0194] FIG. 23 is a cross-sectional view showing an example of a tile-type display device cut along X1-X1' of FIG. 22.

[0195] Referring to FIG. 23, the first display device (11) includes a first display module (DPM1) and a first front cover (COV1). The second display device (12) includes a second display module (DPM2) and a second front cover (COV2).

[0196] Each of the first display module (DPM1) and the second display module (DPM2) includes a substrate (100), a thin-film transistor layer (TFTL), and a light-emitting element layer. The thin-film transistor layer (TFTL) and the light-emitting element layer have already been described in detail in FIG. 11. In FIG. 23, descriptions that overlap with previous embodiments are omitted.

[0197] The first front cover (COV1) may protrude beyond the substrate (100) in the first direction (DR1) and the second direction (DR2). Therefore, the distance (GSUB) between the substrate (100) of the first display device (11) and the substrate (100) of the second display device (12) may be greater than the distance (GCOV) between the first front cover (COV1) and the second front cover (COV2).

[0198] Each of the first front cover (COV1) and the second front cover (COV2) may include an adhesive member (51), a light transmittance control layer (52) disposed on the adhesive member (51), and an anti-glare layer (53) disposed on the light transmittance control layer (52).

[0199] The adhesive member (51) of the first front cover (COV1) serves to attach the first front cover (COV1) to the light-emitting element layer of the first display module (DPM1). The adhesive member (51) of the second front cover (COV2) serves to attach the second front cover (COV2) to the light-emitting element layer of the second display module (DPM2). The adhesive member (51) may be a transparent adhesive member capable of transmitting light. For example, the adhesive member (51) may be an optically clear adhesive film or an optically clear resin.

[0200] The anti-glare layer (53) can be designed to diffusely reflect external light to prevent the external light from being reflected as is and to prevent a decrease in the visibility of the image. Accordingly, due to the anti-glare layer (53), the contrast ratio of the image displayed by the first display device (11) and the second display device (12) can be increased.

[0201] The light transmittance control layer (52) can be designed to reduce the transmittance of external light or light reflected from the first display module (DPM1) and the second display module (DPM2). As a result, the gap (GSUB) between the substrate (100) of the first display module (DPM1) and the substrate (100) of the second display module (DPM2) can be prevented from being visible from the outside.

[0202] The anti-glare layer (53) may be implemented as a polarizing plate, and the light transmittance control layer (52) may be implemented as a phase delay layer, but the embodiments of the present specification are not limited thereto.

[0203] Meanwhile, an example of a tile-type display device cut along X2-X2', X3-X3', and X4-X4' in FIG. 26 is substantially the same as an example of a tile-type display device cut along X1-X1' described in conjunction with FIG. 27, so a description thereof is omitted.

[0204] FIG. 24 is a block diagram showing a tile-type display device according to one embodiment.

[0205] In FIG. 24, the first display device (11) and the host system (HOST) are illustrated for convenience of explanation.

[0206] Referring to FIG. 24, a tile-type display device (TD) according to one embodiment may include a host system (HOST), a broadcast tuning unit (210), a signal processing unit (220), a display unit (230), a speaker (240), a user input unit (250), an HDD (260), a network communication unit (270), a UI generation unit (280), and a control unit (290).

[0207] The host system (HOST) can be implemented as any one of a television system, home theater system, set-top box, navigation system, DVD player, Blu-ray player, personal computer (PC), mobile phone system, or tablet.

[0208] User commands can be input to the host system in various formats. For example, the host system may receive commands via user touch input. Alternatively, the host system may receive user commands via keyboard input or button input from a remote controller.

[0209] The host system (HOST) can receive original video data (ODATA) corresponding to the original image from an external source. The host system (HOST) can divide the original video data (ODATA) according to the number of display devices. For example, the host system (HOST) can divide the original video data (ODATA) into first video data (DATA1) corresponding to the first image, second video data (DATA2) corresponding to the second image, third video data (DATA3) corresponding to the third image, and fourth video data (DATA4) corresponding to the fourth image, corresponding to the first display device (11), second display device (12), third display device (13), and fourth display device (14). The host system (HOST) can transmit the first video data (DATA1) to the first display device (11), transmit the second video data (DATA2) to the second display device (12), transmit the third video data (DATA3) to the third display device (13), and transmit the fourth video data (DATA4) to the fourth display device (14).

[0210] The first display device (11) can display a first image according to the first video data (DATA1), the second display device (12) can display a second image according to the second video data (DATA2), the third display device (13) can display a third image according to the third video data (DATA3), and the fourth display device (14) can display a fourth image according to the fourth video data (DATA4). Accordingly, the user can view an original image in which the first to fourth images displayed on the first to fourth display devices (11, 12, 13, 14) are combined.

[0211] The first display device (11) may include a broadcast tuning unit (210), a signal processing unit (220), a display unit (230), a speaker (240), a user input unit (250), an HDD (260), a network communication unit (270), a UI generation unit (280), and a control unit (290).

[0212] The broadcast tuning unit (210) can receive a broadcast signal of a corresponding channel by tuning a predetermined channel frequency according to the control of the control unit (290). The broadcast tuning unit (210) may include a channel detection module and an RF demodulation module.

[0213] The broadcast signal demodulated by the broadcast tuning unit (210) is processed by the signal processing unit (220) and output to the display unit (230) and speaker (240). Here, the signal processing unit (220) may include a demultiplexer (221), a video decoder (222), a video processing unit (223), an audio decoder (224), and an additional data processing unit (225).

[0214] The demultiplexer (221) separates the demodulated broadcast signal into a video signal, an audio signal, and additional data. The separated video signal, audio signal, and additional data are restored by a video decoder (222), an audio decoder (224), and an additional data processing unit (225), respectively. At this time, the video decoder (222), the audio decoder (224), and the additional data processing unit (225) restore the data into a decoding format corresponding to the encoding format used during broadcast signal transmission.

[0215] Meanwhile, the decoded video signal is converted by the video processing unit (223) to match the vertical frequency, resolution, aspect ratio, etc., that match the output specifications of the display unit (230), and the decoded audio signal is output to the speaker (240).

[0216] The display unit (230) is a device for displaying images and includes the pixel (PX) and panel driving unit described above.

[0217] The user input unit (250) can receive signals transmitted by the host system (HOST). The user input unit (250) can be configured to receive data regarding the selection and operation of the channel transmitted by the host system (HOST), as well as commands regarding communication with other display devices (DV2~DV4), which the user selects and inputs.

[0218] The storage unit (260) stores various software programs including OS programs, recorded broadcast programs, videos, photos, and other data, and may be made of a storage medium such as a hard disk or non-volatile memory.

[0219] The network communication unit (270) is for short-range communication with a host system (HOST) and other display devices (DV2~DV4), and can be implemented as a communication module including an antenna pattern capable of implementing mobile communication, data communication, Bluetooth, RF, Ethernet, etc.

[0220] The network communication unit (270) may transmit and receive wireless signals with at least one of a base station, an external terminal, and a server on a mobile communication network built according to technical standards or communication methods for mobile communication (e.g., GSM (Global System for Mobile communication), CDMA (Code Division Multi Access), CDMA2000 (Code Division Multi Access 2000), EV-DO (Enhanced Voice-Data Optimized or Enhanced Voice-Data Only), WCDMA (Wideband CDMA), HSDPA (High Speed ​​Downlink Packet Access), HSUPA (High Speed ​​Uplink Packet Access), LTE (Long Term Evolution), LTE-A (Long Term Evolution-Advanced), 5G, etc.) through an antenna pattern described later.

[0221] The network communication unit (270) may transmit and receive wireless signals in a communication network according to wireless internet technologies through an antenna pattern described later. Examples of wireless internet technologies include WLAN (Wireless LAN), Wi-Fi (Wireless-Fidelity), Wi-Fi (Wireless Fidelity) Direct, DLNA (Digital Living Network Alliance), WiBro (Wireless Broadband), WiMAX (World Interoperability for Microwave Access), HSDPA (High Speed ​​Downlink Packet Access), HSUPA (High Speed ​​Uplink Packet Access), LTE (Long Term Evolution), LTE-A (Long Term Evolution-Advanced), etc., and the antenna pattern transmits and receives data according to at least one wireless internet technology within a range that includes internet technologies not listed above.

[0222] The UI generation unit (280) generates a UI menu for communication with the host system (HOST) and other display devices (DV2~DV4), and can be implemented by algorithm code and OSD IC. The UI menu for communication with the host system (HOST) and other display devices (DV2~DV4) may be a menu for specifying the corresponding digital TV to communicate with and selecting the desired function.

[0223] The control unit (290) is responsible for overall control of the first display device (11) and for communication control of the host system (HOST) and the second to fourth display devices (12, 13, 14), and can be implemented by an MCU (Micro Controller Unit) in which the corresponding algorithm code for control is stored and the stored algorithm code is executed.

[0224] The control unit (290) controls the transmission of corresponding control commands and data to the host system (HOST) and the second to fourth display devices (12, 13, 14) via the network communication unit (270) according to the input and selection of the user input unit (250). Of course, when a predetermined control command and data are input from the host system (HOST) and the second to fourth display devices (12, 13, 14), an operation is performed according to the corresponding control command.

[0225] Meanwhile, since the block diagram of the second display device (12), the block diagram of the third display device (13), and the block diagram of the fourth display device (14) are substantially identical to the block diagram of the first display device (11), the description thereof is omitted.

[0226] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing the technical concept or essential features thereof. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0227] 10: Display device LE: Light-emitting element 100: Substrate PD1: First driving pad IPD1: First test pad CL1: First connection line PD1a, PD1b: Flat section IPD1a, IPD1b: Flat section SIL: Side wiring

Claims

Claim 1 A substrate comprising: a first surface, a second surface facing the first surface, a first chamfered surface extending from one side of the first surface, a second chamfered surface extending from one side of the second surface, and a first side connecting the first chamfered surface and the second chamfered surface; a pixel comprising a light-emitting element disposed on the first surface of the substrate and emitting light; a first driving pad disposed at the edge of the first surface of the substrate and electrically connected to the pixel; and a side wiring disposed on the first surface of the substrate, the first chamfered surface, the first side, the second chamfered surface, and the second surface, wherein the first driving pad comprises a flat portion connected to the side wiring; and a partition portion surrounding three sides of the flat portion, and the flat portion and the partition portion are electrically connected to each other. Claim 2 In claim 1, a display device in which the thickness of the flat portion is thinner than the thickness of the partition portion. Claim 3 A display device according to claim 1, wherein the upper surface of the flat portion is positioned lower than the upper surface of the bulkhead portion. Claim 4 A display device according to claim 3, further comprising a lower wiring that supplies a power voltage or signal to the pixel on a first surface of the substrate, wherein, in the partition portion, the lower sub-pad among a plurality of sub-pads of the first driving pad includes a first contact portion connected to the lower wiring. Claim 5 A display device according to claim 1, wherein the side wiring overlaps the flat portion and the thickness direction of the substrate, and does not overlap the partition portion and the thickness direction of the substrate. Claim 6 In claim 1, the bulkhead comprises: a first portion extending in a first direction; a second portion extending in a second direction intersecting the first direction and connected to one end of the first portion; and a third portion extending in the second direction and connected to the other end of the first portion, wherein the first portion, the second portion, and the third portion surround three sides of the flat portion. Claim 7 In claim 6, the first part of the above partition is a display device located between the pixel and the flat part. Claim 8 A display device according to claim 1, comprising pad electrodes disposed on a first surface of the substrate and connected to the light-emitting element, wherein the flat portion of the first driving pad is made of the same layer and the same material as the pad electrode. Claim 9 A substrate comprising: a first surface, a second surface facing the first surface, a first chamfered surface extending from one side of the first surface, a second chamfered surface extending from one side of the second surface, and a first side connecting the first chamfered surface and the second chamfered surface; a thin film transistor layer comprising a plurality of thin film transistors disposed on the first surface of the substrate, and a plurality of data metal layers and a plurality of planarization films disposed on the plurality of thin film transistors; a first driving pad spaced apart from the planarization films on the first surface of the substrate; and a side wiring disposed on the first surface of the substrate, the first chamfered surface, the first side, the second chamfered surface, and the second surface, wherein the first driving pad comprises a flat portion having a surface parallel to the first surface of the substrate and in contact with the side wiring; and a partition portion on which the plurality of data metal layers are stacked. Claim 10 In claim 9, the plurality of data metal layers comprises: a lower data metal layer including a first sub-pad and a first connection electrode connected to the thin-film transistor; and an upper data metal layer disposed on the lower data metal layer and including a second sub-pad and an anode pad electrode connected to the first connection electrode, and further comprises a first protective film exposing a portion of the upper surface of the second sub-pad and the anode pad electrode, wherein the second sub-pad overlaps with the first sub-pad at the partition portion and does not overlap with the first sub-pad at the flat portion. Claim 11 In claim 10, the second sub-pad is a display device that contacts a portion of the upper surface and the side of the first sub-pad. Claim 12 In claim 9, the partition wall is a display device disposed between the flat section and the flattening films. Claim 13 In claim 9, the upper surface of the bulkhead portion is higher than the upper surface of the flat portion. Claim 14 A display device according to claim 9, further comprising a lower wiring disposed between a first surface of the substrate and a first driving pad, wherein the partition of the first driving pad includes a first contact portion that exposes the upper surface of the lower wiring. Claim 15 A display device comprising: a first surface, a second surface facing the first surface, a first chamfered surface extending from one side of the first surface, a second chamfered surface extending from one side of the second surface, and a first side connecting the first chamfered surface and the second chamfered surface; a pixel disposed on the first surface of the substrate and comprising a light-emitting element that emits light; a first driving pad disposed at the edge of the first surface of the substrate and electrically connected to the pixel; a first inspection pad on the first surface of the substrate and connected to the first driving pad; and side wiring connected to the first driving pad on the first surface of the substrate, the first chamfered surface, the first side, the second chamfered surface, and the second surface, wherein the inspection pad comprises a flat portion and a partition portion having an upper surface at a position higher than the upper surface of the flat portion. Claim 16 A display device according to claim 15, further comprising a first connection line connecting the first driving pad and the inspection pad, wherein the first connection line is disposed on the same layer as the gate electrode of a thin-film transistor. Claim 17 In claim 15, the inspection pad has an L-shape in cross-sectional view, the flat portion forms the bottom surface of the inspection pad, and the partition portion forms the partition of the inspection pad. Claim 18 In claim 15, the upper surface of the partition portion is 1 μm to 3 μm higher than the upper surface of the flat portion. Claim 19 A display device according to claim 15, further comprising: a plurality of thin-film transistors disposed on a first surface of the substrate; a lower data metal layer disposed on the thin-film transistors; an upper data metal layer disposed on the lower data metal layer; and a first protective film exposing a portion of the upper surface of the upper data metal layer, wherein the upper data metal layer overlaps with the lower data metal layer at the partition portion and does not overlap with the lower data metal layer at the flat portion. Claim 20 A tile-type display device comprising a plurality of display devices and a joint disposed between the display devices, wherein among the plurality of display devices, the first display device comprises: a substrate including a first surface, a second surface facing the first surface, a first chamfered surface extending from one side of the first surface, a second chamfered surface extending from one side of the second surface, and a first side connecting the first chamfered surface and the second chamfered surface; a pixel comprising a light-emitting element disposed on the first surface of the substrate and emitting light; a first driving pad disposed at the edge of the first surface of the substrate and electrically connected to the pixel; a first inspection pad connected to the first driving pad on the first surface of the substrate; and side wiring connected to the first driving pad on the first surface of the substrate, the first chamfered surface, the first side, the second chamfered surface, and the second surface, wherein the inspection pad comprises a flat portion and a partition portion having an upper surface at a position higher than the upper surface of the flat portion. Claim 21 In claim 20, the light-emitting element is a tile-type display device that is a flip-chip type micro light-emitting diode element. Claim 22 In claim 20, the substrate is a tile-type display device made of glass. Claim 23 In claim 20, the first display device further comprises a connecting wire disposed on a second surface of the substrate; and a flexible film connected to the connecting wire through a conductive adhesive member, and the side wiring connected to the connecting wire is a tile-type display device. Claim 24 In claim 20, the plurality of display devices are tile-type display devices arranged in a matrix form with M rows and N columns.

Images