Method, apparatus and program for detecting anomalies in process equipment by integrating multiple anomaly detection techniques

Abstract

A method for detecting anomalies in process equipment by integrating a plurality of anomaly detection techniques according to various embodiments of the present invention is disclosed. The method may include: a step of collecting Bin data, Parametric Characteristic Monitoring (PCM) data, a plurality of wafer maps, and Fault Detection and Classification (FDC) data collected from process equipment; a step of extracting a predetermined number of specific Bin data in order of highest defect rate based on the Bin data; a step of extracting specific components in which specification defects or control defects have occurred based on the PCM data; a step of classifying patterns of each of the plurality of wafer maps based on the plurality of wafer maps and extracting at least one specific defective device corresponding to the classified pattern; a step of extracting whether there is a defect regarding abnormal operation of the process equipment based on the FDC data; and a step of integrating and providing results extracted based on the Bin data, the PCM data, the plurality of wafer maps, and the FDC data, respectively.

Description

Technology Field

[0001] The present invention relates to a method, apparatus, and program for detecting abnormalities in process equipment by integrating a plurality of abnormality detection techniques, and specifically, to a method, apparatus, and program for detecting abnormalities in process equipment by utilizing Bin data, PCM data, a plurality of wafer maps, and FDC data. Background Technology

[0003] Generally, factories that have established a mass production system divide the manufacturing process into multiple stages to increase mass production efficiency, and operate by running automated equipment suitable for each stage of the divided process.

[0004] In the case of automated equipment, abnormal process execution may occur during the repetitive performance of the same process due to errors in the equipment itself or the influence of the surrounding environment. In a manufacturing process system where each process is continuous and organically linked, a malfunction in the equipment of a specific process can lead to defects in the entire process and the products. Accordingly, periodically detecting abnormalities in the process equipment operating for each stage is crucial for the maintenance of the factory's production system.

[0005] Detecting abnormalities in process equipment can be achieved by skilled operators frequently checking the equipment's operating status through various sensor process data. However, even highly skilled operators face limitations in accurately detecting abnormal data (or non-normal data) by reviewing the vast amount of real-time sensor data, and the detection process can be time-consuming. Furthermore, as factory equipment becomes more complex due to the introduction of FA systems, the knowledge and know-how required of operators increase significantly; consequently, it may be difficult for inexperienced workers to identify the causes of abnormal conditions.

[0006] Furthermore, detecting abnormalities in process equipment can be accomplished by checking the output of the equipment. For example, in the case of semiconductor process equipment, abnormalities can be determined by detecting and analyzing defects in the resulting wafers. Specifically, abnormalities in the process equipment are determined by identifying defect patterns in the wafer map (image) and tracing the causes of the defects. Identifying the presence of four well-known types of defect patterns—circular, recessed, scratch, and localized—is a critical task that enables timely corrective action on the process equipment to improve productivity. However, there are various lesser-known defect patterns, and the failure to take timely corrective action against them leads to a problem where the productivity of the process equipment decreases.

[0007] In the case of wafer maps containing defect patterns of unknown types, humans must classify them one by one visually, which can be difficult. For example, there may be subtle differences in the defect patterns classified due to individual differences in opinion among workers. Additionally, there may be differences in classification time between skilled and inexperienced workers.

[0008] Meanwhile, as sensor process data—whether temporary or permanently stored in databases—accumulates, research is being conducted on the automated processing of monitoring data for industrial equipment related to various fields. In particular, as the amount of information that can be processed increases due to advancements in computer technology, artificial intelligence is evolving rapidly; accordingly, research and development are underway on technologies that utilize AI to detect data anomalies.

[0009] Therefore, there is a demand in the industry for technology to detect abnormalities in process equipment. In this regard, Korean Registered Patent Publication No. 10-2265461 discloses a system for detecting abnormal data in a manufacturing process. The problem to be solved

[0011] The present invention has been devised in response to the aforementioned background technology and aims to provide a method for detecting abnormalities in process equipment by integrating a plurality of abnormality detection techniques.

[0012] The technical problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0014] According to an embodiment of the present invention for solving the problem described above, a method for detecting anomalies in process equipment by integrating a plurality of anomaly detection techniques is disclosed. The method may include: a step of collecting Bin data, Parametric Characteristic Monitoring (PCM) data, a plurality of wafer maps, and Fault Detection and Classification (FDC) data collected from process equipment; a step of extracting a predetermined number of specific Bin data in order of highest defect rate based on the Bin data; a step of extracting specific components in which specification defects or control defects have occurred based on the PCM data; a step of classifying patterns of each of the plurality of wafer maps based on the plurality of wafer maps and extracting at least one specific defective device corresponding to the classified pattern; a step of extracting whether there is a defect regarding abnormal operation of the process equipment based on the FDC data; and a step of integrating and providing results extracted based on the Bin data, the PCM data, the plurality of wafer maps, and the FDC data, respectively.

[0015] In an alternative embodiment, the step of extracting a predetermined number of specific Bin data in order of highest defect rate based on the Bin data may include: a step of recognizing the defect rate of each of a plurality of wafer map groups and individual wafer maps based on the Bin data; and a step of extracting the predetermined number of specific Bin data in order of highest defect rate.

[0016] In an alternative embodiment, the method may further include: a step of collecting a plurality of wafer maps produced in the past and containing defective wafer maps in production order, prior to recognizing a plurality of wafer map groups and a defect rate for each of the individual wafer maps based on the Bin data; a step of grouping the plurality of wafer maps into a predetermined unit to create a plurality of wafer map groups; and a step of classifying the patterns of the plurality of wafer maps included in each of the plurality of wafer map groups.

[0017] In an alternative embodiment, the step of extracting a specific device with a specification defect or control defect based on the PCM data may include: a step of recognizing individual devices included in a wafer map corresponding to a preset number of Bin data based on the PCM data; and a step of obtaining test results for the individual devices and extracting a specific device with a specification defect or control defect based on the test results.

[0018] In an alternative embodiment, the step of classifying the pattern of each of the plurality of wafer maps based on the plurality of wafer maps and extracting at least one specific defective device corresponding to the classified pattern may include: a step of recognizing a specific wafer map group containing at least a predetermined number of wafer maps classified as predefined defective patterns; a step of recognizing first process information related to the production of a wafer map included in the specific wafer map group; a step of collecting second process information related to the production of other wafer maps corresponding to the first process information; and a step of extracting a defective device that causes defects in the wafer map based on the first process information and the second process information.

[0019] In an alternative embodiment, the method may further include: a step of collecting a plurality of wafer maps produced in the past and containing defective wafer maps in production order before recognizing the specific wafer map group; a step of creating a plurality of wafer map groups by grouping the plurality of wafer maps into a preset unit; a step of classifying the patterns of the plurality of wafer maps included in each of the plurality of wafer map groups using a pre-trained classification model to classify the plurality of wafer maps; a step of obtaining a classification result for each of the plurality of wafer maps from the classification model; a step of recognizing a specific classification result in which the score value corresponding to the classified pattern in the classification result is lower than a preset value or the classified pattern is determined to be an error; a step of obtaining a normal pattern corresponding to the specific classification result; and a step of retraining a classifier included in the classification model by labeling the wafer map corresponding to the specific classification result and the normal pattern.

[0020] In an alternative embodiment, the step of extracting whether there is a defect regarding abnormal operation of the process equipment based on the FDC data may include: acquiring process sensor data and prior knowledge data corresponding to the process sensor data; generating reconstructed process sensor data corresponding to the process sensor data using a deep learning model; calculating a reconstruction rate error based on the process sensor data and the reconstructed process sensor data; and detecting abnormal operation based on a comparison of the reconstruction rate error and a reference threshold.

[0021] In an alternative embodiment, the step of providing an integrated result extracted based on each of the Bin data, the PCM data, the plurality of wafer maps, and the FDC data may include: a step of comparing a pre-set condition corresponding to each of the Bin data, the PCM data, the plurality of wafer maps, and the FDC data with a result extracted based on each of the Bin data, the PCM data, the plurality of wafer maps, and the FDC data; and a step of providing visualized information corresponding to each of the Bin data, the PCM data, the plurality of wafer maps, and the FDC data based on the result of the comparison.

[0022] According to one embodiment of the present invention for solving the above-described problem, an apparatus is disclosed. The apparatus comprises: a memory for storing one or more instructions; and a processor for executing the one or more instructions stored in the memory, and the processor can perform the above-described methods by executing the one or more instructions.

[0023] According to one embodiment of the present invention for solving the above-described problem, a computer program stored on a recording medium readable by a computer is disclosed, which is combined with a computer, which is hardware, to perform the above-described methods.

[0024] Other specific details of the present invention are included in the detailed description and drawings. Effects of the invention

[0026] The present invention can improve wafer quality costs through integrated analysis and increase work efficiency related to process equipment anomaly detection by integrating a plurality of anomaly detection techniques to detect anomalies in process equipment.

[0027] The effects of the present invention are not limited to those mentioned above, and other unmentioned effects will be clearly understood by a person skilled in the art from the description below. Brief explanation of the drawing

[0029] FIG. 1 is a drawing illustrating a system according to one embodiment of the present invention. FIG. 2 is a hardware configuration diagram of a computing device according to one embodiment of the present invention. FIGS. 3 to 5 are flowcharts illustrating an example of a method for detecting defective equipment based on a wafer map pattern according to an embodiment of the present invention. FIGS. 6 and 7 are drawings illustrating an example of a method for training a model to classify a wafer map pattern and a wafer map pattern according to an embodiment of the present invention. FIGS. 8 and 9 are flowcharts illustrating an example of a method for training a model to classify patterns of a wafer map according to various embodiments of the present invention. FIGS. 10 and FIGS. 11 are flowcharts illustrating an example of a method for detecting anomalies in process equipment by integrating a plurality of anomaly detection techniques according to an embodiment of the present invention. FIG. 12 is a schematic diagram showing one or more network functions related to one embodiment of the present invention. Specific details for implementing the invention

[0030] Various embodiments are now described with reference to the drawings. In this specification, various descriptions are provided to facilitate an understanding of the invention. However, it is evident that these embodiments can be practiced without such specific descriptions.

[0031] As used herein, terms such as “component,” “module,” “system,” etc. refer to computer-related entities, hardware, firmware, software, combinations of software and hardware, or executions of software. For example, a component may be, but is not limited to, a procedure executed on a processor, a processor, an object, an execution thread, a program, and / or a computer. For example, both an application executed on a computing device and the computing device itself may be a component. One or more components may reside within a processor and / or an execution thread. A component may be localized within a single computer. A component may be distributed among two or more computers. Additionally, these components may be executed from various computer-readable media having various data structures stored therein. Components may communicate through local and / or remote processes, for example, according to signals having one or more data packets (e.g., data from a component interacting with another component in a local system or distributed system, and / or data transmitted through signals to other systems and networks such as the Internet).

[0032] Furthermore, the term "or" is intended to mean an implicit "or" rather than an exclusive "or." That is, unless otherwise specified or evident from the context, "X uses A or B" is intended to mean one of the natural implicit substitutions. In other words, if X uses A; if X uses B; or if X uses both A and B, "X uses A or B" may apply to any of these cases. Additionally, the term "and / or" as used herein should be understood to refer to and include all possible combinations of one or more of the enumerated related items.

[0033] Additionally, the terms “comprising” and / or “comprising” should be understood to mean that such features and / or components are present. However, the terms “comprising” and / or “comprising” should be understood not to exclude the presence or addition of one or more other features, components and / or groups thereof. Furthermore, unless otherwise specified or clearly evident from the context to indicate a singular form, the singular in this specification and claims should generally be interpreted to mean “one or more.”

[0034] Those skilled in the art should recognize that the various exemplary logical blocks, configurations, modules, circuits, means, logics, and algorithmic steps described in connection with the embodiments disclosed herein may be implemented in electronic hardware, computer software, or a combination of both. To clearly exemplify the interchangeability of hardware and software, various exemplary components, blocks, configurations, means, logics, modules, circuits, and steps have been generally described above in terms of their functionality. Whether such functionality is implemented in hardware or software depends on the specific application and design constraints imposed on the overall system. Skilled technicians may implement the described functionality in various ways for each specific application. However, such decisions regarding implementation should not be interpreted as moving out of the scope of the invention.

[0035] The description of the presented embodiments is provided to enable those skilled in the art to use or practice the present invention. Various modifications to these embodiments will be apparent to those skilled in the art. The general principles defined herein may be applied to other embodiments without departing from the scope of the present invention. Thus, the present invention is not limited to the embodiments presented herein. The present invention should be interpreted in the broadest possible scope consistent with the principles and novel features presented herein.

[0036] In this specification, the term "computer" refers to any type of hardware device comprising at least one processor, and may be understood to include software configurations operating on said hardware device according to the embodiments. For example, the term "computer" may be understood to include smartphones, tablet PCs, desktops, laptops, and user clients and applications running on each of these devices, but is not limited thereto.

[0037] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings.

[0038] Each step described in this specification is described as being performed by a computer, but the subject of each step is not limited thereto, and depending on the embodiment, at least some of each step may be performed on different devices.

[0040] FIG. 1 is a drawing illustrating a system according to one embodiment of the present invention.

[0041] Referring to FIG. 1, a system according to one embodiment of the present invention may include a computing device (100), a user terminal (200), and an external server (300). The system illustrated in FIG. 1 is according to one embodiment, and its components are not limited to the embodiment illustrated in FIG. 1 and may be added, changed, or deleted as needed.

[0042] According to one embodiment of the present invention, a computing device (100) can detect abnormalities in process equipment. For example, the computing device (100) can classify patterns of a wafer map, train a model for classifying patterns of a wafer map, or detect defective equipment based on patterns of a wafer map in order to detect abnormalities in process equipment. In addition, the computing device (100) can detect abnormalities in process equipment by integrating various analysis techniques, including analysis based on patterns of a wafer map.

[0043] In one embodiment, the computing device (100) of the present invention can detect defective equipment based on the pattern of the wafer map.

[0044] Specifically, the computing device (100) can recognize a specific wafer map group containing more than a preset number of wafer maps classified as predefined defect patterns. Here, the wafer map group may refer to a group created by grouping wafer maps corresponding to wafers by the unit (e.g., Lot) in which the wafers are produced.

[0045] When a computing device (100) recognizes a specific wafer map group, it can recognize first process information related to the production of the wafer map included in the specific wafer map group. Here, the first process information may include process history such as a plurality of process names corresponding to the wafer maps included in the specific wafer map group (i.e., names of processes used to produce wafers) and a plurality of equipment names corresponding to the plurality of process names (i.e., names of equipment used in the process). For example, the computing device (100) can determine which process and which equipment the wafer map included in the specific wafer map group was produced by (i.e., first process information) through the product code of the wafer map included in the specific wafer map group.

[0046] When the computing device (100) recognizes the first process information, it can collect second process information related to the production of other wafer maps corresponding to the first process information. Here, the second process information may include multiple process names corresponding to the other wafer maps and multiple equipment names corresponding to the multiple process names. For example, the computing device (100) can recognize which process and which equipment the other wafer maps were produced with (i.e., second process information) through the product codes of the other wafer maps.

[0047] And, the computing device (100) can detect defective equipment that causes defects in the wafer map based on the first process information and the second process information.

[0048] Therefore, the computing device (100) of the present invention can easily detect defective equipment even in a semiconductor process that passes through hundreds of pieces of equipment.

[0049] Hereinafter, a specific description of the method for a computing device (100) to detect defective equipment based on a pattern of a wafer map will be described later with reference to FIGS. 3 to 5.

[0050] In one embodiment, the computing device (100) of the present invention can train a neural network model for classifying patterns of a wafer map.

[0051] Specifically, the computing device (100) can acquire multiple wafer maps from multiple process equipment. Additionally, the computing device (100) can train a classification model for classifying patterns of wafer maps based on multiple wafer maps. Here, the classification model is a model for classifying images of wafer maps and may be composed of a feature extraction layer consisting of multiple convolutional layers and activation functions, a pooling layer for downsampling feature maps, and a fully connected layer (i.e., a classifier) ​​for classifying wafer maps, but is not limited thereto.

[0052] The computing device (100) can obtain a classification result by inputting a wafer map to classify patterns into a classification model that has completed training. Additionally, the computing device (100) can recognize a specific classification result in which the score value corresponding to the classified pattern in the classification result is lower than a preset value, or the classified pattern is determined to be an error. Additionally, the computing device (100) can obtain a normal pattern corresponding to the specific classification result. Furthermore, the computing device (100) can retrain the classifier included in the classification model by labeling the wafer map and the normal pattern corresponding to the specific classification result.

[0053] Accordingly, the computing device (100) of the present invention can utilize transfer learning techniques to efficiently use human and material resources while simultaneously improving the accuracy of the model.

[0054] Hereinafter, a detailed description of the method for a computing device (100) to train a neural network model for classifying patterns of a wafer map will be described with reference to FIGS. 6 and 7.

[0055] In one embodiment, the computing device (100) can detect abnormalities in process equipment by integrating various analysis techniques.

[0056] Specifically, the computing device (100) can collect Bin data, Parametric Characteristic Monitoring (PCM) data, multiple wafer maps, and Fault Detection and Classification (FDC) data collected from process equipment. Additionally, the computing device (100) can extract a preset number of specific Bin data in order of highest defect rate based on the Bin data. Additionally, the computing device (100) can extract specific components where specification defects or control defects have occurred based on the PCM data. Additionally, the computing device (100) can classify the patterns of each of the multiple wafer maps based on the multiple wafer maps and extract at least one specific defective device corresponding to the classified pattern. Additionally, the computing device (100) can extract whether there is a defect regarding the abnormal operation of the process equipment based on the FDC data. Furthermore, the computing device (100) can integrate the results extracted based on the Bin data, PCM data, multiple wafer maps, and FDC data, and provide them to the user.

[0057] Accordingly, the computing device (100) of the present invention can improve wafer quality costs through integrated analysis and increase work efficiency related to the detection of abnormalities in process equipment.

[0058] Hereinafter, a detailed description of a method in which a computing device (100) integrates various analysis techniques to detect abnormalities in process equipment will be described later with reference to FIG. 10 and FIG. 11.

[0059] In various embodiments, the computing device (100) may provide Web or Application-based services. For example, the computing device (100) may provide anomaly detection services for process equipment. However, it is not limited thereto.

[0060] The computing device (100) may include any type of computer system or computer device, such as, for example, a microprocessor, a mainframe computer, a digital processor, a portable device, and a device controller. However, it is not limited thereto.

[0061] Hereinafter, the hardware configuration of the computing device (100) will be described with reference to FIG. 2.

[0062] Meanwhile, the user terminal (200) may be connected to the computing device (100) via a network (400) and may be a terminal of a user using the process equipment anomaly detection service provided by the computing device (100) or a manager of the process equipment that is the target of anomaly detection performed by the computing device (100).

[0063] Here, the user terminal (200) may include, for example, various types of computer devices. Specifically, for example, the user terminal (200) may refer to various terminal devices such as smartphones, tablet PCs, desktops, and laptops.

[0064] The user terminal (200) includes a display on at least a part of the terminal and may include an operating system for running applications or extension-based services provided by the computing device (100). For example, the user terminal (200) may be a smartphone, but is not limited thereto, and the user terminal (200) may include all kinds of handheld-based wireless communication devices such as navigation, PCS (Personal Communication System), GSM (Global System for Mobile communications), PDC (Personal Digital Cellular), PHS (Personal Handyphone System), PDA (Personal Digital Assistant), IMT (International Mobile Telecommunication)-2000, CDMA (Code Division Multiple Access)-2000, W-CDMA (W-Code Division Multiple Access), Wibro (Wireless Broadband Internet) terminal, smartpad, tablet PC, etc., as wireless communication devices that ensure portability and mobility.

[0065] An external server (300) can be connected to a computing device (100) via a network (400), and can transmit and receive various information / data necessary for the computing device (100) to perform various operations related to the detection of abnormalities in process equipment, and can store and manage various information / data generated as the computing device (100) performs various operations related to the detection of abnormalities in process equipment.

[0066] For example, the external server (300) may be a database server that stores information used in various operations related to the detection of anomalies in process equipment. As another example, the external server (300) may be a server that provides information used in various operations related to the detection of anomalies in process equipment (i.e., a process equipment server).

[0067] The network (400) may refer to a connection structure capable of exchanging information between each node, such as computing devices, multiple terminals, and servers. For example, the network (400) includes a Local Area Network (LAN), a Wide Area Network (WAN), the World Wide Web (WWW), a wired and wireless data network, a telephone network, a wired and wireless television network, etc.

[0068] Wireless data communication networks include, but are not limited to, 3G, 4G, 5G, 3GPP (3rd Generation Partnership Project), 5GPP (5th Generation Partnership Project), LTE (Long Term Evolution), WIMAX (World Interoperability for Microwave Access), Wi-Fi, Internet, LAN (Local Area Network), Wireless LAN (Wireless Local Area Network), WAN (Wide Area Network), PAN (Personal Area Network), RF (Radio Frequency), Bluetooth network, NFC (Near-Field Communication) network, satellite broadcasting network, analog broadcasting network, DMB (Digital Multimedia Broadcasting) network, etc.

[0070] FIG. 2 is a hardware configuration diagram of a computing device according to one embodiment of the present invention.

[0071] Referring to FIG. 2, a computing device (100) according to one embodiment of the present invention may include one or more processors (110), a memory (120) for loading a computer program (151) executed by the processor (110), a bus (130), a communication interface (140), and a storage (150) for storing the computer program (151). Here, FIG. 2 illustrates only the components related to the embodiment of the present invention. Therefore, a person skilled in the art to which the present invention pertains will understand that other general-purpose components may be included in addition to the components illustrated in FIG. 2.

[0072] The processor (110) controls the overall operation of each component of the computing device (100). The processor (110) may be composed of one or more cores and may include processors for data analysis and deep learning, such as a central processing unit (CPU), a general purpose graphics processing unit (GPGPU), or a tensor processing unit (TPU) of the computing device. Alternatively, it may be configured to include any type of processor well known in the art of the present invention.

[0073] Additionally, the processor (110) can perform operations for at least one application or program for executing the method according to embodiments of the present invention, and the computing device (100) may have one or more processors.

[0074] In various embodiments, the processor (110) may further include RAM (Random Access Memory, not shown) and ROM (Read-Only Memory, not shown) for temporarily and / or permanently storing signals (or data) processed within the processor (110). Additionally, the processor (110) may be implemented in the form of a system-on-chip (SoC) comprising at least one of a graphics processing unit, RAM, and ROM.

[0075] Memory (120) stores various data, instructions and / or information. Memory (120) may load a computer program (151) from storage (150) to execute a method / operation according to various embodiments of the present invention. When the computer program (151) is loaded into memory (120), the processor (110) may perform the method / operation by executing one or more instructions constituting the computer program (151). Memory (120) may be implemented as volatile memory such as RAM, but the technical scope of the present invention is not limited thereto.

[0076] The bus (130) provides communication functions between components of the computing device (100). The bus (130) can be implemented as various types of buses, such as an address bus, a data bus, and a control bus.

[0077] The communication interface (140) supports wired and wireless internet communication of the computing device (100). Additionally, the communication interface (140) may support various communication methods other than internet communication. To this end, the communication interface (140) may be configured to include a communication module well known in the art of the present invention. In some embodiments, the communication interface (140) may be omitted.

[0078] Storage (150) can store a computer program (151) non-temporarily. When performing a process according to an embodiment of the present invention through a computing device (100), storage (150) can store various information necessary to perform service provision or analysis according to the disclosed embodiment.

[0079] The storage (150) may be configured to include non-volatile memory such as ROM (Read Only Memory), EPROM (Erasable Programmable ROM), EEPROM (Electrically Erasable Programmable ROM), flash memory, a hard disk, a removable disk, or any form of computer-readable recording medium well known in the art to which the present invention belongs.

[0080] A computer program (151) may include one or more instructions that cause a processor (110) to perform a method / operation according to various embodiments of the present invention when loaded into memory (120). That is, the processor (110) may perform the method / operation according to various embodiments of the present invention by executing the one or more instructions.

[0081] In one embodiment, the computer program (151) may include one or more instructions to perform various methods related to various tasks related to learning a neural network model.

[0082] The steps of the method or algorithm described in connection with embodiments of the present invention may be implemented directly in hardware, implemented as a software module executed by hardware, or implemented by a combination thereof. The software module may reside in RAM (Random Access Memory), ROM (Read Only Memory), EPROM (Erasable Programmable ROM), EEPROM (Electrically Erasable Programmable ROM), Flash Memory, a hard disk, a removable disk, a CD-ROM, or any form of computer-readable recording medium well known in the art to which the present invention belongs.

[0083] The components of the present invention may be implemented as a program (or application) and stored on a medium to be executed in combination with a computer, which is hardware. The components of the present invention may be implemented as software programming or software elements, and similarly, embodiments may be implemented in programming or scripting languages ​​such as C, C++, Java, assembler, etc., including various algorithms implemented as combinations of data structures, processes, routines, or other programming configurations. Functional aspects may be implemented as algorithms executed on one or more processors.

[0085] FIGS. 3 to 5 are flowcharts illustrating an example of a method for detecting defective equipment based on a wafer map pattern according to an embodiment of the present invention.

[0086] Referring to FIG. 3, the computing device (100) can recognize a specific wafer map group containing more than a preset number of wafer maps classified as predefined defect patterns (S110).

[0087] Specifically, the computing device (100) can pre-classify each pattern of wafer maps obtained from process equipment and recognize wafer maps classified as defective patterns among the classified patterns. Additionally, the computing device (100) can recognize wafer map groups to which each of the wafer maps classified as defective patterns belongs. Furthermore, the computing device (100) can recognize a specific wafer map group containing more than a preset number of wafer maps classified as defective patterns.

[0088] Generally, wafer processing is performed in units of lots containing approximately 25 wafers. That is, the 25 wafers included in a single lot are produced using the same process and the same equipment. Therefore, the wafers included in a single lot are highly likely to have the same defect pattern, and if more than a predetermined number of wafer maps included in a single lot are classified as defective, it can be determined that there is an abnormality in the process or equipment associated with that lot. In this invention, the unit, group, or bundle of wafer maps included in such a lot is referred to as a wafer map group.

[0089] In one embodiment, the computing device (100) may collect a plurality of wafer maps produced in the past, including defective wafer maps, in production order, before recognizing a specific wafer map group. Additionally, the computing device (100) may group the plurality of wafer maps into pre-set units to create a plurality of wafer map groups. Furthermore, the computing device (100) may classify the patterns of the plurality of wafer maps included in each of the plurality of wafer map groups.

[0090] In one embodiment, the computing device (100) may use a classification model to classify the patterns of wafer maps included in each of the plurality of wafer map groups.

[0091] Specifically, the computing device (100) can obtain multiple binary images by binarizing multiple wafer maps and adding outlines. Additionally, the computing device (100) can recognize the pattern of each of the multiple binary images. Additionally, the computing device (100) can define multiple classification patterns for classifying wafer maps based on the pattern of each of the multiple binary images. Additionally, the computing device (100) can train a classification model for classifying the patterns of wafer maps based on the multiple binary images and the multiple classification patterns. Furthermore, the computing device (100) can classify the patterns of the multiple wafer maps by inputting the multiple wafer maps into the classification model. Here, the classification model can be trained to output a class-specific score value corresponding to each of the multiple classification patterns when it receives a specific binary image obtained by binarizing a specific wafer map to classify the patterns.

[0092] In one embodiment, the computing device (100) can update the classification model.

[0093] Specifically, the computing device (100) can obtain a classification result for each of the multiple wafer maps from a pre-trained classification model for classifying multiple wafer maps. Additionally, the computing device (100) can recognize a specific classification result in which the score value corresponding to the classified pattern in the classification result is lower than a preset value, or the classified pattern is determined to be an error. Additionally, the computing device (100) can obtain a normal pattern corresponding to the specific classification result. Furthermore, the computing device (100) can retrain the classifier included in the classification model by labeling the wafer map and the normal pattern corresponding to the specific classification result.

[0094] When the computing device (100) recognizes a specific wafer map group containing more than a preset number of wafer maps classified as defective patterns, it can recognize first process information related to the production of the wafer maps included in the specific wafer map group (S120).

[0095] Specifically, the computing device (100) can collect a plurality of first process names corresponding to a specific wafer map group. Additionally, the computing device (100) can collect equipment names corresponding to each of the plurality of first process names. For example, the computing device (100) can recognize the product codes of the wafer maps included in the specific wafer map group. Furthermore, the computing device (100) can recognize which process and which equipment the wafer maps were produced using the product codes. That is, the process information of the present invention can be structured such as a plurality of process names and a plurality of equipment names belonging to each of the plurality of process names.

[0096] When the computing device (100) recognizes the first process information, it may collect second process information related to the production of other wafer maps corresponding to the first process information (S130). Here, the second process information may include data classified as defective patterns and data classified as normal patterns related to a specific wafer map group.

[0097] Specifically, referring to FIG. 4, the computing device (100) can recognize the product codes of wafer maps included in a specific wafer map group (S131). Additionally, the computing device (100) can recognize other wafer maps produced by the same process as the wafer maps included in the specific wafer map group based on the product codes (S132). Additionally, the computing device (100) can collect a plurality of second process names corresponding to the other wafer maps (S133). Furthermore, the computing device (100) can collect a plurality of equipment names corresponding to each of the plurality of second process names (S134).

[0098] In various embodiments, when the computing device (100) collects second process information, it may collect a plurality of second process names and a plurality of equipment names corresponding to each of the plurality of second process names, classifying them as normal and defective.

[0099] That is, the computing device (100) of the present invention can collect various data (i.e., second process information) related to wafer maps produced using the same process and equipment as a wafer production unit (e.g., lot) corresponding to a specific wafer map group.

[0100] Referring again to FIG. 3, when the computing device (100) recognizes the first process information and the second process information, it can detect defective equipment that causes defects in the wafer map based on the first process information and the second process information (S140).

[0101] Specifically, with reference to FIG. 5, the computing device (100) can recognize a preset number of upper process names corresponding to the number of duplicates among a plurality of first process names included in the first process information and a plurality of second process names included in the second process information (S141).

[0102] For example, a specific wafer map group containing more than a preset number of wafer maps classified as defective patterns can be produced by the first process, the second process, the third process, the fourth process, and the fifth process, another wafer map can be produced by the second process, the third process, the fourth process, the sixth process, and the seventh process, and yet another wafer map can be produced by the eighth process, the ninth process, the first process, and the fourth process. There may be numerous processes used for the production of wafer maps, and the computing device (100) can collect process information of wafer maps produced using any one of the multiple processes used in the production of a specific wafer map group, and recognize a higher process name based on the number of duplicates among the process names included therein.

[0103] In addition, the computing device (100) can recognize each of the multiple equipment names used in each of the preset number of upper process names (S142).

[0104] For example, if the pre-set number of upper process names are the first process, the second process, and the third process, the first equipment, the second equipment, and the third equipment used in the first process are recognized, and the second equipment, the third equipment, and the fourth equipment used in the second process are recognized, and the first equipment, the second equipment, and the fifth equipment used in the third process can be recognized.

[0105] And, the computing device (100) can detect defective equipment by inputting each of the multiple equipment names into a defective equipment detection model (S143).

[0106] In the present invention, the defective equipment detection model can be pre-trained to detect defective equipment based on the probability of defects in wafer maps produced using equipment corresponding to a plurality of equipment names. For example, a computing device (100) can create a tree with equipment corresponding to the process used to produce a wafer map having a defect pattern, and train the defective equipment detection model using the number of times defects occurred when a wafer map was produced using each piece of equipment. For example, the defective equipment detection model can be trained as a decision tree to determine the equipment with a high probability of causing defects among at least two pieces of equipment.

[0108] FIGS. 6 and 7 are drawings illustrating an example of a method for training a model to classify a wafer map pattern and a wafer map pattern according to an embodiment of the present invention.

[0109] According to one embodiment of the present invention, a computing device (100) can acquire a plurality of wafer maps from a plurality of process equipment. Additionally, the computing device (100) can acquire a plurality of binary images by binarizing the plurality of wafer maps and adding outlines.

[0110] In the present invention, the binary image is an image in which each pixel constituting the image is distinguished as 0 (black) and 255 (white) or 0 and 1, and the pixel value of a normal pixel is 0, and the pixel value of a defective pixel is 255 or 1, but is not limited thereto. Meanwhile, the outline added to the binary image can be used to define a classification pattern related to the outline in a computing device (100).

[0111] For example, referring to FIG. 6, when a wafer map as shown in FIG. 6 (a) is obtained, the computing device (100) can convert the wafer map into a binary image as shown in FIG. 6 (b).

[0112] A computing device (100) according to one embodiment can recognize whether the number of binary images corresponds to a preset number of images (e.g., 10,000) for training a classification model when a plurality of wafer maps are acquired. And, the computing device (100) can adjust the number of binary images depending on whether it corresponds to a preset number of images for training a classification model.

[0113] Specifically, the computing device (100) can recognize the number of binary images corresponding to each of the plurality of classification patterns. Additionally, the computing device (100) can determine the number of training images for training a classification model based on the number of binary images corresponding to each of the plurality of classification patterns.

[0114] For example, the computing device (100) can determine the average value of the number of binary images corresponding to each of the plurality of classification patterns as the number of training images for training the classification model.

[0115] For example, if the number of binary images corresponding to the first pattern is 1,000, the number of binary images corresponding to the second pattern is 2,000, and the number of binary images corresponding to the third pattern is 1,500, the average value of each number, 1,500, can be determined as the number of training images.

[0116] When the computing device (100) determines the number of training images for training a model, it can adjust the number of binary images corresponding to each of the multiple classification patterns so that the number of binary images corresponding to each of the multiple classification patterns corresponds to the number of training images.

[0117] For example, the computing device (100) can recognize a first pattern corresponding to a number of binary images that is less than or equal to a preset number of training images. Then, the computing device (100) can perform data augmentation based on the binary images corresponding to the first pattern so that the number of binary images corresponding to the first pattern corresponds to the number of training images.

[0118] Additionally, the computing device (100) can recognize a second pattern corresponding to a number of binary images greater than or equal to a preset number than the number of training images. Furthermore, the computing device (100) can perform sampling of the binary images corresponding to the second pattern so that the number of binary images corresponding to the second pattern corresponds to the number of training images.

[0119] For example, in a state where the number of training images is determined to be 1,500, if the number of binary images corresponding to the first pattern is 1,000, the computing device (100) can perform data augmentation based on the binary images corresponding to the first pattern to adjust the number of binary images corresponding to the first pattern to 1,500. Additionally, if the number of binary images corresponding to the second pattern is 2,000, the computing device (100) can sample the binary images corresponding to the second pattern to adjust the number of binary images corresponding to the second pattern to 1,500.

[0120] Accordingly, the computing device (100) of the present invention can increase the accuracy of the classification model by generating a uniform number of training data for each of the plurality of patterns. In addition, the computing device (100) can save resources used to train the classification model.

[0121] In one embodiment, when the computing device (100) acquires a plurality of binary images, it can recognize the pattern of each of the plurality of binary images.

[0122] Specifically, the computing device (100) can recognize multiple defect points in each of the multiple binary images. Additionally, the computing device (100) can perform primary clustering of the defect points to generate at least one defect point cluster for each of the multiple binary images.

[0123] For example, a computing device (100) can extract features for defect points included in each of a plurality of binary images. Here, the features of the defect points may include features such as the location (e.g., coordinates), size, and shape of the defect points.

[0124] The computing device (100) can perform primary clustering by inputting extracted features into a clustering algorithm. The clustering algorithm can divide defect points with similar features into groups (clusters) to generate at least one defect point cluster. For example, the clustering algorithm may include at least one of K-means, DBSCAN, and Hierarchical clustering.

[0125] Meanwhile, when the computing device (100) generates at least one defect point cluster, it can recognize the pattern of each of the plurality of binary images based on the location of at least one defect point cluster and the shape of at least one defect point cluster for each of the plurality of binary images.

[0126] In one embodiment, when the computing device (100) recognizes the pattern of each of the plurality of binary images, it may define a plurality of classification patterns for classifying wafer maps based on the pattern of each of the plurality of binary images.

[0127] Specifically, the computing device (100) can perform secondary clustering on each pattern of a plurality of binary images to generate at least one pattern cluster for each pattern of a plurality of binary images.

[0128] For example, a computing device (100) can extract features for each pattern of a plurality of binary images. Here, the features of the pattern may include features such as pattern location (e.g., coordinates), size, and shape.

[0129] The computing device (100) can perform secondary clustering by inputting the extracted features into a clustering algorithm. The clustering algorithm can generate at least one pattern cluster by dividing defect points with similar features into groups (clusters). For example, the clustering algorithm may include at least one of K-means, DBSCAN, and Hierarchical clustering.

[0130] Meanwhile, the computing device (100) can define a specific pattern corresponding to a specific cluster containing a predetermined number or more binary images among at least one pattern cluster as one of the patterns included in a plurality of classification patterns.

[0131] For example, referring to Fig. 7, an example of a classification pattern defined based on a binary image is illustrated.

[0132] For example, the wafer map shown in Fig. 7(a) is a center pattern, which may be a defective pattern where defects are observed in the central region.

[0133] The wafer map shown in Fig. 7(b) is a donut pattern, where the central area is a good product and the defect is observed in a ring shape (i.e., donut shape) surrounding it.

[0134] The wafer map shown in Fig. 7(c) is a local pattern, which does not include corner areas, and may be a defect pattern in which defects are observed in the form of local clusters.

[0135] The wafer map shown in Fig. 7(d) is an edge_local pattern, which may be a defect pattern in which defects are observed in the form of local clusters that include the edge area.

[0136] The wafer map shown in Fig. 7(e) is an edge_ring pattern, which may be a defect pattern in which more than 75% of the edge area is observed to have continuously connected defects.

[0137] The wafer map shown in (f) of Fig. 7 is a scratch pattern, which may be a defect pattern in which defects are observed across in a linear or curved shape.

[0138] The wafer map shown in (g) of Fig. 7 is a random pattern and may be a defect pattern in which defects are observed in a random form.

[0139] The wafer map shown in (h) of Fig. 7 is a non-pattern pattern, which is mostly good and may be a pattern where no defective patterns are visible.

[0140] The wafer map pattern described with reference to FIG. 7 is merely an example to aid in understanding the present invention and is not limited thereto, and may include a wider variety of patterns.

[0141] According to various embodiments of the present invention, each of the eight patterns illustrated in FIG. 7 may be mapped to a specific part of process equipment or a specific process step. For example, wafer maps classified into similar patterns are likely to have occurred due to the same cause (defect of a specific part or error of a specific process step), so quality improvement measures can be performed on the corresponding patterns.

[0142] That is, when the computing device (100) acquires a wafer map, it classifies it into one of the 13 patterns shown in FIG. 9 and can provide a specific part or specific process step corresponding to the classified pattern to the user terminal (200). In this case, the user can improve productivity by taking action on the corresponding part or process step in a timely manner.

[0143] In one embodiment, when a computing device (100) defines a plurality of classification patterns, it can train a classification model for classifying patterns of a wafer map based on a plurality of binary images and a plurality of classification patterns.

[0144] When a specific binary image obtained by binarizing a specific wafer map is received as input to classify the patterns of the present invention, it can be trained to output class-specific score values ​​corresponding to each of a plurality of classification patterns.

[0145] Specifically, the classification model may include a first sub-model for extracting a first feature for an input image and a second sub-model for outputting a class-specific score value corresponding to each of the plurality of predefined classification patterns based on the first feature. Here, the second sub-model may recognize the similarity between the first feature and each of the second features of the image corresponding to each of the plurality of classification patterns, and output a score value proportional to the similarity.

[0146] In one embodiment, when the training of the classification model is completed, the computing device (100) may obtain a wafer map from a user terminal (200) or process equipment. In this case, the computing device (100) may input the wafer map (specifically, a binary image obtained by binarizing the wafer map) into a pre-trained classification model. Then, the computing device (100) may obtain a classification result (specifically, a score value by class) for the input wafer map from the classification model.

[0147] When the input wafer map in the classification result is classified as a non-normal defective pattern, the computing device (100) transmits the classification information to the user terminal (200) to cause the process equipment to perform the action in a timely manner.

[0148] In various embodiments, the computing device (100) may perform additional classification when the input wafer map is classified as similar to each of two different patterns in the output output by the classification model.

[0149] Specifically, the computing device (100) can input a wafer map into a pre-trained classification model to obtain class-specific score values ​​corresponding to each of a plurality of pre-defined classification patterns. In this case, the computing device (100) can select a pre-set number of patterns in order of increasing class-specific score values. Additionally, the computing device (100) can calculate the difference between the first score value of a first pattern and the second score value of a second pattern included in the pre-set number of patterns. Additionally, the computing device (100) can input the wafer map into a pre-trained decision model to output either the first pattern or the second pattern when the difference value is smaller than a pre-set size, thereby obtaining decision information for a specific pattern.

[0150] For example, the computing device (100) can recognize that when the first score value of the first pattern is 0.7 and the second score value of the second pattern is 0.67, the difference between the first score value and the second score value is 0.03, which is smaller than the preset size of 0.05, when the score value is set to 1 point when the patterns are completely identical. In this case, the computing device (100) can input the wafer map into a pre-trained decision model to obtain decision information for a specific pattern, which is either the first pattern or the second pattern.

[0151] The pre-trained decision model of the present invention can be pre-trained based on a training wafer map and training data in which classification patterns are labeled on each of the training wafer maps.

[0152] Specifically, the pre-trained decision model is trained to decide on one of two patterns, and can output results with higher accuracy than a model that classifies into one of multiple patterns. That is, the pre-trained decision model of the present invention may be a binary classification model.

[0153] Accordingly, the computing device (100) of the present invention can perform more accurate pattern classification for the wafer map.

[0154] In an additional embodiment, the computing device (100) may perform reclassification if the score value for each pattern (or class) of the input wafer map in the output output of the classification model is less than a preset value.

[0155] Specifically, the computing device (100) can input a wafer map into a pre-trained classification model to obtain class-specific score values ​​corresponding to each of a plurality of pre-defined classification patterns. In this case, the computing device (100) can select a pre-set number of patterns in order of increasing class-specific score values.

[0156] Meanwhile, the computing device (100) can obtain a classification result by inputting the wafer map back into a pre-trained classification model when the largest value of the class-specific score value is less than a preset value.

[0157] For example, the computing device (100) can determine that if the highest score value is less than 0.5 when the pattern is completely identical and the score value is set to 1 point, it is highly likely that the pattern will not be classified, and can input the wafer map image back into the classification model.

[0158] Additionally, if the score value for each pattern (or class) in the result obtained through reclassification is less than a preset value, the computing device (100) may recognize the wafer map as a special case and transmit information about the wafer map to a user terminal (200).

[0159] Accordingly, the computing device (100) of the present invention can cause rapid quality improvement measures for a wafer map pattern of a specific case.

[0161] FIGS. 8 and 9 are flowcharts illustrating an example of a method for training a model to classify patterns of a wafer map according to an embodiment of the present invention.

[0162] Referring to FIG. 8, the computing device (100) can obtain multiple wafer maps from multiple process equipment (S210). For example, the computing device (100) can obtain multiple wafer maps from an external server (300) associated with the process equipment.

[0163] The computing device (100) can train a classification model to classify patterns of wafer maps based on a plurality of wafer maps (S220). Then, the computing device (100) can input a wafer map to classify patterns into the trained classification model to obtain a classification result (S230).

[0164] The computing device (100) can recognize a specific classification result in which the score value corresponding to the classified pattern in the classification result is lower than a preset value, or the classified pattern is determined to be an error (S240).

[0165] For example, the computing device (100) can recognize a specific classification result corresponding to the wafer map when the probability of corresponding to the classified pattern is 50% or less (i.e., the score value is 0.5 or less). As another example, the computing device (100) can obtain a specific classification result that is determined to be an error by monitoring by an administrator.

[0166] The computing device (100) can obtain a normal pattern corresponding to a specific classification result (S250). Here, the normal pattern does not mean that the wafer map is not defective, but may mean a pattern in which the wafer map is classified normally.

[0167] Specifically, with reference to FIG. 9, the computing device (100) can generate multiple classifiers by duplicating the classifier among the feature extraction layer and the classifier that constitute the classification model that has been trained (S251). Additionally, the computing device (100) can obtain multiple classification results by inputting features extracted from a wafer map corresponding to a specific classification result by the feature extraction layer into the multiple classifiers (S252). Then, the computing device (100) can recognize the pattern corresponding to the result with the largest number of mutual overlaps among the multiple classification results as the normal pattern (S253).

[0168] For example, assuming there are multiple classifiers, such as a first classifier, a second classifier, a third classifier, a fourth classifier, and a fifth classifier, and when features extracted from a wafer map corresponding to a specific classification result are input to the multiple classifiers, the first classifier classifies the input features into a first pattern, the second classifier classifies the input features into a first pattern, the third classifier classifies the input features into a first pattern, the fourth classifier classifies the input features into a first pattern, and the fifth classifier classifies the input features into a second pattern. In this case, the computing device (100) can recognize the first pattern, which is the result with the largest number of mutual overlaps, as the normal pattern of the wafer map.

[0169] Referring again to FIG. 8, the computing device (100) can retrain the classifier included in the classification model by labeling the wafer map and normal pattern corresponding to a specific classification result (S260).

[0170] Accordingly, the computing device (100) of the present invention can automatically determine a normal classification result for a wafer map that is incorrectly classified, and improve the accuracy of the wafer map classification model by labeling it with the wafer map and retraining the classification model.

[0172] FIGS. 10 and FIGS. 11 are flowcharts illustrating an example of a method for detecting anomalies in process equipment by integrating a plurality of anomaly detection techniques according to an embodiment of the present invention.

[0173] Referring to FIG. 10, the computing device (100) can collect Bin data, PCM data, a plurality of wafer maps, and FDC data collected from process equipment (S310).

[0174] The computing device (100) can extract a preset number of specific Bin data in order of highest defect rate based on Bin data (S320).

[0175] In the present invention, Bin data may refer to data classified according to pre-set conditions for wafers that have completed production (e.g., in the case of DRAM, speed or wafer map groups grouped by lot). Additionally, Bin data may include information on the defect rate (or yield) of wafers classified according to pre-set conditions.

[0176] That is, the computing device (100) can recognize the defect rate of each of the multiple wafer map groups and individual wafer maps based on the Bin data. In addition, the computing device (100) can extract a preset number of specific Bin data in order of highest defect rate.

[0177] In one embodiment, the computing device (100) may collect a plurality of wafer maps produced in the past and containing defective wafer maps in production order, prior to recognizing the defect rate of each of the plurality of wafer map groups and individual wafer maps based on bin data. Additionally, the computing device (100) may create a plurality of wafer map groups by grouping the plurality of wafer maps into pre-set units. Furthermore, the computing device (100) may classify the patterns of the plurality of wafer maps included in each of the plurality of wafer map groups.

[0178] The computing device (100) can extract specific components that have a specification defect or control defect based on PCM data (S330).

[0179] In the present invention, PCM data may include information regarding the defect status of a wafer using a test pattern generated according to the type or characteristics of the wafer. For example, PCM data is obtained by conducting tests on samples in which individual components are placed one by one on the wafer, and may include information regarding the defect status of each individual component. Additionally, PCM data may include test results such as Out of Specification (OOS) or Out of Control (OOC) for each individual component.

[0180] That is, the computing device (100) can recognize individual components included in a wafer map corresponding to a preset number of Bin data based on PCM data. In addition, the computing device (100) can obtain test results for individual components and, based on the test results, extract specific components that have a specification defect or a control defect.

[0181] The computing device (100) can classify the pattern of each of the plurality of wafer maps based on the plurality of wafer maps and extract at least one specific defective device corresponding to the classified pattern (S340).

[0182] Specifically, the computing device (100) can recognize a specific wafer map group containing more than a preset number of wafer maps classified as predefined defect patterns. Additionally, the computing device (100) can recognize first process information related to the production of wafer maps included in the specific wafer map group. Additionally, the computing device (100) can collect second process information related to the production of other wafer maps corresponding to the first process information. Furthermore, the computing device (100) can extract defective equipment that causes defects in wafer maps based on the first process information and the second process information.

[0183] Hereinafter, the method of the computing device (100) extracting defective equipment using process information of the wafer map has been described above with reference to FIGS. 3 to 5, and redundant descriptions are omitted.

[0184] The computing device (100) can extract whether there is a defect in the abnormal operation of the process equipment based on FDC data (S350).

[0185] In the present invention, FDC data may refer to result data obtained by monitoring the operating status and performance of process equipment to detect and classify abnormal situations at an early stage. For example, a computing device (100) can detect whether the process equipment is operating abnormally using process sensor data, and the data related thereto can be used to detect abnormalities in the process equipment.

[0186] In one embodiment, the computing device (100) can detect abnormal operation of process equipment by utilizing a deep learning model.

[0187] Specifically, the computing device (100) can acquire process sensor data and prior knowledge data corresponding to the process sensor data. Additionally, the computing device (100) can generate reconstructed process sensor data corresponding to the process sensor data by utilizing a deep learning model. Furthermore, the computing device (100) can calculate a reconstruction rate error based on the process sensor data and the reconstructed process sensor data. And, the computing device (100) can detect abnormal operation based on a comparison of the reconstruction rate error and a reference threshold value.

[0188] A method for the computing device (100) of the present invention to detect abnormal operation of process equipment using a deep learning model is specifically described in Registered Patent Publication No. 10-2523458, which is incorporated by reference in its entirety in this application.

[0189] Meanwhile, the computing device (100) can provide integrated results extracted based on each of the Bin data, PCM data, multiple wafer maps, and FDC data (S360).

[0190] Specifically, with reference to FIG. 11, the computing device (100) can compare a pre-set condition corresponding to each of the Bin data, PCM data, a plurality of wafer maps, and FDC data with a result extracted based on each of the Bin data, PCM data, a plurality of wafer maps, and FDC data (S361). Then, the computing device (100) can provide visualized information corresponding to each of the Bin data, PCM data, a plurality of wafer maps, and FDC data based on the result of comparison (S362).

[0191] For example, the computing device (100) may display in red if the total yield of a lot is less than 90% in the results extracted based on Bin data, in orange if it is 90% or more but less than 95%, and in green if it is 95% or more. Additionally, the computing device (100) may display in red if both OOS and OOC occurred or if only OOS occurred in the results extracted based on PCM data, in orange if only OOC occurred, and in green if neither occurred. Additionally, the computing device (100) may display in red if the yield is less than 90% in the results extracted based on multiple wafer maps, in orange if the yield is 90% or more and a specific pattern appears, or if the yield is 90% or more but less than 95% and a random pattern appears, and in green if the yield is 95% or more and a random pattern appears or a non-pattern appears. Additionally, the computing device (100) can display red if an abnormality occurs in the result extracted based on FDC data and is determined to be defective, orange if an abnormality occurs but no wafer is determined to be defective, and green if no abnormality occurs.

[0192] In one embodiment, the computing device (100) can simultaneously provide the user with information visualized by data (e.g., displayed in different colors depending on conditions) to enable rapid integrated analysis and further reduce wafer quality control costs.

[0194] FIG. 12 is a schematic diagram showing one or more network functions related to one embodiment of the present invention.

[0195] Throughout this specification, artificial intelligence model, neural network, network function, and neural network may be used interchangeably. A neural network may generally consist of a set of interconnected computational units that may be referred to as “nodes.” These “nodes” may also be referred to as “neurons.”

[0196] A deep neural network (DNN) may refer to a neural network that includes multiple hidden layers in addition to input and output layers. Using a deep neural network allows for the identification of latent structures in data. That is, it is possible to identify the latent structures of photos, text, videos, voice, and music (e.g., what objects are present in a photo, what the content and emotions of a text are, what the content and emotions of a voice are, etc.). Deep neural networks may include convolutional neural networks (CNN), recurrent neural networks (RNN), autoencoders, Generative Adversarial Networks (GAN), restricted Boltzmann machines (RBM), deep belief networks (DBN), Q networks, U networks, Siamese networks, etc. The description of deep neural networks described above is merely illustrative and the present invention is not limited thereto.

[0197] Neural networks can be trained using at least one of supervised learning, unsupervised learning, and semi-supervised learning. The purpose of training a neural network is to minimize the error in the output. The training process involves repeatedly inputting training data into the network, calculating the error between the network's output and the target for the training data, and updating the weights of each node in the network by backpropagating the error from the output layer to the input layer in a direction that reduces the error. In the case of supervised learning, training data is used where the correct answer is labeled for each training data point (i.e., labeled training data), whereas in the case of unsupervised learning, the correct answer may not be labeled for each training data point. That is, for example, in the case of supervised learning regarding data classification, the training data may consist of data where each training data point is labeled with a category. Labeled training data is input into the neural network, and the error can be calculated by comparing the network's output (category) with the label of the training data. As another example, in the case of unsupervised learning for data classification, the error can be calculated by comparing the input training data with the neural network output. The calculated error is backpropagated within the neural network (i.e., from the output layer to the input layer), and this backpropagation can update the connection weights of each node in each layer of the neural network. The amount of change in the connection weights of each updated node can be determined by the learning rate. The neural network's calculation of the input data and the backpropagation of the error can constitute a learning cycle (epoch). The learning rate can be applied differently depending on the number of iterations of the neural network's learning cycle.For example, efficiency can be increased by using a high learning rate during the early stages of neural network training to enable the network to quickly achieve a certain level of performance, and accuracy can be improved by using a low learning rate during the later stages of training.

[0198] In the training of neural networks, the training data is generally a subset of the real-world data (i.e., the data intended to be processed by the trained neural network). Consequently, a training cycle may exist where errors decrease on the training data but increase on the real-world data. Overfitting is a phenomenon where the network learns excessively on the training data, leading to increased errors on real-world data. For example, a neural network trained on yellow cats might fail to recognize cats when seeing anything other than yellow, which can be considered a type of overfitting. Overfitting can act as a cause for increased errors in machine learning algorithms. Various optimization methods can be used to prevent this overfitting. To prevent overfitting, methods such as increasing the training data, regularization, or dropout—which involves omitting some nodes from the network during the training process—can be applied.

[0199] The steps of the method or algorithm described in connection with embodiments of the present invention may be implemented directly in hardware, implemented as a software module executed by hardware, or implemented by a combination thereof. The software module may reside in RAM (Random Access Memory), ROM (Read Only Memory), EPROM (Erasable Programmable ROM), EEPROM (Electrically Erasable Programmable ROM), Flash Memory, a hard disk, a removable disk, a CD-ROM, or any form of computer-readable recording medium well known in the art to which the present invention belongs.

[0200] The components of the present invention may be implemented as a program (or application) and stored on a medium to be executed in combination with a computer, which is hardware. The components of the present invention may be implemented as software programming or software elements, and similarly, embodiments may be implemented in programming or scripting languages ​​such as C, C++, Java, assembler, etc., including various algorithms implemented as combinations of data structures, processes, routines, or other programming configurations. Functional aspects may be implemented as algorithms executed on one or more processors.

[0201] Those skilled in the art will understand that the various exemplary logic blocks, modules, processors, means, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented by electronic hardware, various forms of programs or design code (referred to herein as “software”), or a combination of all such. To clearly illustrate this interoperability between hardware and software, various exemplary components, blocks, modules, circuits, and steps have been generally described above in relation to their functions. Whether such functions are implemented as hardware or software depends on the design constraints imposed on the specific application and the overall system. Those skilled in the art may implement the functions described in various ways for each specific application, but such implementation decisions should not be interpreted as being outside the scope of the invention.

[0202] The various embodiments presented herein may be implemented as methods, devices, or articles of manufacture using standard programming and / or engineering techniques. The term “article of manufacture” includes a computer program, carrier, or medium accessible from any computer-readable device. For example, computer-readable media include, but are not limited to, magnetic storage devices (e.g., hard disks, floppy disks, magnetic strips, etc.), optical discs (e.g., CDs, DVDs, etc.), smart cards, and flash memory devices (e.g., EEPROMs, cards, sticks, key drives, etc.). Additionally, the various storage media presented herein include one or more devices and / or other machine-readable media for storing information. The term “machine-readable media” includes, but is not limited to, wireless channels and various other media capable of storing, holding, and / or transmitting command(s) and / or data.

[0203] It should be understood that the specific order or hierarchy of steps in the presented processes is merely an example of exemplary approaches. It should be understood that, based on design priorities, the specific order or hierarchy of steps in the processes may be rearranged within the scope of the invention. The appended method claims provide various step elements in a sample order, but do not imply limitation to the specific order or hierarchy presented.

[0205] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without altering its technical concept or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive.

Claims

Claim 1 A method performed by a computing device comprising at least one processor, comprising: collecting Bin data, PCM (Process Control Monitoring) data, a plurality of wafer maps, and FDC (Fault Detection and Classification) data collected from process equipment; collecting a plurality of wafer maps produced in the past and including defective wafer maps in production order, and grouping the plurality of wafer maps into a predetermined unit to create a plurality of wafer map groups; classifying the pattern of each of the plurality of wafer maps included in each of the plurality of wafer map groups; extracting at least one specific defective device corresponding to the classified pattern; recognizing the defect rate of each of the plurality of wafer map groups and each individual wafer map based on the Bin data; extracting a predetermined number of specific Bin data in order of highest defect rate; extracting a specific device in which a specification defect or control defect has occurred based on the PCM data; classifying the pattern of each of the plurality of wafer maps based on the plurality of wafer maps and extracting at least one specific defective device corresponding to the classified pattern; and extracting whether there is a defect regarding the abnormal operation of the process equipment based on the FDC data. The method comprises the step of providing a result by integrating the results extracted based on each of the above Bin data, the above PCM data, the plurality of wafer maps, and the above FDC data; wherein the step of extracting at least one specific defective device comprises: the step of recognizing a specific wafer map group containing at least a predetermined number of wafer maps classified by a predefined defect pattern; the step of recognizing first process information related to the production of a wafer map included in the specific wafer map group; the step of collecting second process information related to the production of other wafer maps corresponding to the first process information; and the step of extracting a defective device that causes defects in the wafer map based on the first process information and the second process information.A method for detecting anomalies in process equipment by integrating a plurality of anomaly detection techniques, comprising: a step of extracting a specific device in which a specification defect or control defect has occurred based on the PCM data, wherein the step of recognizing individual devices included in a wafer map corresponding to a preset number of Bin data based on the PCM data; and a step of obtaining test results for the individual devices and extracting a specific device in which a specification defect or control defect has occurred based on the test results. Claim 2 A device comprising: a memory for storing one or more instructions; and a processor for executing the one or more instructions stored in the memory, wherein the processor performs the method of claim 1 by executing the one or more instructions. Claim 3 A computer program stored on a computer-readable recording medium that is combined with a computer, which is hardware, to perform the method of claim 1.

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