Semiconductor devices

Abstract

A semiconductor device may include: a conductive contact plug formed on a substrate and comprising a lower portion having a first width and an upper portion having a second width smaller than the first width; a bit line structure formed on the conductive contact plug and comprising a conductive structure and an insulating structure stacked along a vertical direction perpendicular to the upper surface of the substrate; and first to third lower spacers sequentially stacked on the side wall of the lower portion of the conductive contact plug in a horizontal direction parallel to the upper surface of the substrate, wherein the upper surface of the third lower spacer may be higher than the upper surface of the first and second lower spacers.

Description

Technology Field

[0001] The present invention relates to a semiconductor device. More specifically, the present invention relates to a DRAM device. Background Technology

[0002] In a DRAM device, a conductive contact plug is formed at the bottom of a bit line structure in contact with an active pattern. Since an electrical short circuit may occur between the conductive contact plug and adjacent conductive structures due to misalignment or the like during the manufacturing process of the DRAM device, a method to resolve this is required. Prior art literature

[65535] US Registered Patent 9,209,241 (December 8, 2015) The problem to be solved

[0003] The objective of the present invention is to provide a semiconductor device having improved electrical characteristics. means of solving the problem

[0004] A semiconductor device according to exemplary embodiments for achieving the above-mentioned objective may include: a conductive contact plug formed on a substrate and comprising a lower portion having a first width and an upper portion having a second width smaller than the first width; a bit line structure formed on the conductive contact plug and comprising a conductive structure and an insulating structure stacked along a vertical direction perpendicular to the upper surface of the substrate; and first to third lower spacers sequentially stacked on the side wall of the lower portion of the conductive contact plug in a horizontal direction parallel to the upper surface of the substrate, wherein the upper surface of the third lower spacer may be higher than the upper surface of the first and second lower spacers.

[0005] A semiconductor device according to other embodiments for achieving the above-mentioned objective may include: an active pattern formed on a substrate; a device isolation pattern covering the sidewall of the active pattern; a conductive contact plug in contact with the upper surface of the active pattern; a bit line structure formed on the conductive contact plug; a conductive pad structure formed on the active pattern and the device isolation pattern, which includes first to third pads that are sequentially stacked in a vertical direction perpendicular to the upper surface of the substrate and overlap at least a portion of the conductive contact plug in a horizontal direction parallel to the upper surface of the substrate; and first and second lower spacers stacked in the horizontal direction on the sidewall of the conductive contact plug, wherein the height of the uppermost surface of the second lower spacer may be higher than the height of the upper surface of the second pad.

[0006] A semiconductor device according to another embodiment for achieving the above-mentioned objective comprises: an active pattern formed on a substrate; a device isolation pattern formed on the substrate and covering the sidewall of the active pattern; a gate structure extending in a first direction parallel to the upper surface of the substrate and embedded above the active pattern and the device isolation pattern; a conductive pad structure formed on the active pattern and the device isolation pattern; a conductive contact plug penetrating the conductive pad structure and contacting the upper surface of the central part of the active pattern, comprising a lower portion having a first width and an upper portion having a second width smaller than the first width; a bit line structure formed on the conductive contact plug and the conductive pad structure and extending in a second direction parallel to the upper surface of the substrate and perpendicular to the first direction; first and second lower spacers having different insulating materials, sequentially stacked in a horizontal direction parallel to the upper surface of the substrate on the sidewall of the lower portion of the conductive contact plug; and an insulating embedded pattern formed on the first and second lower spacers. It may include an upper structure formed on the side wall of the bit line structure formed on the insulating embedded pattern; a contact plug structure formed on the conductive pad structure; and a capacitor formed on the contact plug structure, wherein the height of the uppermost surface of the first and second lower spacers may be the same as the height of the upper surface of the lower portion of the conductive contact plug. Effects of the invention

[0007] In a semiconductor device according to exemplary embodiments, conductive contact plugs formed between a bit line structure and an active pattern are uniformly formed, so the semiconductor device including the same can have improved electrical characteristics. In addition, during the process for forming the conductive contact plugs, damage to an adjacent device isolation pattern or conductive pad can be prevented. Brief explanation of the drawing

[0008] FIGS. 1 to 28 are plan and cross-sectional views for illustrating a method of manufacturing a semiconductor device according to exemplary embodiments. FIGS. 29 to 34 are cross-sectional views illustrating a method for manufacturing a semiconductor device according to exemplary embodiments. FIGS. 35 to 38 are cross-sectional views illustrating a method for manufacturing a semiconductor device according to exemplary embodiments. FIGS. 39 to 45 are plan and cross-sectional views illustrating a method for manufacturing a semiconductor device according to exemplary embodiments. FIGS. 46 and 47 are plan and cross-sectional views for illustrating semiconductor devices according to exemplary embodiments. Specific details for implementing the invention

[0009] Hereinafter, a semiconductor device and a method for manufacturing the same according to preferred embodiments of the present invention will be described in detail with reference to the attached drawings. Where materials, layers (films), regions, pads, electrodes, patterns, structures, or processes are referred to as "first," "second," and / or "third" in this specification, it is not intended to limit these components but merely to distinguish each material, layer (film), region, electrode, pad, pattern, structure, and process. Accordingly, "first," "second," and / or "third" may be used selectively or interchangeably for each material, layer (film), region, electrode, pad, pattern, structure, and process.

[0010] [Example]

[0011] FIGS. 1 to 28 are plan views and cross-sectional views for illustrating a method of manufacturing a semiconductor device according to exemplary embodiments. Specifically, FIGS. 1, 3, 5, 22 and 26 are plan views, FIG. 2 includes cross-sections cut along the A-A' and B-B' lines of FIG. 1, respectively, and FIGS. 4, 6-21, 23-25 ​​and 27-28 are cross-sectional views cut along the A-A' line of the corresponding plan views.

[0012] In the following detailed description of the invention, two directions parallel to the upper surface of the substrate (100) and orthogonal to each other are defined as the first and second directions (D1, D2), respectively, and a direction parallel to the upper surface of the substrate (100) and forming an acute angle with each of the first and second directions (D1, D2) is defined as the third direction (D3).

[0013] Referring to FIGS. 1 and 2, an active pattern (103) can be formed on a substrate (100), and a device isolation pattern (112) covering the sidewalls thereof can be formed.

[0014] The substrate (100) may include silicon, germanium, silicon-germanium, or group III-V compounds such as GaP, GaAs, GaSb, etc. According to some embodiments, the substrate (100) may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0015] The active pattern (103) can be formed by removing the upper portion of the substrate (100) to form a first recess, and the active pattern (103) can be formed in multiple numbers such that each extends in a third direction (D3) and is spaced apart from each other along the first and second directions (D1, D2). The device isolation pattern (112) may include, for example, an oxide such as silicon oxide.

[0016] Afterwards, the active pattern (103) and the device isolation pattern (112) can be partially etched to form a second recess extending in the first direction (D1).

[0017] Subsequently, a gate structure (170) can be formed inside the second recess. The gate structure (170) may include a gate insulation pattern (120) formed on the bottom surface and side wall of the second recess, a first barrier pattern (130) formed on the portion of the gate insulation pattern (120) formed on the bottom surface and lower side wall of the second recess, a first conductive pattern (140) formed on the first barrier pattern (130) to fill the lower part of the second recess, a second conductive pattern (150) formed on the upper surface of the first barrier pattern (130) and the first conductive pattern (140), and a gate mask (160) formed on the upper surface of the second conductive pattern (150) and the upper inner wall of the gate insulation pattern (120) to fill the upper part of the second recess. At this time, the first barrier pattern (130), the first conductive pattern (140), and the second conductive pattern (150) may together form a gate electrode.

[0018] The gate insulation pattern (120) may include, for example, an oxide such as silicon oxide, the first barrier pattern (130) may include, for example, a metal nitride such as titanium nitride, tantalum nitride, etc., the first conductivity pattern (140) may include a metal, a metal nitride, a metal silicide, etc., the second conductivity pattern (150) may include polysilicon doped with impurities, and the gate mask (160) may include, for example, an insulating nitride such as silicon nitride.

[0019] In exemplary embodiments, the gate structure (170) may be extended along a first direction (D1) and may be formed in multiple numbers spaced apart from each other along a second direction (D2).

[0020] Referring to FIGS. 3 and 4, a first pad (700) and a second pad (710) can be formed on a substrate (100) on which an active pattern (103), a device isolation pattern (112), and a gate structure (170) are formed.

[0021] In exemplary embodiments, a first pad film may be formed on a substrate (100), and a first pad (700) may be formed by patterning the first pad film to form a first opening that partially exposes the upper surface of an active pattern (103), a device isolation pattern (112), and a gate structure (170), and then a second pad (710) may be formed to fill the first opening. Alternatively, a second pad film may be formed on a substrate (100), and a second pad (710) may be formed by patterning the second pad film, and then the first pad (700) may be formed.

[0022] The first pad (700) may include, for example, impurity-doped polysilicon, metals such as tungsten or ruthenium, metal nitrides such as titanium nitride or tantalum nitride, or conductive materials such as graphene. In one embodiment, the first pad (700) may be a single film comprising one of the aforementioned materials. In another embodiment, the first pad (700) may be a composite film in which films each comprising some of the aforementioned materials are stacked. In the drawings, the first pad (700) is illustrated as a single film comprising the conductive material.

[0023] The second pad (710) may include an insulating material, for example, an insulating nitride such as silicon nitride.

[0024] In exemplary embodiments, the first opening may include a first portion extending in a first direction (D1) and a second portion extending in a second direction (D2), and these may be connected to each other. Accordingly, the second pad (710) formed within the first opening may include a first extension portion extending in the first direction (D1) and a second extension portion extending in the second direction (D2), and these may be connected to each other. Meanwhile, the first pad (700) may be formed in multiple numbers spaced apart from each other along the first and second directions (D1, D2) when viewed from above, and may be arranged, for example, in a grid shape.

[0025] In exemplary embodiments, the first pad (700) may be positioned to overlap along a vertical direction perpendicular to the upper surface of the substrate (100) at the end of each active pattern (103) extending in the third direction (D3) and at the portion of the device isolation pattern (112) adjacent thereto in the first direction (D1).

[0026] Referring to FIGS. 5 and 6, a third pad film is formed on the first and second pads (700, 710) and patterned to form a third pad (720), and then the gate mask (160) included in the lower first and second pads (700, 710), active pattern (103), device isolation pattern (112), and gate structure (170) is used as an etching mask to partially etch the gate mask (160) to form the second opening (230).

[0027] In exemplary embodiments, the third pad (720) may have a circular or elliptical shape when viewed from above and may be formed in multiple numbers spaced apart from each other along the first and second directions (D1, D2) on the substrate (100). In this case, each third pad (720) may overlap in the vertical direction with the end portions of the active patterns (103) adjacent to each other in the first direction (D1) and the portion of the device separation pattern (112) between them. The third pad (720) may include an insulating nitride, for example, silicon nitride.

[0028] Referring to FIG. 7, after forming a first lower spacer membrane (730) on the side wall and bottom surface of the second opening (230) and the upper surface of the third pad (720), a first sacrificial membrane (740) that fills the second opening (230) can be formed on the first lower spacer membrane (730).

[0029] The first lower spacer film (730) may include an insulating nitride, such as silicon nitride, for example, and the first sacrificial film (740) may include, for example, a spin-on-hard mask (SOH), an amorphous carbon layer (ACL), etc.

[0030] Referring to FIG. 8, the upper portion of the first sacrificial membrane (740) may be removed, for example, through an etch-back process, so that the lower portion of the first sacrificial membrane (740) remains at the lower portion of the second opening (230), and the portion of the first lower spacer membrane (730) formed on the upper surface of the third pad (720) and the upper side wall of the second opening (230) may be exposed.

[0031] At this time, the lower portion of the first sacrificial membrane (740) remaining at the lower portion of the second opening (230) may be referred to as the first sacrificial pattern (745). In exemplary embodiments, the height of the upper surface of the first sacrificial pattern (745) may be higher than the height of the upper surface of the device isolation pattern (112) or the lower surface of the first pad (700).

[0032] Subsequently, the exposed portion of the first lower spacer film (730) can be removed, for example, through a stripping process, and accordingly, a first lower spacer (735) can be formed on the lower sidewall and bottom surface of the second opening (230). During the stripping process, the upper surface of the first sacrificial pattern (745) remaining at the bottom of the second opening (230) can act as a kind of etching stop layer, and accordingly, the height of the uppermost surface of the first lower spacers (735) formed in each of the plurality of second openings (230) through the stripping process can be maintained equally.

[0033] In exemplary embodiments, the height of the upper surface of the first lower spacers (735) may be substantially the same as the height of the upper surface of the first sacrificial patterns (745) adjacent thereto, and thus may be higher than the height of the upper surface of the device isolation pattern (112) or the lower surface of the first pad (700).

[0034] Meanwhile, as the upper portions of the first sacrificial membrane (740) and the first lower spacer membrane (730) are removed, a third recess (235) may be formed in the upper portion of the second opening (230).

[0035] Referring to FIG. 9, a first sacrificial spacer film can be formed on the bottom and sidewalls of the third recess (235) and the top surface of the third pad (720) through, for example, an atomic layer deposition (ALD) process, and then an anisotropic etching process can be performed on the first sacrificial spacer film to form a first sacrificial spacer (755) on the sidewalls of the third recess (235).

[0036] The first sacrificial spacer (755) may include, for example, an oxide such as silicon oxide and may be formed on the uppermost surface of the first lower spacer (735).

[0037] Referring to FIG. 10, the first sacrifice pattern (745) can be removed to expose the surface of the first lower spacer (735), and accordingly, most of the second opening (230) can be re-formed.

[0038] Afterwards, a second lower spacer film (760) can be formed on the surface of the exposed first lower spacer (735), the surface of the first sacrificial spacer (755), and the upper surface of the third pad (720).

[0039] The first sacrifice pattern (745) can be removed, for example, through an ashing and / or stripping process.

[0040] The second lower spacer membrane (760) may include, for example, silicon oxycarbon (SiOC).

[0041] Referring to FIG. 11, an anisotropic etching process can be performed on the second lower spacer film (760) and the first lower spacer (735) formed below it.

[0042] By performing the above anisotropic etching process, the portion of the second lower spacer film (760) formed on the upper surface of the third pad (720), and the portion of the first lower spacer (735) and the portion of the second lower spacer film (760) formed on the lower surface of the second opening (230) can be removed.

[0043] Accordingly, a first lower spacer (735) and a first sacrificial spacer (755) may be sequentially stacked along a vertical direction perpendicular to the upper surface of the substrate (100) on the side wall of the second opening (230), and a second lower spacer (765) may be formed on the inner wall of the first lower spacer (735) and the first sacrificial spacer (755). At this time, the first and second lower spacers (735, 765) and the first sacrificial spacer (755) may together form a first preliminary lower spacer structure (770).

[0044] Meanwhile, as the above anisotropic etching process is performed, the upper surface of the active pattern (103) portion formed below the second opening (230), that is, the upper surface of the active pattern (103) portion not covered by the first preliminary lower spacer structure (770), may be exposed. Accordingly, a first metal film may be formed on the upper surface of the exposed active pattern (103) portion, the inner wall of the first preliminary lower spacer structure (770), and the upper surface of the third pad (720), and by heat treating the first metal film thereon, the silicon component contained in the active pattern (103) may be reacted with the first metal film to form a first metal silicide pattern (105) on the upper surface of the active pattern (103) exposed by the second opening (230).

[0045] The first metal silicide pattern (105) may include, for example, titanium silicide, cobalt silicide, nickel silicide, etc., and the portion of the first metal film that does not react with the active pattern (103) may all be removed.

[0046] Subsequently, a first embedment pattern (780) can be formed within the second opening (230). The first embedment pattern (780) can be formed within the second opening (230) by forming a first embedment film that fills the second opening (230) on the upper surface of the first metal silicide pattern (105), the inner wall of the first preliminary lower spacer structure (770), and the upper surface of the third pad (720), and then performing an etch back process and / or chemical mechanical polishing (CMP) process thereon. The first embedment pattern (780) may include, for example, a metal nitride such as titanium nitride, tantalum nitride, tungsten nitride, etc., and / or a metal such as titanium, tantalum, tungsten, etc.

[0047] The first preliminary lower spacer structure (770) and the first burial pattern (780) formed within the second opening (230) and burying it can together form the first preliminary burial structure (790).

[0048] Referring to FIG. 12, an adhesive film, a third conductive film, a first mask film, a first etch stop film, and a first capping film can be sequentially formed on a third pad (720) and a first pre-filled structure (790). Subsequently, the first capping film can be patterned to form a first capping pattern (385), and the first etch stop film, the first mask film, the third conductive film, and the adhesive film can be sequentially etched using this as an etching mask.

[0049] As the above etching process is performed, an adhesive pattern (245), a third conductive pattern (265), a first mask (275), a first etching stop pattern (365), and a first capping pattern (385) can be formed sequentially on the first pre-filled structure (790) and the third pad (720).

[0050] The adhesive pattern (245) may include a metal nitride such as titanium nitride, tantalum nitride, or tungsten nitride, for example, and the third conductive pattern (265) may include a metal such as tungsten, titanium, tantalum, or ruthenium, for example, and each of the first mask (275), the first etching stop pattern (365), and the first capping pattern (385) may include an insulating nitride such as silicon nitride, for example.

[0051] The adhesive pattern (245) can be formed between a third pad (720) containing an insulating nitride, for example, silicon nitride, and a third conductive pattern (265) containing a metal, for example, tungsten, so that they can be well bonded to each other.

[0052] Hereinafter, the sequentially stacked adhesive pattern (245), third conductive pattern (265), first mask (275), first etching stop pattern (365), and first capping pattern (385) will be collectively referred to as a bit line structure (395). At this time, the bit line structure (395) may include a conductive structure comprising the adhesive pattern (245) and the third conductive pattern (265), and an insulating structure formed on the conductive structure comprising the first mask (275), the first etching stop pattern (365), and the first capping pattern (385). In one embodiment, the sequentially stacked first mask (275), the first etching stop pattern (365), and the first capping pattern (385) may be merged together to form a single insulating structure.

[0053] In exemplary embodiments, the bit line structure (395) may be extended in a second direction (D2) on the substrate (100) and may be formed in multiple numbers spaced apart from each other along the first direction (D1).

[0054] Referring to FIG. 13, second and third sacrificial spacer membranes (400, 410) can be formed on the bit line structure (395), the first pre-filled structure (790), and the third pad (720).

[0055] The second sacrificial spacer film (400) may include an insulating nitride, such as silicon nitride, for example, and the third sacrificial spacer film (410) may include the same material as the second lower spacer (765), for example, silicon oxycarbon (SiOC).

[0056] In one embodiment, the second sacrificial spacer membrane (400) may not be formed, in which case a third sacrificial spacer membrane (410) may be formed on the bit line structure (395), the first pre-buried structure (790), and the third pad (720) to be in direct contact with them.

[0057] Meanwhile, prior to forming the second sacrificial spacer membrane (400), a plasma nitriding process may be additionally performed on the bit line structure (395), specifically the third conductive pattern (265) included therein.

[0058] Referring to FIG. 14, an anisotropic etching process can be performed on the second and third sacrificial spacer films (400, 410) to form the second and third sacrificial spacers (405, 415) sequentially stacked on the sidewalls of the bit line structure (395), respectively.

[0059] Accordingly, the upper surface of the first preliminary lower spacer structure (770) included in the first preliminary landfill structure (790), the upper surface of the third pad (720), and the upper surface of the bit line structure (395) may be exposed.

[0060] Referring to FIG. 15, the first sacrificial spacer (755) included in the exposed first preliminary lower spacer structure (770) can be removed, and thereby a third opening (420) that exposes the uppermost surface of the first lower spacer (735) can be formed.

[0061] In exemplary embodiments, the first sacrificial spacer (755) can be removed, for example, through a wet etching process using hydrofluoric acid (HF) as an etchant, and the first lower spacer (735) formed at the bottom can act as an etching stop layer. Accordingly, the bottom surfaces of the third openings (420) formed by removing the first sacrificial spacers (755) formed in each of the plurality of second openings (230) can have the same height as each other.

[0062] Meanwhile, as the first sacrificial spacer (755) is removed, the upper outer wall of the second lower spacer (765) may be exposed.

[0063] Referring to FIG. 16, the third sacrificial spacer (415) formed on the upper part of the exposed second lower spacer (765) and the side wall of the bit line structure (395) can be removed, thereby expanding the width of the third opening (420) and exposing the upper side wall of the first buried pattern (780) and the surface of the second sacrificial spacer (400).

[0064] In exemplary embodiments, the upper part of the second lower spacer (765) and the third sacrificial spacer (415) may be removed through an ashing process using oxygen (O2) and / or a stripping process using hydrofluoric acid (HF).

[0065] In one embodiment, as the upper portion of the second lower spacer (765) is removed, the uppermost surface of the remaining second lower spacer (765) may be formed at substantially the same height as the uppermost surface of the first lower spacer (735).

[0066] Referring to FIG. 17, a second sacrificial spacer (405) formed on the side wall of the bit line structure (395), and a portion of the first buried pattern (780) exposed by the third opening (420) and not covered by the bit line structure (395) can be removed through an etching process.

[0067] After the above etching process, the first buried pattern (780) remaining in the second opening (230) may include a conductive material and may be referred to as a conductive contact plug as it contacts the first metal silicide pattern (105) formed on the bottom surface of the bit line structure (395) and the top surface of the active pattern (103), respectively. The first buried pattern (780) may include a lower portion having a relatively large width and an upper portion formed integrally on the lower portion and having a relatively small width. In one embodiment, the height of the upper surface of the lower portion of the first buried pattern (780) may be substantially the same as the height of the upper surface of the first and second lower spacers (735, 765).

[0068] During the above etching process, the portion of the third pad (720) that is not covered by the bit line structure (395) may also be removed, and accordingly, the upper surface of the first and second pads (700, 710) may be exposed. However, the portion of the third pad (720) formed between the second pad (710) and the bit line structure (395) may remain as a third pad pattern (725).

[0069] Meanwhile, as the above etching process is performed, the width of the third opening (420) can be further expanded.

[0070] Referring to FIG. 18, a second capping film (790) can be formed on the bit line structure (395), the first embedded pattern (780), the first and second lower spacers (735, 765), and the first and second pads (700, 710), for example, through an atomic layer deposition (ALD) process.

[0071] The second capping film (790) may include, for example, an oxide such as silicon oxide, or, for example, an insulating nitride such as silicon nitride.

[0072] Referring to FIG. 19, a second filling film is formed on the second capping film (790) to fill the third opening (420), and the upper part thereof can be removed through an etching process until the upper surface of the first and second pads (700, 710) is exposed.

[0073] During the above etching process, the portion of the second capping film (790) formed outside the third opening (420) may also be removed, and accordingly, the upper surface and side wall of the bit line structure (395), the upper surface of the first and second pads (700, 710), and the side wall of the third pad pattern (725) may be exposed.

[0074] Accordingly, a second capping pattern (795) may remain on the inner wall of the third opening (420), and a second embedding pattern (810) may be formed on the second capping pattern (795). The first and second embedding patterns (780, 810), the first and second lower spacers (735, 765), and the second capping pattern (795) formed within the second opening (230) may together form a first embedding structure. Additionally, the first and second lower spacers (735, 765) formed on the lower side wall of the first embedding pattern (780) may together form a first lower spacer structure.

[0075] The second buried pattern (810) may include an insulating nitride, such as silicon nitride, for example.

[0076] Referring to FIG. 20, a bit line structure (395), first and second pads (700, 710), a third pad pattern (725), and first and second upper spacer films are sequentially formed on a substrate (100) on which the first buried structure is formed, and then anisotropically etched thereon, a first upper spacer (820) can be formed covering the side wall of the bit line structure (395) and a part of the upper surface of the second capping pattern (795) and the second buried pattern (810) included in the first buried structure, and a second upper spacer (830) can also be formed on the outer wall of the first upper spacer (820).

[0077] The first upper spacer (820) may include an insulating nitride, for example, silicon nitride, and the second upper spacer (830) may include an oxide, for example, silicon oxide.

[0078] Afterwards, a dry etching process can be performed using the bit line structure (395) and the first and second upper spacers (820, 830) as an etching mask to form a fourth opening (440) that partially exposes the upper surface of the first and second pads (700, 710).

[0079] Afterward, a third upper spacer film may be formed on the upper surface of the first capping pattern (385) and the first upper spacer (820), the upper surface and outer wall of the second upper spacer (830), a part of the upper surface of the first buried structure, and the upper surface of the first and second pads (700, 710) exposed by the fourth opening (440), and then anisotropically etched to form a third upper spacer (840) covering the outer wall of the second upper spacer (830). At this time, the third upper spacer (840) may also cover a part of the upper surface of the first buried structure. The third upper spacer (840) may include an insulating nitride, such as silicon nitride, for example.

[0080] The first to third upper spacers (820, 830, 840) sequentially stacked on the side wall of the bit line structure (395) can together form a preliminary upper spacer structure (850).

[0081] Referring to FIG. 21, a second sacrificial film (not shown) filling the fourth opening (440) can be formed on the substrate (100) to a sufficient height, and then the upper surface of the first capping pattern (385) can be flattened until the upper surface is exposed to form a second sacrificial pattern (480). In exemplary embodiments, the second sacrificial pattern (480) may be extended in a second direction (D2) and may be formed in multiple numbers spaced apart from each other by bit line structures (395) along the first direction (D1). The second sacrificial pattern (480) may include, for example, an oxide such as silicon oxide.

[0082] Referring to FIGS. 22 and 23, a second mask (not shown) including a plurality of fifth openings that are each extended in a first direction (D1) and spaced apart from each other in a second direction (D2) can be formed on a first capping pattern (385), a second sacrifice pattern (480), and a preliminary upper spacer structure (850), and an etching process can be performed using the second mask as an etching mask to etch the second sacrifice pattern (480), thereby forming a sixth opening that exposes the upper surface of the gate mask (160) of the gate structure (170).

[0083] In exemplary embodiments, each of the fifth openings may overlap the gate structure (170) in the vertical direction, and the sixth opening may be formed in multiple numbers so as to be spaced apart from each other along the second direction (D2) between bit line structures (395) adjacent to each other in the first direction (D1).

[0084] After removing the second mask, a third capping pattern (485) can be formed to fill each of the sixth openings. Depending on the layout of the sixth openings, the third capping pattern (485) may be formed in multiple numbers spaced apart from each other along the second direction (D2) between bit line structures (395) adjacent to each other in the first direction (D1). The third capping pattern (485) may include an insulating nitride, for example, silicon nitride.

[0085] Meanwhile, the second sacrifice pattern (480) can be separated into multiple parts and remain spaced apart from each other in the second direction (D2) between the bit line structures (395).

[0086] Afterward, the remaining second sacrifice patterns (480) can be removed to form seventh openings that partially expose the upper surfaces of the first and second pads (700, 710). At this time, the seventh openings may be formed in multiple numbers so as to be spaced apart from each other along the second direction (D2) between bit line structures (395) adjacent to each other in the first direction (D1).

[0087] Subsequently, a lower contact plug membrane filling the seventh openings can be formed to a sufficient height, and the upper surface can be flattened until the upper surface of the first and third capping patterns (385, 485) and the preliminary upper spacer structure (850) is exposed. Accordingly, the lower contact plug membrane can be converted into a plurality of lower contact plugs (475) spaced apart from each other by the third capping patterns (485) along the second direction (D2) between the bit line structures (395).

[0088] The lower contact plug (475) may include, for example, polysilicon doped with impurities and may be electrically connected to the active pattern (103) by contacting the first pad (700).

[0089] Referring to FIG. 24, the upper part of the lower contact plug (475) is removed to expose the upper part of the preliminary upper spacer structure (850) formed on the side wall of the bit line structure (395), and then the upper parts of the second and third upper spacers (830, 840) of the exposed preliminary upper spacer structure (850) can be removed.

[0090] The upper part of the lower contact plug (475) can be removed, for example, through an etch back process, and the upper parts of the second and third upper spacers (830, 840) can be removed, for example, through a wet etching process.

[0091] Subsequently, by forming a fourth upper spacer film on the bit line structure (395), the preliminary upper spacer structure (850), the lower contact plug (475), and the third capping pattern (485) and anisotropically etching it, a fourth upper spacer (490) can be formed on the outer wall of the first upper spacer (820) portion formed on the upper side wall of the bit line structure (395).

[0092] The fourth upper spacer (490) formed through the above anisotropic etching process can cover the upper surface of the second upper spacer (830) and at least a portion of the upper surface of the third upper spacer (840). Accordingly, during the anisotropic etching process, the upper portion of the lower contact plug (475) may be partially removed, and a portion of the third upper spacer (840) that is not covered by the fourth upper spacer (490) may also be removed together.

[0093] Subsequently, in one embodiment, a fifth upper spacer film (not shown) may be formed on a bit line structure (395), a first upper spacer (820), a fourth upper spacer (490), a lower contact plug (475), and a third capping pattern (485), and the same may be etched to form a fifth upper spacer (not shown) on the side wall of the fourth upper spacer (490), and the upper portion of the lower contact plug (475) may be additionally removed by performing an etching process using these as an etching mask. Accordingly, the upper surface of the lower contact plug (475) may be lower than the upper surface of the second and third spacers (830, 840).

[0094] Subsequently, a second metal silicide pattern (500) can be formed on the upper surface of the lower contact plug (475). In exemplary embodiments, the second metal silicide pattern (500) can be formed by forming a second metal film on the bit line structure (395), the first upper spacer (820), the fourth upper spacer (490), the lower contact plug (475), and the third capping pattern (485), and by performing a heat treatment process to react the second metal film with the silicon component contained in the lower contact plug (475), and the unreacted portion of the second metal film can be removed.

[0095] The second metal silicide pattern (500) may include, for example, cobalt silicide, nickel silicide, titanium silicide, etc.

[0096] Referring to FIG. 25, after forming a second barrier film (530) on a bit line structure (395), a first upper spacer (820), a fourth upper spacer (490), a second metal silicide pattern (500), and a third capping pattern (485), a third metal film (540) can be formed on the second barrier film (530) to fill the space between the bit line structures (395).

[0097] Afterward, a planarization process may be additionally performed on the upper surface of the third metal film (540). The planarization process may include, for example, a chemical mechanical polishing (CMP) process and / or an etch back process.

[0098] Referring to FIGS. 26 and 27, the third metal film (540) and the second barrier film (530) can be patterned to form an upper contact plug (549), and an eighth opening (547) can be formed between the upper contact plugs (549).

[0099] The eighth opening (547) can be formed by partially removing the third metal film (540) and the second barrier film (530), as well as the preliminary upper spacer structure (850) and the fourth upper spacer (490) and the third capping pattern (485) formed on the upper side wall of the insulating structure included in the bit line structure (395), thereby exposing the upper surface of the second upper spacer (830).

[0100] As the eighth opening (547) is formed, the third metal film (540) and the second barrier film (530) can each be converted into a third metal pattern (545) and a second barrier pattern (535) covering the lower surface thereof, and together they can form an upper contact plug (549). In exemplary embodiments, the upper contact plugs (549) may be formed in multiple numbers spaced apart from each other along each first and second direction (D1, D2) and may be arranged in a honeycomb or grid shape when viewed from above. Each upper contact plug (549) may have a circular, elliptical, or polygonal shape when viewed from above.

[0101] A lower contact plug (475), a second metal silicide pattern (500), and an upper contact plug (549) sequentially stacked on a substrate (100) can together form a contact plug structure.

[0102] Afterward, the exposed second upper spacer (830) can be removed to form an air gap (835) communicating with the eighth opening (547). The second upper spacer (830) can be removed, for example, by a wet etching process.

[0103] In exemplary embodiments, the second upper spacer (830) formed on the side wall of the bit line structure (395) extending in the second direction (D2) can be removed not only in the portion directly exposed by the eighth opening (547) but also in the portion parallel to the upper surface of the substrate (100) in the horizontal direction. That is, not only the portion of the second upper spacer (830) exposed by the eighth opening (547) and not covered by the upper contact plug (549) but also the portion covered by the upper contact plug (549) can be removed.

[0104] Referring to FIG. 28, after forming a first insulating pattern (610) on the side wall of the eighth opening (547), a second insulating pattern (620) can be formed to fill the remaining part of the eighth opening (547), and accordingly, the top of the air gap (835) can be closed by these.

[0105] The air gap (835) may be referred to as an air spacer (835) and may form an upper spacer structure (855) together with the first upper spacer (820) and the third upper spacer (840).

[0106] The first insulating pattern (610) can be formed by forming a first insulating film on the inner wall of the eighth opening (547), the upper contact plug (549), and the third capping pattern (485), and by anisotropic etching.

[0107] The second insulation pattern (620) can be formed by forming a second insulation film on the first insulation pattern (610), the upper contact plug (549), and the third capping pattern (485), and performing an etch back process thereon.

[0108] Each of the first and second insulating patterns (610, 620) may include an insulating nitride, such as silicon nitride, for example, and together they may form an insulating pattern structure.

[0109] Subsequently, on the first insulation pattern (620), the upper contact plug (549), and the third capping pattern (485) 2 An etch stop layer (630) may be formed, and a mold layer (not shown) may be formed on the second etch stop layer (630). A ninth opening (not shown) may be formed by etching a portion of the mold layer and a portion of the second etch stop layer (630) formed below it to expose the upper surface of the upper contact plug (549).

[0110] As the upper contact plugs (549) are spaced apart from each other along the first and second directions (D1, D2), for example, arranged in a honeycomb or grid shape when viewed from above, the ninth openings exposing them may also be formed to be arranged in a honeycomb or grid shape when viewed from above.

[0111] Afterward, a lower electrode film is formed on the side wall of the ninth opening, the upper surface of the exposed upper contact plug (549), and the mold film, and a third sacrificial film (not shown) that fills the remaining part of the ninth opening is formed on the lower electrode film, and then the lower electrode film can be node-separated by flattening the upper surface of the lower electrode film and the third sacrificial film until the upper surface of the mold film is exposed.

[0112] Accordingly, a lower electrode (640) having a cylinder shape may be formed within the ninth opening. However, if the width of the ninth opening is small, the lower electrode (640) may be formed to have a pillar shape rather than a cylinder shape. The lower electrode (640) may include, for example, a metal, a metal nitride, a metal silicide, or polysilicon doped with impurities.

[0113] Afterwards, the remaining third sacrificial film and the mold film can be removed by performing a wet etching process, for example, using an LAL solution as an etchant.

[0114] Subsequently, a dielectric film (650) can be formed on the surface of the lower electrode (640) and the second etching stop layer (630). The dielectric film (650) may include, for example, a metal oxide.

[0115] Subsequently, an upper electrode (660) can be formed on the dielectric film (650). The upper electrode (660) may include, for example, a metal, a metal nitride, a metal silicide, or silicon-germanium (SiGe) doped with impurities. In one embodiment, the upper electrode (660) may be formed to include a first upper electrode comprising a metal or a metal nitride and a second upper electrode comprising silicon-germanium (SiGe) doped with impurities.

[0116] The lower electrode (640), dielectric film (650), and upper electrode (660) stacked sequentially can form a capacitor (670) together.

[0117] Afterwards, the manufacturing of the semiconductor device can be completed by additionally forming upper wirings on the capacitor (670).

[0118] As described above, the first preliminary burial structure (790) formed within the second opening (230) may include a first preliminary lower spacer structure (770) formed on the side wall of the first burial pattern (780), and the first preliminary lower spacer structure (770) may include a second lower spacer (765) formed on the side wall of the first burial pattern (780), and a first lower spacer (735) and a first sacrificial spacer (755) formed on the outer wall thereof and stacked in the vertical direction.

[0119] In exemplary embodiments, a first sacrificial spacer (755) is removed to form a third opening (420), and the upper portion of a second lower spacer (765) exposed by the third opening (420) is removed to expand the width of the third opening (420) thereby exposing the upper portion of a first buried pattern (780), and then the exposed upper portion of the first buried pattern (780) can be removed.

[0120] In exemplary embodiments, when the first sacrificial spacer (755) is removed, the first lower spacer (735) formed below the first sacrificial spacer (755) can act as an etching stop layer, and accordingly, the depth of the third openings (420) formed within each of the plurality of second openings (230) can have a substantially constant depth with little variation.

[0121] That is, if the first lower spacer (735) and the first sacrifice spacer (755) are not formed separately and only the first sacrifice spacer (755) is formed, the amount of the first sacrifice spacer (755) removed depends on the process time, and accordingly, the variation in the depth of the third openings (420) formed within each of the plurality of second openings (230) may be very large. However, in exemplary embodiments, the first lower spacer (735) acts as an etching stop layer, so the third openings (420) formed by removing the first sacrifice spacer (755) may have a very small variation in depth, and accordingly, the amount of each first buried pattern (780) portion removed through the third openings (420) may be constant within the plurality of second openings (230), so the semiconductor device including the same may have improved electrical characteristics.

[0122] Additionally, the first sacrificial spacer (755) may include an oxide, such as silicon oxide, for example, and the device isolation pattern (112) formed on the sidewall of the active pattern (103) may also include substantially the same material. Accordingly, if only the first sacrificial spacer (755) is formed without forming a separate first lower spacer (735), and the amount of the first sacrificial spacer (735) removed to form the third opening (420) is not properly controlled and is excessively removed, a defect may occur in which the device isolation pattern (112) in contact with it is removed together.

[0123] However, in exemplary embodiments, a first lower spacer (735) containing a different material is separately present below the first sacrificial spacer (755), and since the height of the upper surface of the first lower spacer (735) is higher than the height of the upper surface of the device separation pattern (112) or the lower surface of the first pad (700), the first lower spacer (735) comes into contact with the device separation pattern (112) instead of the first sacrificial spacer (755), thereby preventing a defect in which the device separation pattern (112) is removed together when the third opening (420) is formed.

[0124] Furthermore, compared to the case where a triple film is formed along the horizontal direction on the side wall of the first embedded pattern (780) to prevent the problem of the device separation pattern (112) being removed together when the third opening (420) is formed as above, the first preliminary lower spacer structure (770) according to exemplary embodiments forms only a double film in the horizontal direction, so even if the size of the second opening (230) is reduced, a margin of space for forming it can be secured.

[0125] The semiconductor device manufactured through the aforementioned processes may have the following structural features.

[0126] Referring to FIGS. 26 and 28, the semiconductor device comprises: an active pattern (103) formed on a substrate (100); a device isolation pattern (112) formed on the substrate (100) and covering the sidewall of the active pattern (103); a gate structure (170) extending in a first direction (D1) and embedded above the active pattern (103) and the device isolation pattern (112); a conductive pad (700) formed on the active pattern (103) and the device isolation pattern (112); a conductive contact plug (780) penetrating the conductive pad (700) and contacting the upper surface of the central portion in a third direction (D3) of the active pattern (103), and comprising a lower portion having a first width and an upper portion having a second width smaller than the first width; and a bit line structure (395) formed on the conductive contact plug (780) and the conductive pad (700) and extending in a second direction (D2). It may include second and first lower spacers (765, 735) comprising different insulating materials that are sequentially stacked in the horizontal direction on the side wall of the lower portion of the conductive contact plug (780); an insulating embedded pattern (810) formed on the first and second lower spacers (735, 765); an upper spacer structure (855) formed on the side wall of the bit line structure (395) and formed on the insulating embedded pattern (810); a contact plug structure (475, 500, 549) formed on the conductive pad (700); and a capacitor (670) formed on the contact plug structure (475, 500, 549), and the height of the upper surface of the first and second lower spacers (735, 765) may be substantially the same as the height of the upper surface of the lower portion of the conductive contact plug (780).

[0127] In exemplary embodiments, a capping pattern (795) covering the upper side wall of the conductive contact plug (780), the upper surface of the lower part of the conductive contact plug (780), and the upper surface of the first and second lower spacers (735, 765) may be further formed.

[0128] In exemplary embodiments, the conductive contact plugs (780) are formed in a plurality of numbers spaced apart from each other along the first and second directions (D2), and accordingly, the first and second lower spacers (735, 765) may also be formed in a plurality of numbers along the first and second directions (D1, D2), and the height of the uppermost surface of the plurality of first lower spacers (735) may be the same.

[0129] FIGS. 29 to 34 are cross-sectional views illustrating a method for manufacturing a semiconductor device according to exemplary embodiments. Since the method for manufacturing the semiconductor device includes processes that are substantially identical or similar to the processes described with reference to FIGS. 1 to 28, a redundant description thereof is omitted.

[0130] Referring to FIG. 29, the first sacrifice pattern (745) can be removed after performing processes that are substantially identical or similar to the processes described with reference to FIGS. 1 through 8.

[0131] Accordingly, the surface of the first lower spacer (735) may be exposed, and subsequently, a first sacrificial spacer film (750) may be formed on the exposed surface of the first lower spacer (735), the side wall of the third recess (235), and the upper surface of the third pad (720), for example, through an atomic layer deposition (ALD) process.

[0132] Referring to FIG. 30, a second pre-filled structure (797) that fills the second opening (230) can be formed by performing processes that are substantially the same or similar to those described with reference to FIG. 11.

[0133] At this time, the second preliminary burial structure (797) may include a first lower spacer (735) formed on the lower side wall and edge bottom surface of the second opening (230), a fourth sacrificial spacer (757) formed on the surface of the first lower spacer (735) and the upper side wall of the second opening (230), a third lower spacer (767) formed on the side wall of the fourth sacrificial spacer (757), and a first burial pattern (780).

[0134] Referring to FIG. 31, the upper part of the fourth sacrificial spacer (757) can be removed to form the tenth opening (422) by performing a process substantially identical or similar to the processes described with reference to FIG. 12 to 15.

[0135] In exemplary embodiments, the upper portion of the fourth sacrifice spacer (757) may be removed through a wet etching process using, for example, hydrofluoric acid (HF) as the etchant. The fourth sacrifice spacer (757) may have a relatively thin thickness at the height of the uppermost surface of the first lower spacer (735), so that during the wet etching process, the etchant is difficult to penetrate to the lower portion of the fourth sacrifice spacer (757), and thus only the upper portion of the fourth sacrifice spacer (757) may be removed.

[0136] Accordingly, unlike what was explained with reference to FIG. 15, the first sacrifice spacer (755) is not completely removed but partially remains, so the fourth sacrifice spacer (757) will be referred to as the fourth lower spacer (757) below.

[0137] Referring to FIG. 32, the upper part of the third lower spacer (767) can be removed by performing a process substantially identical or similar to the processes described with reference to FIG. 16, and accordingly, the width of the tenth opening (422) can be expanded.

[0138] Referring to FIG. 33, by performing processes substantially identical or similar to those described with reference to FIG. 17, the second sacrificial spacer (405) formed on the side wall of the bit line structure (395) and the first buried pattern (780) exposed by the tenth opening (422) that is not covered by the bit line structure (395) can be removed through an etching process.

[0139] Referring to FIG. 34, the manufacture of the semiconductor device can be completed by performing processes that are substantially identical or similar to the processes described with reference to FIG. 18 to FIG. 28.

[0140] By performing the aforementioned processes, a second buried structure may be formed within the second opening (230), comprising first and second buried patterns (780, 810), first, third, and fourth lower spacers (735, 767, 757), and a second capping pattern (795). At this time, the first, third, and fourth lower spacers (735, 767, 757) formed on the lower side wall of the first buried pattern (780) may together form a second lower spacer structure.

[0141] Unlike the semiconductor device illustrated in FIG. 28, the semiconductor device may include a second lower spacer structure having a triple film structure comprising a third lower spacer (767), a fourth lower spacer (757), and a first lower spacer (735) sequentially stacked in the horizontal direction on the lower side wall of the first buried pattern (780). Accordingly, the insulation between the first buried pattern (780) and the first pad (700), each comprising a conductive material, can be enhanced, thereby preventing an electrical short circuit between them.

[0142] In exemplary embodiments, the heights of the top surfaces of the first, third, and fourth lower spacers (735, 767, 757) may be substantially the same as each other.

[0143] FIGS. 35 to 38 are cross-sectional views illustrating a method for manufacturing a semiconductor device according to exemplary embodiments. Since the method for manufacturing the semiconductor device includes processes that are substantially identical or similar to the processes described with reference to FIGS. 29 to 34, a redundant description thereof is omitted.

[0144] Referring to FIG. 35, the upper part of the fourth lower spacer (757) can be removed to form the tenth opening (422) by performing processes substantially identical or similar to those described with reference to FIG. 29 to FIG. 31.

[0145] Compared to what is shown in FIG. 31, during the wet etching process, the fourth lower spacer (757) may be removed not only in the portion higher than the top surface of the first lower spacer (735) but also in the portion lower than it. However, the fourth lower spacer (757) may not be completely removed but may remain partially, and the height of the top surface of the remaining fourth lower spacer (757) may be lower than the height of the top surface of the first lower spacer (735). This may occur because, during the wet etching process, some of the etching solution penetrates into the portion of the fourth lower spacer (757) formed in the portion lower than the height of the top surface of the first lower spacer (735).

[0146] Referring to FIG. 36, by performing processes substantially identical or similar to those described with reference to FIG. 32, the portion of the third lower spacer (767) exposed by the tenth opening (422) can be removed, and accordingly, the width of the tenth opening (422) can be expanded.

[0147] At this time, since the height of the bottom surface of the 10th opening (422) is higher than the height of the top surface of the 1st lower spacer (735), the 3rd lower spacer (767) can be removed more than shown in FIG. 32. The height of the top surface of the remaining 3rd lower spacer (767) can be substantially the same as the height of the top surface of the 4th lower spacer (757), and ultimately lower than the height of the top surface of the 1st lower spacer (735).

[0148] Referring to FIG. 37, by performing processes substantially identical or similar to those described with reference to FIG. 33, the second sacrificial spacer (405) formed on the side wall of the bit line structure (395) and the first buried pattern (780) exposed by the tenth opening (422) that is not covered by the bit line structure (395) can be removed through an etching process.

[0149] Accordingly, the first embedment pattern (780) may include a lower portion having a relatively large width and an upper portion formed integrally on the lower portion having a relatively small width, and the height of the upper surface of the lower portion may be substantially the same as the height of the upper surface of the third and fourth lower spacers (767, 757) and lower than the height of the upper surface of the first lower spacer (735).

[0150] Referring to FIG. 38, the manufacturing of the semiconductor device can be completed by performing processes that are substantially identical or similar to the processes described with reference to FIG. 34.

[0151] FIGS. 39 to 45 are plan views and cross-sectional views for illustrating a method of manufacturing a semiconductor device according to exemplary embodiments. Specifically, FIGS. 39 and 41 are plan views, and FIGS. 40 and 42-45 are cross-sectional views cut along the A-A' line of the corresponding plan views. Since the method of manufacturing the semiconductor device includes processes that are substantially identical or similar to the processes described with reference to FIGS. 1 to 28, a redundant description thereof is omitted.

[0152] Referring to FIGS. 39 and 40, an active pattern (103) and a device isolation pattern (112) can be formed on a substrate (100) by performing processes substantially identical or similar to those described with reference to FIGS. 1 and 2.

[0153] Afterwards, a conductive pad structure (930) can be formed on the active pattern (103) and the device isolation pattern (112).

[0154] The conductive pad structure (930) may include fourth to sixth pads (900, 910, 920) sequentially stacked along the vertical direction. In exemplary embodiments, the fourth pad (900) may include, for example, impurity-doped polysilicon, the fifth pad (910) may include, for example, a metal silicide such as titanium silicide, cobalt silicide, nickel silicide, etc., a metal nitride such as titanium nitride, tantalum nitride, tungsten nitride, etc., or a metal silicon nitride such as titanium silicon nitride, tantalum silicon nitride, etc., and the sixth pad (920) may include, for example, a metal such as tungsten, ruthenium, etc. That is, compared to the first pad (700) shown in FIGS. 3 and 4 having a single film structure, the conductive pad structure (930) may have a composite film structure.

[0155] Subsequently, a conductive pad structure (930) can be patterned through an etching process to form a first opening (940) that exposes the upper surface of the active pattern (103), the device isolation pattern (112), and the gate structure (170), and the upper surface of the active pattern (103) and the device isolation pattern (112) can also be partially removed during the etching process.

[0156] The eleventh opening (940) may have a layout corresponding to the first opening described with reference to FIGS. 3 and 4. That is, the eleventh opening (940) may include a first part extending in a first direction (D1) and a second part extending in a second direction (D2), and these may be connected to each other. Accordingly, the conductive pad structure (930) may be formed in a plurality of such that they are spaced apart from each other along the first and second directions (D1, D2) when viewed from above, and arranged in a grid shape.

[0157] In exemplary embodiments, the conductive pad structure (930) may be positioned to overlap along a vertical direction perpendicular to the upper surface of the substrate (100) at the end of each active pattern (103) extending in the third direction (D3) and at the part of the device isolation pattern (112) adjacent thereto in the first direction (D1).

[0158] Referring to FIGS. 41 and 42, an insulating pad film structure (980) can be formed to fill the 11th opening (940) on a conductive pad structure (930).

[0159] In exemplary embodiments, the insulating pad film structure (980) may include sequentially stacked seventh to ninth pad films (950, 960, 970), and the seventh pad film (950) may fill the eleventh opening (940). In exemplary embodiments, the seventh and ninth pad films (950, 970) may include an insulating nitride, for example, silicon nitride, and the eighth pad film (960) may include a metal oxide, for example, hafnium oxide, zirconium oxide, etc.

[0160] Afterwards, a 10th pad film is formed on an insulating pad film structure (980) and patterned to form a 10th pad (990). Then, the 12th opening (995) can be formed by using the etching mask to partially etch the gate mask (160) included in the lower insulating pad film structure (980), conductive pad structure (930), active pattern (103), device isolation pattern (112), and gate structure (170).

[0161] The 12th opening (995) may have substantially the same layout as the 2nd opening (230) described with reference to FIGS. 5 and 6. That is, the 10th pad (990) may have a circular or elliptical shape when viewed from above and may be formed in multiple numbers spaced apart from each other along the first and second directions (D1, D2) on the substrate (100). In this case, each 10th pad (990) may overlap in the vertical direction with the end portions of the active patterns (103) adjacent to each other in the first direction (D1) and the portion of the device separation pattern (112) between them.

[0162] Referring to FIG. 43, a first preliminary landfill structure (790) that fills the 12th opening (995) can be formed by performing processes substantially identical or similar to those described with reference to FIG. 7 through FIG. 11.

[0163] In one embodiment, the height of the uppermost surface of the first lower spacer (735) included in the first pre-buried structure (790) may be higher than the upper surface of the fifth pad (910) included in the conductive pad structure (930).

[0164] Referring to FIG. 44, by performing processes substantially identical or similar to those described with reference to FIG. 12 to FIG. 17, a first embedding pattern (780) and first and second lower spacers (735, 765) can be formed within the 12th opening (995).

[0165] Meanwhile, the ninth pad film (970) included in the insulating pad film structure (980) may remain as a ninth pad pattern (975) only at the bottom of the bit line structure (395).

[0166] Referring to FIG. 45, the manufacture of the semiconductor device can be completed by performing processes that are substantially identical or similar to the processes described with reference to FIG. 18 to FIG. 28.

[0167] In exemplary embodiments, the lower contact plug (475) may include a metal such as tungsten, for example, in addition to impurity-doped polysilicon, and in this case, the contact plug structure may include both the lower and upper contact plugs (475, 549) of the same metal. Accordingly, a second metal silicide pattern (500) may not be formed between the lower and upper contact plugs (475, 549).

[0168] In exemplary embodiments, the lower contact plug (475) can be electrically connected to the active pattern (103) through the fourth to sixth pads (900, 910, 920) by contacting the upper surface of the sixth pad (920) included in the conductive pad structure (930).

[0169] As described above, a conductive pad structure (930) and an insulating pad film structure (980) may be formed on the active pattern (103) and the device isolation pattern (112), and a first pre-buried structure (790) may be formed within a 12th opening (995) that penetrates them to expose the active pattern (103) and the device isolation pattern (112).

[0170] When forming a third opening (420) by removing the first sacrificial spacer (755) included in the first pre-filled structure (790), the first lower spacer (735) can act as an etching barrier, and the height of the uppermost surface of the first lower spacer (735) may be higher than the upper surface of the fifth pad (910) included in the conductive pad structure (930). Accordingly, since the height of the bottom surface of the third opening (420) is higher than the height of the upper surface of the fifth pad (910), which includes, for example, metal silicide, a defect in which the fifth pad (910) is also removed when the first sacrificial spacer (755) is removed can be prevented.

[0171] If a separate first lower spacer (735) is not formed and only the first sacrificial spacer (755) is formed, when the first sacrificial spacer (755) is removed to form the third opening (420), the first sacrificial spacer (755) may be excessively removed, causing the height of the bottom surface of the third opening (420) to be lower than the height of the top surface of the fifth pad (910), and consequently, the fifth pad (910) may be removed together. To prevent this, it is necessary to increase the thickness of the sixth pad (920) which is included in the conductive pad structure (930) and formed on the fifth pad (910).

[0172] However, in exemplary embodiments, the height of the bottom surface of the third opening (420) cannot be lower than the height of the top surface of the fifth pad (910) due to the first lower spacer (735) formed below the first sacrificial spacer (755), so the thickness of the sixth pad (920) containing metal can be avoided unnecessarily.

[0173] FIGS. 46 and 47 are plan and cross-sectional views for illustrating semiconductor devices according to exemplary embodiments. The semiconductor devices may be similar to the semiconductor devices described with reference to FIGS. 34 and 38, but are manufactured through a process of forming a conductive pad structure (930) and an insulating pad film structure (980) on an active pattern (103) and a device isolation pattern (112) as described with reference to FIGS. 39 through 45.

[0174] Accordingly, with reference to FIG. 46, a third lower spacer (767), a fourth lower spacer (757), and a first lower spacer (735) may be sequentially stacked along a horizontal direction parallel to the upper surface of the substrate (100) on the lower side wall of the first embedded pattern (780). In one embodiment, the height of the uppermost surface of the first, third, and fourth lower spacers (735, 757, 767) may be higher than the height of the upper surface of the fifth pad (910) included in the conductive pad structure (930).

[0175] Meanwhile, referring to FIG. 47, a third lower spacer (767), a fourth lower spacer (757), and a first lower spacer (735) may be sequentially stacked along the horizontal direction on the lower side wall of the first embedding pattern (780). In exemplary embodiments, the height of the upper surface of the first lower spacer (735) may be higher than the height of the upper surface of the fifth pad (910) included in the conductive pad structure (930).

[0176] In exemplary embodiments, the height of the top surface of the third and fourth lower spacers (757, 767) may be lower than the height of the top surface of the first lower spacer (735). Explanation of the symbols

[0177] 100: Substrate 103: Active pattern 105, 500: 1st and 2nd metal silicide patterns 112: Device isolation pattern 120: Gate isolation pattern 130, 535: 1st and 2nd barrier patterns 140, 150, 265: 1st to 3rd challenge patterns 160: Gate Mask 170: Gate Structure 230, 420, 440, 547, 422, 940, 995: 2nd, 3rd, 4th, 8th, 10th, 11th, 12th openings 235: 3rd recess 245: Adhesion pattern 275: First mask 365: First etch stop pattern 385, 795, 485: 1st to 3rd capping patterns 395: Bit line structure 475, 549: Lower, upper contact plugs 530: Second barrier membrane 540: Third metal membrane 545: Third metal pattern 610, 620: First and second insulation patterns 630: Second etch stop layer 640, 660: Lower and upper electrodes 650: Dielectric film 670: Capacitor 700, 710, 720, 900, 910, 920, 950, 960, 970, 990: 1st to 10th pads 725, 975: 3rd and 9th pad patterns 730, 760: 1st and 2nd lower spacer membranes 735, 765, 767, 757: 1st to 4th lower spacers 770, 777: 1st and 2nd preliminary lower spacer structures 750, 810: 1st and 2nd landfill patterns 760: 1st Landfill Structure 780: 1st Sacrifice Pattern 790, 797: 1st and 2nd preliminary landfill structures 820, 830, 840, 490: 1st to 4th upper spacers 850: Reserve upper spacer structure 930; Conductive pad structure 980: Insulating pad membrane structure

Claims

Claim 1 A conductive contact plug formed on a substrate and comprising a lower portion having a first width and an upper portion having a second width smaller than the first width; a bit line structure formed on the conductive contact plug and comprising a conductive structure and an insulating structure stacked along a vertical direction perpendicular to the upper surface of the substrate; and first to third lower spacers sequentially stacked in a horizontal direction parallel to the upper surface of the substrate from the side wall of the lower portion of the conductive contact plug, wherein the upper surface of the third lower spacer is higher than the upper surface of the first and second lower spacers. Claim 2 A semiconductor device according to claim 1, wherein the height of the uppermost surface of the first and second lower spacers is the same. Claim 3 In claim 1, the first to third lower spacers each comprise silicon oxycarbon (SiOC), silicon oxide, and silicon nitride, forming a semiconductor device. Claim 4 A semiconductor device according to claim 1, further comprising: a capping pattern covering the side wall of the upper portion of the conductive contact plug, the upper surface of the lower portion of the conductive contact plug, the upper surfaces of the first and second lower spacers, and the upper surface and upper side wall of the third lower spacer; and an insulating embedded pattern formed on the capping pattern. Claim 5 A semiconductor device according to claim 1, wherein an active pattern and a device isolation pattern covering the sidewalls thereof are formed on the substrate, and the conductive contact plug contacts the upper surface of the central part of the active pattern. Claim 6 A semiconductor device according to claim 5, wherein the height of the uppermost surface of the third lower spacer is higher than the height of the upper surface of the element isolation pattern. Claim 7 A semiconductor device comprising: an active pattern formed on a substrate; a device isolation pattern covering the sidewall of the active pattern; a conductive contact plug in contact with the upper surface of the active pattern; a bit line structure formed on the conductive contact plug; a conductive pad structure formed on the active pattern and the device isolation pattern, overlapping in a horizontal direction parallel to at least a portion of the conductive contact plug and the upper surface of the substrate, and including first to third pads sequentially stacked in a vertical direction perpendicular to the upper surface of the substrate; and first and second lower spacers stacked in the horizontal direction on the sidewall of the conductive contact plug, wherein the height of the uppermost surface of the second lower spacer is higher than the height of the upper surface of the second pad. Claim 8 A semiconductor device according to claim 7, wherein the height of the uppermost surface of the first and second lower spacers is the same. Claim 9 In claim 7, the first to third pads each comprise a semiconductor device comprising impurity-doped polysilicon, metal silicide, and metal. Claim 10 An active pattern formed on a substrate; a device isolation pattern formed on the substrate and covering the sidewall of the active pattern; a gate structure extending in a first direction parallel to the upper surface of the substrate and embedded above the active pattern and the device isolation pattern; a conductive pad structure formed on the active pattern and the device isolation pattern; a conductive contact plug penetrating the conductive pad structure and contacting the upper surface of the central part of the active pattern, comprising a lower portion having a first width and an upper portion having a second width smaller than the first width; a bit line structure formed on the conductive contact plug and the conductive pad structure and extending in a second direction parallel to the upper surface of the substrate and perpendicular to the first direction; and first and second lower spacers comprising different insulating materials, sequentially stacked in a horizontal direction parallel to the upper surface of the substrate on the sidewall of the lower portion of the conductive contact plug. A semiconductor device comprising: an insulating embedded pattern formed on the first and second lower spacers; an upper spacer structure formed on the insulating embedded pattern and formed on the side wall of the bit line structure; a contact plug structure formed on the conductive pad structure; and a capacitor formed on the contact plug structure, wherein the height of the uppermost surface of the first and second lower spacers is the same as the height of the upper surface of the lower conductive contact plug.

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