Semiconductor package and method for fabricating the same

Abstract

The present invention comprises a substructure and an upper redistribution layer provided on the substructure, wherein the substructure comprises a first bump layer including a bump pattern, a lower redistribution layer including a plurality of first lower redistribution layers stacked on the first bump layer, a semiconductor chip mounted on the lower redistribution layer, a molding film covering the semiconductor chip on the lower redistribution layer, a conductive pillar provided on the lower redistribution layer and penetrating the molding film, and an under pad layer disposed on the molding film and including an under pad, and the upper redistribution layer comprises a second bump layer including an upper bump pattern, and a plurality of second lower redistribution layers stacked between the second bump layer and the under pad layer, wherein each of the plurality of first lower redistribution layers includes a lower redistribution pattern, and the lower redistribution pattern includes a first line portion and a first via portion, wherein the width of the first via portion increases as it extends in a vertical direction toward the first line portion from its bottom surface, and each of the plurality of second lower redistribution layers includes an upper redistribution pattern, and the upper The rewiring pattern includes a second line portion and a second via portion, wherein the second via portion is provided on the second line portion, and the second via portion provides a semiconductor package in which its width increases as it extends in a vertical direction toward the second line portion from its upper surface.

Description

Technology Field

[0001] The present invention relates to a semiconductor package and a method for manufacturing the same, and more specifically, to a fan-out package and a method for manufacturing the same. Background Technology

[0002] In the semiconductor industry, the increasing demand for high capacity, thinness, and miniaturization of semiconductor devices and electronic products utilizing them has led to the rapid emergence of various related packaging technologies. A semiconductor package is an integrated circuit chip implemented in a form suitable for use in electronic products. Typically, semiconductor packages involve mounting semiconductor chips on a printed circuit board (PCB) and electrically connecting them using bonding wires or bumps. With the advancement of the electronics industry, there is a growing demand for high functionality, high speed, and miniaturization of semiconductor packages. The problem to be solved

[0003] The problem that the present invention aims to solve is to provide a semiconductor package and a method for manufacturing the same that improves problems such as a decrease in process yield as the FRDL formation, assembly process, and BRDL process proceed sequentially during the semiconductor package process. means of solving the problem

[0004] An embodiment according to the present invention comprises a lower structure and an upper redistribution layer provided on the lower structure, wherein the lower structure comprises a first bump layer including a bump pattern, a lower redistribution layer including a plurality of first lower redistribution layers stacked on the first bump layer, a semiconductor chip mounted on the lower redistribution layer, a molding film covering the semiconductor chip on the lower redistribution layer, a conductive pillar provided on the lower redistribution layer and penetrating the molding film, and an under pad layer disposed on the molding film and including an under pad, and the upper redistribution layer comprises a second bump layer including an upper bump pattern, and a plurality of second lower redistribution layers stacked between the second bump layer and the under pad layer, wherein each of the plurality of first lower redistribution layers includes a lower redistribution pattern, and the lower redistribution pattern includes a first line portion and a first via portion, wherein the width of the first via portion increases as it extends in a vertical direction toward the first line portion from its bottom surface, and each of the plurality of second lower redistribution layers includes an upper redistribution pattern The upper rewiring pattern includes a second line portion and a second via portion, wherein the second via portion is provided on the second line portion, and the second via portion includes a semiconductor package in which its width increases as it moves in a vertical direction toward the second line portion from its upper surface.

[0005] An embodiment according to the present invention comprises a method for manufacturing a semiconductor package, comprising forming a substructure on a first carrier, forming the substructure by forming a first bump layer including a bump pattern on the first carrier, forming a lower redistribution layer on the first bump layer, forming a conductive pillar extending vertically on the lower redistribution layer, mounting a semiconductor chip on the lower redistribution layer, forming a molding film covering the semiconductor chip and the conductive pillar on the lower redistribution layer, wherein the molding film exposes the upper surface of the conductive pillar and forms an under pad layer on the molding film including an under pad in contact with the upper surface of the conductive pillar, forming an upper redistribution layer on a second carrier, wherein the upper redistribution layer includes an upper bonding pad at its uppermost portion, and bonding the substructure and the upper redistribution layer together so that the under pad and the upper bonding pad are connected to each other, and removing the first carrier and the second carrier. Effects of the invention

[0006] According to the present invention, a semiconductor package can be manufactured by separately fabricating a rear structure and an upper redistribution layer. Accordingly, the manufacturing process of the semiconductor package according to the present invention can shorten the process time of the semiconductor package compared to a process of forming a rear structure and then directly forming an upper redistribution layer on the rear structure. Brief explanation of the drawing

[0007] FIG. 1 is a cross-sectional view showing one embodiment of a semiconductor package of the present invention. Figure 2 is an enlarged view of area A in Figure 1. Figure 3 is an enlarged view of area B in Figure 1. Figure 4 is an enlarged view of area C in Figure 1. Figure 5 is a diagram showing the formation of a redistribution layer and a conductive column. Figure 6 is a diagram showing the die being mounted on the redistribution layer. Figure 7 is a diagram showing the formation of a molding film on a redistribution layer. Figure 8 is a drawing showing the formation of an underpad layer on a molding film and a conductive column. FIG. 9 is a drawing showing the formation of a second bump layer and first to third upper redistribution layers. FIG. 10 is a diagram showing the formation of a second insulating film on a third lower redistribution layer. FIG. 11 is a drawing showing the first carrier and the second carrier aligned facing each other. FIG. 12 is a drawing showing the lower structure bonded to the upper redistribution layer, after which the first carrier is separated and an external terminal is attached. Figure 13 is a diagram showing the second carrier separated. FIG. 14 is a drawing showing the formation of a first insulating film on a molding film and a conductive column. FIG. 15 is a diagram showing the formation of an opening in the first insulating film. FIG. 16 is a diagram showing the formation of a seed pad layer on the opening and the first insulating film. Figure 17 is a diagram showing the formation of a conductive layer on a seed pad layer. FIGS. 18a to 18c are drawings showing embodiments of an under pad. FIG. 19 is a drawing showing a second insulating layer and an upper bonding pad protruding on the second insulating layer. Figure 20 is a diagram showing that a second insulating film has been formed. Figure 21 is a drawing showing the polishing of the second insulating film. FIG. 22 is a drawing showing an application example of a semiconductor package according to the present invention. Specific details for implementing the invention

[0008] In order to fully understand the structure and effects of the present invention, preferred embodiments of the present invention will be described in detail with reference to the attached drawings.

[0009] Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 1 to 22.

[0010] FIG. 1 is a cross-sectional view showing one embodiment of a semiconductor package of the present invention. FIG. 2 is an enlarged view of region A in FIG. 1, FIG. 3 is an enlarged view of region B in FIG. 1, and FIG. 4 is an enlarged view of region C in FIG. 1.

[0011] Referring to FIGS. 1 to 4, a semiconductor package (PKG) according to the present embodiment may include a substructure (FSTL), an upper redistribution layer (URL), and external terminals (SB). The substructure (FSTL) may include a lower redistribution layer (RLL), a die (DIE), a molding film (MOL), conductive pillars (CPIL), and an under-pad layer (NPL). The substructure (FSTL) may be a structure including a front redistribution layer of the semiconductor package (PKG).

[0012] The lower redistribution layer (RLL) may include a first bump layer (BPL1), a first lower redistribution layer (RLL1), a second lower redistribution layer (RLL2), and a third lower redistribution layer (RLL3) that are sequentially stacked. The first bump layer (BPL1) may include first bump patterns (BUMP). The first lower redistribution layer (RLL1) may include first lower redistribution patterns (RDP1). The second lower redistribution layer (RLL2) may include second lower redistribution patterns (RDP2). The third lower redistribution layer (RLL3) may include lower bonding pads (RDP3). The upper portion of each of the lower bonding pads (RDP3) may protrude over the third lower redistribution layer (RLL3). Each of the first lower redistribution patterns (RDP1), the second lower redistribution patterns (RDP2), and the lower bonding pads (RDP3) may include a first seed pattern (SP1) and a conductive pattern (CP) thereon. The first seed patterns (SP1) may include a conductive seed material. The conductive seed material may include copper, titanium, and / or an alloy thereof.

[0013] The number of redistribution layers and redistribution patterns in the lower redistribution layer (RLL) may be varied without being limited to what is described.

[0014] Referring to FIG. 2, a first lower redistribution pattern (RDP1) among the first and second lower redistribution patterns (RDP1, RDP2) and lower bonding pads (RDP3) of the lower redistribution layer (RLL) is exemplified. The first lower redistribution pattern (RDP1) may include a first line portion (LP1) and a first via portion (VP1).

[0015] The first via (VP1) may include a portion of the first seed pattern (SP1) and a portion of the conductive pattern (CP) on the first seed pattern. A first line portion (LP1) may be provided on the first via (VP1). The upper surface (LP1a) of the first line portion (LP1) may be in contact with the first insulating layer (PL1), a portion of a separate redistribution pattern, or a portion of the lower bonding pad. A portion of the lower surface (LP1b) of the first line portion (LP1) may be connected to the upper surface (VP1a) of the first via (VP1). The first via (VP1) may be provided between the first line portion (LP1) and the lower bump pattern (or a separate redistribution pattern). The first line portion (LP1) may be electrically connected to the lower bump pattern (or a separate redistribution pattern) through the first via (VP1).

[0016] The first via (VP1) may have a first width (W1). The first width (W1) may be defined as the length from one side of the first via (VP1) to the opposite side. The first width may increase in the direction toward the upper surface (VP1a) of the first via (VP1) from the lower surface (VP1b) of the first via (VP1), i.e., the second direction (D2). The width at the lower surface (VP1b) of the first via may be smaller than the width at the upper surface (VP1a) of the first via (VP1).

[0017] The lower redistribution layer (RLL) may include a plurality of first insulating layers (PL1). The first insulating layers (PL1) may include an organic material, for example, a photo-imageable dielectric (PID) material. The photo-imageable dielectric material may be a polymer. The photo-imageable dielectric material may include at least one of, for example, photosensitive polyimide, polybenzoxazole, phenolic polymer, and benzocyclobutene polymer. The number of stacked first insulating layers (PL1) may vary. For example, a plurality of first insulating layers (PL1) may include the same material. The interface between adjacent first insulating layers (PL1) may not be distinguishable.

[0018] A plurality of lower bump patterns (BUMP) may be provided below the first lower redistribution layer (RLL1). The lower bump patterns (BUMP) may each be connected to the first lower redistribution patterns (RDP1). A plurality of external terminals (SB) may each be provided below the lower bump patterns (BUMP). The lower bump patterns (BUMP) may be interposed between the external terminals (SB) and the first lower redistribution pattern (RDP1) to connect them to each other. For example, the external terminals (SB) may be solder balls. For example, the external terminals (SB) may include tin, bismuth, lead, silver, or an alloy thereof.

[0019] A die (DIE) may be provided on the lower redistribution layer (RLL). The die (DIE) may be a semiconductor chip. For example, the semiconductor chip may include any one of a logic chip, a memory chip, and a power management chip. The semiconductor chip may include an ASIC chip or an application processor (AP) chip. The ASIC chip may include an application-specific integrated circuit (ASIC). As another example, the die (DIE) may include a Central Processing Unit (CPU) or a Graphics Processing Unit (GPU).

[0020] A die (DIE) may have an upper and lower surface facing each other. The lower surface of the die (DIE) may face the lower redistribution layer (RLL) and may be an active surface. The upper surface of the die (DIE) may be an inactive surface. For example, the die (DIE) may include a semiconductor substrate, integrated circuits, and connection members (ECT). The semiconductor substrate may include silicon, germanium, and / or silicon-germanium. The semiconductor substrate may be a silicon wafer. The integrated circuits may be adjacent to the lower surface of the die (DIE). The connection members (ECT) may be connected to the integrated circuits. Being electrically connected to the die (DIE) may mean being electrically connected to the integrated circuits of the die (DIE) through the external connection members (ECT) of the die (DIE).

[0021] Unlike what is described, additional dies (i.e., semiconductor chips) may be mounted on the lower redistribution layer (RLL). In other words, multiple dies (DIE) may be mounted on the lower redistribution layer (RLL).

[0022] External connection members (ECTs) of the die (DIE) can be placed on the lower bonding pads (RDP3) of the lower redistribution layer (RLL), respectively. By connecting the connection members (ECTs) to the lower bonding pads (RDP3), the die (DIE) and the lower redistribution layer (RLL) can be electrically connected to each other. As an example, the external connection members (ECTs) may include microbumps.

[0023] At least one conductive pillar (CPIL) may be provided on the lower redistribution layer (RLL). The conductive pillar (CPIL) may be provided on the edge region of the lower redistribution layer (RLL). The conductive pillar (CPIL) may be horizontally spaced from the die (DIE). The conductive pillar (CPIL) may extend from its lower surface in a direction perpendicular to the lower surface, i.e., a second direction (D2). As described below, the conductive pillar (CPIL) may penetrate the interior of the molding film (MOL).

[0024] The conductive pillar (CPIL) can be connected to the corresponding lower bonding pad (RDP3). In other words, the conductive pillar (CPIL) can be electrically connected to the lower redistribution layer (RLL). For example, the conductive pillar (CPIL) can be electrically connected to the die (DIE) or external terminals (SB) through the lower redistribution layer (RLL). The conductive pillar (CPIL) may be a metal pillar containing a metal such as copper.

[0025] A molding film (MOL) may be provided on the lower redistribution layer (RLL) to cover the die (DIE). The molding film (MOL) may cover the sidewalls of the conductive pillars (CPIL). The sidewalls of the molding film (MOL) may be aligned with the sidewalls of the lower redistribution layer (RLL). The molding film (MOL) may expose the upper surface (CPILa) of the conductive pillars (CPIL). For example, the molding film (MOL) may comprise an insulating polymer, such as an epoxy-based molding compound.

[0026] An underpad layer (NPL) may be provided on the upper surface (CPILa) of a conductive pillar (CPIL) and the upper surface (MOLa) of a molding film (MOL). The underpad layer (NPL) may include at least one underpad (NPD) and a first insulating film (PID1). The underpad (NPD) may be provided on the upper surface (CPLIa) of a conductive pillar (CPIL). The underpad (NPD) may be directly connected to the conductive pillar (CPIL).

[0027] The under pad (NPD) may include a seed pad (SDP) and a conductive pad (CD) above it. The seed pad (SDP) may include a conductive seed material. The conductive seed material may include copper, titanium, and / or an alloy thereof. A first insulating film (PID1) may be provided on the upper surface (MOLa) of the molding film (MOL).

[0028] The under pad layer (NPL) may expose the upper surface of the under pad (NPD). The under pad (NPD) may not protrude above the under pad layer (NPL). In other words, the level of the under pad (NPD) may be the same as the level of the first insulating film (PID1). In this specification, the level may refer to a vertical level, and the level may be measured in a second direction, which is a direction perpendicular to the bottom surface from the bottom surface to the top surface. The fact that the levels of certain components are the same may mean the sameness of the error range that may occur during the process.

[0029] Referring to FIG. 4, when the upper surface (MOLa) of the molding film (MOL) is viewed in magnification, the upper surface (MOLa) of the molding film may not be flat. For example, the flatness (Total Thickness Variation, TV) of the upper surface of the molding film may be 1 to 10 micrometers. The flatness (TV) of the upper surface (MOLa) of the molding film may vary depending on the particle size of the molding compound. A first insulating film (PID1) may be provided on the upper surface of the molding film (MOL). There may not be any voids between the molding film (MOL) and the first insulating film (PID1). In other words, the upper surface (MOLa) of the molding film and the lower surface of the first insulating film (PID1) may be in close contact with each other without any gaps.

[0030] An upper redistribution layer (URL) may be provided on a substructure (FSTL). The upper redistribution layer (URL) may include a back redistribution layer of a semiconductor package (PKG). The upper redistribution layer (URL) may include a second bump layer (BPL2), a first upper redistribution layer (URL1), a second upper redistribution layer (URL2), a third upper redistribution layer (URL3), and an upper pad layer (UPL).

[0031] The second bump layer (BPL2) may include upper bump patterns (UMP). The first upper redistribution layer (URL1) may include first upper redistribution patterns (URP1). The second upper redistribution layer (URL2) may include second upper redistribution patterns (URP2). The third upper redistribution layer (URL3) may include upper bonding pads (URP3) and a second insulating film (PID2). The upper bonding pad (URP3) may be connected to the upper surface (CPILa) of the conductive pillar (CPIL) through an under pad (NPD). The under pad (NPD) may be interposed between the upper bonding pad (URP3) and the conductive pillar (CPIL) electrically connected thereto. The second insulating film (PID2) may be provided on the first insulating film (PID1). The upper bonding pads (URP3) may not protrude below the third upper rewiring layer (URL3).

[0032] Each of the first upper redistribution patterns (URP1), the second upper redistribution patterns (URP2), and the upper bonding pads (URP3) may include a second seed pattern (SP2) and a conductive pattern (CP) underneath. The second seed patterns (SP2) may include a conductive seed material. The conductive seed material may include copper, titanium, and / or an alloy thereof.

[0033] The number of redistribution layers and redistribution patterns in the upper redistribution layer (URL) may be varied without being limited to what is described.

[0034] Referring to FIG. 3, a first upper rewiring pattern (URP1) among the first and second upper rewiring patterns (URP1, URP2) and upper bonding pads (RDP3) of the upper rewiring layer (URL) is exemplified. The first upper rewiring pattern (URP1) may include a second line portion (LP2) and a second via portion (VP2).

[0035] The second via (VP2) may include a portion of the second seed pattern (SP2) and a portion of the conductive pattern (CP) below the second seed pattern. The second via (VP2) may be provided on the second line portion (LP2). The lower surface (LP2b) of the second line portion (LP2) may be in contact with the second insulating layer (PL2), a portion of a separate redistribution pattern, or a portion of the upper bonding pad. A portion of the upper surface (LP2a) of the second line portion (LP2) may be connected to the lower surface (VP1b) of the second via (VP2). The second via (VP2) may be provided between the second line portion (LP2) and the upper bump pattern (or a separate redistribution pattern). The second line portion (LP2) may be electrically connected to the upper bump pattern (or a separate redistribution pattern) through the second via (VP2).

[0036] The second via (VP2) may have a second width (W2). The second width (W2) may be defined as the length from one side of the second via (VP2) to the opposite side. The second width may decrease as it goes in the direction from the lower surface (VP1b) of the second via (VP2) toward the upper surface (VP2a) of the second via (VP2), that is, the second direction (D2). The width at the lower surface (VP2b) of the second via may be greater than the width at the upper surface (VP2a) of the second via (VP2).

[0037] The upper bonding pads (URP3) can be connected to the under pad (NPD). The conductive pattern (CP) of each upper bonding pad (URP3) can be directly connected to the conductive pad (CD) of the under pad (NPD).

[0038] The upper bump patterns (UBP) can be electrically connected to a die (DIE) or external terminals (SB) through first and second upper rewiring patterns (URP1, URP2), upper bonding pads (URP3), under pads (NPD), and conductive pillars (CPIL). Since the first and second upper rewiring patterns (URP1, URP2), etc. are provided, the upper bump patterns (UBP) can be positioned offset from the conductive pillars (CPIL).

[0039] The upper redistribution layer (URL) may include a plurality of second insulating layers (PL2). The second insulating layers (PL2) may include an organic material, for example, a photo-imageable dielectric (PID) material. The photo-imageable dielectric material may be a polymer. The photo-imageable dielectric material may include at least one of, for example, a photosensitive polyimide, a polybenzoxazole, a phenolic polymer, and a benzocyclobutene polymer. The number of stacked second insulating layers (PL2) may vary. For example, a plurality of second insulating layers (PL2) may include the same material. The interface between adjacent second insulating layers (PL2) may not be distinguishable.

[0042] FIGS. 5 to 13 are drawings sequentially illustrating a method for manufacturing an embodiment of a semiconductor package according to the present invention. FIGS. 14 to 18 are drawings illustrating a specific process for forming region D of FIG. 8. FIGS. 19 to 21 are drawings illustrating a specific process for forming region E of FIG. 10. Hereinafter, an embodiment of a method for manufacturing a semiconductor package according to the present invention will be described in detail with reference to FIGS. 5 to 21.

[0043] FIGS. 5 to 8 are drawings showing the formation of a substructure.

[0044] Referring to FIG. 5, an adhesive film (RL), a peel film (SM), and a redistribution layer (RSUB) may be sequentially provided on a first carrier (CA1). A conductive pillar (CPIL) may be formed on the redistribution layer (RSUB). As described below, the adhesive film (RL) may be removed by irradiating it with a laser.

[0045] Forming the lower redistribution layer (RLL) may include sequentially forming a first bump layer (BPL1), a first lower redistribution layer (RLL1), a second lower redistribution layer (RLL2), and a third lower redistribution layer (RLL3) on a first carrier (CA1).

[0046] The first bump layer (BPL1) may include lower bump patterns (BUMP). The first lower redistribution layer (RLL1) may include first lower redistribution patterns (RDP1). The second lower redistribution layer (RLL2) may include second lower redistribution patterns (RDP2). The third lower redistribution layer (RLL3) may include lower bonding pads (RDP3). The number of redistribution layers and redistribution patterns in the lower redistribution layer (RLL) may vary without being limited to what is shown in the drawings.

[0047] The formation of each lower bump pattern (BUMP), the first and second lower redistribution patterns (RDP1, RDP2) and the lower bonding pads (RDP3) can be achieved through a photoresist process after forming the first insulating layer (PL1) for each layer.

[0048] Specifically, forming each of the first to third lower redistribution layers (RLL1, RLL2, RLL3) may include forming a first insulating layer, forming an opening in the first insulating layer, forming a seed layer within the opening, and performing an electroplating process to form a conductive layer on the seed layer. Thus, each of the first to third lower redistribution layers (RLL1, RLL2, RLL3) may include a plurality of redistribution patterns formed spaced apart from each other.

[0049] At least one conductive pillar (CPIL) may be formed on the lower redistribution layer (RLL). The conductive pillar (CPIL) may be provided on the edge region of the lower redistribution layer (RLL). The conductive pillar (CPIL) may be connected to a corresponding lower bonding pad (RDP3). In other words, the conductive pillar (CPIL) may be electrically connected to the lower redistribution layer (RLL).

[0050] FIG. 6 is a diagram showing mounting a die on a redistribution layer. Referring to FIG. 6, a die (DIE) can be mounted on a lower redistribution layer (RLL). The die (DIE) may be a semiconductor chip.

[0051] A die (DIE) may have an upper and lower surface facing each other. The lower surface of the die (DIE) may face the lower redistribution layer (RLL) and may be an active surface. The upper surface of the die (DIE) may be an inactive surface. For example, the die (DIE) may include a semiconductor substrate, integrated circuits, and connection members (ECT). The integrated circuits may be adjacent to the lower surface of the die (DIE). The connection members (ECT) may be connected to the integrated circuits. That a component is electrically connected to the die (DIE) may mean that it is electrically connected to the integrated circuits of the die (DIE) through the external connection members (ECT) of the die (DIE).

[0052] Unlike what is described, an additional die (i.e., a semiconductor chip) can be mounted on the lower redistribution layer (RLL).

[0053] Referring to FIG. 7, a molding film (MOL) is formed on the lower redistribution layer (RLL) to cover the die (DIE). The molding film (MOL) can cover the sidewalls of the conductive pillars (CPIL). The sidewalls of the molding film (MOL) can be aligned with the sidewalls of the lower redistribution layer (RLL).

[0054] The molding film (MOL) may include an insulating polymer such as an epoxy-based molding compound. For example, forming the molding film (MOL) may include applying heat and pressure to the molding compound to liquefy it and then curing it. Subsequently, the cured molding film may further include grinding. By grinding, the level of the molding film (MOL) may be equal to or smaller than the level of the conductive pillar (CPIL). By grinding, the upper surface (MOLa) of the molding film (MOL) may have a rough surface. For example, the flatness of the upper surface of the molding film may be 1 to 10 micrometers. The molding film (MOL) may expose the upper surface (CPILa) of the conductive pillar (CPIL).

[0055] FIG. 8 is a diagram illustrating the formation of an underpad layer on a molding film and a conductive column. Referring to FIG. 8, an underpad layer (NPL) may be formed on the upper surface (MOLa) of the molding film and the upper surface (CPILa) of the conductive column. The underpad layer (NPL) may include at least one underpad (NPD) and a first insulating film (PID1). The underpad (NPD) may be formed on the upper surface (CPILa) of the conductive column.

[0056] The process of forming the under pad (NPD) is explained in detail with reference to FIGS. 14 to 18a.

[0057] Referring to FIGS. 8 and FIGS. 14, a first insulating film (PID1) may be provided on a molding film (MOL) and a conductive pillar (CPIL).

[0058] Referring to FIGS. 8 and FIGS. 15, an opening (OPN) can be formed within the first insulating film (PID1) so that the upper surface (CPILa) of the conductive pillar (CPIL) is exposed. Forming the opening (OPN) may include a process of etching the first insulating film (PID1) using a photoresist.

[0059] Referring to FIGS. 8 and FIGS. 16, a seed pad layer (SDL) may be provided on an opening (OPN) and a first insulating film (PID1). The seed pad layer (SDL) may include a conductive seed material. The conductive seed material may include copper, titanium, and / or an alloy thereof.

[0060] Referring to FIG. 17, a conductive layer (CPL) can be formed on a seed pad layer (SPL). Forming the conductive layer (CPL) may include electroplating a conductive material. Referring to FIG. 8 and FIG. 18a, a polishing process may be performed to remove a portion of the upper surface of the conductive layer (CPL) and the seed pad layer (SPL). The polishing process may include a Chemical Mechanical Planarization (CMP) process. By the polishing process, seed pads (SDP) and conductive patterns (CP) spaced apart from each other may be provided. By the polishing process, the upper surface of the conductive pattern (CP), i.e., the upper surface of the under pad (NPD), may have the same level as the upper surface of the first insulating film (PID1).

[0061] FIGS. 18b and FIGS. 18c are drawings showing various embodiments of the under pad in FIG. 18a of the present invention.

[0062] Referring to FIGS. 18a and 18b, the under pad (NPD) may have an under pad width (NPDW). The under pad width (NPDW) may be defined as the length from one side of the under pad (NPD) to the opposite side. The conductive pillar (CPIL) may have a conductive pillar width (PILW). The conductive pillar width (PILW) may be defined as the length from one side of the conductive pillar (CPIL) to the opposite side.

[0063] In one embodiment according to the present invention, the underpad width (NPDW) may be the same as the conductive pillar width (PILW) (Fig. 18a).

[0064] In one embodiment according to the present invention, the underpad width (NPDW) may be smaller than the conductive pillar width (PILW) (Fig. 18b).

[0065] In one embodiment according to the present invention, the underpad width (NPDW) may be larger than the conductive pillar width (PILW) (Fig. 18c).

[0066] If the upper redistribution layer is bonded immediately after the molding film grinding process, a void may be formed between the molding film and the upper redistribution layer due to the rough surface of the upper surface of the molding film. Additionally, a problem of undulation may occur in the upper redistribution layer bonded to the upper surface of the molding film. However, in the case of the present invention, as described above, an under-pad layer including a first insulating film is provided, so there can be no gap between the upper surface of the molding film and the under-pad layer. Furthermore, since the upper surface of the under-pad layer is flat, the problem of undulation in the upper redistribution layer can be resolved.

[0067] Figures 9 and 10 are drawings showing the formation of an upper redistribution layer.

[0068] FIG. 9 is a drawing showing the formation of a second bump layer and first to third upper redistribution layers. FIG. 10 is a drawing showing the formation of a second insulating film on the third lower redistribution layer.

[0069] Referring to FIGS. 9 and 10, a second carrier (CA2) and an upper redistribution layer (URL) on the second carrier (CA2) may be provided.

[0070] The upper redistribution layer (URL) may include a second bump layer (BPL2), a first upper redistribution layer (URL1), a second upper redistribution layer (URL2), a third upper redistribution layer (URL3), and an upper pad layer (UPL) that are sequentially stacked. The second bump layer (BPL2) may include upper bump patterns (UMP). The first upper redistribution layer (URL1) may include first upper redistribution patterns (URP1). The second upper redistribution layer (URL2) may include second upper redistribution patterns (URP2). The third upper redistribution layer (URL3) may include upper bonding pads (URP3) and a second insulating film (PID2). The number of redistribution layers and redistribution patterns in the upper redistribution layer (URL) may vary without being limited to what is shown in the drawings.

[0071] The formation of each upper bump pattern (UBP), the first and second upper redistribution patterns (URP1, URP2) and the upper bonding pads (URP3) can be achieved through a photoresist process after forming a second insulating layer (PL2) for each layer.

[0072] Forming each of the upper bump patterns (UBP), the first and second upper redistribution patterns (URP1, URP2), and the upper bonding pads (URP3) can be done in the same way as forming the redistribution layer (RSUP) in FIG. 5.

[0073] The third upper redistribution layer (URL3) may further include a second insulating film (PID2). With further reference to FIGS. 19 to 21, the process of forming the second insulating film (PID2) will be explained in detail.

[0074] Referring to FIGS. 10 and 19, forming a third upper redistribution layer (URL3) includes forming an upper bonding pad (URP3) on a second insulating layer (PL2). The upper bonding pad (URP3) may include a second seed pattern (SP2) and a conductive pattern (CP) on the second seed pattern (SP2). The upper bonding pad (URP3) may have a protruding shape on the second insulating layer (PL2).

[0075] Referring to FIGS. 10 and 20, a second insulating film (PID2) may be formed on the second insulating layer (PL2) and the upper bonding pad (URP3). The second insulating film (PID2) may cover the second insulating layer (PL2) and the upper bonding pads (URP3).

[0076] Referring to FIGS. 10 and FIGS. 21, a process for polishing the second insulating film (PID2) may be provided. By this process, the level of the upper surface of the second insulating film (PID2) may be the same as the level of the upper surface of the upper bonding pads (URP3).

[0078] FIGS. 11 to 13 are drawings sequentially illustrating the joining of a lower structure and an upper redistribution layer. FIG. 11 is a drawing showing a first carrier and a second carrier aligned facing each other. FIG. 12 is a drawing showing the first carrier separated and an external terminal attached after joining the lower structure to the upper redistribution layer. FIG. 13 is a drawing showing the second carrier separated.

[0079] Referring to FIGS. 11 through 13, the second carrier (CA2) can be inverted so that the upper surface (URLa) of the upper redistribution layer (URL) faces the upper surface (FSTLa) of the lower structure (FSTL). The upper redistribution layer (URL) and the lower structure (FSTL) can be aligned with each other so that the upper bonding pads (URP3) of the upper redistribution layer (URL) are vertically overlapped with the under pads (NPD) of the lower structure (FSTL), respectively. Redistribution layer lower structure

[0080] Referring to FIG. 12, upper bonding pads (URP3) can be bonded to under pads (NPD) respectively. A process of bonding the first insulating film (PID1) to the second insulating film (PID2) can be performed. Accordingly, the upper redistribution layer (URL) can be attached to the lower structure (FSTL). The bonding process between the upper bonding pads (URP3) and the under pads (NPD) may include a high-speed surface bonding process using Ar plasma (Surface activated bonding).

[0081] After the bonding process is completed, a laser can be irradiated onto the first carrier (CA1) in a second direction (D2) to remove the adhesive film (RL). Accordingly, the first carrier (CA1) can be separated from the substructure (FSTL). Subsequently, a process for removing the peel film (SM) can be performed. A plurality of external terminals (SB) may be provided under the lower bump patterns (BUMP). For example, the external terminals (SB) may be solder balls.

[0082] Referring to FIG. 13, the second carrier (CA2) can be separated from the upper redistribution layer (URL). Separating the second carrier (CA2) can be done in the same way as separating the first carrier (CA1). After separating the second carrier (CA2), a process for removing the peel film (SM) can be performed.

[0084] In the case of a conventional process (hereinafter referred to as the conventional process) in which a process for forming a front redistribution layer on a carrier, a die mounting process, a molding film forming process, and a process for forming a rear redistribution layer on the molding film are sequentially performed, the carrier may be damaged as a repetitive thermal process is performed during the rear redistribution layer forming process. However, according to the present invention, the front redistribution layer and the rear redistribution layer are formed separately and joined together, thereby preventing damage to the carrier. In addition, the lifespan of the carrier can be extended.

[0085] In the case of existing processes, there is a problem in that even if a defect occurs during the manufacturing process of the rear redistribution layer, the front redistribution layer and the die attached thereto must all be discarded. However, according to the present invention, since the rear redistribution layer is manufactured individually, even if a defect occurs during the manufacturing of the rear redistribution layer, only the relevant rear redistribution layer can be discarded. In addition, the process yield of the present invention can be increased compared to the existing process.

[0086] In the case of the conventional process, an adhesive is required to attach a carrier to the rear redistribution layer. However, according to the present invention, a second carrier is provided, so a separate bonding process is not required. In addition, according to the present invention, there can be an advantage in terms of cost compared to the conventional process.

[0087] In the case of conventional processes, since the process of forming the rear redistribution layer proceeds after the molding film formation process, a curing temperature condition for the molding member is required. However, according to the present invention, since the process of forming the rear redistribution layer is performed separately, the selection range of the molding member can be expanded.

[0088] In the case of conventional processes, heat is applied when forming an insulating layer in each redistribution layer, so there is a problem that the reliability of the semiconductor package decreases as the number of accumulated heat processes accumulates after the formation of the insulating layer. However, according to the present invention, since the front redistribution layer and the rear redistribution layer are formed separately, the number of accumulated heat processes applied to each redistribution layer is reduced, and the reliability of the semiconductor package can be improved.

[0089] According to the present invention, a process of forming a first insulating film on a molding film is performed after forming a molding film. This can solve the problem of the rear redistribution layer becoming undulated during the process of laminating a rear redistribution layer on the upper surface of the molding film after the molding film grinding process.

[0092] FIG. 22 is a drawing showing an application example of a semiconductor package according to the present invention.

[0093] Referring to FIG. 22, a semiconductor package according to the present embodiment may include a lower semiconductor package (LPKG) and an upper semiconductor package (UPKG). The lower semiconductor package (LPKG) may include a lower structure (FSTL), external terminals (SB), and an upper redistribution layer. The lower structure may include a lower redistribution layer (RLL), connection terminals (IM), a first die (DIE1), a second die (DIE2), a molding film (MOL), an under-pad layer (NPL), conductive pillars (CPIL), and an upper redistribution layer (URL).

[0094] The lower redistribution layer (RLL) may include a first bump layer (BPL1), a first lower redistribution layer (RLL1), a second lower redistribution layer (RLL2), and a third lower redistribution layer (RLL3) that are sequentially stacked. The first lower redistribution layer (RLL1) may include first lower redistribution patterns (RDP1). The second lower redistribution layer (RLL2) may include second lower redistribution patterns (RDP2). The third lower redistribution layer (RLL3) may include lower bonding pads (RDP3). The upper portion of each of the lower bonding pads (RDP3) may protrude over the third lower redistribution layer (RLL3). Each of the first lower redistribution patterns (RDP1), the second lower redistribution patterns (RDP2), and the lower bonding pads (RDP3) may include a first seed pattern (SP1) and a conductive pattern (CP) above it. The first seed patterns (SP1) may include a conductive seed material. The conductive seed material may include copper, titanium, and / or alloys thereof.

[0095] A plurality of lower bump patterns (BUMP) may be provided below the first lower redistribution layer (RLL1). The lower bump patterns (BUMP) may each be connected to the first lower redistribution patterns (RDP1). A plurality of external terminals (SB) may each be provided below the lower bump patterns (BUMP). The lower bump patterns (BUMP) may be interposed between the external terminals (SB) and the first lower redistribution pattern (RDP1) to connect them to each other. For example, the external terminals (SB) may be solder balls. For example, the external terminals (SB) may include tin, bismuth, lead, silver, or an alloy thereof.

[0096] A first die (DIE1) and a second die (DIE2) may be provided on a lower redistribution layer (RLL). The second die (DIE2) and the first die (DIE1) may be mounted side by side in a first direction (D1) on the lower redistribution layer (RLL).

[0097] The first die (DIE1) may be a semiconductor chip of a different type from the semiconductor chip (SMC) of the second die (DIE2). For example, the first die (DIE1) may include any one of a logic chip, a memory chip, and a power management chip, and the second die (DIE2) may include another one of a logic chip, a memory chip, and a power management chip.

[0098] Unlike what is described, an additional die (i.e., a semiconductor chip) can be mounted on the lower redistribution layer (RLL).

[0099] External connection members (ECTs) of the first die (DIE1) can be placed on the lower bonding pads (RDP3) of the lower redistribution layer (RLL), respectively. By connecting the connection members (ECTs) to the lower bonding pads (RDP3), the first die (DIE1) and the lower redistribution layer (RLL) can be electrically connected to each other.

[0100] Connection terminals (IM) may be interposed between the second die (DIE2) and the lower bonding pads (RDP3) of the lower redistribution layer (RLL). The second die (DIE2) and the lower redistribution layer (RLL) may be electrically connected to each other through the connection terminals (IM). For example, the connection terminals (IM) may include microbumps.

[0101] At least one conductive pillar (CPIL) may be provided on the lower redistribution layer (RLL). The conductive pillar (CPIL) may be provided on the edge region of the lower redistribution layer (RLL). The conductive pillar (CPIL) may be horizontally spaced from the second die (DIE2) and the first die (DIE1).

[0102] The conductive pillar (CPIL) can be connected to the corresponding lower bonding pad (RDP3). In other words, the conductive pillar (CPIL) can be electrically connected to the lower redistribution layer (RLL). For example, the conductive pillar (CPIL) can be electrically connected to the first die (DIE1), the second die (DIE2), or external terminals (SB) through the lower redistribution layer (RLL). The conductive pillar (CPIL) may be a metal pillar containing a metal such as copper.

[0103] A molding film (MOL) may be provided on a lower redistribution layer (RLL) to cover the first die (DIE1) and the second die (DIE2). The molding film (MOL) may cover the sidewalls of the conductive pillars (CPIL). The sidewalls of the molding film (MOL) may be aligned with the sidewalls of the lower redistribution layer (RLL). The molding film (MOL) may expose the upper surface (CPILa) of the conductive pillars (CPIL). For example, the molding film (MOL) may comprise an insulating polymer, such as an epoxy-based molding compound.

[0104] An under-pad layer (NPL) may be provided on the upper surface of a molding film (MOL). The under-pad layer (NPL) may include an under-pad (NPD) and a first insulating film (PID1). The under-pad (NPD) may be provided on a conductive pillar (CPIL). The under-pad (NPD) may be electrically connected to the upper surface (CPLIa) of the conductive pillar. The under-pad (NPD) may include a seed pad (SDP) and a conductive pad (CD) above it. The seed pad may include a conductive seed material. The conductive seed material may include copper, titanium, and / or an alloy thereof. The first insulating film (PID1) may be provided on the upper surface of the molding film (MOL).

[0105] The under pad layer (NPL) may expose the upper surface of the under pad (NPD). The under pad (NPD) may not protrude above the under pad layer (NPL). In other words, the level of the under pad (NPD) may be the same as the level of the first insulating film (PID1).

[0106] An upper redistribution layer (URL) may be provided on an under pad (NPD). The upper redistribution layer (URL) may include a second bump layer (BPL2), a first upper redistribution layer (URL1), a second upper redistribution layer (URL2), a third upper redistribution layer (URL3), and an upper pad layer (UPL).

[0107] The second bump layer (BPL2) may include upper bump patterns (UMP). The first upper redistribution layer (URL1) may include first upper redistribution patterns (URP1). The second upper redistribution layer (URL2) may include second upper redistribution patterns (URP2). The third upper redistribution layer (URL3) may include upper bonding pads (URP3) and a second insulating film (PL2). The upper bonding pads (URP3) may be connected to the upper surface (CPILa) of the conductive pillar (CPIL). The second insulating film (PID2) may be provided on the first insulating film (PID1). The upper bonding pads (URP3) may not protrude below the third upper redistribution layer (URL3).

[0108] Each of the first upper rewiring patterns (URP1), the second upper rewiring patterns (URP2), and the upper bonding pads (URP3) may include a second seed pattern (SP2) and a conductive pattern (CP) underneath.

[0109] The upper bonding pads (URP3) can be connected to the under pad (NPD). The conductive pattern (CP) of each upper bonding pad can be directly connected to the conductive pad (CD) of the under pad.

[0110] The upper bump patterns (UBP) can be electrically connected to a die (DIE) or external terminals (SB) through first and second upper rewiring patterns (URP1, URP2), upper bonding pads (URP3), under pads (NPD), and conductive pillars (CPIL). Since the first and second upper rewiring patterns (URP1, URP2), etc. are provided, the upper bump patterns (UBP) can be positioned offset from the conductive pillars (CPIL).

[0111] An upper semiconductor package (UPKG) may be provided on a lower semiconductor package (LPKG). For example, the upper semiconductor package (UPKG) may be mounted on an upper redistribution layer (URL). The upper semiconductor package (UPKG) may include an upper substrate (USUB), a third die (DIE3), and an upper molding film (UMOL). For example, the upper substrate (USUB) may be a printed circuit board. As another example, the upper substrate (USUB) may be a redistribution substrate such as the lower redistribution layer (RLL) of the lower semiconductor package (LPKG).

[0112] A first conductive pad (CPD1) and a second conductive pad (CPD2) may be disposed on the lower and upper surfaces, respectively, of an upper substrate (USUB). A wiring (INL) may be provided within the upper substrate (USUB) to be connected to the first conductive pad (CPD1) and the second conductive pad (CPD2). The illustration of the wiring (INL) is schematic, and the shape and arrangement of the wiring (INL) may be varied. The first conductive pad (CPD1), the second conductive pad (CPD2), and the wiring (INL) may include a conductive material such as metal.

[0113] A third die (DIE3) may be placed on an upper substrate (USUB). The third die (DIE3) may include an integrated circuit (not shown), and said integrated circuit may include a memory circuit, a logic circuit, or a combination thereof. The third die (DIE3) may be a semiconductor chip of a different type from the second die (DIE2) and the first die (DIE1). For example, the third die (DIE3) may be a memory chip. A connection terminal (IM) may be interposed between the second conductive pad (CPD2) and the second die (DIE2) to connect the upper substrate (USUB) and the third die (DIE3) to each other. The third die (DIE3) may be electrically connected to the first conductive pad (CPD1) through the connection terminal (IM) and wiring (INL).

[0114] An upper molding film (UMOL) is provided on an upper substrate (USUB) to cover a third die (DIE3). The upper molding film (UMOL) may include an insulating polymer, such as an epoxy-based polymer.

[0115] The top semiconductor package (UPKG) may further include a heat dissipation structure (HES). The heat dissipation structure (HES) may include a heat sink, a heat slug, or a layer of heat transfer material. For example, the heat dissipation structure (HES) may include a metal. The heat dissipation structure (HES) may be disposed on the upper surface of the top molding film (UMOL). The heat dissipation structure (HES) may also extend further onto the sidewall of the top molding film (UMOL).

[0116] Upper external terminals (BP) may be provided between the lower semiconductor package (LPKG) and the upper semiconductor package (UPKG). The upper external terminals (BP) may be interposed between the upper bonding pad (URP3) and the first conductive pad (CPD1) to connect the lower semiconductor package (LPKG) and the upper semiconductor package (UPKG) to each other. For example, the upper semiconductor package (UPKG) may be electrically connected to the third die (DIE3), the first die (DIE1), or the second external terminals (SB) through the upper external terminals (BP). The electrical connection of the upper semiconductor package (UPKG) may mean an electrical connection with the integrated circuit within the second die (DIE2). The upper external terminals (BP) may include solder, bumps, or a combination thereof. The upper external terminals (BP) may include solder material.

[0118] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing its technical concept or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0120] FSTL: Substructure URL: Upper redistribution layer DIE: Die MOL: Molding film

Claims

Claim 1 A substructure; and an upper redistribution layer provided on the substructure, wherein the substructure comprises: a first bump layer having a bump pattern; a lower redistribution layer comprising a plurality of first redistribution layers stacked on the first bump layer; a semiconductor chip mounted on the lower redistribution layer; a molding film covering the upper surface and sides of the semiconductor chip on the lower redistribution layer; a conductive pillar provided on the lower redistribution layer and penetrating the molding film; and an underpad layer disposed on the molding film, wherein the underpad layer comprises an underpad and a first insulating film covering the sides of the underpad, and the upper redistribution layer comprises: a second bump layer having an upper bump pattern; A semiconductor package comprising a plurality of second redistribution layers stacked between the second bump layer and the under pad layer, wherein each of the plurality of first redistribution layers includes a lower redistribution pattern, the lower redistribution pattern includes a first line portion and a first via portion, the width of the first via portion increases as it extends in a vertical direction toward the first line portion from its bottom surface, and each of the plurality of second redistribution layers includes an upper redistribution pattern, the upper redistribution pattern includes a second line portion and a second via portion, the second via portion is provided on the second line portion, the width of the second via portion increases as it extends in a vertical direction toward the second line portion from its top surface, the under pad is disposed on the conductive column, the level of the upper surface of the under pad is different from the level of the upper surface of the molding film, and the level of the lower surface of the under pad is the same as the level of the upper surface of the molding film. Claim 2 A semiconductor package according to claim 1, wherein the level of the upper surface of the under pad and the level of the upper surface of the first insulating film are the same, so that the upper surface of the lower structure is flat. Claim 3 A semiconductor package according to claim 1, wherein there is no empty gap between the molding film and the first insulating film. Claim 4 A semiconductor package according to claim 1, wherein the upper redistribution layer further comprises upper bonding pads and a second insulating film, the second insulating film is provided between the second redistribution layer and the under pad layer, and the upper bonding pads and the second insulating film are provided on the upper surface of the under pad layer. Claim 5 A semiconductor package according to claim 4, wherein the level of the lower surface of the upper bonding pads and the level of the lower surface of the second insulating film are the same, so that the lower surface of the upper redistribution layer is flat. Claim 6 Forming a substructure on a first carrier, wherein forming the substructure comprises: forming a first bump layer including a bump pattern on the first carrier; forming a lower redistribution layer on the first bump layer; forming a conductive pillar extending vertically on the lower redistribution layer; mounting a semiconductor chip on the lower redistribution layer; forming a molding film covering the semiconductor chip and the conductive pillar on the lower redistribution layer, wherein the molding film exposes the upper surface of the conductive pillar; and forming an underpad layer on the molding film including an underpad in contact with the upper surface of the conductive pillar, wherein forming an upper redistribution layer on a second carrier, wherein the upper redistribution layer includes an upper bonding pad at its uppermost portion; and bonding the substructure and the upper redistribution layer together so that the underpad and the upper bonding pad are connected to each other; and removing the first carrier and the second carrier, wherein forming the upper redistribution layer comprises: forming a second insulating film to cover the upper bonding pad; A method for manufacturing a semiconductor package that includes polishing the second insulating film so that the upper surface of the upper bonding pad is exposed, and by polishing, the levels of the second insulating film and the upper bonding pad are equal so that the upper surface of the upper redistribution layer is flat. Claim 7 delete Claim 8 delete Claim 9 A method for manufacturing a semiconductor package according to claim 6, wherein the lower redistribution layer includes a lower redistribution pattern, the lower redistribution pattern includes a first line portion and a first via portion, and the width of the first via portion increases as it extends in a vertical direction toward the first line portion from its bottom surface. Claim 10 A method for manufacturing a semiconductor package according to claim 6, wherein the upper redistribution layer includes an upper redistribution pattern, the upper redistribution pattern includes a second line portion and a second via portion, and the width of the second via portion increases as it extends in a vertical direction toward the second line portion from its bottom surface.

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