Display device, method of manufacturing the same and tiled display device including the same

Abstract

A display device according to one embodiment comprises a first substrate including a first contact hole, a first barrier insulating layer disposed on the first substrate and including second contact holes that overlap with the first contact hole, pad electrodes disposed on the first barrier insulating layer and having at least a portion disposed within the second contact holes, a display layer disposed on the pad electrodes, and a flexible film disposed on the lower portion of the first substrate and electrically connected to the pad electrodes through the first contact hole and the second contact holes, wherein the first substrate includes a substrate buffer portion that overlaps with the first contact hole and does not overlap with the second contact holes.

Description

Technology Field

[0001] The present invention relates to a display device, a method for manufacturing the same, and a tile-type display device including the same. Background Technology

[0002] As the information society develops, the demand for display devices for displaying images is increasing in various forms. For example, display devices are being applied to a wide range of electronic devices, such as smartphones, digital cameras, laptop computers, navigation systems, and smart televisions. Display devices may be flat panel display devices, such as Liquid Crystal Display Devices, Field Emission Display Devices, and Organic Light Emitting Display Devices. Among these flat panel display devices, light-emitting display devices include light-emitting elements in which each pixel of the display panel can emit light independently, thereby enabling the display of images without a backlight unit that provides light to the display panel.

[0003] When manufacturing display devices in large sizes, the increase in the number of pixels can lead to an increase in the defect rate of light-emitting elements and a decrease in productivity or reliability. To address this, a tile-type display can realize a large screen by connecting multiple display devices that are relatively small in size. A tile-type display may include boundary areas called seams between multiple display devices due to the non-display areas or bezel areas of each of the adjacent display devices. When a single image is displayed across the entire screen, these boundary areas create a sense of discontinuity, thereby reducing the immersion of the image. Prior art literature

[65535] Japanese Patent Publication No. 2018-005004 The problem to be solved

[0004] The problem that the present invention aims to solve is to provide a display device capable of preventing damage to a substrate during the manufacturing process of the display device, a method for manufacturing the same, and a tile-type display device including the same.

[0005] The problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0006] A display device according to one embodiment for solving the above problem comprises a first substrate including a first contact hole, a first barrier insulating layer disposed on the first substrate and including second contact holes that overlap with the first contact hole, pad electrodes disposed on the first barrier insulating layer and having at least a portion disposed within the second contact holes, a display layer disposed on the pad electrodes, and a flexible film disposed on the lower portion of the first substrate and electrically connected to the pad electrodes through the first contact hole and the second contact holes, wherein the first substrate may include a substrate buffer portion that overlaps with the first contact hole and does not overlap with the second contact holes.

[0007] The thickness of the substrate buffer portion may be smaller than the thickness of the first substrate that does not overlap with the first contact hole.

[0008] The first substrate may include sub-contact holes that overlap with the first contact hole and overlap with the second contact holes.

[0009] The above substrate buffer portion is positioned around the sub-contact holes and can surround the sub-contact holes.

[0010] The above substrate buffer portion overlaps with the first barrier insulating layer and can surround the second contact holes.

[0011] The thickness of the substrate buffer portion may be 0.5㎛ to 1.5㎛.

[0012] The above pad electrodes include a first metal layer and a second metal layer disposed on the first metal layer, and the first metal layer may be disposed adjacent to the flexible film.

[0013] The apparatus further includes a second barrier insulating layer and a second substrate disposed between the pad electrode and the display layer, wherein the second barrier insulating layer covers the pad electrodes and the second substrate may be disposed on the second barrier insulating layer.

[0014] The device further includes a connection film disposed between the flexible film and the pad electrodes, wherein the connection film can electrically connect the pad electrodes and the flexible film.

[0015] The above display layer may include a thin-film transistor layer disposed on the pad electrodes, a light-emitting element layer disposed on the thin-film transistor layer, a wavelength conversion layer disposed on the light-emitting element layer, and a color filter layer disposed on the wavelength conversion layer.

[0016] Additionally, a method for manufacturing a display device according to one embodiment may include the steps of: preparing a first substrate; forming a first barrier insulating layer on one surface of the first substrate and forming first contact holes in the first barrier insulating layer; forming pad electrodes on the first barrier insulating layer and the first contact holes; forming a display layer on the pad electrodes; etching the other surface of the first substrate that overlaps with the first contact holes to form first grooves; etching the other surface of the first substrate including the first grooves to form second contact holes; and electrically connecting a flexible film on the pad electrodes.

[0017] The first grooves can be formed to overlap with the first contact holes of the first barrier insulation layer and the pad electrodes.

[0018] The second etching above can etch the first substrate to form sub-contact holes that expose the pad electrodes, and a substrate buffer portion that does not overlap with the first contact holes.

[0019] The first substrate in the area overlapping with the first grooves is completely removed to form the sub-contact holes that expose the pad electrodes, and the first substrate in the area not overlapping with the first grooves is partially removed to form the substrate buffer portion.

[0020] The above second etching can remove the first substrate by a predetermined thickness to form a second groove on the bottom surface in which the first grooves are arranged.

[0021] Sub-contact holes that expose the pad electrodes and a substrate buffer portion that does not overlap with the first contact holes can be formed by etching the first substrate disposed within the second groove a third time.

[0022] The above third etching can be performed using an atmospheric pressure plasma etching process.

[0023] The first etching and the second etching can be performed using a pulsed laser etching process.

[0024] Additionally, a method for manufacturing a display device according to one embodiment may include the steps of: preparing a first substrate; forming a first barrier insulating layer on one surface of the first substrate and forming first contact holes in the first barrier insulating layer; forming pad electrodes on the first barrier insulating layer and the first contact holes; forming a display layer on the pad electrodes; etching the other surface of the first substrate that overlaps with the first contact hole to form a second contact hole; etching the first substrate disposed within the second contact hole to form sub-contact holes that expose the pad electrodes and a substrate buffer portion that does not overlap with the first contact holes; and electrically connecting a flexible film on the pad electrodes.

[0025] Additionally, a tile-type display device according to one embodiment includes a plurality of display devices, each including a display area having a plurality of pixels and a non-display area surrounding the display area, and a coupling member for combining the plurality of display devices, wherein each of the plurality of display devices includes a first substrate having a first contact hole, a first barrier insulating layer disposed on the first substrate and having second contact holes that overlap with the first contact hole, pad electrodes disposed on the first barrier insulating layer and having at least a portion disposed within the second contact holes, a display layer disposed on the pad electrodes, and a flexible film disposed on the lower part of the first substrate and electrically connected to the pad electrodes through the first contact hole and the second contact holes, and the first substrate may include a substrate buffer portion that overlaps with the first contact hole and does not overlap with the second contact holes.

[0026] Specific details of other embodiments are included in the detailed description and drawings. Effects of the invention

[0027] According to the display device according to the embodiments, the method of manufacturing the same, and the tile-type display device including the same, a substrate buffer portion of the first substrate is formed in the process of etching the first substrate, thereby preventing the second substrate from being damaged by a laser.

[0028] The effects according to the embodiments are not limited to those exemplified above, and a wider variety of effects are included in this specification. Brief explanation of the drawing

[0029] FIG. 1 is a plan view showing a tile-type display device according to one embodiment. FIG. 2 is a plan view showing a display device according to one embodiment. Figure 3 is a cross-sectional view taken along the line I-I' of Figure 2. Figure 4 is an enlarged view of area A of Figure 3. FIG. 5 is a bottom view showing a first contact hole portion of a display device according to one embodiment. FIG. 6 is a bottom view showing a display device according to one embodiment. FIGS. 7 to 16 are drawings showing a method for manufacturing a display device according to one embodiment, by process. FIG. 17 is a plan view showing the combined structure of a tile-type display device according to one embodiment. Figure 18 is a cross-sectional view taken along the line II-II' of Figure 17. FIGS. 19 to 22 are cross-sectional views showing a method for manufacturing a display device according to another embodiment, by process. FIGS. 23 to 26 are cross-sectional views showing a method for manufacturing a display device according to another embodiment, by process. Specific details for implementing the invention

[0030] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims.

[0031] When elements or layers are referred to as being "on" another element or layer, this includes cases where another layer or element is interposed directly on or in the middle of another element. Throughout the specification, the same reference numerals refer to the same components. Shapes, sizes, ratios, angles, numbers, etc., disclosed in the drawings for describing embodiments are exemplary and therefore the invention is not limited to the depicted details.

[0032] Although terms such as "first," "second," etc., are used to describe various components, it goes without saying that these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, it goes without saying that the first component mentioned below may also be the second component within the technical scope of the present invention.

[0033] The features of each of the various embodiments of the present invention may be combined or combined with one another, either partially or wholly, and may technically enable various interlocking and operation. Each embodiment may be implemented independently of one another or may be implemented together in an associated relationship.

[0034] Specific embodiments will be described below with reference to the attached drawings.

[0035] FIG. 1 is a plan view showing a tile-type display device according to one embodiment.

[0036] Referring to FIG. 1, a tile-type display device (TD) may include a plurality of display devices (10). The plurality of display devices (10) may be arranged in a grid pattern, but are not limited thereto. The plurality of display devices (10) may be connected in a first direction (X-axis direction) or a second direction (Y-axis direction), and the tile-type display device (TD) may have a specific shape. For example, each of the plurality of display devices (10) may have the same size as each other, but is not limited thereto. As another example, the plurality of display devices (10) may have different sizes.

[0037] Each of the plurality of display devices (10) may have a rectangular shape including a long side and a short side. The plurality of display devices (10) may be arranged such that their long sides or short sides are connected to one another. Some of the display devices (10) may be placed at the edges of the tile-type display device (TD) to form one side of the tile-type display device (TD). Other of the display devices (10) may be placed at the corners of the tile-type display device (TD) to form two adjacent sides of the tile-type display device (TD). Still other of the display devices (10) may be placed inside the tile-type display device (TD) and surrounded by other display devices (10).

[0038] Each of the plurality of display devices (10) may include a display area (DA) and a non-display area (NDA). The display area (DA) may include a plurality of pixels to display an image. Each of the plurality of pixels may include at least one of an organic light-emitting diode (OLED) including an organic light-emitting layer, a quantum dot light-emitting diode (QD) including a quantum dot light-emitting layer, an inorganic light-emitting diode (ILED) including an inorganic semiconductor, and a micro LED. In the following description, the case where each of the plurality of pixels includes an inorganic light-emitting diode is described primarily, but is not limited thereto. The non-display area (NDA) may be placed around the display area (DA) to surround the display area (DA) and may not display an image.

[0039] The tile-type display device (TD) may have a planar shape overall, but is not limited thereto. The tile-type display device (TD) may have a three-dimensional shape to provide a sense of three-dimensionality to the user. For example, when the tile-type display device (TD) has a three-dimensional shape, at least some of the display devices (10) among the plurality of display devices (10) may have a curved shape. As another example, the tile-type display device (TD) may have a three-dimensional shape by each of the plurality of display devices (10) having a planar shape and being connected to each other at a predetermined angle.

[0040] A tile-type display device (TD) may include a bonding area (SM) positioned between a plurality of display areas (DA). The tile-type display device (TD) may be formed by connecting the non-display areas (NDA) of each adjacent display device (10). A plurality of display devices (10) may be connected to each other through a bonding member or an adhesive member positioned in the bonding area (SM). A bonding area (SM) of each of the plurality of display devices (10) may not include a pad portion or a flexible film attached to the pad portion. Accordingly, the distance between the display areas (DA) of each of the plurality of display devices (10) may be close enough that the bonding area (SM) between the plurality of display devices (10) is not perceived by the user. Additionally, the external light reflectance of the display area (DA) of each of the plurality of display devices (10) and the external light reflectance of the bonding area (SM) between the plurality of display devices (10) may be substantially the same. Accordingly, the tile-type display device (TD) can improve the sense of disconnection between the multiple display devices (10) and enhance the immersion of the image by preventing the user from perceiving the combined area (SM) between the multiple display devices (10).

[0041] FIG. 2 is a plan view showing a display device according to one embodiment.

[0042] Referring to FIG. 2, a display device (10) may include a plurality of pixels arranged along a plurality of rows and columns in a display area (DA). Each of the plurality of pixels may include a light-emitting region (LA) defined by a pixel defining film or bank, and may emit light having a predetermined peak wavelength through the light-emitting region (LA). For example, the display area (DA) of the display device (10) may include first to third light-emitting regions (LA1, LA2, LA3). Each of the first to third light-emitting regions (LA1, LA2, LA3) may be a region where light generated from a light-emitting element of the display device (10) is emitted to the outside of the display device (10).

[0043] The first to third light-emitting regions (LA1, LA2, LA3) can emit light having a predetermined peak wavelength to the outside of the display device (10). The first light-emitting region (LA1) can emit light of a first color, the second light-emitting region (LA2) can emit light of a second color, and the third light-emitting region (LA3) can emit light of a third color. For example, the first color light may be red light having a peak wavelength in the range of 610 nm to 650 nm, the second color light may be green light having a peak wavelength in the range of 510 nm to 550 nm, and the third color light may be blue light having a peak wavelength in the range of 440 nm to 480 nm, but is not limited thereto.

[0044] The first to third light-emitting regions (LA1, LA2, LA3) may be sequentially and repeatedly arranged along the first direction (X-axis direction) of the display region (DA). For example, the area of ​​the third light-emitting region (LA3) may be larger than the area of ​​the first light-emitting region (LA1), and the area of ​​the first light-emitting region (LA1) may be larger than the area of ​​the second light-emitting region (LA2). As another example, the area of ​​the first light-emitting region (LA1), the area of ​​the second light-emitting region (LA2), and the area of ​​the third light-emitting region (LA3) may be substantially the same.

[0045] The display area (DA) of the display device (10) may include a light-blocking area (BA) surrounding a plurality of light-emitting areas (LA). The light-blocking area (BA) can prevent the mixing of light emitted from the first to third light-emitting areas (LA1, LA2, LA3).

[0046] FIG. 3 is a cross-sectional view taken along the line I-I' of FIG. 2. FIG. 4 is an enlarged view of area A of FIG. 3. FIG. 5 is a bottom view showing a first contact hole portion of a display device according to one embodiment. FIG. 6 is a bottom view showing a display device according to one embodiment.

[0047] Referring to FIGS. 3 to 6, the display area (DA) of the display device (10) may include first to third light-emitting areas (LA1, LA2, LA3). Each of the first to third light-emitting areas (LA1, LA2, LA3) may be an area where light generated from a light-emitting element (ED) of the display device (10) is emitted to the outside of the display device (10).

[0048] The display device (10) may include a first substrate (SUB1), a first barrier insulating layer (BIL1), a pad electrode (PD), a second barrier insulating layer (BIL2), a second substrate (SUB2), a display layer (DPL), an encapsulation layer (TFE), an anti-reflective film (ARF), a flexible film (FPCB), and a display driving unit (DIC).

[0049] The first substrate (SUB1) can support the display device (10). The first substrate (SUB1) may be a base substrate or a base member. The first substrate (SUB1) may be a flexible substrate capable of bending, folding, rolling, etc. For example, the first substrate (SUB1) may include an insulating material such as a polymer resin such as polyimide (PI), but is not limited thereto. As another example, the first substrate (SUB1) may be a rigid substrate including a glass material.

[0050] The first substrate (SUB1) may include a first contact hole (CNT1) and sub-contact holes (SCNT). The first contact hole (CNT1) may be a groove shape that is etched from the bottom surface of the first substrate (SUB1) and penetrates into a part of the first substrate (SUB1). The first contact hole (CNT1) may overlap with pad electrodes (PD: PD1, PD2) in the thickness direction (Z-axis direction).

[0051] The sub-contact holes (SCNT: SCNT1, SCNT2) are holes penetrating the first substrate (SUB1) and can be placed within the first contact hole (SCNT1). The sub-contact holes (SCNT) can expose the lower surfaces of the pad electrodes (PD) during the manufacturing process of the display device (10). The sub-contact holes (SCNT) may include a first sub-contact hole (SCNT1) and a second sub-contact hole (SCNT2) that expose the pad electrodes (PD), respectively. The first sub-contact hole (SCNT1) overlaps with the first pad electrode (PD1) in the thickness direction (Z-axis direction) and can expose the first pad electrode (PD1). The second sub-contact hole (SCNT2) overlaps with the second pad electrode (PD2) in the thickness direction (Z-axis direction) and can expose the second pad electrode (PD2). The sub-contact holes (SCNTs) are spaced apart from each other, and a part of the first substrate (SUB1) may be placed in the spaced interval between the sub-contact holes (SCNTs).

[0052] The width of the first contact hole (CNT1), for example, the width measured in the first direction (X-axis direction), may be greater than the width of each sub-contact hole (SCNT). The sum of the individual widths of the sub-contact holes (SCNT) may be smaller than the width of the first contact hole (CNT1). The sub-contact holes (SCNT) may be placed within the larger width of the first contact hole (CNT1). The sub-contact holes (SCNT) and the first contact hole (CNT1) may expose the pad electrodes (PDs) for bonding the flexible film (FPCB) and the pad electrodes (PDs).

[0053] The first barrier insulating layer (BIL1) may be disposed on the first substrate (SUB1). The first barrier insulating layer (BIL1) may include an inorganic film capable of preventing the penetration of air or moisture. For example, the first barrier insulating layer (BIL1) may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer, but is not limited thereto.

[0054] The first barrier insulating layer (BIL1) may include second contact holes (CNT2). The second contact holes (CNT2) may be etched from the bottom surface of the first barrier insulating layer (BIL1) and penetrate to the top surface of the first barrier insulating layer (BIL1). The second contact holes (CNT2) may be through holes penetrating the first barrier insulating layer (BIL1). The second contact holes (CNT2) may expose pad electrodes (PDs) during the manufacturing process of the display device (10). The second contact holes (CNT2) may be spaced apart from each other and overlap with the sub-contact holes (SCNT) in the thickness direction (Z-axis direction). The second contact holes (CNT2) may be aligned and matched with the sub-contact holes (SCNT), for example, the first sub-contact hole (SCNT1) and the second sub-contact hole (SCNT2). Pad electrodes (PDs) can be exposed through second contact holes (CNT2) and sub-contact holes (SCNT).

[0055] Pad electrodes (PDs) can be placed on the first barrier insulating layer (BIL1). The pad electrodes (PDs) can be placed in the display area (DA) or across the display area (DA) and the non-display area (NDA). The display device (10) can minimize the area of ​​the non-display area (NDA) by including pad electrodes (PDs) in which at least a portion is placed in the display area (DA). The pad electrodes (PDs) can be electrically connected to the thin-film transistors (TFTs) of the pixels, although not illustrated. Thus, the pad electrodes (PDs) can supply electrical signals transmitted from the flexible film (FPCB) to the thin-film transistors (TFTs) of the pixels.

[0056] Pad electrodes (PDs) may overlap with the first contact hole (CNT1), sub-contact holes (SCNT), and second contact hole (CNT2), and may be exposed to the outside by the first contact hole (CNT1), sub-contact holes (SCNT), and second contact hole (CNT2). Pad electrodes (PDs) may be disposed extending from the upper surface of the first barrier insulating layer (BIL1) into the second contact hole (CNT2).

[0057] Pad electrodes (PDs) may include a first metal layer (MTL1) and a second metal layer (MTL2). The first metal layer (MTL1) may form the lower layer of the pad electrode (PD), and the second metal layer (MTL2) may be disposed on the first metal layer (MTL1) to form the upper layer of the pad electrode (PD). The first metal layer (MTL1) may be disposed below the upper surface of the first barrier insulating layer (BIL1). By depositing the first metal layer (MTL1) after the second contact holes (CNT2) are formed in the first barrier insulating layer (BIL1), the first metal layer (MTL1) may be disposed below the upper surface of the first barrier insulating layer (BIL1). For example, the upper surface of the first metal layer (MTL1) may be disposed below the upper surface of the first barrier insulating layer (BIL1). A portion of the second metal layer (MTL2) may be positioned below the upper surface of the first barrier insulation layer (BIL1). For example, the lower surface of the second metal layer (MTL2) may be positioned below the upper surface of the first barrier insulation layer (BIL1), and the upper surface of the second metal layer (MTL2) may be positioned above the upper surface of the first barrier insulation layer (BIL1).

[0058] The first metal layer (MTL1) and the second metal layer (MTL2) may include metal. The first metal layer (MTL1) serves to cap the second metal layer (MTL2), and the second metal layer (MTL2) may serve as low-resistance wiring for the pad electrode (PD). For example, the first metal layer (MTL1) may include titanium (Ti), and the second metal layer (MTL2) may include copper (Cu). However, it is not limited thereto, and any metal that is a low-resistance metal may be applied to the second metal layer (MTL2). The thickness of the first metal layer (MTL1) may be about 100 to 300 Å, and the thickness of the second metal layer (MTL2) may be 3000 to 5000 Å. However, it is not limited thereto.

[0059] As illustrated in FIGS. 4 and 5, in one embodiment, the first substrate (SUB1) may include a substrate buffer portion (BSUB) disposed in an area overlapping with the first contact hole (CNT1). The substrate buffer portion (BSUB) may correspond to an area where the thickness of the first substrate (SUB1) is relatively thin. For example, the thickness of the substrate buffer portion (BSUB) may be smaller than the thickness of the first substrate (SUB1) that does not overlap with the first contact hole (CNT1). The substrate buffer portion (BSUB) may overlap with the first contact hole (CNT1) and may not overlap with the second contact hole (CNT2). The substrate buffer portion (BSUB) may be disposed around the second contact hole (CNT2) and may be arranged to surround the second contact hole (CNT2). The substrate buffer portion (BSUB) for the second contact hole (CNT2) can be positioned around the first sub-contact hole (SCNT1) and the second sub-contact hole (SCNT2), and can be positioned to surround the first sub-contact hole (SCNT1) and the second sub-contact hole (SCNT2).

[0060] The substrate buffer (BSUB) can prevent the laser from passing through the first substrate (SUB1) and further transmitting upward during the manufacturing process of the display device (10). A laser can be irradiated onto the first substrate (SUB1) to form a first contact hole (CNT1). As the first substrate (SUB1) is etched, the thickness of the first substrate (SUB1) decreases and the transmittance of the laser increases, which can damage the second substrate (SUB2) placed on top. In this embodiment, by forming a substrate buffer (BSUB) on the first substrate (SUB1), damage to the second substrate (SUB2) by the laser during the process of forming the first contact hole (CNT1) can be prevented.

[0061] The substrate buffer portion (BSUB) may be smaller than the thickness of the first substrate (SUB1), for example, with a thickness of 0.5 μm to 1.5 μm. Here, if the thickness of the substrate buffer portion (BSUB) is 0.5 μm or more, the laser can be transmitted to the second substrate (SUB2) and prevent damage to the second substrate (SUB2). If the thickness of the substrate buffer portion (BSUB) is 1.5 μm or less, it is made smaller than the diameter of the conductive ball contained within the connection film (ACF), thereby facilitating connection between the pad electrode (PD) and the conductive ball.

[0062] A second barrier insulating layer (BIL2) may be disposed on the first barrier insulating layer (BIL1) and the pad electrodes (PDs). The second barrier insulating layer (BIL2) may insulate the pad electrodes (PDs). The second barrier insulating layer (BIL2) may include an inorganic film capable of preventing the penetration of air or moisture. For example, the second barrier insulating layer (BIL2) may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer, but is not limited thereto.

[0063] The second substrate (SUB2) may be disposed on the second barrier insulating layer (BIL2). The second substrate (SUB2) may be a base substrate or a base member. The second substrate (SUB2) may be a flexible substrate capable of bending, folding, rolling, etc. For example, the second substrate (SUB2) may include an insulating material such as a polymer resin such as polyimide (PI), but is not limited thereto.

[0064] The display layer (DPL) may be disposed on the second substrate (SUB2). The display layer (DPL) may include a thin film transistor layer (TFTL), a light-emitting element layer (EML), a wavelength conversion layer (WLCL), and a color filter layer (CFL).

[0065] The thin film transistor layer (TFTL) may include a lower metal layer (BML), a buffer layer (BF), an active layer (ACTL), a gate insulating layer (GI), a gate electrode (GE), an interlayer insulating layer (ILD), a connection electrode (CNE), a first protection layer (PV1), and a first planarization layer (OC1).

[0066] The lower metal layer (BML) may be disposed on the second substrate (SUB2). The lower metal layer (BML) may overlap with the thin-film transistor (TFT) in the thickness direction (Z-axis direction) to block external light incident on the thin-film transistor (TFT). As another example, the lower metal layer (BML) may include data lines or power lines. The lower metal layer (BML) may be formed as a single layer or a multilayer comprising at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), palladium (Pd), indium (In), neodymium (Nd), and copper (Cu).

[0067] A buffer layer (BF) may be disposed on a lower metal layer (BML) and a second substrate (SUB2). The buffer layer (BF) may include an inorganic material capable of preventing the penetration of air or moisture. For example, the buffer layer (BF) may include a plurality of alternately stacked inorganic films.

[0068] The active layer (ACTL) may be disposed on the buffer layer (BF). The active layer (ACTL) may include a semiconductor region (ACT), a drain electrode (DE), and a source electrode (SE) of the thin-film transistor (TFT). The semiconductor region (ACT) may overlap with the gate electrode (GE) in the thickness direction (Z-axis direction) and may be insulated from the gate electrode (GE) by a gate insulating layer (GI). The drain electrode (DE) and the source electrode (SE) may be formed by making the material of the semiconductor region (ACT) conductive. The thin-film transistor (TFT) may constitute a pixel circuit for each of a plurality of pixels. For example, the thin-film transistor (TFT) may be a driving transistor or a switching transistor of the pixel circuit.

[0069] A gate insulating layer (GI) may be disposed on an active layer (ACTL) and a buffer layer (BF). The gate insulating layer (GI) may insulate the semiconductor region (ACT) and the gate electrode (GE) of the thin-film transistor (TFT). The gate insulating layer (GI) may include contact holes through which connection electrodes (CNE) pass.

[0070] A gate electrode (GE) may be disposed on a gate insulating layer (GI). The gate electrode (GE) may overlap with a semiconductor region (ACT) with the gate insulating layer (GI) in between. The gate electrode (GE) may receive a gate signal from a gate line. For example, the gate electrode (GE) may be formed as a single layer or a multilayer comprising at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), palladium (Pd), indium (In), neodymium (Nd), and copper (Cu).

[0071] An interlayer insulating layer (ILD) may be disposed on a gate electrode (GE). The interlayer insulating layer (ILD) may insulate the gate electrode (GE) from the connecting electrodes (CNE). The interlayer insulating layer (ILD) may include contact holes through which the connecting electrodes (CNE) pass.

[0072] Connecting electrodes (CNE) may be disposed on an interlayer insulating layer (ILD). Connecting electrodes (CNE) may include a first connecting electrode (CNE1) and a second connecting electrode (CNE2). The first connecting electrode (CNE1) and the second connecting electrode (CNE2) may be formed of the same material in the same layer, but are not limited thereto. For example, the first connecting electrode (CNE1) and the second connecting electrode (CNE2) may be formed as a single layer or a multilayer comprising at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), palladium (Pd), indium (In), neodymium (Nd), and copper (Cu).

[0073] The first connection electrode (CNE1) can connect a data line or power line to the drain electrode (DE) of the thin-film transistor (TFT). The first connection electrode (CNE1) can be contacted to the drain electrode (DE) through a contact hole formed in the interlayer insulating layer (ILD) and the gate insulating layer (GI). The second connection electrode (CNE2) can connect the source electrode (SE) of the thin-film transistor (TFT) to the first electrode (RME1). The second connection electrode (CNE2) can be contacted to the source electrode (SE) through a contact hole formed in the interlayer insulating layer (ILD) and the gate insulating layer (GI).

[0074] The first protective layer (PV1) may be disposed on the connecting electrodes (CNE) and the interlayer insulating layer (ILD). The first protective layer (PV1) may protect the thin-film transistor (TFT). The first protective layer (PV1) may include a contact hole through which the first electrode (RME1) passes.

[0075] The first planarization layer (OC1) may be disposed on the first protection layer (PV1). The first planarization layer (OC1) may planarize the top of the thin-film transistor layer (TFTL). For example, the first planarization layer (OC1) may include a contact hole through which the first electrode (RME1) passes. The contact hole of the first planarization layer (OC1) may be connected to the contact hole of the first protection layer (PV1). The first planarization layer (OC1) may include an organic insulating material such as polyimide (PI).

[0076] A light-emitting element layer (EML) may be disposed on a thin-film transistor layer (TFTL). The light-emitting element layer (EML) may include bank patterns (BP), a first electrode (RME1), a second electrode (RME2), a first insulating layer (PAS1), a sub-bank (SB), a light-emitting element (ED), a second insulating layer (PAS2), a first contact electrode (CTE1), a second contact electrode (CTE2), and a third insulating layer (PAS3).

[0077] Bank patterns (BP) may be disposed on a first planarization layer (OC1). Bank patterns (BP) may protrude from the upper surface of the first planarization layer (OC1). Bank patterns (BP) may be arranged so as to extend in a second direction (Y-axis direction) and be spaced apart from each other in a first direction (X-axis direction). Bank patterns (BP) may be disposed in the light-emitting region (LA) or aperture region of each of a plurality of pixels. A plurality of light-emitting elements (ED) may be disposed between the bank patterns (BP). Bank patterns (BP) may have inclined sides, and light emitted from the plurality of light-emitting elements (ED) may be reflected by first and second electrodes (RME1, RME2) disposed on the bank patterns (BP). For example, bank patterns (BP) may include an organic insulating material such as polyimide (PI).

[0078] A first electrode (RME1) may be disposed on a first planarization layer (OC1) and bank patterns (BP). The first electrode (RME1) may be disposed on a bank pattern (BP) disposed on one side of a plurality of light-emitting elements (ED). The first electrode (RME1) may be disposed on an inclined side of the bank pattern (BP) to reflect light emitted from the light-emitting elements (ED). The first electrode (RME1) may be inserted into a contact hole formed in the first planarization layer (OC1) and the first protection layer (PV1) and connected to a second connecting electrode (CNE2). The first electrode (RME1) may be electrically connected to one end of the light-emitting element (ED) through a first contact electrode (CTE1). For example, the first electrode (RME1) may receive a voltage proportional to the brightness of the light-emitting element (ED) from a thin-film transistor (TFT) of the pixel.

[0079] The second electrode (RME2) may be placed on the first planarization layer (OC1) and the bank pattern (BP). The second electrode (RME2) may be placed on the bank pattern (BP) which is placed on the other side of a plurality of light-emitting elements (ED). The second electrode (RME2) may be placed on the inclined side of the bank pattern (BP) to reflect light emitted from the light-emitting elements (ED). The second electrode (RME2) may be electrically connected to the other end of the light-emitting element (ED) through a second contact electrode (CTE2). For example, the second electrode (RME2) may receive a low potential voltage supplied to the entire pixel from a low potential line.

[0080] The first and second electrodes (RME1, RME2) may include a conductive material with high reflectivity. For example, the first and second electrodes (RME1, RME2) may include at least one of aluminum (Al), silver (Ag), copper (Cu), nickel (Ni), and lanthanum (La). As another example, the first and second electrodes (RME1, RME2) may include materials such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), ITZO (Indium Tin Zinc Oxide), etc. As yet another example, the first and second electrodes (RME1, RME2) may include a plurality of layers having a transparent conductive material layer and a metal layer with high reflectivity, or a single layer including a transparent conductive material and a metal with high reflectivity. The first and second electrodes (RME1, RME2) may have a stacked structure such as ITO / Ag / ITO, ITO / Ag / IZO, or ITO / Ag / ITZO / IZO.

[0081] The first insulating layer (PAS1) may be disposed on the first planarization layer (OC1) and the first and second electrodes (RME1, RME2). The first insulating layer (PAS1) can insulate the first and second electrodes (RME1, RME2) from each other while protecting them. The first insulating layer (PAS1) can prevent the light-emitting element (ED) and the first and second electrodes (RME1, RME2) from coming into direct contact and being damaged during the alignment process of the light-emitting element (ED).

[0082] Sub-banks (SB) can be arranged overlapping with a light-blocking region (BA) on the first insulating layer (PAS1). Sub-banks (SB) can be arranged at the boundaries of multiple pixels to distinguish multiple pixels. Sub-banks (SB) can have a predetermined height and may include an organic insulating material such as polyimide (PI).

[0083] A plurality of light-emitting elements (ED) may be disposed on a first insulating layer (PAS1). A plurality of light-emitting elements (ED) may be aligned parallel to each other between the first and second electrodes (RME1, RME2). The length of the light-emitting elements (ED) may be longer than the length between the first and second electrodes (RME1, RME2). The light-emitting elements (ED) may include a plurality of semiconductor layers, and one end and the other end opposite to the one end may be defined based on one semiconductor layer. One end of the light-emitting elements (ED) may be disposed on the first electrode (RME1), and the other end of the light-emitting elements (ED) may be disposed on the second electrode (RME2). One end of the light-emitting elements (ED) may be electrically connected to the first electrode (RME1) through a first contact electrode (CTE1), and the other end of the light-emitting elements (ED) may be electrically connected to the second electrode (RME2) through a second contact electrode (CTE2).

[0084] The light-emitting element (ED) may have a size in the micrometer or nanometer range and may be an inorganic light-emitting diode containing inorganic material. The inorganic light-emitting diode may be aligned between the first and second electrodes (RME1, RME2) according to an electric field formed in a specific direction between the first and second electrodes (RME1, RME2) facing each other.

[0085] For example, a plurality of light-emitting elements (EDs) may include an active layer having the same material and emit light of the same wavelength range or light of the same color. The light emitted from each of the first to third light-emitting regions (LA1, LA2, LA3) of the light-emitting element layer (EML) may have the same color. For example, a plurality of light-emitting elements (EDs) may emit light of the third color or blue light having a peak wavelength in the range of 440 nm to 480 nm, but are not limited thereto.

[0086] The second insulating layer (PAS2) may be disposed on a plurality of light-emitting elements (ED). For example, the second insulating layer (PAS2) may partially wrap the plurality of light-emitting elements (ED) and may not cover both ends of each of the plurality of light-emitting elements (ED). The second insulating layer (PAS2) may protect the plurality of light-emitting elements (ED) and may fix the plurality of light-emitting elements (ED) during the manufacturing process of the display device (10). The second insulating layer (PAS2) may fill the space between the light-emitting element (ED) and the first insulating layer (PAS1).

[0087] The first contact electrode (CTE1) may be disposed on the first insulating layer (PAS1) and may be inserted into a contact hole formed in the first insulating layer (PAS1) to be connected to the first electrode (RME1). For example, the contact hole of the first insulating layer (PAS1) may be formed on a bank pattern (BP), but is not limited thereto. One end of the first contact electrode (CTE1) may be connected to the first electrode (RME1) on the bank pattern (BP), and the other end of the first contact electrode (CTE1) may be connected to one end of a light-emitting element (ED).

[0088] The second contact electrode (CTE2) may be disposed on the first insulating layer (PAS1) and may be inserted into a contact hole formed in the first insulating layer (PAS1) to be connected to the second electrode (RME2). For example, the contact hole of the first insulating layer (PAS1) may be provided on a bank pattern (BP), but is not limited thereto. One end of the second contact electrode (CTE2) may be connected to the other end of the light-emitting element (ED), and the other end of the second contact electrode (CTE2) may be connected to the second electrode (RME2) on the bank pattern (BP).

[0089] The third insulating layer (PAS3) may be disposed on the first and second contact electrodes (CTE1, CTE2), the sub-bank (SB), and the first and second insulating layers (PAS1, PAS2). The third insulating layer (PAS3) may be disposed on the light-emitting element layer (EML) to protect the light-emitting element layer (EML).

[0090] A wavelength conversion layer (WLCL) may be disposed on a light-emitting element layer (EML). The wavelength conversion layer (WLCL) may include a first light-blocking member (BK1), a first wavelength conversion part (WLC1), a second wavelength conversion part (WLC2), a light-transmitting part (LTU), a second protective layer (PV2), and a second planarization layer (OC2).

[0091] The first light-blocking member (BK1) is placed on the third insulating layer (PAS3) and may be placed overlapping with the light-blocking region (BA). The first light-blocking member (BK1) may be overlapped with the sub-bank (SB) in the thickness direction (Z-axis direction). The first light-blocking member (BK1) can block the transmission of light. The first light-blocking member (BK1) can improve the color reproduction rate of the display device (10) by preventing light from interfering and mixing between the first to third light-emitting regions (LA1, LA2, LA3). The first light-blocking member (BK1) may be placed in a grid shape surrounding the first to third light-emitting regions (LA1, LA2, LA3) on a plane.

[0092] The first wavelength conversion unit (WLC1) is disposed on the third insulating layer (PAS3) and may be disposed overlapping with the first light-emitting region (LA1). The first wavelength conversion unit (WLC1) may be surrounded by a first light-blocking member (BK1). The first wavelength conversion unit (WLC1) may include a first base resin (BS1), a first scatterer (SCT1), and a first wavelength shifter (WLS1).

[0093] The first base resin (BS1) may include a material with a relatively high light transmittance. The first base resin (BS1) may be made of a transparent organic material. For example, the first base resin (BS1) may include at least one of organic materials such as an epoxy resin, an acrylic resin, a cardo resin, and an imide resin.

[0094] The first scatterer (SCT1) may have a refractive index different from that of the first base resin (BS1) and may form an optical interface with the first base resin (BS1). For example, the first scatterer (SCT1) may include a light-scattering material or light-scattering particles that scatter at least a portion of the transmitted light. For example, the first scatterer (SCT1) may include metal oxides such as titanium oxide (TiO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), indium oxide (In2O3), zinc oxide (ZnO), or tin oxide (SnO2), or may include organic particles such as acrylic resin or urethane resin. The first scatterer (SCT1) may scatter light in random directions regardless of the incident direction of the incident light without substantially changing the peak wavelength of the incident light.

[0095] The first wavelength shifter (WLS1) can convert or shift the peak wavelength of incident light to the first peak wavelength. For example, the first wavelength shifter (WLS1) can convert and emit blue light provided by the display device (10) into red light having a single peak wavelength in the range of 610 nm to 650 nm. The first wavelength shifter (WLS1) may be a quantum dot, a quantum rod, or a phosphor. A quantum dot may be a particulate material that emits a specific color as electrons transition from the conduction band to the valence band.

[0096] A portion of the blue light provided by the light-emitting element layer (EML) may pass through the first wavelength conversion unit (WLC1) without being converted into red light by the first wavelength shifter (WLS1). Among the blue light provided by the light-emitting element layer (EML), the light incident on the first color filter (CF1) without being converted by the first wavelength conversion unit (WLC1) may be blocked by the first color filter (CF1). Furthermore, among the blue light provided by the light-emitting element layer (EML), the red light converted by the first wavelength conversion unit (WLC1) may pass through the first color filter (CF1) and be emitted to the outside. Therefore, the first light-emitting region (LA1) may emit red light.

[0097] The second wavelength conversion unit (WLC2) is disposed on the third insulating layer (PAS3) and may be disposed overlapping with the second light-emitting region (LA2). The second wavelength conversion unit (WLC2) may be surrounded by the first light-blocking member (BK1). The second wavelength conversion unit (WLC2) may include a second base resin (BS2), a second scatterer (SCT2), and a second wavelength shifter (WLS2).

[0098] The second base resin (BS2) may include a material with relatively high light transmittance. The second base resin (BS2) may be made of a transparent organic material. For example, the second base resin (BS2) may be made of the same material as the first base resin (BS1) or may be made of the material exemplified in the first base resin (BS1).

[0099] The second scatterer (SCT2) may have a refractive index different from that of the second base resin (BS2) and may form an optical interface with the second base resin (BS2). For example, the second scatterer (SCT2) may include a light-scattering material or light-scattering particles that scatter at least a portion of the transmitted light. For example, the second scatterer (SCT2) may be made of the same material as the first scatterer (SCT1) or may be made of the material exemplified in the first scatterer (SCT1).

[0100] The second wavelength shifter (WLS2) can convert or shift the peak wavelength of incident light to a second peak wavelength different from the first peak wavelength of the first wavelength shifter (WLS1). For example, the second wavelength shifter (WLS2) can convert and emit blue light provided by the display device (10) into green light having a single peak wavelength in the range of 510 nm to 550 nm. The second wavelength shifter (WLS2) may be a quantum dot, a quantum rod, or a phosphor. The second wavelength shifter (WLS2) may include the material exemplified in the first wavelength shifter (WLS1). The wavelength conversion range of the second wavelength shifter (WLS2) may be made of a quantum dot, a quantum rod, or a phosphor such that it is different from the wavelength conversion range of the first wavelength shifter (WLS1).

[0101] The light-transmitting unit (LTU) is disposed on the third insulating layer (PAS3) and may be disposed overlapping with the third light-emitting region (LA3). The light-transmitting unit (LTU) may be surrounded by the first light-blocking member (BK1). The light-transmitting unit (LTU) may transmit while maintaining the peak wavelength of the incident light. The light-transmitting unit (LTU) may include the third base resin (BS3) and the third scatterer (SCT3).

[0102] The third base resin (BS3) may include a material with relatively high light transmittance. The third base resin (BS3) may be made of a transparent organic material. For example, the third base resin (BS3) may be made of the same material as the first or second base resin (BS1, BS2), or may be made of the material exemplified in the first base resin (BS1).

[0103] The third scatterer (SCT3) may have a refractive index different from that of the third base resin (BS3) and may form an optical interface with the third base resin (BS3). For example, the third scatterer (SCT3) may include a light-scattering material or light-scattering particles that scatter at least a portion of the transmitted light. For example, the third scatterer (SCT3) may be made of the same material as the first or second scatterer (SCT1, SCT2) or may be made of the material exemplified in the first scatterer (SCT1).

[0104] Since the wavelength conversion layer (WLCL) is placed directly on the third insulating layer (PAS3) of the light-emitting element layer (EML), the display device (10) may not require a separate substrate for the first and second wavelength conversion sections (WLC1, WLC2) and the light-transmitting section (LTU). Accordingly, the first and second wavelength conversion sections (WLC1, WLC2) and the light-transmitting section (LTU) can be easily aligned with each of the first to third light-emitting regions (LA1, LA2, LA3), and the thickness of the display device (10) can be relatively reduced.

[0105] The second protective layer (PV2) may cover the first and second wavelength conversion sections (WLC1, WLC2), the light transmission section (LTU), and the first light-blocking member (BK1). For example, the second protective layer (PV2) may seal the first and second wavelength conversion sections (WLC1, WLC2) and the light transmission section (LTU) to prevent damage or contamination of the first and second wavelength conversion sections (WLC1, WLC2) and the light transmission section (LTU). For example, the second protective layer (PV2) may include an inorganic material.

[0106] The second flattening layer (OC2) is disposed on the second protective layer (PV2) to flatten the upper portion of the first and second wavelength conversion sections (WLC1, WLC2) and the light transmission section (LTU). For example, the second flattening layer (OC2) may include an organic insulating material such as polyimide (PI).

[0107] A color filter layer (CFL) may be disposed on a wavelength conversion layer (WLCL). The color filter layer (CFL) may include a second light-blocking member (BK2), first to third color filters (CF1, CF2, CF3), and a third protective layer (PV3).

[0108] The second light-blocking member (BK2) is placed on the second flattening layer (OC2) of the wavelength conversion layer (WLCL) and may be placed overlapping with the light-blocking region (BA). The second light-blocking member (BK2) may be overlapped with the first light-blocking member (BK1) or the sub-bank (SB) in the thickness direction (Z-axis direction). The second light-blocking member (BK2) can block the transmission of light. The second light-blocking member (BK2) can improve the color reproduction rate of the display device (10) by preventing light from invading and mixing between the first to third light-emitting regions (LA1, LA2, LA3). The second light-blocking member (BK2) may be arranged in a grid shape surrounding the first to third light-emitting regions (LA1, LA2, LA3) on a plane.

[0109] The first color filter (CF1) is disposed on the second flattening layer (OC2) and may be disposed overlapping with the first light-emitting region (LA1). The first color filter (CF1) may be surrounded by the second light-blocking member (BK2). The first color filter (CF1) may be overlapped with the first wavelength conversion unit (WLC1) in the thickness direction (Z-axis direction). The first color filter (CF1) may selectively transmit light of the first color (e.g., red light) and block or absorb light of the second color (e.g., green light) and light of the third color (e.g., blue light). For example, the first color filter (CF1) may be a red color filter and may include a red colorant.

[0110] The second color filter (CF2) is disposed on the second flattening layer (OC2) and may be disposed overlapping with the second light-emitting region (LA2). The second color filter (CF2) may be surrounded by a second light-blocking member (BK2). The second color filter (CF2) may be overlapped with the second wavelength conversion unit (WLC2) in the thickness direction (Z-axis direction). The second color filter (CF2) may selectively transmit light of the second color (e.g., green light) and block or absorb light of the first color (e.g., red light) and light of the third color (e.g., blue light). For example, the second color filter (CF2) may be a green color filter and may include a green colorant.

[0111] The third color filter (CF3) is disposed on the second flattening layer (OC2) and may be disposed overlapping with the third light-emitting region (LA3). The third color filter (CF3) may be surrounded by the second light-blocking member (BK2). The third color filter (CF3) may be overlapped with the light-transmitting portion (LTU) in the thickness direction (Z-axis direction). The third color filter (CF3) may selectively transmit light of the third color (e.g., blue light) and block or absorb light of the first color (e.g., red light) and light of the second color (e.g., green light). For example, the third color filter (CF3) may be a blue color filter and may include a blue colorant.

[0112] The first to third color filters (CF1, CF2, CF3) can absorb a portion of the light entering from outside the display device (10) to reduce reflected light caused by external light. Accordingly, the first to third color filters (CF1, CF2, CF3) can prevent color distortion caused by external light reflection.

[0113] Since the first to third color filters (CF1, CF2, CF3) are placed directly on the second planarization layer (OC2) of the wavelength conversion layer (WLCL), the display device (10) may not require a separate substrate for the first to third color filters (CF1, CF2, CF3). Accordingly, the thickness of the display device (10) may be relatively reduced.

[0114] The third protective layer (PV3) can cover the first to third color filters (CF1, CF2, CF3). The third protective layer (PV3) can protect the first to third color filters (CF1, CF2, CF3).

[0115] The encapsulation layer (TFE) may be placed on the third protective layer (PV3) of the color filter layer (CFL). The encapsulation layer (TFE) may cover the upper surface and sides of the display layer (DPL). For example, the encapsulation layer (TFE) may include at least one inorganic film to prevent oxygen or moisture from penetrating. Additionally, the encapsulation layer (TFE) may include at least one organic film to protect the display device (10) from foreign substances such as dust.

[0116] An anti-reflective film (ARF) may be placed on the encapsulation layer (TFE). By preventing the reflection of external light, the anti-reflective film (ARF) can reduce the degradation of visibility caused by the reflection of external light. The anti-reflective film (ARF) can protect the upper surface of the display device (10). Optionally, the anti-reflective film (ARF) may be omitted. As another example, the anti-reflective film (ARF) may be replaced with a polarizing film.

[0117] Meanwhile, the flexible film (FPCB) may be placed on the lower side of the first substrate (SUB1). The flexible film (FPCB) may be attached to the lower surface of the first substrate (SUB1) using an adhesive member (ADM). Optionally, the adhesive member (ADM) may be omitted. The flexible film (FPCB) may support a display driver (DIC) placed on the other side of the lower surface. A film pad (PAE) may be placed on one side of the flexible film (FPCB), for example, on the side facing the first substrate (SUB1). The film pad (PAE) of the flexible film (FPCB) may be electrically connected to a pad electrode (PD) through a connection film (ACF). The other side of the flexible film (FPCB) may be connected to a source circuit board (not shown) on the lower side of the first substrate (SUB1). The flexible film (FPCB) may transmit a signal from the display driver (DIC) to a display device (10).

[0118] The display driver (DIC) may be an integrated circuit (IC). For example, the display driver (DIC) may convert digital video data into an analog data voltage based on a data control signal from the timing control unit and supply it to the data line of the display area (DA) through a flexible film (FPCB). As another example, the display driver (DIC) may generate a gate signal based on a gate control signal from the timing control unit and supply it to the gate line of the display area (DA) through a flexible film (FPCB). The display device (10) may minimize the area of ​​the non-display area (NDA) by including a flexible film (FPCB) and a display driver (DIC) disposed on the lower part of the first substrate (SUB1).

[0119] Hereinafter, a method for manufacturing the above-described display device (10) will be explained with reference to other drawings.

[0120] FIGS. 7 to 16 are drawings showing a method for manufacturing a display device according to one embodiment, by process.

[0121] Referring to FIG. 7, a first carrier substrate (CG1) is prepared. The first carrier substrate (CG1) can support the display device (10) during the manufacturing process of the display device (10). For example, the first carrier substrate (CG1) may be a glass substrate, but is not limited thereto.

[0122] Next, a first substrate (SUB1) is formed on a first carrier substrate (CG1). The first substrate (SUB1) can be formed by applying an insulating material, such as a polymer resin like polyimide (PI), via a solution process. The first substrate (SUB1) may be a base substrate or a base member. Next, a first barrier insulating layer (BIL1) is formed on the first substrate (SUB1). The first barrier insulating layer (BIL1) can be formed by laminating an inorganic material capable of preventing the penetration of air or moisture.

[0123] Next, second contact holes (CNT2) are formed in the first barrier insulating layer (BIL1). The second contact holes (CNT2) can be formed using a dry etching process. The second contact holes (CNT2) can penetrate the first barrier insulating layer (BIL1) and expose the upper surface of the first substrate (SUB1).

[0124] Next, referring to FIG. 8, pad electrodes (PDs) are formed. The pad electrodes (PDs) are formed by sequentially stacking a first metal layer material and a second metal layer material and etching them in batches to form the first metal layer (MTL1) and the second metal layer (MTL2) of the pad electrodes (PDs). The pad electrodes (PDs) can be formed as the first pad electrode (PD1) and the second pad electrode (PD2) within the second contact holes (CNT2). According to one embodiment, the first metal layer (MTL1) may be positioned below the upper surface of the first barrier insulating layer (BIL1), and the second metal layer (MTL2) may have its lower surface positioned below the upper surface of the first barrier insulating layer (BIL1) and its upper surface positioned above the upper surface of the first barrier insulating layer (BIL1).

[0125] Next, referring to FIG. 9, a second barrier insulating layer (BIL2) is formed on the first barrier insulating layer (BIL1) and the pad electrodes (PD). The second barrier insulating layer (BIL2) is formed by the same process as the first barrier insulating layer (BIL1) described above and may include an inorganic material capable of preventing the penetration of air or moisture. Subsequently, a second substrate (SUB2) is formed on the second barrier insulating layer (BIL2). The second substrate (SUB2) is formed by the same process as the first substrate (SUB1) described above and may be formed of the same material.

[0126] Next, referring to FIG. 10, a display layer (DPL) is formed on a second substrate (SUB2). The display layer (DPL) may have a thin film transistor layer (TFTL), a light-emitting element layer (EML), a wavelength conversion layer (WLCL), and a color filter layer (CFL) sequentially stacked on the second substrate (SUB2). Then, an encapsulation layer (TFE) is formed to cover the upper surface and side surface of the display layer (DPL), and an anti-reflection film (ARF) is formed on the encapsulation layer (TFE).

[0127] Next, referring to FIGS. 11 and 12, the display device (10) is inverted vertically to form a flexible film (FPCB), and the first carrier substrate (CG1) is removed from the first substrate (SUB1). The first carrier substrate (CG1) can be removed from the lower surface of the first substrate (SUB1) using a sacrificial layer (not shown) disposed between the first carrier substrate (CG1) and the first substrate (SUB1), but is not limited thereto.

[0128] Next, one surface of the first substrate (SUB1) is etched (1 etch ) to form first grooves (GRO1) on the first substrate (SUB1). First etching (1 etchThe process is performed using at least one of a dry etching process, a plasma etching process, and a laser etching process. For example, the first grooves (GRO1) of the first substrate (SUB1) can be etched through a pulse laser etching process. Pulse laser etching may utilize a laser wavelength of 190 nm to 360 nm. The power of the pulse laser etching may be 0.4 W to 30 W, the laser spot size may be 20 µm to 200 µm, the pulse width may be 0.1 to 20 ps (pico second), and the repetition rate may be 50 kHz to 2000 kHz. In an exemplary embodiment, pulse laser etching may be performed under conditions of a wavelength of 355 nm, a power of 20 W, a spot size of 150 µm, a pulse width of 15 ps, and a repetition rate of 800 kHz. However, it is not limited to this.

[0129] First grooves (GRO1) can be formed on one surface of the first substrate (SUB1) using the pulsed laser etching described above. The first grooves (GRO1) can be formed in a concave shape with a predetermined depth from one surface of the first substrate (SUB1). Each of the first grooves (GRO1) can be arranged to overlap with the second contact holes (CNT2) of the first barrier insulating layer (BIL1), and can be aligned and matched with the second contact holes (CNT2) in the thickness direction (Z-axis direction). The first grooves (GRO1) can be arranged spaced apart from each other in the first direction (X-axis direction).

[0130] Next, referring to FIGS. 13 and 14, one surface of the first substrate (SUB1) is subjected to a second etching (2 etch ) to form the first contact hole (CNT1) and sub-contact hole (SCNT). The first contact hole (CNT1) can be formed on the first substrate (SUB1) in an area including the first grooves (GRO1) using pulsed laser etching. The second etching (2 etch ) is the aforementioned first etching (1etch A pulsed laser etching identical to ) can be used, and the first etching (1 etch It can be performed within the process conditions of ).

[0131] 2nd etching (2 etch When ) the first substrate (SUB1) is etched and removed by the same thickness, and the etching is terminated when the pad electrodes (PD) are exposed. The area where the first grooves (GRO1) of the first substrate (SUB1) are formed is etched to form sub-contact holes (SCNT), thereby exposing the pad electrodes (PD). For example, the first sub-contact hole (SCNT1) exposes the first pad electrode (PD1), and the second sub-contact hole (SCNT2) exposes the second pad electrode (PD2). The area of ​​the first substrate (SUB1) other than the first grooves (GRO1) is not completely etched and remains to form a substrate buffer portion (BSUB). According to one embodiment, the second etching (2 etch When the pad electrodes (PDs) are exposed and laser irradiation is terminated, a substrate buffer portion (BSUB) is formed in an area other than the pad electrodes (PDs) to prevent the laser from being irradiated onto the second substrate (SUB2). That is, the substrate buffer portion (BSUB) can serve to protect the second substrate (SUB2) so that the laser is no longer transmitted. Therefore, in one embodiment, the second etching (2 etch It is possible to prevent the second substrate (SUB2) from being damaged during the process.

[0132] Next, referring to FIGS. 15 and 16, a flexible film (FPCB) is prepared. A display driver (DIC) is placed on one side of the flexible film (FPCB), and a film pad (PAE) is placed on the other side. The flexible film (FPCB) is aligned on one side of a first substrate (SUB1), such that the film pad (PAE) faces the first substrate (SUB1). Then, the film pad (PAE) of the flexible film (FPCB) and the pad electrodes (PD) are connected using a connection film (ACF). The film pad (PAE) of the flexible film (FPCB) can be electrically connected to the pad electrode (PD) through the connection film (ACF).

[0133] Next, a flexible film (FPCB) is attached and fixed to one side of the first substrate (SUB1) using an adhesive member (ADM). However, this is not limited thereto, and the adhesive member (ADM) may be omitted. Accordingly, a display device (10) according to one embodiment can be manufactured.

[0134] FIG. 17 is a plan view showing the combined structure of a tile-type display device according to one embodiment. FIG. 18 is a cross-sectional view taken along the line II-II' of FIG. 17.

[0135] Referring to FIGS. 17 and 18, a tile-type display device (TD) may include a plurality of display devices (10), a connecting member (20), and a cover member (30). The plurality of display devices (10) may be arranged in a grid pattern, but are not limited thereto. The plurality of display devices (10) may be connected in a first direction (X-axis direction) or a second direction (Y-axis direction), and the tile-type display device (TD) may have a specific shape. For example, each of the plurality of display devices (10) may have the same size as each other, but is not limited thereto. As another example, the plurality of display devices (10) may have different sizes.

[0136] The tile-type display device (TD) may include first to fourth display devices (10-1 to 10-4). The number and combination relationship of the display devices (10) are not limited to the embodiment of FIG. 17. The number of display devices (10) may be determined according to the size of each display device (10) and the tile-type display device (TD). For example, the tile-type display device (TD) may include the display device (10) shown in FIG. 3.

[0137] The display device (10) may include a display area (DA) and a non-display area (NDA). The display area (DA) may include a plurality of pixels to display an image. The non-display area (NDA) may be placed around the display area (DA) to surround the display area (DA) and may not display an image.

[0138] A tile-type display device (TD) may include a bonding area (SM) positioned between a plurality of display areas (DA). The tile-type display device (TD) may be formed by connecting the non-display areas (NDA) of each adjacent display device (10). A plurality of display devices (10) may be connected to each other through a bonding member (20) or an adhesive member positioned in the bonding area (SM). A bonding area (SM) of each of the plurality of display devices (10) may not include a flexible film. Accordingly, the distance between the display areas (DA) of each of the plurality of display devices (10) may be close enough that the bonding area (SM) between the plurality of display devices (10) is not perceived by the user. Additionally, the external light reflectance of the display area (DA) of each of the plurality of display devices (10) and the external light reflectance of the bonding area (SM) between the plurality of display devices (10) may be substantially the same. Accordingly, the tile-type display device (TD) can improve the sense of disconnection between the multiple display devices (10) and enhance the immersion of the image by preventing the user from perceiving the combined area (SM) between the multiple display devices (10).

[0139] A display device (10) may include a plurality of pixels arranged along a plurality of rows and columns in a display area (DA). Each of the plurality of pixels may include a light-emitting region (LA) defined by a pixel defining film or bank, and may emit light having a predetermined peak wavelength through the light-emitting region (LA). For example, the display area (DA) of the display device (10) may include first to third light-emitting regions (LA1, LA2, LA3). Each of the first to third light-emitting regions (LA1, LA2, LA3) may be a region where light generated from a light-emitting element of the display device (10) is emitted to the outside of the display device (10).

[0140] The first to third light-emitting regions (LA1, LA2, LA3) may be sequentially and repeatedly arranged along the first direction (X-axis direction) of the display region (DA). For example, the area of ​​the third light-emitting region (LA3) may be larger than the area of ​​the first light-emitting region (LA1), and the area of ​​the first light-emitting region (LA1) may be larger than the area of ​​the second light-emitting region (LA2). As another example, the area of ​​the first light-emitting region (LA1), the area of ​​the second light-emitting region (LA2), and the area of ​​the third light-emitting region (LA3) may be substantially the same.

[0141] The display area (DA) of the display device (10) may include a light-blocking area (BA) surrounding a plurality of light-emitting areas (LA). The light-blocking area (BA) can prevent the mixing of light emitted from the first to third light-emitting areas (LA1, LA2, LA3).

[0142] A tile-type display device (TD) can connect the sides of adjacent display devices (10) by using a connecting member (20) positioned between each of the multiple display devices (10). The connecting member (20) can implement the tile-type display device (TD) by connecting the sides of the first to fourth display devices (10-1 to 10-4) arranged in a grid shape. The connecting member (20) can connect the sides of the first substrate (SUB1), the sides of the first and second barrier insulation layers (BIL1, BIL2), the sides of the second substrate (SUB2), the sides of the display layer (DPL), the sides of the encapsulation layer (TFE), and the sides of the anti-reflection film (ARF) of the adjacent display devices (10).

[0143] For example, the connecting member (20) can be made of an adhesive or double-sided tape having a relatively thin thickness, thereby minimizing the gap between multiple display devices (10). As another example, the connecting member (20) can be made of a connecting frame having a relatively thin thickness, thereby minimizing the gap between multiple display devices (10). Thus, the tile-type display device (TD) can prevent the connecting area (SM) between multiple display devices (10) from being perceived by the user.

[0144] The cover member (30) is disposed on the upper surface of a plurality of display devices (10) and a coupling member (20) to cover the plurality of display devices (10) and the coupling member (20). For example, the cover member (30) may be disposed on the upper surface of the anti-reflection film (ARF) of each of the plurality of display devices (10). The cover member (30) may protect the upper surface of a tile-type display device (TD).

[0145] FIGS. 19 to 22 are cross-sectional views showing a method for manufacturing a display device according to another embodiment, by process.

[0146] Referring to FIGS. 19 to 22, this embodiment differs from the embodiment of FIGS. 7 to 16 described above in that the thickness of the first substrate (SUB1) is reduced during the second etching process, and the first contact hole (CNT1) and sub-contact hole (SCNT) are formed by performing a third etching process. Hereinafter, descriptions that overlap with the embodiment described above will be omitted, and the differences will be explained.

[0147] As shown in FIG. 19, the process described above in FIG. 7 to FIG. 12 is performed in the same way to form first grooves (GRO1) on one surface of the first substrate (SUB1).

[0148] Next, referring to FIGS. 19 to 21, one surface of the first substrate (SUB1) is subjected to a second etching (2 etch ) to form a second groove (GRO2). Second etching (2 etch ) is the aforementioned first etching (1 etch A method identical to the process can be used, for example, pulsed laser etching can be used. The second groove (GRO2) can be formed by reducing the thickness of the first substrate (SUB1) while maintaining the shape of the first grooves (GRO1). The first grooves (GRO1) can be formed on the bottom surface within the second groove (GRO2) while maintaining their shape. The first grooves (GRO1) can be aligned with each other by overlapping the second contact holes (CNT2) of the first barrier insulating layer (BIL1) in the thickness direction (Z-axis direction).

[0149] In one embodiment, the second etching (2 etch ) Form a second groove (GRO2) but do not expose the lower pad electrodes (PD). Second etching (2 etch The laser used in the process can be irradiated up to the second substrate (SUB2) as its transmittance increases as the thickness of the first substrate (SUB1) decreases. If the laser is transmitted and irradiated onto the second substrate (SUB2), the second substrate (SUB2) may be damaged. In this embodiment, the second etching (2 etchBy forming the second groove (GRO2) at ) time, damage to the second substrate (SUB2) can be prevented.

[0150] Next, referring to FIG. 22, the second groove (GRO2) of the first substrate (SUB1) is etched in the third etching (3 etch ) to form the first contact hole (CNT1) and sub-contact hole (SCNT). Third etching (3 etch When ) the first substrate (SUB1) is etched and removed by the same thickness, and the etching is terminated when the pad electrodes (PD) are exposed. Specifically, the area where the first groove (GRO1) of the first substrate (SUB1) is formed is etched to form sub-contact holes (SCNT), thereby exposing the lower pad electrodes (PD). For example, the first sub-contact hole (SCNT1) exposes the first pad electrode (PD1), and the second sub-contact hole (SCNT2) exposes the second pad electrode (PD2). Within the second groove (GRO2), the area of ​​the first substrate (SUB1) other than the first grooves (GRO1) is not completely etched and remains to form a substrate buffer portion (BSUB). The substrate buffer portion (BSUB) is formed during the second etching (2 etch In the process, damage to the second substrate (SUB2) by the laser can be prevented.

[0151] According to one embodiment, the third etching (3 etch ) can utilize a dry etching process or a plasma etching process, and, for example, can be performed using a plasma etching process using atmospheric pressure plasma (AP Plasma). The plasma etching process etches the exposed surface, thereby preventing damage to the second substrate (SUB2) placed inside. The third etching (3 etch ) can be performed, for example, by adjusting the power output of 100 to 1000 W and the flow rate ratio of oxygen and nitrogen gases, and preferably by using a power output of 700 W. In addition, the third etching (3 etch) can be performed using a mask in which the area where the second groove (GRO2) is formed is open.

[0152] The subsequent process can be performed as described in FIGS. 15 and FIGS. 16 to manufacture a display device (10).

[0153] FIGS. 23 to 26 are cross-sectional views showing a method for manufacturing a display device according to another embodiment, by process.

[0154] Referring to FIGS. 23 to 26, the order of the etching processes of FIGS. 11 to 14 described above may be changed in this embodiment. Hereinafter, descriptions that overlap with the above embodiment will be omitted, and the differences will be described.

[0155] As shown in FIG. 23, the display device (10) is inverted by performing the same process of FIG. 7 to FIG. 10 described above.

[0156] Next, referring to FIGS. 23 and 24, one surface of the first substrate (SUB1) is subjected to a first etching (1 etch ) to form a first contact hole (CNT1). First etching (1 etch ) can be etched through a pulse laser etching process and can be performed under the pulse laser etching process conditions described above. The first contact hole (CNT1) can be formed by overlapping with the pad electrodes (PD). The thickness of the first substrate (SUB1) overlapping with the first contact hole (CNT1) can be reduced, and this thickness can be the thickness of the substrate buffer portion (BSUB) of the first substrate (SUB1) described later. In one embodiment, the first etching (1 etch ) When forming the first contact hole (CNT1), the lower pad electrodes (PD) are not exposed. The first etching (1 etchThe laser used in the process can be irradiated up to the second substrate (SUB2) as the transmittance increases as the thickness of the first substrate (SUB1) decreases. If the laser is transmitted and irradiated onto the second substrate (SUB2), the second substrate (SUB2) may be damaged. In this embodiment, the first etching (1 etch By forming a first contact hole (CNT1) that does not penetrate the first substrate (SUB1), damage to the second substrate (SUB2) can be prevented.

[0157] Next, referring to FIGS. 25 and 26, one surface of the first substrate (SUB1) is subjected to a second etching (2 etch ) to form sub-contact holes (SCNTs). Second etching (2 etch ) is the aforementioned first etching (1 etch The same method as the ) process can be used, for example, pulsed laser etching can be used. Second etching (2 etch When ), a predetermined area of ​​the first substrate (SUB1), for example, an area overlapping with the pad electrodes (PDs), is etched and removed, and the etching is terminated when the pad electrodes (PDs) are exposed. Specifically, the first substrate (SUB1) overlapping with the pad electrodes (PDs) is etched to form sub-contact holes (SCNTs), and the lower pad electrodes (PDs) are exposed by the sub-contact holes (SCNTs). For example, the first sub-contact hole (SCNT1) exposes the first pad electrode (PD1), and the second sub-contact hole (SCNT2) exposes the second pad electrode (PD2). Within the first contact hole (SCNT1), the area of ​​the first substrate (SUB1) other than the sub-contact holes (SCNTs) is not etched and is formed as a substrate buffer portion (BSUB). The substrate buffer portion (BSUB) is formed during the first etching (1 etch In the process, damage to the second substrate (SUB2) by the laser can be prevented.

[0158] The subsequent process can be performed as described in FIGS. 15 and FIGS. 16 to manufacture a display device (10).

[0159] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing the technical concept or essential features thereof. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0160] 10: Display device SUB1, 2: First and second substrates BIL1, 2: First and second barrier insulating layers PD: Pad electrode BSUB: Substrate buffer section MTL1, 2: First and second metal layers CNT1, 2: 1st and 2nd contact holes GRO1, 2: 1st and 2nd grooves FPCB: Flexible Film SCNT: Sub-contact Hole ACF: Connection Film DPL: Display Layer

Claims

Claim 1 A display device comprising: a first substrate including a display area and a non-display area adjacent to the display area, and including a first contact hole in the display area; a first barrier insulating layer disposed on the first substrate and including second contact holes that overlap with the first contact hole in the display area; pad electrodes disposed on the first barrier insulating layer, at least a portion of which is disposed within the second contact holes; a display layer disposed on the pad electrodes and including pixels in the display area; and a flexible film disposed on the lower portion of the first substrate and electrically connected to the pad electrodes through the first contact hole and the second contact hole, wherein the first substrate includes a substrate buffer portion that overlaps with the first contact hole in the display area and does not overlap with the second contact holes, the first thickness of the substrate buffer portion is smaller than the second thickness of the first substrate that does not overlap with the first contact hole, and the substrate buffer portion is surrounded by the first substrate having the second thickness. Claim 2 delete Claim 3 A display device according to claim 1, wherein the first substrate overlaps with the first contact hole and includes sub-contact holes that overlap with the second contact holes. Claim 4 In claim 3, the substrate buffer portion is disposed around the sub-contact holes, and the display device surrounding the sub-contact holes. Claim 5 In claim 1, the substrate buffer portion overlaps with the first barrier insulating layer and is a display device surrounding the second contact holes. Claim 6 A display device according to claim 1, wherein the thickness of the substrate buffer portion is 0.5㎛ to 1.5㎛. Claim 7 In claim 1, the pad electrodes comprise a first metal layer and a second metal layer disposed on the first metal layer, wherein the first metal layer is disposed adjacent to the flexible film. Claim 8 A display device according to claim 1, further comprising a second barrier insulating layer and a second substrate disposed between the pad electrode and the display layer, wherein the second barrier insulating layer covers the pad electrodes and the second substrate is disposed on the second barrier insulating layer. Claim 9 A display device according to claim 1, further comprising a connection film disposed between the flexible film and the pad electrodes, wherein the connection film electrically connects the pad electrodes and the flexible film. Claim 10 A display device according to claim 1, wherein the display layer comprises: a thin-film transistor layer disposed on the pad electrodes; a light-emitting element layer disposed on the thin-film transistor layer; a wavelength conversion layer disposed on the light-emitting element layer; and a color filter layer disposed on the wavelength conversion layer. Claim 11 A method for manufacturing a display device comprising: a step of preparing a first substrate; a step of forming a first barrier insulating layer on one side of the first substrate and forming first contact holes in the first barrier insulating layer; a step of forming pad electrodes on the first barrier insulating layer and the first contact holes; a step of forming a display layer on the pad electrodes; a step of first etching the other side of the first substrate that overlaps with the first contact holes to form first grooves; a step of second etching the other side of the first substrate including the first grooves to form second contact holes; and a step of electrically connecting a flexible film on the pad electrodes. Claim 12 A method for manufacturing a display device according to claim 11, wherein the first grooves are formed to overlap with the first contact holes of the first barrier insulating layer and the pad electrodes. Claim 13 A method for manufacturing a display device according to claim 11, wherein the second etching etches the first substrate to form sub-contact holes that expose the pad electrodes, and a substrate buffer portion that does not overlap with the first contact holes. Claim 14 A method for manufacturing a display device according to claim 13, wherein the first substrate in the area overlapping with the first grooves is completely removed to form the sub-contact holes that expose the pad electrodes, and the first substrate in the area not overlapping with the first grooves is partially removed to form the substrate buffer portion. Claim 15 In claim 11, the second etching is a method for manufacturing a display device in which the first substrate is removed by a predetermined thickness to form a second groove on the bottom surface in which the first grooves are arranged. Claim 16 A method for manufacturing a display device according to claim 15, wherein the first substrate disposed within the second groove is etched a third time to expose the pad electrodes, and the substrate buffer portion is formed that does not overlap with the first contact holes. Claim 17 In claim 16, the method for manufacturing a display device wherein the third etching is performed by an atmospheric pressure plasma etching process. Claim 18 A method for manufacturing a display device according to claim 11, wherein the first etching and the second etching are performed by a pulsed laser etching process. Claim 19 A method for manufacturing a display device comprising: a step of preparing a first substrate; a step of forming a first barrier insulating layer on one side of the first substrate and forming first contact holes in the first barrier insulating layer; a step of forming pad electrodes on the first barrier insulating layer and the first contact holes; a step of forming a display layer on the pad electrodes; a step of first etching the other side of the first substrate that overlaps with the first contact hole to form a second contact hole; a step of second etching the first substrate disposed within the second contact hole to form sub-contact holes that expose the pad electrodes and a substrate buffer portion that does not overlap with the first contact holes; and a step of electrically connecting a flexible film on the pad electrodes. Claim 20 A tile-type display device comprising: a plurality of display devices including a display area having a plurality of pixels and a non-display area surrounding the display area; and a coupling member for coupling the plurality of display devices, wherein each of the plurality of display devices comprises: a first substrate including a first contact hole; a first barrier insulating layer disposed on the first substrate and including second contact holes that overlap with the first contact hole; pad electrodes disposed on the first barrier insulating layer, at least a portion of which is disposed within the second contact holes; a display layer disposed on the pad electrodes; and a flexible film disposed on the lower part of the first substrate and electrically connected to the pad electrodes through the first contact hole and the second contact holes, wherein the first substrate comprises a substrate buffer portion that overlaps with the first contact hole and does not overlap with the second contact holes.

Images