Field-effect transistor with modified access regions

Abstract

A transistor device comprises a semiconductor epitaxial layer structure including a channel layer and a barrier layer on the channel layer having a bandgap higher than that of the channel layer. A modified access region is provided on the upper surface of the barrier layer facing the channel layer. The modified access region comprises a material having a surface barrier height lower than that of the barrier layer. A source contact and a drain contact are formed on the barrier layer, and a gate contact is formed between the source contact and the drain contact. The modified access region may include a plurality of optional modified access regions on the upper surface of the barrier layer facing the channel layer. The plurality of optional modified access regions are spaced apart on the barrier layer along the length of the gate contact.

Description

Technology Field

[0001] Cross-reference regarding related applications

[0002] This application claims the benefit and priority of U.S. Patent Application No. 17 / 325,643 filed May 20, 2021, under the title "FIELD EFFECT TRANSISTOR WITH SELECTIVE MODIFIED ACCESS REGIONS" and U.S. Patent Application No. 17 / 325,635 filed May 20, 2021, under the title "FIELD EFFECT TRANSISTOR WITH MODIFIED ACCESS REGIONS", the disclosures and contents thereof, the whole of which are incorporated herein by reference.

[0003] The present disclosure relates to transistor structures, and in particular to high electron mobility transistors. Background Technology

[0004] Narrow bandgap semiconductor materials, such as silicon (Si) and gallium arsenide (GaAs), are widely used in semiconductor devices for low-power and, in the case of Si, low-frequency applications. However, these semiconductor materials may not be suitable for high-power and / or high-frequency applications, for example, due to their relatively small bandgaps (1.12 eV for Si and 1.42 for GaAs at room temperature) and relatively small breakdown voltages.

[0005] Interest in high-power, high-temperature and / or high-frequency applications and devices has focused on wide-bandgap semiconductor materials such as silicon carbide (3.2 eV for 4H-SiC at room temperature) and group III nitrides (e.g., 3.36 eV for GaN at room temperature). These materials can have higher electric field breakdown strengths and higher electron saturation velocities than GaAs and Si.

[0006] A device of particular interest for high-power and / or high-frequency applications is the High Electron Mobility Transistor (HEMT), also known as the Modulation-Doped Field Effect Transistor (MODFET). In HEMT devices, a two-dimensional electron gas (2DEG) can be formed at a heterojunction of two semiconductor materials having different bandgap energies, wherein the smaller bandgap material has higher electron affinity than the wider bandgap material. The 2DEG is an accumulation layer within the undoped smaller bandgap material, for example, 10 13 Carrier / cm 2It may include a relatively high sheet electron concentration exceeding [value]. Additionally, electrons originating from the wider bandgap semiconductor can move to the 2DEG, allowing for relatively high electron mobility due to reduced ionized impurity scattering. This combination of relatively high carrier concentration and carrier mobility can provide the HEMT with relatively large transconductance and offer performance advantages over metal-semiconductor field effect transistors (MESFETs) for high-frequency applications.

[0007] HEMTs fabricated in gallium nitride / aluminum gallium nitride (GaN / AlGaN) material systems can generate a large amount of RF power due to a combination of material properties such as relatively high breakdown fields, relatively wide band gaps, relatively large conduction band offset, and / or relatively high saturated electron drift velocity. Most of the electrons in the 2DEG can be attributed to polarization in AlGaN.

[0008] FIG. 1a illustrates a conventional gallium nitride-based HEMT structure. The structure comprises a substrate (10) which may be a semi-insulating 4H silicon carbide (SiC) substrate. Optional buffers, nucleation and / or transition layers (not illustrated) may be provided on the substrate (10). A channel layer (20) is provided on the substrate (10). The channel layer (20) may be a group III nitride such as GaN. A barrier layer (22) is provided on the channel layer (20). The barrier layer (22) has a band gap greater than the band gap of the channel layer (20), and the channel layer (20) may have an electron affinity greater than that of the barrier layer (22). The barrier layer (22) may be AlN, AlInN, AlGaN, or AlInGaN, and is sufficiently thick and has an Al composition and doping sufficiently high to induce a significant carrier concentration at the interface between the channel layer (20) and the barrier layer (22). This induced carrier concentration forms a two-dimensional electron gas (2DEG), which provides a conductive channel to the device. The conductivity of the 2DEG channel can be controlled by applying a voltage to the gate contact (32) formed on the barrier layer (22).

[0009] FIG. 1a also illustrates a cap layer (24) on a barrier layer (22), and a gate contact (32) is located within a recess (36) through the cap layer (24). The cap layer (24) can reduce surface effects of the device by physically moving the uppermost (outer) surface of the device away from the channel. The cap layer (24) can be formed as a blanket on the barrier layer (22), and can be formed by epitaxial growth and / or deposition. Typically, the cap layer (24) can have a thickness of about 2 nm to about 500 nm.

[0010] As further illustrated in FIG. 1a, ohmic source / drain contacts (30) are provided on a barrier layer (22), and a gate recess is provided through a cap layer (24) to expose a portion of the barrier layer (22). A gate contact (32) is formed within the recess and contacts the exposed portion of the barrier layer (22). The gate contact (32) may be a "T" gate as illustrated in FIG. 1a.

[0011] A passivation layer (not shown) may also be provided on the structure of FIG. 1a. For example, referring to FIG. 1b, a SiN layer (52) may be formed in situ on the surface of the device. The structure of FIG. 1b including the passivation layer may be annealed in a nitrogen environment to improve process parameters.

[0012] Despite the presence of the cap layer (24) and the annealing of the structure, conventional HEMT structures may suffer from trapped charges in the barrier layer or channel layer of the device, which can cause distortion of signals passing through the device. For example, trapped charges can cause output lag, which can undesirably reduce the switching speed of the device, and thus the bandwidth.

[0013] A transistor device according to some embodiments comprises a semiconductor epitaxial layer structure including a channel layer and a barrier layer on the channel layer, wherein the barrier layer has a higher bandgap than the channel layer, and a modified access region on the upper surface of the barrier layer facing the channel layer. The modified access region comprises a material having a surface barrier height lower than that of the barrier layer. A source contact and a drain contact are formed on the barrier layer, and a gate contact is formed between the source contact and the drain contact.

[0014] In some embodiments, the gate contact may form a Schottky contact with the modified access region. In other embodiments, the gate contact may not contact the modified access region.

[0015] The transistor device may further include a doped source region in the barrier layer—where the source contact is in contact with the source region—and a doped drain region in the barrier layer—where the drain contact is in contact with the drain region. The source region and the drain region define an active region of the device between the source region and the drain region, and a modified access region is on the barrier layer over the entire active region of the device.

[0016] In some embodiments, the modified access region includes a region of increased conductivity on the upper surface of the barrier layer facing the channel layer.

[0017] In some embodiments, the modified access region includes an injected region comprising dopants injected at the upper surface of the barrier layer facing the channel layer.

[0018] In some embodiments, the modified access region has a thickness of about 0.1 nm to about 40 nm and about 1E14 cm -3 to about 1E17 cm -3 It has a doping concentration of . In some embodiments, the modified access region has a thickness of about 0.5 nm to about 10 nm.

[0019] In some embodiments, the modified access region comprises an epitaxial semiconductor layer of a material having a bandgap lower than that of the barrier layer. In some embodiments, the barrier layer comprises AlGaN, and the modified access region comprises AlGaN having an Al concentration lower than that of the barrier layer. In some embodiments, the barrier layer comprises AlGaN, and the modified access region comprises GaN. The modified access region may be doped with n-type dopants.

[0020] The modified access region can provide a charge release path that allows charge carriers present on the upper surface of the barrier layer facing the channel layer to conduct toward the drain contact.

[0021] In some embodiments, the modified access region is not provided in the region between the source contact and the gate contact. In some embodiments, the modified access region is in the region between the gate contact and the drain contact and does not extend completely from the source contact to the drain contact. The gate contact may not contact the modified access region.

[0022] The transistor device may further include a drain region doped in the barrier layer, a drain contact contacts the drain region, and a modified access region contacts the drain region.

[0023] A method for forming a transistor device according to some embodiments comprises the steps of: providing a semiconductor epitaxial layer structure comprising a channel layer and a barrier layer on the channel layer, wherein the barrier layer has a bandgap higher than that of the channel layer; forming a modified access region on the upper surface of the barrier layer facing the channel layer; forming a source contact and a drain contact on the barrier layer; and forming a gate contact between the source contact and the drain contact. The modified access region comprises a material having a surface barrier height lower than that of the barrier layer.

[0024] In some embodiments, the step of forming a modified access region includes forming a sacrificial dielectric layer on a barrier layer, annealing the sacrificial dielectric layer and the barrier layer, and removing the sacrificial dielectric layer. The sacrificial dielectric layer may comprise SiN, SiOx, AlN, AlO, and / or HfO.

[0025] In some embodiments, the step of forming a modified access region includes the step of forming an epitaxial layer of a material having a bandgap lower than that of the barrier layer on the barrier layer. The epitaxial layer may be doped with n-type dopants.

[0026] In some embodiments, the step of forming a modified access region includes the step of injecting n-type dopants into the upper surface of a barrier layer facing the channel layer.

[0027] In some embodiments, the modified access region is located in the region between the gate contact and the drain contact, and does not extend completely between the source contact and the drain contact.

[0028] The gate contact may not come into contact with the modified access area.

[0029] The method may further include the step of forming a drain region doped in the barrier layer, a drain contact in contact with the drain region, and a modified access region in contact with the drain region.

[0030] A transistor device according to additional embodiments comprises a semiconductor epitaxial layer structure comprising a channel layer and a barrier layer on the channel layer—the barrier layer having a bandgap higher than that of the channel layer—a source contact and a drain contact on the barrier layer, and a gate contact between the source contact and the drain contact on the barrier layer. The device further comprises a plurality of optionally modified access regions on the upper surface of the barrier layer facing the channel layer. The optionally modified access regions comprise a material having a surface barrier height lower than that of the barrier layer, and the plurality of optionally modified access regions are spaced apart on the barrier layer along the length of the gate contact.

[0031] The transistor device may further include a drain region doped in the barrier layer, a drain contact in contact with the drain region, and optionally modified access regions are located between the gate contact and the drain region on the barrier layer.

[0032] In some embodiments, optionally modified access regions include regions of increased conductivity on the upper surface of the barrier layer facing the channel layer. Optionally modified access regions include injected regions that may contain injected dopants on the upper surface of the barrier layer facing the channel layer.

[0033] In some embodiments, the optionally modified access regions have a thickness of about 0.1 nm to about 40 nm and about 1E14 cm -3 to about 1E17 cm -3 It has the doping concentration of

[0034] In some embodiments, the optionally modified access regions comprise epitaxial semiconductor layers of a material having a bandgap lower than that of the barrier layer. The barrier layer may comprise AlGaN, and the optionally modified access regions comprise AlGaN having an Al concentration lower than that of the barrier layer. In some embodiments, the barrier layer comprises AlGaN, and the optionally modified access regions comprise GaN.

[0035] Selectively modified access regions can be doped with n-type dopants.

[0036] In some embodiments, the optionally modified access regions have a thickness of about 0.1 nm to about 40 nm and about 1E14 cm -3 to about 1E17 cm -3 It can have a doping concentration of

[0037] Selectively modified access regions can provide charge release paths that allow charge carriers present on the upper surface of the barrier layer facing the channel layer to conduct toward the drain contact.

[0038] The gate contact may not come into contact with the optionally modified access areas.

[0039] In some embodiments, optional modified access regions have a first width d1 and are spaced apart by a second width d2 on the barrier layer along the length of the gate contact. The first width d1 may be about 1 micron to 100 microns, and the second width d2 may be about 1 micron to 100 microns.

[0040] A method for forming a transistor device according to some embodiments comprises the steps of: providing a semiconductor epitaxial layer structure comprising a channel layer and a barrier layer on the channel layer, wherein the barrier layer has a bandgap higher than that of the channel layer; forming a source contact and a drain contact on the barrier layer; forming a gate contact between the source contact and the drain contact on the barrier layer; and forming a plurality of optionally modified access regions on the upper surface of the barrier layer facing the channel layer. The optionally modified access regions comprise a material having a surface barrier height lower than that of the barrier layer and are spaced apart along the length of the gate contact.

[0041] In some embodiments, the step of forming selectively modified access regions comprises the step of forming a mask on a barrier layer—the mask having a plurality of openings therein that expose each portion of the upper surface of the barrier layer—and the step of forming selectively modified access regions in the portions of the upper surface of the barrier layer exposed by the openings.

[0042] The step of forming charge cap emission regions may include the step of forming a sacrificial dielectric layer on a mask and a barrier layer—the sacrificial dielectric layer extends into the openings and contacts the barrier layer at portions of the upper surface of the barrier layer exposed by the openings—the step of annealing the sacrificial dielectric layer and the barrier layer, and the step of removing the sacrificial dielectric layer.

[0043] In some embodiments, the sacrificial dielectric layer comprises SiN, SiOx, AlN, AlO, and / or HfO.

[0044] In some embodiments, the step of forming selectively modified access regions includes the step of selectively forming epitaxial layers on portions of the upper surface of the barrier layer exposed by the openings, and the epitaxial layers comprise a material having a band gap lower than that of the barrier layer. The epitaxial layers may be doped with n-type dopants.

[0045] In some embodiments, the step of forming selectively modified access regions includes the step of injecting n-type dopants into portions of the upper surface of the barrier layer exposed by the openings.

[0046] The gate contact may or may not contact the optionally modified access areas.

[0047] The method may further include the step of forming a drain region doped in the barrier layer, a drain contact in contact with the drain region, and optionally modified access regions in contact with the drain region.

[0048] The optionally modified access regions may have a first width d1 and may be spaced apart by a second width d2 on the barrier layer along the length of the gate contact. The first width d1 may be about 1 micron to 100 microns, and the second width d2 may be about 1 micron to 100 microns. Brief explanation of the drawing

[0049] FIG. 1a is a cross-sectional view of a conventional transistor device including a field plate. FIG. 1b is a cross-sectional view of an intermediate structure of a conventional transistor device. FIG. 2 is a schematic plan view of a HEMT device according to some embodiments. FIGS. 3a to 3d are cross-sectional views illustrating operations for forming HEMT device structures according to various embodiments. FIG. 4a illustrates the results of a test setup including a conventional GaN HEMT and a GaN HEMT including a modified access region. Figure 4b is a chart comparing the Schottky barrier heights of conventional transistors with the Schottky barrier heights of transistors including charge-emission cap layers. Figure 4c is a band diagram illustrating the surface barrier height in HEMT. FIGS. 5a to 5d are cross-sectional views illustrating HEMT device structures according to additional embodiments. FIG. 6a illustrates the results of a test setup including a conventional GaN HEMT and GaN HEMTs including selectively modified access regions according to various embodiments. FIG. 6b is a chart comparing the Schottky barrier heights of conventional transistors with the Schottky barrier heights of transistors including selectively modified access regions according to various embodiments. FIGS. 7a to 7c are cross-sectional views illustrating operations for forming HEMT device structures according to various embodiments. FIG. 7d is a block diagram illustrating operations for forming a transistor device according to some embodiments. FIGS. 8a through 8f, FIGS. 8ga, FIGS. 8gb, and FIGS. 8gc are cross-sectional views illustrating operations for forming HEMT device structures according to additional embodiments. FIG. 8h is a block diagram illustrating operations for forming a transistor device according to some embodiments. FIGS. 9a through 9c are schematic block diagrams of multiple-amplifier circuits in which RF transistor amplifiers including transistor devices according to embodiments can be used. FIG. 10 is a schematic diagram of an MMIC amplifier including a HEMT transistor according to some embodiments. FIGS. 11a and FIGS. 11b are schematic cross-sectional views illustrating exemplary packages for RF transistor amplifier dies according to some embodiments. FIG. 12 is a schematic diagram of the band gap and lattice constant for InAlGaN materials having various different compositions. Specific details for implementing the invention

[0050] Now, embodiments of the concepts of the present invention will be described in conjunction with the accompanying drawings. Some embodiments described herein provide a transistor device comprising a field plate that is a self-aligned gate, and in some embodiments, the field plate is laterally spaced from the gate so as not to overlap with the gate in a vertical direction. In some embodiments, the field plate is recessed toward the barrier layer in a recessed region. In other embodiments, the field plate may be connected to a source outside the active region of the device by a non-crossing connection over the gate of the device.

[0051] Additionally, while ordinal terms such as first, second, third, etc. may be used herein to describe various elements, it is understood that these elements should not be limited by these terms. These terms are used solely to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0052] Additionally, relative terms such as "lower" or "bottom" and "upper" or "top" may be used in this specification to describe the relationship of one element to another as illustrated in the drawings. It is understood that relative terms are intended to include different orientations of the device in addition to the orientations illustrated in the drawings. For example, if the device in one of the drawings is flipped, features described as being on the "lower" side of the element will subsequently be oriented on the "upper" side of the element. Thus, the exemplary term "lower" may describe both lower and upper orientations depending on the specific orientation of the device. Similarly, if the device in one of the drawings is flipped, elements described as being "lower" or "below" of other elements will be oriented on top of these other elements. Thus, the exemplary terms "lower" or "below" may describe both upper and lower orientations.

[0053] The terms used in the description of the disclosure herein are intended only to describe specific embodiments and are not intended to limit the disclosure. As used in the description of the disclosure and in the appended claims, singular forms (“an” and “the”) are intended to include plural forms unless the context clearly indicates otherwise. It is also understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated enumerated items. It will also be understood that the terms “comprises” and “comprising,” as used herein, specify the presence of the mentioned steps, actions, features, elements, and / or components, but do not exclude the presence or addition of one or more other steps, actions, features, elements, components, and / or groups thereof.

[0054] Embodiments of the present disclosure are described herein with reference to cross-sectional drawings, which are schematic diagrams of ideal embodiments of the present disclosure. Accordingly, variations from the shapes of the examples are expected, for example, as a result of manufacturing techniques and / or tolerances. Accordingly, the embodiments of the present disclosure should not be interpreted as being limited to the specific shapes of the regions illustrated herein, but should include, for example, variations in shapes resulting from manufacturing. The regions illustrated in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the regions of the device, nor are they intended to limit the scope of the disclosure unless otherwise explicitly stated. Also, for schematic reasons, lines that appear straight, horizontal, or vertical in the drawings below may often be inclined, curved, not horizontal, or not vertical. Additionally, the thicknesses of the elements are intended to be schematic in nature.

[0055] Unless otherwise defined, all terms used to disclose embodiments of this disclosure, including technical and scientific terms, have the same meaning as generally understood by a person skilled in the art and are not necessarily limited to specific definitions known at the time of this disclosure. Accordingly, these terms may include equivalent terms that arise thereafter. It is further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of this specification and the relevant art.

[0056] Trapped charges in semiconductor devices, such as GaN HEMT devices, can cause nonlinear distortion in the output signals generated by the devices. To reduce such distortion, it is desirable to reduce the presence of trapped charges in the barrier layer of the HEMT device. Although not to be bound by any specific theory, it is currently believed that charges can be injected from the gate contact of the device into the barrier and / or channel layer of the HEMT device, and that such charges can be trapped in the barrier layer, which can adversely affect the switching characteristics of the device. Some embodiments provide a modified access region having a low surface barrier height (SBH) on or above the upper surface of the barrier layer, which forms a charge release path that allows some charges that would have been injected into the barrier and / or channel layer to instead be conducted along the upper surface of the barrier layer to the drain contact of the device. The modified access region comprises a material having a surface barrier height lower than that of the barrier layer of the HEMT relative to the gate contact. By reducing the number of charges that can be trapped in the barrier and / or channel layer, the switching characteristics of the device can be improved.

[0057] A GaN HEMT structure (100) according to some embodiments is illustrated in FIG. 2. As illustrated herein, the structure comprises a substrate (110) on which a channel layer (120) is formed. A barrier layer (122) is formed on the channel layer. Doped source and drain regions (123, 125) are formed on the barrier layer (122) and may extend into the channel layer (120), and source and drain ohmic contacts (124, 126) are formed on the source and drain regions (123, 125), respectively.

[0058] As further illustrated in FIG. 2, a modified access region (140) having a low surface barrier height (SBH) is formed on the upper surface of a barrier layer (122) facing the channel layer (120) within the active region of the device between the source region (123) and the drain region (125). A gate contact (130) is formed on the modified access region (140).

[0059] Although not to be bound by any specific theory, the presence of a modified access region (140) is believed to provide a charge discharge path that allows charges present on the surface of the barrier layer (122), such as charges that may have been injected from the gate contact (130), to flow into the drain region (125) instead of being trapped in the barrier layer (122) and / or channel layer (120), which could affect the charge transfer characteristics of the device.

[0060] A passivation film (128), such as a dielectric film, is formed on the structure, and a gate contact (130) is formed on the passivation film (128). The gate contact (130) extends through an opening in the passivation film (128) and contacts a modified access region (140).

[0061] The substrate (110) may be a semi-insulating silicon carbide (SiC) substrate, for example, which may be a 4H polytype silicon carbide. Other silicon carbide candidate polytypes include 3C, 6H, and 15R polytypes. In specific embodiments of the concepts of the present invention, the silicon carbide bulk crystal is about 1 × 10⁻⁶ at room temperature. 5It has a resistivity of Ω-cm or greater. Optional buffer, nucleation, and / or transition layers (not shown) may be provided on the substrate (110). For example, an AlN buffer layer may be provided to provide a suitable crystal structure transition between the silicon carbide substrate and the rest of the device.

[0062] While silicon carbide can be used as a substrate material, some embodiments may use any suitable substrate such as sapphire, aluminum nitride, aluminum gallium nitride, gallium nitride, silicon, GaAs, LGO, ZnO, LAO, InP, etc.

[0063] Referring still to FIG. 2, the channel layer (120) can be deposited on the substrate (110) using buffer layers, transition layers, and / or nucleation layers as described above. Furthermore, the channel layer and / or buffer nucleation and / or transition layers can be deposited by MOCVD, or by other techniques known to those skilled in the art, such as MBE or HVPE.

[0064] In some embodiments, if the energy of the conduction band edge of the channel layer (120) is less than the energy of the conduction band edge of the barrier layer (122) at the interface between the channel layer and the barrier layer, the channel layer (120) is a Group III nitride such as AlxGa1-xN, where 0 ≤ x < 1. In some embodiments, x = 0, which indicates that the channel layer (120) is GaN. The channel layer (120) may also be other Group III nitrides such as InGaN, AlInGaN, etc. The channel layer (120) may not be doped ("unintentionally doped"), and about 20 It can be grown to a greater thickness. The channel layer (120) may also be a multilayer structure such as a superlattice or combinations of GaN, AlGaN, etc.

[0065] The channel layer (120) may have a band gap smaller than that of the barrier layer (122), and the channel layer (120) may also have an electron affinity greater than that of the barrier layer (122). In some embodiments, the barrier layer (122) is AlN, AlInN, AlGaN, or AlInGaN having a thickness of about 0.1 nm to about 40 nm. In certain embodiments, the barrier layer (122) is sufficiently thick and has a sufficiently high Al composition and doping to induce a significant carrier concentration at the interface between the channel layer (120) and the barrier layer (122).

[0066] In some embodiments, the barrier layer (122) is AlGaN, AlInGaN and / or AlN or a combination of layers thereof. The barrier layer (122) may be, for example, about 0.1 nm to about 40 nm thick, but not thick enough to cause cracks or substantial defect formation therein. In some embodiments, the barrier layer (122) is undoped or about 10 with an n-type dopant. 19 cm -3 It is doped to a concentration less than 0. In some embodiments of the concepts of the present invention, the barrier layer (122) is AlxGa1-xN, where 0 <x≤1이다. 특정 실시예들에서, 알루미늄 농도는 약 25 %이다. 그러나, 본 발명의 개념들의 다른 실시예들에서, 장벽층(122)은 약 5 % 내지 약 100 %의 알루미늄 농도를 갖는 AlGaN을 포함한다. 본 발명의 개념들의 특정 실시예들에서, 알루미늄 농도는 약 10 %보다 크다.

[0067] The gate contact (130) may be a "T" gate as shown in FIG. 2 and may be manufactured using conventional manufacturing techniques. Suitable gate materials may depend on the composition of the barrier layer. In some embodiments, conventional materials capable of forming Schottky contacts for nitride-based semiconductor materials, such as Ni, Pt, NiSix, Cu, Pd, Cr, W and / or WSiN, may be used.

[0068] The passivation layer (128) may be a SiN layer. Optionally, the structure including the passivation layer may be annealed in a nitrogen environment at a temperature of 100°C to 1200°C to activate the injected dopants.

[0069] The modified access region (140) can be formed in various ways. For example, some options for forming the modified access region (140) are illustrated in FIGS. 3a through 3d. Referring to FIG. 3a, in some embodiments, after forming a barrier layer (122) on the channel layer (120), a sacrificial layer (152) is formed on the barrier layer (122). The sacrificial layer (152) may be a dielectric film having a stoichiometry different from that of the barrier layer (122). In certain embodiments, the sacrificial layer (152) may comprise a dielectric material such as SiN, SiOx, AlN, AlO, HfO, etc. The sacrificial layer (152) may be doped or undoped and may have a thickness of about 10 nm to about 200 nm.

[0070] With the sacrificial membrane (152) in place, the structure is annealed by exposing the structure to heat (154). The structure may be annealed at a temperature of about 100 °C to about 1200 °C for a period of about 10 seconds to about 1 hour. The annealing may be performed in an atmosphere such as nitrogen, argon, or other inert gas.

[0071] During annealing, a modified access region (140) is formed on the surface of the barrier layer (122). The modified access region (140) may extend about 0.1 nm to about 40 nm into the barrier layer (122). In certain embodiments, the modified access region may extend about 0.5 nm to about 10 nm into the barrier layer (122).

[0072] Next, the sacrificial film (152) is stripped using, for example, HF etching or another stripping process to clean the surface of the barrier layer (122) and leave the modified access region (140) in place. Then, the remaining operations of device manufacturing are performed (e.g., formation of source / drain regions (123, 125), source / drain contacts (124, 126), passivation layer (128), gate (130), and other dielectric / metallization layers).

[0073] Referring to FIG. 3b, the modified access region (140) may be formed as an epitaxial layer on the barrier layer (122) in some embodiments. The modified access region (140) may be formed as a thin epitaxial layer of a group III nitride-based material having a band gap lower than that of the barrier layer (122), for example. In certain embodiments, the modified access region (140) may be formed as an epitaxial layer of InAlGaN having relative concentrations of In, Al, and Ga such that the modified access region (140) has a band gap lower than that of the barrier layer (122). The relationship between the concentrations of In, Al, and Ga in the InAlGaN material and the band gap of the material is illustrated in FIG. 12, which is a schematic diagram of the band gap and lattice constant for InAlGaN materials having various different compositions (i.e., different relative levels of In, Al, and Ga). As can be seen in Figure 12, as the percentage of Al in the material increases, the band gap of the material generally increases to a high level exceeding 6 eV for AlN, whereas as the percentage of In in the material increases, the band gap of the material decreases to a low level of less than 2 eV for InN.

[0074] In some embodiments, the modified access region (140) may comprise GaN or InGaN. The modified access region (140) may have a thickness of about 0.1 nm to about 40 nm, and in some embodiments, about 0.5 nm to about 10 nm, and may be doped or undoped. In some embodiments, the modified access region (140) may comprise highly doped AlGaN (e.g., about 1E14 cm⁻¹). -3 It may include AlGaN doped with an excess doping concentration. In other embodiments, the charge-releasing cap layer (140) is about 1E14 cm -3 to 1E17 cm -3At the doping concentration, it can be doped with n-type dopants such as silicon and can have a band gap identical or similar to that of the barrier layer (122).

[0075] Referring to FIG. 3c, the modified access region (140) can be formed by injecting dopant ions (156) into the barrier layer (122). The modified access region (140) can be formed by injecting n-type dopants (156), such as silicon, into the surface of the barrier layer (122) to form a region of increased conductivity on the surface of the barrier layer (122). When formed as a region injected into the barrier layer (122), the modified access region (140) is approximately 1E14 cm -3 to about 1E17 cm -3 It can have a doping concentration of and a thickness of about 0.1 nm to about 40 nm.

[0076] Injection energy of approximately 10 keV to approximately 100 keV and approximately 1E14 cm -3 to about 1E17 cm -3 By injecting silicon ions into the barrier layer (122) at a dose suitable for forming a layer having a doping concentration, a suitable charge-releasing cap layer (140) can be formed in the barrier layer (122).

[0077] The presence of modified access regions (140) can increase the switching speed in transistors according to some embodiments. For example, FIG. 4a illustrates the results of a test setup including a conventional GaN HEMT transistor and a GaN HEMT transistor including modified access regions (140) as described herein, while FIG. 4b compares the Schottky barrier heights of the conventional transistors with the Schottky barrier heights of transistors including modified access regions (140) as described herein.

[0078] Referring to FIG. 4a, devices without a modified access region (140) (upper graph) and devices with a modified access region (140) (lower graph) received RF pulse inputs. In particular, device transient behaviors were tested with the setup of loads and input / output matching network circuits under appropriate bias conditions and RF pulse inputs to the gate terminals of each device. The resulting output waveforms are shown on the right.

[0079] Devices without a modified access region (140) exhibited a significant drain current drop (delay before recovery) at the start of the applied RF pulse signal, which is believed to be affected by defects associated with trapped charges. In particular, devices without a charge-releasing cap layer (140) exhibited a recovery time constant (τ) of several milliseconds, whereas devices with a charge-releasing cap layer (140) exhibited a significantly shorter recovery time constant (τ) of several microseconds. However, as can be seen in FIG. 4a, devices with a modified access region (140) also exhibited some undesirable overshoot of the output signal.

[0080] Referring to FIG. 4b, devices with a modified access area (140) have lower average Schottky barrier heights than devices without a modified access area (140), which may not be desirable. For example, a reduced Schottky barrier height may cause the overshoot evident in FIG. 4a.

[0081] FIG. 4c shows the Fermi level E at the surface of the barrier layer (122). F and conduction band E CThe surface barrier height of the HEMT device, which is the energy barrier between them, is illustrated. As can be seen in FIG. 4c, it is believed that lowering the surface barrier height of the device may allow carriers that would otherwise be trapped in the barrier layer (122) to move to the 2DEG region between the barrier layer (122) and the channel layer (120), where the carriers can be conducted to the drain of the device. To overcome this effect, some embodiments provide a selectively modified access region only in selective portions of the device active region between the source and drain regions (123, 125) of the device. In particular, some embodiments may overcome these disadvantages by confining the charge release path provided by the modified access region (140) to the region between the gate contact and the drain contact. Referring to FIG. 5a, a localized charge discharge path is provided to the GaN HEMT device (200) by an optional modified access region (240) provided only in the region between the gate contact (130) and the drain region (125) (labeled as the GD region in FIG. 5a). In certain embodiments, the optional modified access region (240) may not extend below the gate contact (130), and thus the gate contact (130) is in direct contact with the barrier layer (122).

[0082] The optionally modified access region (240) may have a reduced surface barrier height compared to the portion of the barrier layer (122) below the gate contact (130) and between the gate contact (130) and the source region (123). Optionally providing the optionally modified access region (240) can improve the Schottky barrier height of the device as well as the transient behavior of the device. In some embodiments, the optionally modified access region (240) may be formed by masking and optional epitaxial growth of a low SBH epitaxial layer (140), similar to the embodiments illustrated in FIG. 3b.

[0083] Referring to FIG. 5b, in some embodiments, an optionally modified access region (242) may be provided in the barrier layer (122) between the gate contact (130) and the drain region (125). The optionally modified access region (242) may be formed by the optional formation of an optional sacrificial film (162) prior to annealing (as shown in FIG. 3d), for example, by masking and etching the sacrificial film (152) of FIG. 3a prior to annealing to form the optional sacrificial film (162). A protective film (164) may be formed on the optional sacrificial film (162) prior to annealing. In further embodiments, referring to FIG. 3c, the optionally modified access region (242) may be formed by the optional injection and masking of ions (156) into the barrier layer (122).

[0084] Referring to FIG. 5c, a GaN HEMT structure (200C) according to additional embodiments is illustrated. In the GaN HEMT structure (200C), a modified access region (244) having a reduced surface barrier height is provided only in the SG region between the source region (123) and the gate contact (130) (but not below the gate contact (130)). Thus, the device illustrated in FIG. 5c can have a reduced surface barrier height in the region between the source contact (124) and the gate contact (130) while maintaining a high Schottky barrier between the gate contact (130) and the barrier layer (122). Although not illustrated in FIG. 5c, it will be known that the modified access region (244) can be formed as a surface region within the barrier layer (122) as described above in relation to FIG. 5b.

[0085] Referring to FIG. 5d, a GaN HEMT structure (200D) according to additional embodiments is illustrated. In the GaN HEMT structure (200C), a first modified access region (246) having a reduced surface barrier height is provided in an SG region between the source region (123) and the gate contact (130) (but not below the gate contact (130)), and a second modified access region (248) having a reduced surface barrier height is provided in a GD region between the gate contact (130) and the drain region (125) (but not below the gate contact (130)). Accordingly, the device illustrated in FIG. 5d may have a reduced surface barrier height in the region between the source contact (124) and the gate contact (130) and in the region between the gate contact (130) and the drain contact (126), while maintaining a high Schottky barrier between the gate contact (130) and the barrier layer (122). Although not illustrated in FIG. 5d, it will be known that one or both of the first modified access region (246) and the second modified access region (248) may be formed as surface regions within the barrier layer (122) as described above in relation to FIG. 5b.

[0086] The presence of an optional modified access region (240) or region (242) in the GD region can increase the switching speed in the transistor according to some embodiments without causing undesirable overshoot of the drain current. For example, FIG. 6a illustrates the results of a test setup including a conventional GaN HEMT transistor, a GaN HEMT transistor including a modified access region (140) over the entire active region between source and drain regions (123, 125), and a GaN HEMT transistor including an optional modified access region (240) only in the GD region. FIG. 6b compares the Schottky barrier heights of the conventional transistors with the Schottky barrier heights of the transistors including the modified access regions (140) and the transistors including the optional modified access regions (240) only in the GD region as described herein.

[0087] Referring to FIG. 6a, devices without modified access regions (top graph), with full modified access regions (140) (middle graph), and with modified optional access regions (240) (bottom graph) received RF pulse inputs. In particular, device transient behaviors were tested with the setup of loads and input / output matching network circuits under appropriate bias conditions and RF pulse inputs to the gate terminals of each device. The resulting output waveforms are shown on the right.

[0088] Devices having a partially selectively deformed access area (240) exhibited a recovery time constant (τ) of about several microseconds, which is similar to the performance of devices with full deformed access areas (140). However, as can be seen in FIG. 6a, devices having a partially selectively deformed access area (240) did not exhibit an apparent overshoot of the output signal. Additionally, referring to FIG. 6b, devices having a selectively deformed access area (240) had Schottky barrier heights similar to those of devices without a deformed access area.

[0089] The selective formation of selectively modified access regions (240, 242) is illustrated in FIGS. 7a through 7c. For example, referring to FIG. 7a, after forming a channel layer (120) and a barrier layer (122) on a substrate (110), an epitaxial growth mask (702) may be selectively formed on the upper surface of the barrier layer (122) in an area corresponding to the SG region (Fig. 5a) of the device. The epitaxial growth mask (702) exposes a portion of the surface of the barrier layer corresponding to the GD region of the device. Next, to form the selectively modified access region (240), an epitaxial layer is selectively formed on the exposed portion of the barrier layer (122).

[0090] Referring to FIG. 7b, in some embodiments, an injection mask (704) is optionally formed on the upper surface of the barrier layer (122) in an area corresponding to the SG region of the device. The injection mask (704) exposes a portion of the surface of the barrier layer corresponding to the GD region of the device. Next, dopant ions (756) are injected into the exposed surface of the barrier layer (122) to form an optionally modified access region (240).

[0091] Referring to FIG. 7c, in some embodiments, a sacrificial layer (708) is optionally formed on the upper surface of the barrier layer (122) in an area corresponding to the GD region of the device. An injection mask (704) exposes a portion of the surface of the barrier layer corresponding to the SG region of the device. Then, the structure is annealed (754) to form an optionally modified access region (242). A surface protection layer (not shown) may be formed on the sacrificial layer prior to annealing to prevent surface desorption of the barrier layer during annealing. The sacrificial layer is subsequently removed, for example, by etching.

[0092] In some embodiments, the optional modified access region (240) may not fill the entire GD region between the gate contact (130) and the drain region (125). For example, a plurality of modified access regions may be formed on the upper surface of the barrier layer (122) and spaced apart along the length of the gate. The use of a plurality of modified access regions may provide a mechanism for controlling the conductivity of charge release from the surface of the barrier layer (122) to the drain region (125) through the dimensioning and arrangement of the regions.

[0093] FIG. 7d illustrates a method for forming a transistor device. The method comprises providing a semiconductor epitaxial layer structure comprising a channel layer and a barrier layer on the channel layer—the barrier layer having a higher bandgap than the channel layer—(Block 722). A modified access region is formed on the upper surface of the barrier layer facing the channel layer (Block 724). A source contact and a drain contact are formed on the barrier layer (Block 726), and a gate contact is formed between the source contact and the drain contact (Block 728). The modified access region comprises a material having a lower surface barrier height relative to the gate contact than the barrier layer.

[0094] Forming a modified access region may include forming a sacrificial dielectric layer on a barrier layer, annealing the sacrificial dielectric layer and the barrier layer, and removing the sacrificial dielectric layer. The sacrificial dielectric layer may include SiN, SiOx, AlN, AlO, and / or HfO.

[0095] Forming a modified access region may include forming an epitaxial layer of a material having a bandgap lower than that of the barrier layer on the barrier layer. The epitaxial layer may be doped with n-type dopants.

[0096] In some embodiments, forming a modified access region includes injecting n-type dopants into the upper surface of a barrier layer facing the channel layer.

[0097] In some embodiments, the modified access region is located in the area between the gate contact and the drain contact and does not extend completely between the source contact and the drain contact. In some embodiments, the gate contact forms a non-ohmic contact with the barrier layer and does not contact the modified access region.

[0098] The method may further include forming a drain region doped in the barrier layer, a drain contact in contact with the drain region, and a modified access region in contact with the drain region.

[0099] FIGS. 8a through 8f illustrate operations for forming HEMT devices according to various additional embodiments. FIGS. 8a through 8f illustrate operations for forming a modified access region in the GD region of a HEMT device structure. However, it will be understood that similar operations may be performed to form a modified access region in the SG region as illustrated in FIG. 5c, or in both the SG region and the GD region of a HEMT device structure as illustrated in FIG. 5d.

[0100] FIG. 8a is a cross-sectional view of a precursor structure of a GaN HEMT device comprising a substrate (110), a channel layer (120), and a barrier layer (122) taken along line AA of FIG. 8b, which is a plan view of the structure of FIG. 8a. A mask (803) is formed on the upper surface of the barrier layer (122) to expose a plurality of regions (122A) on the surface of the barrier layer (122). The regions (122A) extend across the GD region of the precursor structure. The regions (122A) each have widths d1 and d2 which may be from 1 micron to 100 microns. The number of regions (122A) may depend on the values ​​of d1 and d2 along with the total gate width of the device. Although they are depicted as rectangles in FIG. 8b, it will be understood that the regions (122A) may have any desired shape.

[0101] Referring to FIGS. 8c and 8d, a sacrificial membrane (805) is formed on the mask layer and on the barrier layer in regions (122A). The sacrificial membrane (805) may have a composition similar to the sacrificial membrane (152) described above in relation to FIG. 3A. Then, the structure is annealed (854) in a manner similar to that described above in relation to FIG. 3A to form a plurality of regions (842) in the regions (122A) exposed on the surface of the barrier layer (122).

[0102] Referring to FIG. 8e, in some embodiments, the region (842) may be formed by injecting ions (856) into the exposed region (122A) on the surface of the barrier layer (122).

[0103] Referring to FIG. 8f, in some embodiments, the region (842) may be formed by selective epitaxial growth on the barrier layer within the exposed regions (122A).

[0104] Referring to FIG. 8ga, in some embodiments, regions (122B) may be formed to cover the entire length between source and drain contacts, and thus optional modified access regions (842) are formed in the SG region as well as the GD region of the device.

[0105] Referring to FIG. 8gb, in some embodiments, regions (122B) may be formed between source and gate contacts, and thus optional modified access regions (842) are formed in the SG region of the device.

[0106] Referring to FIG. 8gc, in some embodiments, regions (122B) may be formed between source and drain contacts rather than below the gate contact, and thus optional modified access regions (842) are formed in the SG region and GD region of the device rather than below the gate contact.

[0107] FIG. 8h illustrates a method for forming a transistor device. The method comprises providing a semiconductor epitaxial layer structure comprising a channel layer and a barrier layer on the channel layer—the barrier layer having a higher bandgap than the channel layer (Block 802). The method further comprises forming a source contact and a drain contact on the barrier layer (Block 804), and forming a gate contact between the source contact and the drain contact on the barrier layer (Block 806). The method further comprises forming a plurality of optionally modified access regions on the upper surface of the barrier layer facing the channel layer (Block 808). The optionally modified access regions comprise a material having a lower surface barrier height relative to the gate contact than the barrier layer, and a plurality of charge-emission cap regions are spaced apart along the length of the gate contact.

[0108] Forming selectively modified access regions may include forming a mask on a barrier layer—the mask having a plurality of openings therein that expose each portion of the upper surface of the barrier layer—and forming selectively modified access regions in the portions of the upper surface of the barrier layer exposed by the openings.

[0109] Forming selectively modified access regions may include forming a sacrificial dielectric layer on a mask and a barrier layer—the sacrificial dielectric layer extends into the openings and contacts the barrier layer at portions of the upper surface of the barrier layer exposed by the openings—annealing the sacrificial dielectric layer and the barrier layer, and removing the sacrificial dielectric layer. The sacrificial dielectric layer may comprise SiN, SiOx, AlN, AlO, and / or HfO.

[0110] In some embodiments, forming selectively modified access regions may include selectively forming epitaxial layers on portions of the upper surface of the barrier layer exposed by the openings, and the epitaxial layers comprise a material having a band gap lower than that of the barrier layer. The epitaxial layers may be doped with n-type dopants.

[0111] In some embodiments, forming selectively modified access regions includes injecting n-type dopants into portions of the upper surface of the barrier layer exposed by the openings.

[0112] In some embodiments, the gate contact forms a non-ohmic contact with the barrier layer and does not contact the charge-emitting cap regions.

[0113] The method may further include forming a drain region doped in the barrier layer, the drain contacts contact the drain region, and the charge-releasing cap regions contact the drain region.

[0114] The optionally modified access regions may have a first width d1 and may be spaced apart by a second width d2 on the barrier layer along the length of the gate contact.

[0115] The first width d1 may be about 1 micron to 100 microns, and the second width d2 may be about 1 micron to 100 microns.

[0116] Transistor devices comprising optional modified access regions as described herein may be used in amplifiers operating in a wide variety of different frequency bands. In some embodiments, RF transistor amplifiers comprising transistor devices as described herein may be configured to operate at frequencies greater than 1 GHz. In other embodiments, RF transistor amplifiers may be configured to operate at frequencies greater than 2.5 GHz. In yet another embodiment, RF transistor amplifiers may be configured to operate at frequencies greater than 3.1 GHz. In yet another embodiment, RF transistor amplifiers may be configured to operate at frequencies greater than 5 GHz. In some embodiments, RF transistor amplifiers may be configured to operate in at least one of the 2.5-2.7 GHz, 3.4-4.2 GHz, 5.1-5.8 GHz, 12-18 GHz, 18-27 GHz, 27-40 GHz, or 40-75 GHz frequency bands or sub-parts thereof.

[0117] Although embodiments of the concepts of the present invention have been discussed above with respect to HEMT devices, it will be understood that the concepts of the present invention described herein may be applied to other types of semiconductor devices, such as MOSFETs, DMOS transistors, and / or lateral diffusion MOS (LDMOS) transistors.

[0118] RF transistor amplifiers comprising the transistor devices described herein may be used in standalone RF transistor amplifiers and / or multiple RF transistor amplifiers. Examples of ways in which RF transistor amplifiers according to some embodiments may be used in applications comprising multiple amplifiers will be discussed with reference to FIGS. 9a through 9c.

[0119] Referring to FIG. 9a, an RF transistor amplifier (1000A) is schematically illustrated, comprising a pre-amplifier (1010) and a main amplifier (1030) electrically connected in series. As illustrated in FIG. 9a, the RF transistor amplifier (1000A) comprises an RF input (1001), a pre-amplifier (1010), an inter-stage impedance matching network (1020), a main amplifier (1030), and an RF output (1002). The inter-stage impedance matching network (1020) may include, for example, inductors and / or capacitors arranged in any suitable configuration to form a circuit that improves impedance matching between the output of the pre-amplifier (1010) and the input of the main amplifier (1030). Although not illustrated in FIG. 9a, the RF transistor amplifier (1000A) may further include an input matching network interposed between the RF input (1001) and the preamplifier (1010), and / or an output matching network interposed between the main amplifier (1030) and the RF output (1002). RF transistor amplifiers according to the embodiments may be used to implement either or both of the preamplifier (1010) and the main amplifier (1030).

[0120] Referring to FIG. 9b, an RF transistor amplifier (1000B) is schematically illustrated, comprising an RF input (1001), a pair of preamplifiers (1010-1, 1010-2), a pair of inter-stage impedance matching networks (1020-1, 1020-2), a pair of main amplifiers (1030-1, 1030-2), and an RF output (1002). A splitter (1003) and a coupler (1004) are also provided. The preamplifiers (1010-1) and main amplifiers (1030-1) (electrically connected in series) are arranged electrically in parallel with the preamplifiers (1010-2) and main amplifiers (1030-2) (electrically connected in series). As in the RF transistor amplifier (1000A) of FIG. 9a, the RF transistor amplifier (1000B) may further include an input matching network interposed between the RF input (1001) and the preamplifiers (1010-1, 1010-2), and / or an output matching network interposed between the main amplifiers (1030-1, 1030-2) and the RF output (1002).

[0121] As illustrated in FIG. 9c, RF transistor amplifiers according to some embodiments may also be used to implement Doherty amplifiers. As is known in the art, a Doherty amplifier circuit includes first and second (or more) power-coupled amplifiers. The first amplifier is referred to as the "main" or "carrier" amplifier, and the second amplifier is referred to as the "peaking" amplifier. The two amplifiers may be biased differently. For example, in one common Doherty amplifier implementation, the main amplifier may include a Class AB or Class B amplifier, while the peaking amplifier may be a Class C amplifier. Doherty amplifiers may operate more efficiently than balanced amplifiers when operating at power levels backed off from saturation. An RF signal input to a Doherty amplifier is split (e.g., using an orthogonal coupler), and the outputs of the two amplifiers are combined. The main amplifier is configured to turn on first (i.e., at lower input power levels), and thus only the main amplifier will operate at lower power levels. As the input power level increases toward saturation, the peaking amplifier turns on and the input RF signal is split between the main amplifier and the peaking amplifier.

[0122] As illustrated in FIG. 9c, the Doherty RF transistor amplifier (1000C) includes an RF input (1001), an input splitter (1003), a main amplifier (1040), a peaking amplifier (1050), an output combiner (1004), and an RF output (1002). The Doherty RF transistor amplifier (1000C) includes a 90° transformer (1007) at the input of the peaking amplifier (1050) and a 90° transformer (1005) at the input of the main amplifier (1040), and may optionally include input matching networks and / or output matching networks (not shown). The main amplifier (1040) and / or the peaking amplifier (1050) may be implemented using any of the aforementioned RF transistor amplifiers according to the embodiments.

[0123] RF transistor amplifiers according to the embodiments may be formed as individual devices or as part of a Monolithic Microwave Integrated Circuit (MMIC). An MMIC refers to an integrated circuit that operates on radio and / or microwave frequency signals in which all circuits for a specific function are integrated within a single semiconductor chip. An exemplary MMIC device is a transistor amplifier comprising associated matching circuits, feed networks, etc., all implemented on a common substrate. MMIC transistor amplifiers typically include a plurality of unit cell HEMT transistors connected in parallel.

[0124] FIG. 10 is a plan view of an MMIC RF transistor amplifier (400) according to embodiments of the concepts of the present invention. As shown in FIG. 10, the MMIC RF transistor amplifier (400) includes an integrated circuit chip (430) contained within a package (410). The package (410) may include a protective housing that surrounds and protects the integrated circuit chip (430). The package (410) may be formed of, for example, a ceramic material.

[0125] The package (410) includes an input lead (412) and an output lead (418). The input lead (412) may be mounted to an input lead pad (414), for example, by soldering. One or more input bond wires (420) may electrically connect the input lead pad (414) to an input bond pad on an integrated circuit chip (430). The integrated circuit chip (430) includes an input feed network (438), an input impedance matching network (450), a first RF transistor amplifier stage (460), an intermediate impedance matching network (440), a second RF transistor amplifier stage (462), an output impedance matching stage (470), and an output feed network (482).

[0126] The package (410) further includes an output lead (418) connected to an output lead pad (416) by, for example, soldering. One or more output bond wires (490) may electrically connect the output lead pad (416) to an output bond pad on an integrated circuit chip (430). The first RF transistor amplifier stage (460) and / or the second RF transistor amplifier stage (462) may be implemented using any of the RF transistor amplifiers according to embodiments of the concepts of the present invention.

[0127] RF transistor amplifiers according to embodiments of the concepts of the present invention can be designed to operate in a wide variety of different frequency bands. In some embodiments, these RF transistor amplifier dies may be configured to operate in at least one of the 0.6-2.7 GHz, 3.4-4.2 GHz, 5.1-5.8 GHz, 12-18 GHz, 18-27 GHz, 27-40 GHz, or 40-75 GHz frequency bands or sub-parts thereof. The techniques according to embodiments of the concepts of the present invention may be particularly advantageous for RF transistor amplifiers operating at frequencies above 10 GHz.

[0128] FIGS. 11a and FIGS. 11b are schematic cross-sectional views illustrating some exemplary ways in which RF transistor amplifier dies are packaged to provide RF transistor amplifiers (600A and 600B), respectively, according to embodiments of the concepts of the present invention.

[0129] FIG. 11a is a schematic side view of a packaged group III nitride-based RF transistor amplifier (600A). As shown in FIG. 11a, the packaged RF transistor amplifier (600A) comprises an RF transistor amplifier die (100) packaged in an open cavity package (610A). The package (610A) comprises metal gate leads (622A), metal drain leads (624A), a metal submount (630), sidewalls (640), and a lid (642).

[0130] The submount (630) may include materials configured to assist in the thermal management of the package (600A). For example, the submount (630) may include copper and / or molybdenum. In some embodiments, the submount (630) may be composed of a number of layers and / or include vias / interconnects. In an exemplary embodiment, the submount (630) may be a multilayer copper / molybdenum / copper metal flange comprising a core molybdenum layer having copper cladding layers on any one of its main surfaces. In some embodiments, the submount (630) may include a metal heat sink that is part of a lead frame or a metal slug. The side walls (640) and / or the cover (642) may be formed of or comprise an insulating material in some embodiments. For example, the side walls (640) and / or the cover (642) may be formed of or comprise ceramic materials.

[0131] In some embodiments, the sidewalls (640) and / or the cover (642) may be formed of, for example, Al2O3. The cover (642) may be bonded to the sidewalls (640) using epoxy glue. The sidewalls (640) may be attached to the submount (630), for example, by brazing. The gate lead (622A) and the drain lead (624A) may be configured to extend through the sidewalls (640), but embodiments of the concepts of the present invention are not limited thereto.

[0132] The RF transistor amplifier die (100) is mounted on the upper surface of the metal submount (630) in an air-filled cavity (612) defined by the metal submount (630), ceramic sidewalls (640), and ceramic cover (642). The gate and drain terminals of the RF transistor amplifier die (100) may be on the uppermost side of the structure, while the source terminal is on the lowermost side of the structure.

[0133] The gate lead (622A) may be connected to the gate terminal of the RF transistor amplifier die (100) by one or more bond wires (654). Similarly, the drain lead (624A) may be connected to the drain terminal of the RF transistor amplifier die (100) by one or more bond wires (654). The source terminal may be mounted on a metal submount (630) using, for example, a conductive die attachment material (not shown). The metal submount (630) may provide electrical connection to the source terminal (126) and may also serve as a heat dissipation structure to dissipate heat generated in the RF transistor amplifier die (100).

[0134] Heat is primarily generated in the upper part of the RF transistor amplifier die (100), where relatively high current densities are generated in the channel regions of the unit cell transistors, for example. This heat can be transferred to the source terminal and then to the metal submount (630) through the source vias (146) and the semiconductor layer structure of the device.

[0135] FIG. 11b is a schematic side view of a different packaged group III nitride-based RF transistor amplifier (600B). The RF transistor amplifier (600B) differs from the RF transistor amplifier (600A) in that it includes a different package (610B). The package (610B) includes metal gate and drain leads (622B, 624B) as well as a metal submount (630). The RF transistor amplifier (600B) also includes a plastic overmold (660) that at least partially surrounds the RF transistor amplifier die (100), the leads (622B, 624B), and the metal submount (630).

[0136] Many variations of the features of the above embodiments are possible. Transistor structures having features that can be utilized in the embodiments of the present invention are disclosed in the following jointly assigned publications, the contents of which are incorporated herein by reference in their entirety: U.S. Patent No. 6,849,882 titled "Group-III Nitride Based High Electron Mobility Transistor (HEMT) With Barrier / Spacer Layer" (Chavarkar et al.); U.S. Patent No. 7,230,284 titled "Insulating Gate AlGaN / GaN HEMT" (Parikh et al.); U.S. Patent No. 7,501,669 titled "Wide Bandgap Transistor Devices With Field Plates" (Parikh et al.); U.S. Patent No. 7,126,426 titled "Cascode Amplifier Structures Including Wide Bandgap Field Effect Transistor With Field Plates" (Mishra et al.); U.S. Patent No. 7,550,783 titled "Wide Bandgap HEMTs With Source Connected Field Plates" (Wu et al.); U.S. Patent No. 7,573,078 titled "Wide Bandgap Transistors With Multiple Field Plates" (Wu et al.); U.S. Patent Publication No. 2005 / 0253167 titled "Wide Bandgap Field Effect Transistors With Source Connected Field Plates" (Wu et al.); U.S. Patent Publication No. 2006 / 0202272 titled "Wide Bandgap Transistors With Gate-Source Field Plates" (Wu et al.);U.S. Patent Publication No. 2008 / 0128752 titled "GaN Based HEMTs With Buried Field Plates" (Wu); U.S. Patent Publication No. 2010 / 0276698 titled "Gate Electrodes For Millimeter-Wave Operation and Methods of Fabrication" (Moore et al.); U.S. Patent Publication No. 2012 / 0049973 titled "High Power Gallium Nitride Field Effect Transistor Switches" (Smith, Jr. et al.); U.S. Patent Publication No. 2012 / 0194276 titled "Low Noise Amplifiers Including Group III Nitride Based High Electron Mobility Transistors" (Fisher); and U.S. Patent No. 9,847,411 titled "Recessed field plate transistor structures" (Sriram et al.).;

[0137] Although embodiments of the concepts of the present invention have been described in considerable detail with reference to their specific configurations, other versions are possible. Field plates and gates may also have many different shapes and may be connected to source contacts in many different ways. Accordingly, the spirit and scope of the present invention should not be limited to the specific embodiments described above.

Claims

Claim 1 A transistor device comprising: a semiconductor epitaxial layer structure including a channel layer and a barrier layer on the channel layer, wherein the barrier layer has a bandgap higher than that of the channel layer; a source contact and a drain contact on the barrier layer, wherein the source contact and the drain contact are spaced apart in a first direction; a doped drain region on the barrier layer, wherein the drain contact is in contact with the drain region; and a gate contact between the source contact and the drain contact on the barrier layer. and a plurality of optionally modified access regions on the upper surface of the barrier layer facing the channel layer—the optionally modified access regions comprise a material having a surface barrier height lower than that of the barrier layer, and the plurality of optionally modified access regions are spaced apart on the barrier layer along the width of the gate contact in a second direction perpendicular to the first direction—the optionally modified access regions are doped with n-type dopants and are in contact with the doped drain region, and the optionally modified access regions comprise a region of increased conductivity on the upper surface of the barrier layer facing the channel layer, and the optionally modified access regions are 1E14 cm -3 to 1E17 cm -3 A transistor device having a doping concentration of Claim 2 A transistor device according to claim 1, wherein the selectively modified access regions are located between the gate contact and the drain region on the barrier layer. Claim 3 A transistor device according to claim 1, wherein the selectively modified access regions include regions of increased conductivity on the upper surface of the barrier layer facing the channel layer. Claim 4 A transistor device according to paragraph 3, wherein the selectively modified access regions include injected regions comprising dopants injected at the upper surface of the barrier layer facing the channel layer. Claim 5 In paragraph 3, the transistor device, wherein the selectively modified access regions have a thickness of 0.1 nm to 40 nm. Claim 6 A transistor device according to claim 1, wherein the selectively modified access regions comprise epitaxial semiconductor layers of a material having a bandgap lower than that of the barrier layer. Claim 7 delete Claim 8 In claim 6, the transistor device, wherein the selectively modified access regions have a thickness of 0.1 nm to 40 nm. Claim 9 delete Claim 10 A transistor device according to claim 1, wherein the selectively modified access regions have a first width d1 and are spaced apart by a second width d2 along the width of the gate contact on the barrier layer, the first width d1 is 1 micron to 100 microns and the second width d2 is 1 micron to 100 microns. Claim 11 A method for forming a transistor device, comprising the steps of: providing a semiconductor epitaxial layer structure including a channel layer and a barrier layer on the channel layer, wherein the barrier layer has a bandgap higher than that of the channel layer; forming a source contact and a drain contact on the barrier layer, wherein the source contact and the drain contact are spaced apart in a first direction; forming a drain region doped in the barrier layer, wherein the drain contact contacts the drain region; and forming a gate contact between the source contact and the drain contact on the barrier layer. and forming a plurality of selectively modified access regions on the upper surface of the barrier layer facing the channel layer - the selectively modified access regions comprise a material having a surface barrier height lower than that of the barrier layer, and the plurality of selectively modified access regions are spaced apart along the width of the gate contact in a second direction perpendicular to the first direction - wherein the selectively modified access regions are doped with n-type dopants and are in contact with the doped drain region, and the selectively modified access regions comprise a region of increased conductivity on the upper surface of the barrier layer facing the channel layer, and the selectively modified access regions are 1E14 cm -3 to 1E17 cm -3 A method having the doping concentration of Claim 12 In claim 11, the step of forming the selectively modified access regions comprises: forming a mask on the barrier layer—the mask having a plurality of openings therein that expose each portion of the upper surface of the barrier layer—; and forming the selectively modified access regions in the portions of the upper surface of the barrier layer exposed by the openings. Claim 13 In claim 12, the step of forming the selectively modified access regions comprises: forming a sacrificial dielectric layer on the mask and the barrier layer—the sacrificial dielectric layer extending into the openings and contacting the barrier layer at portions of the upper surface of the barrier layer exposed by the openings—; annealing the sacrificial dielectric layer and the barrier layer; and removing the sacrificial dielectric layer. Claim 14 In claim 12, the step of forming the selectively modified access regions comprises the step of selectively forming epitaxial layers on portions of the upper surface of the barrier layer exposed by the openings, wherein the epitaxial layers comprise a material having a band gap lower than that of the barrier layer. Claim 15 In claim 12, the step of forming the selectively modified access regions comprises the step of injecting the n-type dopants into portions of the upper surface of the barrier layer exposed by the openings. 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