Image sensor

Abstract

An image sensor according to the concept of the present invention comprises: a substrate including a first pixel region and a second pixel region adjacent to each other; the substrate including a first surface and a second surface opposite to each other; a pixel separation pattern provided within the substrate to define the first and second pixel regions; a transmission gate disposed on the first surface of the substrate on the first pixel region; a floating diffusion region adjacent to one side of the transmission gate; a first ground impurity region adjacent to the first surface of the substrate on the first pixel region; and a second ground impurity region adjacent to the first surface of the substrate on the second pixel region, wherein the bottom surface of the first ground impurity region may be located at a lower level than the bottom surface of the floating diffusion region.

Description

Technology Field

[0001] The present invention relates to an image sensor, and more specifically, to a CMOS type image sensor. Background Technology

[0002] An image sensor is a device that converts an optical image into an electrical signal. Image sensors can be classified into CCD (Charge Coupled Device) type and CMOS (Complementary Metal Oxide Semiconductor) type. A CMOS type image sensor is abbreviated as CIS (CMOS Image Sensor). The CIS comprises a plurality of unit pixel regions arranged two-dimensionally. Each of the unit pixel regions includes a photodiode. The photodiode serves to convert incident light into an electrical signal. The problem to be solved

[0003] The problem that the present invention aims to solve is to provide an image sensor with improved electrical characteristics. means of solving the problem

[0004] An image sensor according to the concept of the present invention comprises: a substrate including a first pixel region and a second pixel region adjacent to each other; the substrate including a first surface and a second surface opposite to each other; a pixel separation pattern provided within the substrate to define the first and second pixel regions; a transmission gate disposed on the first surface of the substrate on the first pixel region; a floating diffusion region adjacent to one side of the transmission gate; a first ground impurity region adjacent to the first surface of the substrate on the first pixel region; and a second ground impurity region adjacent to the first surface of the substrate on the second pixel region, wherein the bottom surface of the first ground impurity region may be located at a lower level than the bottom surface of the floating diffusion region.

[0005] An image sensor according to another concept of the present invention comprises: a substrate having a plurality of unit pixel regions having opposite first and second surfaces, each of which includes a photoelectric conversion region within the substrate; a pixel separation pattern penetrating the substrate to define the unit pixel regions; a trench exposing the pixel separation pattern; a transmission gate provided on the first surface of the substrate; a floating diffusion region adjacent to one side of the transmission gate, wherein the floating diffusion region is adjacent to the first surface of the substrate; a ground impurity region adjacent to the trench; a connection pattern provided within the trench, wherein the connection pattern is in contact with the ground impurity region; a contact connected to the floating diffusion region; and a ground contact connected to the ground impurity region, wherein the bottom surface of the ground contact may be located at a lower level than the bottom surface of the contact.

[0006] An image sensor according to another concept of the present invention comprises: a substrate having a first surface and a second surface opposite to each other; the substrate including a pixel array region, an optical black region and a pad region, wherein the pixel array region each includes a first pixel region, a second pixel region, a third pixel region and a fourth pixel region, each having a photoelectric conversion region; a pixel separation pattern provided within the substrate and defining the first to fourth pixel regions, wherein the pixel separation pattern includes a first separation pattern and a second separation pattern interposed between the first separation pattern and the substrate; a barrier impurity region provided on the sidewall of the pixel separation pattern; a device separation pattern each provided within the first to fourth pixel regions and adjacent to the first surface of the substrate; a transmission gate and a gate electrode each provided on the first to fourth pixel regions and disposed on the first surface of the substrate; a floating diffusion region adjacent to one side of the transmission gate; and source / drain regions disposed on both sides of the gate electrode. A first ground impurity region, a second ground impurity region, a third ground impurity region, and a fourth ground impurity region, respectively provided within the first to fourth pixel regions adjacent to the first surface of the substrate; a trench exposing the pixel separation pattern, wherein the trench is vertically superimposed with a portion of each of the first to fourth pixel regions; an insulating layer covering the gate electrode and the transmission gate; wiring provided within the insulating layer; a contact electrically connected to any one of the transmission gate, the gate electrode, and the floating diffusion region through the insulating layer; a ground contact electrically connected to at least one of the first to fourth ground impurity regions through the insulating layer; and color filters disposed on the second surface of the substrate.and includes a micro-lens portion disposed on the color filters, wherein each of the first to fourth ground impurity regions can contact the bottom surface and side wall of the trench.; Effects of the invention

[0007] According to the present invention, a ground impurity region can be formed along the bottom surface and sidewall of a third trench that exposes a pixel separation pattern. Accordingly, the area occupied by the ground impurity region in the unit pixel area can be significantly reduced. This increases the design freedom of the image sensor and makes it possible to manufacture a larger size for the second active pattern in which the gate electrode and source / drain regions are formed. As a result, electrical defects such as short-channel effects and noise in the image sensor can be reduced.

[0008] In addition, according to the present invention, a connection pattern may be provided that connects first to fourth ground impurity regions disposed adjacent to a third trench. Accordingly, the number of ground contacts, as well as the number and length of first wires connected to the ground contacts, can be reduced. That is, the parasitic capacitance between adjacent first wires and adjacent ground contacts can be reduced. As a result, the electrical characteristics of the image sensor can be improved.

[0009] In addition, since it is possible to form active patterns with relatively large widths and sizes, defects occurring during the image sensor manufacturing process can be effectively reduced. As a result, the reliability of the image sensor can be improved. Brief explanation of the drawing

[0010] FIG. 1 is a circuit diagram of an image sensor according to embodiments of the present invention. FIG. 2 is a plan view showing an image sensor according to embodiments of the present invention. Figure 3 is a cross-sectional view along the line A-A' of Figure 2. Figure 4 is an enlarged plan view of the M region of Figure 2. FIGS. 5a and FIGS. 5b are cross-sectional views along the lines A-A' and B-B' of FIGS. 4, respectively. Figure 6 is an enlarged cross-sectional view of the N region of Figure 5a. FIG. 7 is a plan view of the enlarged area M of FIG. 2, intended to explain an image sensor according to a comparative example of the present invention. Figure 8 is a cross-sectional view along the line A-A' of Figure 7. FIGS. 9a to 9g are cross-sectional views along line A-A' of FIG. 4, respectively, for illustrating a method of manufacturing an image sensor according to embodiments of the present invention. FIG. 10 is a cross-sectional view illustrating an image sensor according to embodiments of the present invention. FIG. 11 is a cross-sectional view illustrating an image sensor according to embodiments of the present invention. FIG. 12 is a plan view of the enlarged area M of FIG. 2, intended to explain an image sensor according to embodiments of the present invention. Figure 13 is a cross-sectional view along the line A-A' of Figure 12. Figure 14 is an enlarged cross-sectional view of the N region of Figure 13. Specific details for implementing the invention

[0011] FIG. 1 is a circuit diagram of an image sensor according to embodiments of the present invention.

[0012] Referring to FIG. 1, the unit pixel regions of the image sensor may include photodiodes (PD1, PD2, PD3, PD4), transfer transistors (TX), source follower transistors (SX), reset transistors (RX), dual conversion transistors (DCX), and select transistors (AX). The transfer transistors (TX), source follower transistors (SX), reset transistors (RX), dual conversion transistors (DCX), and select transistors (AX) may each include transfer gates (TG1-TG4), source follower gates (SF), reset gates (RG), dual conversion gates (DCG), and select gates (SEL).

[0013] Each of the photodiodes (PD1, PD2, PD3, PD4) may be a photodiode containing an n-type impurity region and a p-type impurity region. The floating diffusion region (FD) may function as the drain of the transfer transistor (TX). The floating diffusion region (FD) may function as the source of the dual conversion transistor (DCX). The floating diffusion region (FD) may be electrically connected to the source follower gate (SF) of the source follower transistor (SX). The source follower transistor (SX) may be connected to a selection transistor (AX).

[0014] The operation of the image sensor is described with reference to FIG. 1 as follows. First, with light blocked, a power supply voltage (VDD) is applied to the drain of the reset transistor (RX) and the drain of the source follower transistor (SX), and the reset transistor (RX) and the dual conversion transistor (DCX) are turned on to release the charges remaining in the floating diffusion region (FD). Then, the reset transistor (RX) is turned off, and when external light is incident on the photodiodes (PD1, PD2, PD3, PD4), electron-hole pairs are generated in the photodiodes (PD1, PD2, PD3, PD4). Holes move to the p-type impurity region of each photodiode (PD1, PD2, PD3, PD4), and electrons move to the n-type impurity region and accumulate. When one of the transfer transistors (TX) is turned on, charges such as these electrons and holes are transferred to and accumulated in the floating diffusion region (FD). The source potential of the source follower transistor (SX) changes in proportion to the amount of accumulated charge. At this time, when the selector transistor (AX) is turned on, a signal due to the charge is read through the column line.

[0015] A wiring line may be electrically connected to at least one of the transmission gates (TG1-TG4), source follower gate (SF), reset gate (RG), dual conversion gate (DCG), and select gate (SEL). The wiring line may be configured to apply a power supply voltage (VDD) to the drain of the reset transistor (RX) or the drain of the source follower transistor (SX). The wiring line may include a column line connected to the select transistor (AX). The wiring line may be the wirings described below.

[0016] FIG. 1 illustrates a configuration in which photodiodes (PD1, PD2, PD3, PD4) are connected to a floating diffusion region (FD), but embodiments of the present invention are not limited thereto. For example, a unit pixel region may include any one of the photodiodes (PD1, PD2, PD3, PD4), a floating diffusion region (FD), and one of the transfer transistors (TX). Additionally, as an example, a unit pixel region may include at least one of a reset transistor (RX), a source follower transistor (SX), a dual conversion transistor (DCX), and a select transistor (AX). As another example, at least one of the reset transistor (RX), the source follower transistor (SX), the dual conversion transistor (DCX), and the select transistor (AX) may be shared by neighboring unit pixel regions. Accordingly, the integration density of the image sensor may be improved.

[0018] FIG. 2 is a plan view showing an image sensor according to embodiments of the present invention. FIG. 3 is a cross-sectional view along line A-A' of FIG. 2.

[0019] Referring to FIGS. 2 and 3, the image sensor may include a sensor chip (1000) and a logic chip (2000). The sensor chip (1000) may include a photoelectric conversion layer (10), a first wiring layer (20), and a light transmission layer (30). The photoelectric conversion layer (10) may include a first substrate (100), a pixel separation pattern (150), a device separation pattern (103), and photoelectric conversion regions (110) provided within the first substrate (100). Light incident from the outside may be converted into an electrical signal in the photoelectric conversion regions (110).

[0020] The first substrate (100) may include a pixel array region (AR), an optical black region (OB), and a pad region (PAD) in a planar view. The pixel array region (AR) may be positioned in the center portion of the first substrate (100) in a planar view. The pixel array region (AR) may include a plurality of unit pixel regions (PX). The unit pixel regions (PX) may output a photoelectric signal from incident light. The unit pixel regions (PX) may form columns and rows and may be arranged two-dimensionally. The columns may be parallel to a first direction (D1). The rows may be parallel to a second direction (D2). In this specification, the first direction (D1) may be parallel to a first surface (100a) of the first substrate (100). The second direction (D2) may be parallel to the first surface (100a) of the first substrate (100) and may intersect the first direction (D1). The third direction (D3) may be substantially perpendicular to the first surface (100a) of the first substrate (100). The fourth direction (D4) may be a direction that is not parallel to both the first direction (D1) and the second direction (D2).

[0021] A pad area (PAD) is provided on the edge portion of the first substrate (100) and can surround a pixel array area (AR) in a planar view. Second pad terminals (83) may be provided on the pad area (PAD). The second pad terminals (83) can output electrical signals generated in unit pixel areas (PX) to the outside. Alternatively, external electrical signals or voltages may be transmitted to the unit pixel areas (PX) through the second pad terminals (83). Since the pad area (PAD) is positioned on the edge portion of the first substrate (100), the second pad terminals (83) can be easily connected to the outside.

[0022] An optical black region (OB) may be positioned between the pixel array region (AR) and the pad region (PAD) of the first substrate (100). The optical black region (OB) may surround the pixel array region (AR) in a planar view. The optical black region (OB) may include a plurality of dummy regions (111). Signals generated in the dummy regions (111) may subsequently be used as information to remove process noise. Hereinafter, the pixel array region (AR) of the image sensor will be described in more detail with reference to FIGS. 4, 5a, 5b, and 6.

[0023] FIG. 4 is an enlarged plan view of region M of FIG. 2. FIG. 5a and FIG. 5b are cross-sectional views along the lines A-A' and B-B' of FIG. 4, respectively. FIG. 6 is an enlarged cross-sectional view of region N of FIG. 5a.

[0024] Referring to FIGS. 4, 5a, and 5b, the image sensor may include a photoelectric conversion layer (10), a first wiring layer (20), and a light-transmitting layer (30). The photoelectric conversion layer (10) may include a first substrate (100), a pixel separation pattern (150), and an element separation pattern (103).

[0025] The first substrate (100) may include a first surface (100a) and a second surface (100b) opposite each other. Light may be incident on the second surface (100b) of the first substrate (100). A first wiring layer (20) may be disposed on the first surface (100a) of the first substrate (100), and a light-transmitting layer (30) may be disposed on the second surface (100b) of the first substrate (100). The first substrate (100) may be a semiconductor substrate or a silicon-on-insulator (SOI) substrate. The semiconductor substrate may include, for example, a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The first substrate (100) may include impurities of a first conductivity type. For example, the first type of impurity may include p-type impurities such as aluminum (Al), boron (B), indium (In) and / or gallium (Ga).

[0026] The first substrate (100) may include a plurality of unit pixel regions (PX) defined by a pixel separation pattern (150). The plurality of unit pixel regions (PX) may be arranged in a matrix form along a first direction (D1) and a second direction (D2) that intersect each other. The first substrate (100) may include photoelectric conversion regions (110). The photoelectric conversion regions (110) may be provided to each of the unit pixel regions (PX) within the first substrate (100). The photoelectric conversion regions (110) may perform the same function and role as the photodiodes (PD1, PD2, PD3, PD4) of FIG. 1.

[0027] The photoelectric conversion regions (110) may be regions doped with second conductivity type impurities within the first substrate (100). The second conductivity type impurities may have a conductivity type opposite to that of the first conductivity type impurities. The second conductivity type impurities may include n-type impurities such as phosphorus, arsenic, bismuth, and / or antimony. In one example, the photoelectric conversion regions (110) may be adjacent to the second surface (100b) of the first substrate (100). The photoelectric conversion regions (110) may be positioned closer to the second surface (100b) than to the first surface (100a). In another example, the photoelectric conversion regions (110) may be closer to the first surface (100a) of the first substrate (100). For example, each photoelectric conversion region (110) may include a first region adjacent to a first surface (100a) and a second region adjacent to a second surface (100b). There may be a difference in impurity concentration between the first region and the second region of the photoelectric conversion region (110). Accordingly, the photoelectric conversion region (110) may have a potential gradient between the first surface (100a) and the second surface (100b) of the first substrate (100). As another example, the photoelectric conversion region (110) may not have a potential gradient between the first surface (100a) and the second surface (100b) of the first substrate (100).

[0028] The first substrate (100) and the photoelectric conversion region (110) can form a photodiode. That is, a photodiode can be formed by a pn junction between the first substrate (100) of the first conductivity type and the photoelectric conversion region (110) of the second conductivity type. The photoelectric conversion region (110) forming the photodiode can generate and accumulate photocharges in proportion to the intensity of incident light.

[0029] A pixel isolation pattern (150) is provided within the first substrate (100) and may define unit pixel regions (PX). For example, the pixel isolation pattern (150) may be provided between the unit pixel regions (PX) of the first substrate (100). In a planar view, the pixel isolation pattern (150) may have a grid structure. In a planar view, the pixel isolation pattern (150) may completely surround each of the unit pixel regions (PX). The pixel isolation pattern (150) may be provided within a first trench (TR1). The first trench (TR1) may be recessed from the first surface (100a) of the first substrate (100). The pixel isolation pattern (150) may extend from the first surface (100a) of the first substrate (100) toward the second surface (100b). The pixel isolation pattern (150) may be a deep trench isolation (DTI) film. The pixel separation pattern (150) can penetrate the first substrate (100). The vertical height of the pixel separation pattern (150) may be substantially the same as the vertical thickness of the first substrate (100). The width of the pixel separation pattern (150) may gradually decrease from the first surface (100a) to the second surface (100b) of the first substrate (100). The upper width of the pixel separation pattern (150) may be the second width (W2). The lower width of the pixel separation pattern (150) may be the first width (W1). The second width (W2) may be larger than the first width (W1).

[0030] The pixel separation pattern (150) may include a first separation pattern (151), a second separation pattern (153), and a capping pattern (155). The first separation pattern (151) may be provided along the sidewall of the first trench (TR1). The first separation pattern (151) may, for example, include a silicon-based insulating material (e.g., silicon nitride, silicon oxide, and / or silicon oxynitride) and / or a high dielectric material (e.g., hafnium oxide and / or aluminum oxide). For another example, the first separation pattern (151) may include a plurality of layers, and said layers may include different materials. The first separation pattern (151) may have a lower refractive index than the first substrate (100). Accordingly, crosstalk between unit pixel regions (PX) of the first substrate (100) may be prevented or reduced.

[0031] A second separation pattern (153) may be provided within the first separation pattern (151). For example, the sidewalls of the second separation pattern (153) may be surrounded by the first separation pattern (151). The first separation pattern (151) may be interposed between the second separation pattern (153) and the first substrate (100). The second separation pattern (153) may be spaced apart from the first substrate (100) by the first separation pattern (151). Accordingly, when the image sensor is operated, the second separation pattern (153) may be electrically separated from the first substrate (100). The second separation pattern (153) may include a crystalline semiconductor material, for example, polysilicon. As an example, the second separation pattern (153) may further include a dopant, said dopant may include an impurity of the first conductivity type or an impurity of the second conductivity type. For example, the second separation pattern (153) may include doped polysilicon. As another example, the second separation pattern (153) may include an undoped crystalline semiconductor material. For example, the second separation pattern (153) may include undoped polysilicon. The term “undoped” may mean that no intentional doping process is performed.

[0032] A capping pattern (155) may be provided on the upper surface of the second separation pattern (153). The capping pattern (155) may be disposed adjacent to the first surface (100a) of the first substrate (100). The capping pattern (155) may include a non-conductive material. For example, the capping pattern (155) may include a silicon-based insulating material (e.g., silicon nitride, silicon oxide, and / or silicon oxynitride) and / or a high dielectric material (e.g., hafnium oxide and / or aluminum oxide). Accordingly, the pixel separation pattern (150) can prevent photocharges generated by incident light incident on each of the unit pixel regions (PX) from being incident on adjacent unit pixel regions (PX) by random drift. That is, the pixel separation pattern (150) can prevent crosstalk between unit pixel regions (PX).

[0033] A barrier impurity region (33) may be provided along the sidewall of the pixel separation pattern (150). The barrier impurity region (33) may be provided within the first substrate (100) adjacent to the sidewall of the first separation pattern (151). The barrier impurity region (33) may contain impurities of a first conductivity type (e.g., p-type). The impurity concentration doped in the barrier impurity region (33) may be higher than the impurity concentration of the first substrate (100). The barrier impurity region (33) may reduce the occurrence of dark current caused by electron-hole pairs generated by surface defects in the first trench (TR1).

[0034] A device isolation pattern (103) may be provided within the first substrate (100). For example, the device isolation pattern (103) may be provided within a second trench (TR2). The second trench (TR2) may be recessed from the first surface (100a) of the first substrate (100). The device isolation pattern (103) may be a shallow trench isolation (STI) film. The bottom surface of the device isolation pattern (103) may be provided within the first substrate (100). The width of the device isolation pattern (103) may gradually decrease from the first surface (100a) of the first substrate (100) to the second surface (100b). The bottom surface of the device isolation pattern (103) may be vertically spaced apart from the photoelectric conversion regions (110). A pixel isolation pattern (150) may overlap with a portion of the device isolation pattern (103). At least a portion of the device isolation pattern (103) is disposed on the sidewall of the pixel isolation pattern (150) and may be in contact with the sidewall of the pixel isolation pattern (150). The sidewall and bottom surface of the device isolation pattern (103) and the sidewall of the pixel isolation pattern (150) may have a stepped structure. The pixel isolation pattern (150) may penetrate the device isolation pattern (103). The depth of the device isolation pattern (103) may be smaller than the depth of the pixel isolation pattern (150). The device isolation pattern (103) may include a silicon-based insulating material. For example, the device isolation pattern (103) may include silicon nitride, silicon oxide, and / or silicon oxynitride. For another example, the device isolation pattern (103) may include a plurality of layers, and said layers may include different materials.

[0035] Each unit pixel region (PX) may include a first active pattern (ACT1) and a second active pattern (ACT2). The first active pattern (ACT1) and the second active pattern (ACT2) may be defined by a device isolation pattern (103). The first active pattern (ACT1) and the second active pattern (ACT2) may be separated by the device isolation pattern (103). The first active pattern (ACT1) may have a rectangular planar shape, and the second active pattern (ACT2) may have an 'L'-shaped planar shape. The planar shapes of the first and second active patterns (ACT1, ACT2), and the gate electrode (GE), transmission gate (TG), and ground impurity region (160) described later are not limited to the shape shown in FIG. 4 and may be changed in various ways.

[0036] The transfer transistor (TX), source follower transistor (SX), reset transistor (RX), dual conversion transistor (DCX), and select transistor (AX) described above with reference to FIG. 1 may be provided on the first surface (100a) of the first substrate (100). The transfer transistor (TX) may be provided on the first active pattern (ACT1). Any one of the source follower transistor (SX), reset transistor (RX), dual conversion transistor (DCX), and select transistor (AX) may be provided on the second active pattern (ACT2). The transfer transistor (TX) may be electrically connected to the photoelectric conversion region (110). The transfer transistor (TX) may include a transfer gate (TG) and a floating diffusion region (FD). A transmission gate (TG) may include a first portion (TGa) provided on a first surface (100a) of a first substrate (100) and a second portion (TGb) extending from the first portion (TGa) into the first substrate (100). The maximum width of the first portion (TGa) may be greater than the maximum width of the second portion (TGb). A gate dielectric pattern (GI) may be interposed between the transmission gate (TG) and the first substrate (100). The gate dielectric pattern (GI) may extend along the bottom surface and sidewalls of the second portion (TGb). A floating diffusion region (FD) may be adjacent to one side of the transmission gate (TG). The floating diffusion region (FD) may have a second conductivity type (e.g., n-type) opposite to that of the first substrate (100).

[0037] Gate electrodes (GE) may be provided on a first surface (100a) of a first substrate (100). The gate electrode (GE) may be any one of the select gate (SEL), source follower gate (SF), dual conversion gate (DCG), and reset gate (RG) described with reference to FIG. 1. The source follower transistor (SX), reset transistor (RX), dual conversion transistor (DCX), and select transistor (AX) may each include a gate electrode (GE) and source / drain regions (SDR). A gate dielectric pattern (GI) may be interposed between the gate electrode (GE) and the first substrate (100). A gate spacer (GS) may be provided on the sidewall of each of the gate electrodes (GE). A gate spacer (GS) may be provided on the sidewall of a first portion (TGa) of a transmission gate (TG). The gate spacer (GS) may include, for example, silicon nitride, silicon carbide nitride, or silicon oxide nitride. Source / drain regions (SDRs) may be provided within the first substrate (100). The source / drain region (SDR) may be a region doped within the second active pattern (ACT2). For example, the source / drain region (SDR) may have a second conductivity type (e.g., n-type) opposite to that of the first substrate (100).

[0038] Each unit pixel region (PX) may include a ground impurity region (160) provided within the first substrate (100). The ground impurity region (160) may be adjacent to the first surface (100a) of the first substrate (100). The bottom surface of the ground impurity region (160) may be spaced apart from the photoelectric conversion region (110). The ground impurity region (160) may be a doped region within the first substrate (100). The ground impurity region (160) may, for example, have the same first conductivity type (e.g., p-type) as the first substrate (100).

[0039] Unit pixel regions (PX) may include a first pixel region (PX1), a second pixel region (PX2), a third pixel region (PX3), and a fourth pixel region (PX4). The second pixel region (PX2) may be adjacent to the first pixel region (PX1) in a second direction (D2). The third pixel region (PX3) may be adjacent to the first pixel region (PX1) in a first direction (D1). The fourth pixel region (PX4) may be adjacent to the second pixel region (PX2) in a first direction (D1). The fourth pixel region (PX4) may be adjacent to the third pixel region (PX3) in a second direction (D2).

[0040] A third trench (TR3) recessed from the first surface (100a) of the first substrate (100) may be provided. The third trench (TR3) may expose the pixel separation pattern (150), the barrier impurity region (33), and the first substrate (100). For example, the third trench (TR3) may have a circular shape in a planar view. The third trench (TR3) may be vertically overlapped with a portion of each of the first to fourth pixel regions (PX1-PX4).

[0041] The ground impurity region (160) may include a first ground impurity region (160a) on the first pixel region (PX1), a second ground impurity region (160b) on the second pixel region (PX2), a third ground impurity region (160c) on the third pixel region (PX3), and a fourth ground impurity region (160d) on the fourth pixel region (PX4). In a planar view, each of the first to fourth ground impurity regions (160a, 160b, 160c, 160d) may be positioned adjacent to the third trench (TR3). That is, the first to fourth ground impurity regions (160a, 160b, 160c, 160d) may be positioned adjacent to each other with the pixel separation pattern (150) in between. A portion of each of the first to fourth ground impurity regions (160a, 160b, 160c, 160d) may overlap with the barrier impurity region (33).

[0042] A connection pattern (170) may be provided within the third trench (TR3). The connection pattern (170) may cover the bottom surface of the third trench (TR3). The connection pattern (170) may come into contact with the first to fourth ground impurity regions (160a, 160b, 160c, 160d). The connection pattern (170) may electrically connect the first to fourth ground impurity regions (160a, 160b, 160c, 160d) to one another. The connection pattern (170) may, for example, comprise polysilicon doped with p-type impurities (e.g., boron). For other examples, the connection pattern (170) may comprise a metallic material such as tungsten, copper, aluminum, and titanium, or a metallic nitride such as titanium nitride.

[0043] The first wiring layer (20) may include insulating layers (221, 222, 223), wirings (212, 213), vias (215), contacts (CT) and ground contacts (GCT). The insulating layers (221, 222, 223) may include a first insulating layer (221), a second insulating layer (222), and a third insulating layer (223). The first insulating layer (221) may cover a first surface (100a) of the first substrate (100). The first insulating layer (221) may cover gate electrodes (GE) and transmission gates (TG). The first insulating layer (221) may extend into a third trench (TR3). A second insulating layer (222) may be provided on the first insulating layer (221). A third insulating layer (223) may be provided on the second insulating layer (222). The first to third insulating layers (221, 222, 223) may comprise a non-conductive material. For example, the first to third insulating layers (221, 222, 223) may comprise a silicon-based insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride.

[0044] Wiring (212, 213) may be provided on the first insulating layer (221). Wiring (212, 213) may include first wiring (212) and second wiring (213). The first wiring (212) may be provided within the second insulating layer (222). The second wiring (213) may be provided within the third insulating layer (223). Via (215) may be provided within the second insulating layer (222). The via (215) may connect the first and second wiring (212, 213) to each other. The first and second wiring (212, 213) may be connected to any one of a transmission gate (TG), a gate electrode (GE), and a floating diffusion region (FD) through contacts (CT). The first wiring (212) can be electrically connected to the connection pattern (170) and the ground impurity region (160) through a ground contact (GCT). The ground contact (GCT) can be vertically superimposed with the pixel separation pattern (150). As another example, the ground contact (GCT) can be horizontally offset from the pixel separation pattern (150).

[0045] The contacts (CT) and the ground contact (GCT) may penetrate the first insulating layer (221). The arrangement of the wiring (212, 213) may be arranged independently of the arrangement of the photoelectric conversion regions (110) and may be varied, not limited to the illustrated arrangement. The first and second wirings (212, 213), vias (215), contacts (CT) and the ground contact (GCT) may comprise a metallic material. For example, the first and second wirings (212, 213), vias (215), contacts (CT) and the ground contact (GCT) may comprise copper (Cu).

[0046] Referring again to FIG. 3, the image sensor may further include a logic chip (2000). The logic chip (2000) may be laminated on the sensor chip (1000). The logic chip (2000) may include a second substrate (40) and a second wiring layer (45). The second wiring layer (45) may be interposed between the first wiring layer (20) and the second substrate (40).

[0047] A first connection structure (50), a first pad terminal (81), and a bulk color filter (90) may be provided on a first substrate (100) in an optical black area (OB). The first connection structure (50) may include a first light-blocking pattern (51), a first insulation pattern (53), and a first capping film (55). The first light-blocking pattern (51) may be provided on a second surface (100b) of the first substrate (100). The first light-blocking pattern (51) may conformally cover the inner walls of the fourth trench (TR4) and the fifth trench (TR5). The first light-blocking pattern (51) may penetrate the photoelectric conversion layer (10), the first wiring layer (20), and the second wiring layer (45) to electrically connect the photoelectric conversion layer (10) and the first wiring layer (20). More specifically, the first light-blocking pattern (51) can come into contact with the wirings in the first wiring layer (20) and the pixel separation pattern (150) in the photoelectric conversion layer (10). Accordingly, the first connection structure (50) can be electrically connected to the wirings in the first wiring layer (20). The first light-blocking pattern (51) can block light incident into the optical black area (OB).

[0048] A first pad terminal (81) is provided inside the fourth trench (TR4) to fill the remainder of the fourth trench (TR4). The first pad terminal (81) may include a metallic material, for example, aluminum. The first pad terminal (81) may be connected to a pixel separation pattern (150), more specifically to a second separation pattern (153). Accordingly, a negative voltage can be applied to the pixel separation pattern (150) through the first pad terminal (81).

[0049] A first insulating pattern (53) is provided on the first light-blocking pattern (51) to fill the remainder of the fifth trench (TR5). The first insulating pattern (53) can penetrate the photoelectric conversion layer (10) and the first wiring layer (20). A first capping film (55) may be provided on the first insulating pattern (53). The first capping film (55) may be provided on the first insulating pattern (53). The first capping film (55) may contain the same material as the capping pattern (155).

[0050] A bulk color filter (90) may be provided on a first pad terminal (81), a first light-blocking pattern (51), and a first capping film (55). The bulk color filter (90) may cover the first pad terminal (81), the first light-blocking pattern (51), and the first capping film (55). A first protective film (71) may be provided on the bulk color filter (90) to cover the bulk color filter (90).

[0051] A photoelectric conversion region (110') and a dummy region (111) may be provided in the optical black region (OB) of the first substrate (100). The photoelectric conversion region (110') may be doped with, for example, an impurity of a second conductivity type (e.g., n-type) different from the first conductivity type. The photoelectric conversion region (110') may have a structure similar to the photoelectric conversion region (110) described in FIG. 5a, but may not perform the operation of receiving light and generating an electrical signal. The dummy region (111) may be a region that is not doped with impurities. The signals generated in the photoelectric conversion region (110') and the dummy region (111) may be used as information to remove process noise.

[0052] In the pad area (PAD), a second connection structure (60), a second pad terminal (83), and a second protective film (73) may be provided on the first substrate (100). The second connection structure (60) may include a second light-blocking pattern (61), a second insulation pattern (63), and a second capping film (65).

[0053] A second light-blocking pattern (61) may be provided on a second surface (100b) of the first substrate (100). More specifically, the second light-blocking pattern (61) may conformally cover the inner walls of the sixth trench (TR6) and the seventh trench (TR7). The second light-blocking pattern (61) may penetrate a portion of the photoelectric conversion layer (10) and the first wiring layer (20). More specifically, the second light-blocking pattern (61) may come into contact with the wirings (231, 232) within the second wiring layer (45). The second light-blocking pattern (61) may include a metallic material, for example, tungsten.

[0054] A second pad terminal (83) may be provided inside the sixth trench (TR6). The second pad terminal (83) may be provided on the second light-blocking pattern (61) to fill the remainder of the sixth trench (TR6). The second pad terminal (83) may include a metallic material, for example, aluminum. The second pad terminal (83) may serve as an electrical connection passage between the image sensor element and the outside. A second insulating pattern (63) may fill the remainder of the seventh trench (TR7). The second insulating pattern (63) may penetrate the photoelectric conversion layer (10) and the first wiring layer (20). A second capping film (65) may be provided on the second insulating pattern (63). The second capping film (65) may include the same material as the capping pattern (155). The second protective film (73) can cover part of the second light-blocking pattern (61) and the second capping film (65).

[0055] Current applied through the second pad terminal (83) can flow to the pixel separation pattern (150) through the second light-blocking pattern (61), the wirings (231, 232) in the second wiring layer (45), and the first light-blocking pattern (51). Electrical signals generated from the photoelectric conversion regions (110, 110') and the dummy region (111) can be transmitted externally through the wirings of the first wiring layer (20), the wirings (231, 232) in the second wiring layer (45), the second light-blocking pattern (61), and the second pad terminal (83).

[0056] The light-transmitting layer (30) may include color filters (303) and a micro-lens section (306). The light-transmitting layer (30) may collect and filter light incident from the outside and provide the light to the photoelectric conversion layer (10). Color filters (303) may be provided on the second surface (100b) of the first substrate (100). Color filters (303) may be disposed on unit pixel regions (PX). The color filters (303) may include primary color filters. The color filters (303) may include first to third color filters having different colors. For example, the first to third color filters may each include green, red, and blue color filters. The first to third color filters may each include green, red, and blue color filters. The first to third color filters may be arranged in a Bayer pattern. As another example, the first to third color filters may include other colors such as cyan, magenta, or yellow.

[0057] The light-transmitting layer (30) may further include a first fixed charge film (132), a second fixed charge film (134), and a planarization film (136) provided sequentially between the second surface (100b) of the first substrate (100) and the color filters (303). Each of the first fixed charge film (132), the second fixed charge film (134), and the planarization film (136) may comprise different materials. For example, the first fixed charge film (132) may comprise aluminum oxide, the second fixed charge film (134) may comprise hafnium oxide, and the planarization film (136) may comprise silicon oxide. The first fixed charge film (132), the second fixed charge film (134), and the flattening film (136) can prevent light reflection so that light incident on the second surface (100b) of the first substrate (100) can smoothly reach the photoelectric conversion regions (110).

[0058] A micro-lens section (306) may be provided on the color filters (303). The micro-lens section (306) may include a flat section (305) in contact with the color filters (303) and micro-lenses (307) provided on the flat section (305) and disposed on each unit pixel area (PX). The flat section (305) may, for example, include an organic material. For another example, the flat section (305) may include silicon oxide or silicon oxynitride. The micro-lenses (307) may have a convex shape so as to concentrate light incident on the unit pixel areas (PX). Each micro-lens (307) may be vertically superimposed with the photoelectric conversion area (110).

[0059] The light-transmitting layer (30) may further include a low-refractive index pattern (311), a protective film (316), and a light-blocking pattern (315). The light-blocking pattern (315) may be provided on the bottom surface of the planarization film (136). The light-blocking pattern (315) may be vertically superimposed with the pixel separation pattern (150). That is, the light-blocking pattern (315) may have a grid structure. The light-blocking pattern (315) may include at least one of a metal or a metal nitride, such as titanium, tantalum, tungsten, or titanium nitride.

[0060] A low-refractive index pattern (311) can be placed between adjacent color filters (303) to separate them from each other. The low-refractive index pattern (311) can be placed on the bottom surface of a light-blocking pattern (315). The low-refractive index pattern (311) can be vertically superimposed with the pixel separation pattern (150) and the light-blocking pattern (315). That is, the low-refractive index pattern (311) can have a grid structure. The low-refractive index pattern (311) can be made of a material having a lower refractive index than the color filters (303). The low-refractive index pattern (311) can be made of an organic material. For example, the low-refractive index pattern (311) can be a polymer layer containing silica nanoparticles. Since the low-refractive index pattern (311) has a low refractive index, it can increase the amount of light incident on the photoelectric conversion region (110) and reduce crosstalk between unit pixel regions (PX). That is, the light reception efficiency can be increased in each photoelectric conversion region (110), and the SNR (Signal Noise Ratio) characteristics can be improved.

[0061] The protective film (316) can cover the surface of the low-refractive index pattern (311) with a substantially uniform thickness. The protective film (316) can be further extended over the bottom surface of each of the color filters (303). The protective film (316) may comprise, for example, a single film or multiple films of at least one of an aluminum oxide film and a silicon carbide oxide film. The protective film (316) can protect the color filters (303) and perform a moisture absorption function.

[0062] Referring to FIG. 6, the ground impurity region (160) and the connection pattern (170) will be described in more detail.

[0063] Referring to FIG. 6, the top surface of the first substrate (100) and the top surface of the device isolation pattern (103) may be co-planes with each other. The top surface of the first substrate (100) and the top surface of the device isolation pattern (103) may be located at the first level (LV1). The bottom surface of the second trench (TR2) may be located at the second level (LV2). The bottom surface of the device isolation pattern (103) may be located at the second level (LV2). The bottom surface of the contact (CT) may be located at a level substantially the same as or higher than the first level (LV1).

[0064] The bottom surface of the ground contact (GCT) may be located at the third level (LV3). The third level (LV3) may be located at a level lower than the first level (LV1). The third level (LV3) may be located at a level higher than the second level (LV2). The bottom surface of the third trench (TR3) may be located at the fourth level (LV4). For example, the fourth level (LV4) may be located at substantially the same level as the second level (LV2). For another example, the fourth level (LV4) may be located at a different level from the second level (LV2). The third level (LV3) may be located at a level higher than the fourth level (LV4). The bottom surface of the ground contact (GCT) may be located at a level lower than the bottom surface of the contact (GCT).

[0065] The bottom surface of the ground contact (GCT) may come into contact with the connection pattern (170). For example, the third level (LV3) may be located at a level lower than the top surface of the connection pattern (170). For another example, the third level (LV3) may be located at substantially the same level as the top surface of the connection pattern (170).

[0066] A ground impurity area (160) may be formed along the sidewalls and bottom surface of the third trench (TR3). The ground impurity area (160) may be in contact with the sidewalls and bottom surface of the third trench (TR3). The bottom surface of the ground impurity area (160) may be located at a level lower than the fourth level (LV4). The bottom surface of the ground impurity area (160) may be located at a level lower than the bottom surface of the floating diffusion area (FD) (see FIG. 5a). The ground impurity area (160) may be spaced apart from the top surface of the first substrate (100). That is, the ground impurity area (160) may be located at a level lower than the first level (LV1). The top surface of the ground impurity area (160) may be located at a level higher than the fourth level (LV4). A portion of the ground impurity area (160) may overlap with the barrier impurity area (33) and be adjacent to the first separation pattern (151).

[0068] FIG. 7 is a plan view of the enlarged area M of FIG. 2, intended to illustrate an image sensor according to a comparative example of the present invention. FIG. 8 is a cross-sectional view along the line A-A' of FIG. 7. In this comparative example, details identical to those described with reference to FIG. 4, 5a, and 5b are omitted, and the differences are described in detail.

[0069] Referring to FIGS. 7 and 8, each unit pixel region (PX) may include a first active pattern (ACT1) and a second active pattern (ACT2). The first active pattern (ACT1) and the second active pattern (ACT2) may be defined by a device isolation pattern (103). The first active pattern (ACT1) may have a rectangular planar shape, and the second active pattern (ACT2) may have a planar shape extending in a second direction (D2).

[0070] The ground impurity region (160) may be adjacent to the first active pattern (ACT1) in the second direction (D2) and to the second active pattern (ACT2) in the first direction (D1). The ground impurity region (160) may be positioned adjacent to the first surface (100a) of the first substrate (100). In other words, the ground impurity region (160) may be positioned adjacent to the top surface of the first substrate (100). The top surface of the ground impurity region (160) may be located at substantially the same level as the top surface of the floating diffusion region (FD). In a planar view, the area of ​​the ground impurity region (160) relative to the area of ​​the unit pixel region (PX) may be larger than that described with reference to FIG. 4.

[0071] The first to fourth ground impurity regions (160a, 160b, 160c, 160d) may not be arranged adjacent to each other. A ground contact (GCT) may be connected to each of the first ground impurity region (160a) and the second ground impurity region (160b). The ground contacts (GCT) may be connected by a first wiring (212). The first wiring (212) connecting the ground contacts (GCT) may cross a pixel separation pattern (150) between the first pixel region (PX1) and the second pixel region (PX2).

[0072] Although image sensors are becoming increasingly smaller, it is essential that the ground impurity region (160) has a certain amount of area to connect the ground contact (GCT). Accordingly, the area of ​​the ground impurity region (160) has become increasingly larger relative to the unit pixel area (PX).

[0073] According to a comparative example of the present invention, a ground impurity region (160) may be formed adjacent to the uppermost surface of the first substrate (100). To secure the area in which the ground impurity region (160) is formed, the width and size of the active patterns defined by the device isolation pattern (103) may be reduced. When the width and size of the active patterns are reduced, a phenomenon in which the active patterns tilt may occur during the manufacturing process. Accordingly, defects may occur during subsequent processes, thereby reducing the reliability of the image sensor.

[0074] Additionally, if the area occupied by the ground impurity region (160) in the unit pixel region (PX) increases, the size of the gate electrode (GE) formed on the unit pixel region (PX) decreases, and the distance between the source / drain regions (SDR) may also decrease. Consequently, electrical defects such as the single-channel effect may occur, and noise in the image sensor may increase.

[0075] In addition, the first ground impurity region (160a) on the first pixel region (PX1) and the second ground impurity region (160b) on the second pixel region (PX2) may not be arranged adjacently. Accordingly, the number of ground contacts (GCTs), as well as the number and length of the first wiring (212) connecting the ground contacts (GCTs) to each other, may be increased.

[0076] According to the present invention, a ground impurity region (160) can be formed along the bottom surface and sidewall of a third trench (TR3) that exposes a pixel separation pattern (150). Accordingly, the area occupied by the ground impurity region (160) in the unit pixel region (PX) can be significantly reduced. This increases the design freedom of the image sensor and makes it possible to manufacture a larger size of the second active pattern (ACT2) in which the gate electrode (GE) and source / drain region (SDR) are formed. As a result, electrical defects such as single-channel effects and noise in the image sensor can be reduced.

[0077] Additionally, according to the present invention, a connection pattern (170) may be provided to connect first to fourth ground impurity regions (160a, 160b, 160c, 160d) arranged adjacent to the third trench (TR3). Accordingly, the number of ground contacts (GCTs), as well as the number and length of the first wiring (212) connected to the ground contacts (GCTs), may be reduced. That is, the parasitic capacitance between adjacent first wirings (212) and adjacent ground contacts (GCTs) may be reduced. As a result, the electrical characteristics of the image sensor may be improved.

[0078] In addition, since it is possible to form active patterns with relatively large widths and sizes, tilting of the active patterns can be prevented, thereby effectively mitigating defects during the image sensor manufacturing process. As a result, the reliability of the image sensor can be improved.

[0080] FIGS. 9a to 9g are cross-sectional views along line A-A' of FIG. 4, respectively, for illustrating a method of manufacturing an image sensor according to embodiments of the present invention.

[0081] Referring to FIG. 9a, a first substrate (100) having a first surface (100a) and a second surface (100b) opposite to each other may be prepared. The first substrate (100) may contain impurities of a first conductivity type (e.g., p-type). In one example, the first substrate (100) may be a substrate in which a first conductivity type epitaxial layer is formed on a first conductivity type bulk silicon substrate. In another example, the first substrate (100) may be a bulk substrate including wells of the first conductivity type.

[0082] A second trench (TR2) can be formed on a first surface (100a) of a first substrate (100). Forming the second trench (TR2) may include forming a first mask pattern (MK1) on the first surface (100a) of the first substrate (100) and performing an etching process on the first surface (100a) of the first substrate (100) using the first mask pattern (MK1).

[0083] Referring to FIG. 9b, a first trench (TR1) may be formed from a first surface (100a) of a first substrate (100). Prior to forming the first trench (TR1), a preliminary device isolation pattern (103p) may be formed on the first surface (100a) of the first substrate (100). The preliminary device isolation pattern (103p) may be formed by performing a deposition process on the first surface (100a) of the first substrate (100). The preliminary device isolation pattern (103p) may completely fill the second trench (TR2) and cover the first mask pattern (MK1). The upper surface of the preliminary device isolation pattern (103p) may be formed at a higher level than the first surface (100a) of the first substrate (100). A mask (not shown) may be formed on a preliminary device isolation pattern (103p), and a first trench (TR1) may be formed by anisotropically etching the preliminary device isolation pattern (103p) and the first substrate (100). The bottom surface (TR1b) of the first trench (TR1) may be located at a higher level than the second surface (100b) of the first substrate (100). The preliminary device isolation pattern (103p) may include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0084] A barrier impurity region (33) may be formed within a first substrate (100) adjacent to a first trench (TR1). For example, the barrier impurity region (33) may be formed by performing a plasma doping process (PLAD) within the first trench (TR1). In the case of a plasma doping process, a source material may be supplied into a process chamber in a gaseous state. After plasma ionizing the source material, a high-voltage bias may be applied to an electrostatic chuck (not shown) on which the first substrate (100) is loaded, thereby injecting the ionized source material into the first substrate (100). Plasma doping can achieve uniform doping even at relatively very deep locations and can improve the doping process speed. As another example, the barrier impurity region (33) may be formed by forming a sacrificial film containing impurities of the first conductivity type within a deep trench and diffusing the impurities within the sacrificial film into the semiconductor substrate (100) through a heat treatment process. The barrier impurity region (33) may contain p-type impurities.

[0085] Referring to FIG. 9c, a first preliminary isolation pattern (151p) may be formed to conformally cover the inner wall of the first trench (TR1). The first preliminary isolation pattern (151p) may cover the inner wall of the first trench (TR1) and the upper surface of the preliminary device isolation pattern (103p). The first preliminary isolation pattern (151p) may be formed by depositing an insulating material on the first substrate (100) on which the first trench (TR1) is formed. The first preliminary isolation pattern (151p) may include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0086] A second preliminary separation pattern (153p) may be formed on the first preliminary separation pattern (151p). The second preliminary separation pattern (153p) may be formed by performing a deposition process on the first substrate (100) on which the first preliminary separation pattern (151p) is formed. The second preliminary separation pattern (153p) may cover the first preliminary separation pattern (151p) on the inner wall of the first trench (TR1) and may cover the upper surface of the preliminary device separation pattern (103p). The second preliminary separation pattern (153p) may include, for example, polysilicon.

[0087] Referring to FIG. 9d, a first etching process may be performed to remove the upper portion of the second preliminary separation pattern (153p) so that the second separation pattern (153) may be formed. Accordingly, a portion of the first preliminary separation pattern (151p) may be exposed to the outside. The first etching process may be performed until the upper surface of the second separation pattern (153) is positioned at a level lower than the bottom surface of the preliminary device separation pattern (103p).

[0088] According to one embodiment, after the first etching process is performed, a doping process may be performed on the second separation pattern (153). The doping process may be, for example, a beam line ion implantation process or a plasma doping process (PLAD). In the case of a beam line ion implantation process, because the width of the first trench (TR1) is relatively deep and narrow, it may be difficult to dope uniformly along the vertical depth on the second separation pattern (153). Accordingly, when the doping process is performed by a beam line ion implantation process, the impurity concentration of the second separation pattern (153) may vary along the vertical depth. In an image sensor device, when a negative voltage is applied to the second separation pattern (153), the dark current characteristics of the image sensor may be improved.

[0089] A preliminary capping pattern (155p) may be formed to cover the front surface of the first substrate (100) and fill the upper portion of the first trench (TR1). Forming the preliminary capping pattern (155p) may include performing a deposition process on the first surface (100a) of the first substrate (100). The preliminary capping pattern (155p) may include silicon oxide, silicon nitride, and / or silicon oxynitride.

[0090] Referring to FIG. 9e, a capping pattern (155), a first separation pattern (151), and a device separation pattern (103) may be formed. Forming the capping pattern (155), the first separation pattern (151), and the device separation pattern (103) may include performing a planarization process on a first surface (100a) of a first substrate (100). According to one example, the first mask pattern (MK1) may be removed after the planarization process, thereby preventing damage to the first surface (100a) of the first substrate (100).

[0091] Referring to FIG. 9f, photoelectric conversion regions (110) may be formed by doping impurities within each unit pixel region (PX). The photoelectric conversion regions (110) may have a second conductivity type (e.g., n-type) different from the first conductivity type (e.g., p-type). The vertical thickness of the first substrate (100) may be reduced by performing a thinning process that removes a portion of the first substrate (100). The thinning process may include grinding or polishing the second surface (100b) of the first substrate (100) and performing anisotropic or isotropic etching. To thin the first substrate (100), the top and bottom of the first substrate (100) may be inverted. A portion of the first substrate (100) may be removed by a grinding or polishing process, and subsequently, an anisotropic or isotropic etching process may be performed to remove remaining surface defects of the first substrate (100).

[0092] As a thin film process is performed on the second surface (100b) of the first substrate (100), the bottom surfaces of the first separation pattern (151) and the second separation pattern (153) may be exposed. The bottom surfaces of the first separation pattern (151) and the second separation pattern (153) may be located at substantially the same level as the second surface (100b) of the first substrate (100).

[0093] A third trench (TR3) may be formed on a first surface (100a) of a first substrate (100). Forming the third trench (TR3) may include forming a second mask pattern (MK2) on the first surface (100a) of the first substrate (100) and performing an etching process on the first surface (100a) using the second mask pattern (MK2). The third trench (TR3) may expose a barrier impurity region (33) provided on the sidewall of a pixel separation pattern (150) disposed between unit pixel regions (PX).

[0094] An ion implantation process may be performed on the third trench (TR3) to form a ground impurity region (160). The ground impurity region (160) may be formed along the bottom surface and sidewalls of the third trench (TR3). A portion of the ground impurity region (160) may overlap with the barrier impurity region (33). The ground impurity region (160) may be spaced apart from the top surface of the first substrate (100). The ground impurity region (160) may be a region doped with the same first conductivity type (e.g., p-type) as the first substrate (100).

[0095] A connection pattern (170) may be formed within the third trench (TR3). For example, the connection pattern (170) may be formed using a deposition process. The connection pattern (170) may cover the bottom surface of the third trench (TR3). The connection pattern (170) may be in contact with the ground impurity region (160). For example, the connection pattern (170) may comprise polysilicon doped with p-type impurities (e.g., boron). For another example, the connection pattern (170) may comprise a metallic material such as tungsten, copper, aluminum, and titanium, or a metallic nitride such as titanium nitride.

[0096] Referring to FIG. 9g, a transmission gate (TG) and a gate electrode (GE) may be formed on a first surface (100a) of a first substrate (100). An impurity may be doped on one side of the transmission gate (TG) to form a floating diffusion region (FD). Although not illustrated, source / drain regions (SDR) described with reference to FIG. 4 may be formed by doping impurities on both sides of the gate electrode (GE).

[0097] A first insulating layer (221) may be formed on a first surface (100a) of a first substrate (100). The first insulating layer (221) may cover gate electrodes (GE) and transmission gates (TG). The first insulating layer (221) may fill the remainder of a third trench (TR3). Contacts (CT) and a ground contact (GCT) may be formed penetrating the first insulating layer (221). The contact (CT) may be connected to at least one of a floating diffusion region (FD), a gate electrode (GE), and a transmission gate (TG). The ground contact (GCT) may be connected to a connection pattern (170). First wiring (212) may be formed on the first insulating layer (221).

[0098] Referring again to FIG. 4, FIG. 5a, FIG. 5b and FIG. 6, a second insulating layer (222) may be formed on a first insulating layer (221). The second insulating layer (222) may cover the first wiring (212). Via (215) penetrating the second insulating layer (222) may be formed. Second wiring (213) may be formed on the second insulating layer (222). A third insulating layer (223) may be formed on the second insulating layer (222). The third insulating layer (223) may cover the second wiring (213). Via (215) may connect the first and second wiring (212, 213) to each other.

[0099] A first fixed charge film (132), a second fixed charge film (134), and a flattening film (136) may be sequentially formed on a second surface (100b) of a first substrate (100). A light-blocking pattern (315) and a low-refractive index pattern (311) may be formed on the flattening film (136). A protective film (316) covering the low-refractive index pattern (311) and the light-blocking pattern (315) may be formed. Color filters (303) may be formed on the protective film (316). A micro-lens portion (306) may be formed on the color filters (303).

[0101] FIG. 10 is a cross-sectional view illustrating an image sensor according to embodiments of the present invention. In this embodiment, details that overlap with those described with reference to FIG. 4, 5a, 5b, and 6 are omitted, and the differences are described in detail.

[0102] Referring to FIG. 10, a pixel separation pattern (150) may be provided within a first trench (TR1). The first trench (TR1) may be recessed from a second surface (100b) of the first substrate (100). The width of the first trench (TR1) may decrease as it moves from the second surface (100b) of the first substrate (100) toward the first surface (100a).

[0103] The pixel separation pattern (150) may include a fixed charge film (159) provided conformally along the inner wall of the first trench (TR1) and a buried insulation pattern (157) provided on the fixed charge film (159). The fixed charge film (159) may have a negative fixed charge. The fixed charge film (159) may be made of a metal oxide or metal fluoride comprising at least one metal selected from the group comprising hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), titanium (Ti), yttrium (Y), and lanthanides. For example, the fixed charge film (159) may be a hafnium oxide film or an aluminum oxide film. Hole accumulation may occur around the fixed charge film (159). This can effectively reduce the occurrence of dark current and white spots. The buried insulation pattern (157) may include an insulating material with good step coverage characteristics. For example, the buried insulation pattern (157) may include a silicon oxide film. The fixed charge film (159) may extend onto the second surface (100b) of the first substrate (100). The buried insulation pattern (157) may also extend onto the second surface (100b) of the first substrate (100).

[0104] A first passivation film (322) and a second passivation film (324) may be sequentially provided on the bottom surface of the buried insulation pattern (157). Each of the first passivation film (322) and the second passivation film (324) may include an inorganic oxide. For example, each of the first passivation film (322) and the second passivation film (324) may include silicon oxide.

[0105] A ground impurity area (160) may be provided along the bottom surface and sidewall of the third trench (TR3). For example, one ground impurity area (160) may be shared by the first to fourth pixel areas (PX1, PX2, PX3, PX4). The ground impurity area (160) may be spaced apart from the pixel separation pattern (150).

[0107] FIG. 11 is a cross-sectional view illustrating an image sensor according to embodiments of the present invention. In this embodiment, details that overlap with those described with reference to FIG. 4, 5a, 5b, and 6 are omitted, and the differences are described in detail.

[0108] Referring to FIG. 11, a first floating diffusion region (FD1) and a second floating diffusion region (FD2) may be provided on the upper surface of the first substrate (100). The second floating diffusion region (FD2) may be separated from the first floating diffusion region (FD1) by a device isolation pattern (103).

[0109] A first insulating film (138) may be provided on a second surface (100b) of a first substrate (100). Color filters (303a, 303c) may be disposed on the first insulating film (138) for each unit pixel area (PX). A light-blocking pattern (315) may be disposed on the first insulating film (138) between the color filters (303a, 303c). The sides and bottom surfaces of the color filters (303a, 303c) and the bottom surface of the light-blocking pattern (315) may be covered by a second insulating film (139). The space between the color filters (303a, 303c) may be filled with a low-refractive index pattern (311).

[0110] A third insulating film (140) may be provided on the second insulating film (139) and the low-refractive index pattern (311). Pixel electrodes (142) may be provided on the third insulating film (140) for each unit pixel region (PX). An insulating pattern (148) may be interposed between the pixel electrodes (142). The insulating pattern (148) may include, for example, a silicon oxide film or a silicon nitride film. A photoelectric conversion pattern (163) may be provided on the pixel electrodes (142). A common electrode (144) may be provided on the photoelectric conversion pattern (163). A passivation film (149) may be provided on the common electrode (144). Microlenses (307) may be provided on the passivation film (149).

[0111] The pixel electrode (142) and the common electrode (144) may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and / or an organic transparent conductive material. The photoelectric conversion pattern (163) may be, for example, an organic photoelectric conversion layer. The photoelectric conversion pattern (163) may include a p-type organic semiconductor material and an n-type organic semiconductor material, and the p-type organic semiconductor material and the n-type organic semiconductor material may form a pn junction. Alternatively, the photoelectric conversion pattern (163) may include a quantum dot or a chalcogenide.

[0112] The pixel electrode (142) can be electrically connected to the pixel separation pattern (150) by a via plug (146). More specifically, the pixel electrode (142) can be electrically connected to the second separation pattern (153) of the pixel separation pattern (150). The via plug (146) can come into contact with the pixel separation pattern (150) by penetrating the third insulating film (140), the low-refractive index pattern (311), the second insulating film (139), the light-blocking pattern (315), and the first insulating film (138). The sidewalls of the via plug (146) can be covered with a via insulating film (147). The pixel separation pattern (150) can be electrically connected to the second floating diffusion region (FD2) by the first wiring (212) and contacts (CTa, CTb). The first contacts (CTa) can be connected to at least one of the transmission gate (TG), the gate electrode (GE), and the first and second floating diffusion regions (FD1, FD2). The second contact (CTb) can be connected to the second separation pattern (155). The bottom surface of the second contact (CTb) can be located at a lower level than the bottom surfaces of the first contacts (CTa).

[0114] FIG. 12 is a plan view of the enlarged region M of FIG. 2, intended to illustrate an image sensor according to embodiments of the present invention. FIG. 13 is a cross-sectional view along the line A-A' of FIG. 12. FIG. 14 is a cross-sectional view of the enlarged region N of FIG. 13. In this embodiment, details that overlap with those described with reference to FIG. 4, 5a, 5b, and 6 are omitted, and the differences are described in detail.

[0115] Referring to FIGS. 12 and 13, ground contacts (GCTs) may each contact the first to fourth ground impurity regions (160a, 160b, 160c, 160d). The ground contacts (GCTs) may be directly connected to the ground impurity region (160). The ground contacts (GCTs) may be vertically overlapped with at least one of the first to fourth ground impurity regions (160a, 160b, 160c, 160d). At least one ground contact (GCT) may be placed on each unit pixel region (PX). The ground contacts (GCTs) on the first to fourth pixel regions (PX1, PX2, PX3, PX4) may be connected to each other by a first wiring (212). The first wiring (212) can cross the pixel separation pattern (150) between the first to fourth pixel regions (PX1, PX2, PX3, PX4).

[0116] The bottom surface of the ground contact (GCT) may be located at the third level (LV3). The bottom surface of the third trench (TR3) may be located at the fourth level (LV4). For example, the third level (LV3) may be located at a level lower than the fourth level (LV4). In this case, the bottom surface of the ground contact (GCT) and a portion of the sidewall may be in contact with the ground impurity area (160). As another example, the third level (LV3) may be located at substantially the same level as the fourth level (LV4). That is, the bottom surface of the ground contact (GCT) may be in contact with the top surface of the ground impurity area (160).

[0117] According to the present embodiment, a number of first wires (212) may be provided that connect all ground contacts (GCTs) connected to the first to fourth ground impurity regions (160a, 160b, 160c, 160d), respectively. Accordingly, parasitic capacitance that may occur between adjacent first wires (212) can be reduced. As a result, the electrical characteristics of the image sensor can be improved.

[0119] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing its technical concept or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive.

Claims

Claim 1 A substrate comprising a first pixel region and a second pixel region adjacent to each other, wherein the substrate comprises a first surface and a second surface opposite to each other; a pixel separation pattern provided within the substrate and defining the first and second pixel regions; a transmission gate disposed on the first surface of the substrate on the first pixel region; a floating diffusion region adjacent to one side of the transmission gate; a first ground impurity region adjacent to the first surface of the substrate on the first pixel region; a second ground impurity region adjacent to the first surface of the substrate on the second pixel region; a trench exposing the pixel separation pattern; a connection pattern covering the bottom surface of the trench; and a ground contact connected to the connection pattern. An image sensor comprising a contact connected to the floating diffusion region, wherein the bottom surface of the first ground impurity region is located at a lower level than the bottom surface of the floating diffusion region, the trench is vertically superimposed with a part of the first pixel region and a part of the second pixel region, each of the first ground impurity region and the second ground impurity region is in contact with the bottom surface and side wall of the trench, and the bottom surface of the ground contact is located at a lower level than the bottom surface of the contact. Claim 2 delete Claim 3 delete Claim 4 In claim 1, the ground contact is an image sensor that overlaps vertically with the pixel separation pattern. Claim 5 In claim 1, the connection pattern is an image sensor comprising polysilicon. Claim 6 An image sensor according to claim 1, further comprising a barrier impurity region provided on the sidewall of the pixel separation pattern, wherein a portion of the first ground impurity region overlaps with the barrier impurity region. Claim 7 In claim 1, the width of the pixel separation pattern becomes smaller as it goes from the second surface of the substrate to the first surface of the image sensor. Claim 8 The image sensor according to claim 1 further comprises: a first ground contact connected to the first ground impurity region; a second ground contact connected to the second ground impurity region; and wiring connecting the first ground contact and the second ground contact, wherein the wiring crosses the pixel separation pattern between the first pixel region and the second pixel region. Claim 9 In claim 8, the first ground contact is an image sensor that overlaps vertically with the first ground impurity region. Claim 10 In claim 8, the bottom surface of the first ground contact is an image sensor located at a lower level than the bottom surface of the trench.

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