Semiconductor device and method for manufacturing the same

Abstract

The present invention relates to a semiconductor device and a method for manufacturing the same, and more specifically, comprises a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, wherein the cell region includes a first active pattern and the core region includes a second active pattern; a device isolation layer on the boundary region, wherein the device isolation layer fills a trench between the first active pattern and the second active pattern; a line structure provided on the first active pattern and extending from the cell region to the boundary region; and a capping pattern covering one end of the line structure on the boundary region. The device isolation layer includes a recess region formed adjacent to the one end of the line structure, and the capping pattern extends along the one end of the line structure to the recess region, wherein the bottom surface of the capping pattern is lower than the top surface of the device isolation layer below the line structure.

Description

Technology Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same, and more specifically, to a semiconductor memory device with improved reliability and a method for manufacturing the same. Background Technology

[0002] Semiconductor devices are gaining prominence as important elements in the electronics industry due to characteristics such as miniaturization, multifunctionality, and / or low manufacturing costs. Among semiconductor devices, information storage devices can store logical data. With the advancement of the electronics industry, information storage devices are becoming more highly integrated. Consequently, the linewidths of the components constituting information storage devices are decreasing.

[0003] In addition, along with the high integration of information storage devices, high reliability of information storage devices is required. However, due to high integration, the reliability of information storage devices may be degraded. Therefore, much research is being conducted to improve the reliability of information storage devices. The technology forming the background of the present invention is disclosed in the following documents: 1. U.S. Patent Publication US 8928073 B2 (January 6, 2015) 2. U.S. Patent Publication US 10269808 B2 (April 23, 2019) 3. U.S. Patent Publication US 2021 / 0118886 A1 (April 22, 2021) The problem to be solved

[0004] The problem that the present invention aims to solve is to provide a semiconductor memory device with improved reliability.

[0005] Another problem that the present invention aims to solve is to provide a method for manufacturing a semiconductor memory device with improved reliability. means of solving the problem

[0006] According to the concept of the present invention, a semiconductor device may comprise a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, wherein the cell region includes a first active pattern and the core region includes a second active pattern; a device isolation layer on the boundary region, wherein the device isolation layer fills a trench between the first active pattern and the second active pattern; a line structure provided on the first active pattern and extending from the cell region to the boundary region; and a capping pattern covering one end of the line structure on the boundary region. The device isolation layer may comprise a recess region formed adjacent to the one end of the line structure, and the capping pattern extends along the one end of the line structure to the recess region, and the bottom surface of the capping pattern may be lower than the top surface of the device isolation layer below the line structure.

[0007] According to another concept of the present invention, a semiconductor device comprises a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, wherein the cell region includes a first active pattern and the core region includes a second active pattern; a device isolation layer on the boundary region, wherein the device isolation layer fills a trench between the first active pattern and the second active pattern; a line structure provided on the first active pattern and extending from the cell region to the boundary region; a core gate structure provided on the second active pattern; a sidewall spacer provided on the boundary region and covering a sidewall of the core gate structure; and a capping pattern provided on the boundary region and covering one end of the line structure. The capping pattern may comprise a material different from the sidewall spacer.

[0008] According to another concept of the present invention, a semiconductor device comprises a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, wherein the cell region includes a first active pattern and the core region includes a second active pattern, wherein the first active pattern has a long axis in a first direction and the first active pattern includes a first source / drain region and a second source / drain region spaced apart from each other in the first direction; a gate electrode provided within a groove between the first and second source / drain regions of the first active pattern, wherein the gate electrode extends in a second direction; a gate dielectric film interposed between the gate electrode and the first active pattern; a gate capping film provided on the gate electrode to fill the groove; a device isolation film provided on the substrate to define the first active pattern and the second active pattern; and a buffer film on the cell region. A line structure extending in a third direction intersecting the second direction and traversing the first active pattern on the buffer membrane, wherein the line structure extends from the cell region to the boundary region, and the line structure includes a first conductive pattern penetrating the buffer membrane to connect to the first source / drain region, a bit line on the first conductive pattern, and a first barrier pattern between the bit line and the first conductive pattern; a pair of spacers respectively provided on both sidewalls of the line structure; a contact connecting to the second source / drain region; a landing pad on the contact; an information storage element on the landing pad; a core gate structure on the second active pattern, wherein the core gate structure includes a second conductive pattern corresponding to the first conductive pattern, a second barrier pattern corresponding to the first barrier pattern, and a core gate electrode corresponding to the bit line; and a sidewall spacer on the sidewall of the core gate structure;and may include a capping pattern covering one end of the line structure on the boundary region.

[0009] A method for manufacturing a semiconductor device according to another concept of the present invention may include: forming a first active pattern on a cell region of a substrate; forming a second active pattern on a core region of the substrate; forming a device isolation film on a boundary region between the cell region and the core region; forming a plate structure including a conductive film on the cell region, wherein one end of the plate structure is located on the boundary region; forming a sidewall spacer on the one end of the plate structure; forming a first etching mask pattern that covers the core region while exposing the boundary region and the cell region; performing a first etching process using the first etching mask pattern to selectively remove the sidewall spacer on the one end of the plate structure; forming a mask film on the plate structure, wherein the mask film caps the one end of the plate structure; patterning the mask film to form a line-shaped mask pattern; and etching the plate structure using the mask pattern as an etching mask to form a line structure that crosses the first active pattern. Effects of the invention

[0010] According to the semiconductor device of the present invention, a capping pattern can cap one end of a line structure on a boundary region. The capping structure prevents the bit line of the line structure from being exposed to an oxide environment, thereby resolving process defects that cause the line width of the bit line to decrease. As a result, the reliability of the semiconductor device according to the present invention can be improved. Brief explanation of the drawing

[0011] FIG. 1 is a plan view of a semiconductor device according to embodiments of the present invention. Figure 2 is an enlarged plan view of the boundary between the cell region and the core region of Figure 1. FIG. 3a is a cross-sectional view along line A-A' of FIG. 2, FIG. 3b is a cross-sectional view along line B-B' of FIG. 2, FIG. 3c is a cross-sectional view along line C-C' of FIG. 2, and FIG. 3d is a cross-sectional view along line D-D' of FIG. 2. Figure 4 is an enlarged cross-sectional view of the M region of Figure 3d. FIGS. 5 and FIGS. 6 are each intended to illustrate a semiconductor device according to another embodiment of the present invention and are enlarged cross-sectional views of the M region of FIG. 3d. FIGS. 7, FIGS. 9, FIGS. 11, FIGS. 13 and FIGS. 15 are plan views for illustrating a method of manufacturing a semiconductor device according to embodiments of the present invention. FIGS. 8a, FIGS. 10a, FIGS. 12a, FIGS. 14a, and FIGS. 16a are cross-sectional views along the line A-A' of FIGS. 7, FIGS. 9, FIGS. 11, FIGS. 13, and FIGS. 15, respectively. FIGS. 8b, FIGS. 10b, FIGS. 12b, FIGS. 14b, and FIGS. 16b are cross-sectional views along the line B-B' of FIGS. 7, FIGS. 9, FIGS. 11, FIGS. 13, and FIGS. 15, respectively. FIGS. 8c, FIGS. 10c, FIGS. 12c, FIGS. 14c, and FIGS. 16c are cross-sectional views along the C-C' line of FIGS. 7, FIGS. 9, FIGS. 11, FIGS. 13, and FIGS. 15, respectively. FIGS. 8d, FIGS. 10d, FIGS. 12d, FIGS. 14d, and FIGS. 16d are cross-sectional views along the line D-D' of FIGS. 7, FIGS. 9, FIGS. 11, FIGS. 13, and FIGS. 15, respectively. FIGS. 8e, FIGS. 10e, FIGS. 12e, FIGS. 14e, and FIGS. 16e are cross-sectional views along the line E-E' of FIGS. 7, FIGS. 9, FIGS. 11, FIGS. 13, and FIGS. 15, respectively. FIGS. 17 to 21 are cross-sectional views for explaining a method of forming the N region of FIG. 14d. Specific details for implementing the invention

[0012] FIG. 1 is a plan view of a semiconductor device according to embodiments of the present invention. The semiconductor device (10) may include cell regions (CAR). The cell regions (CAR) may each form a unit cell block consisting of regions including a plurality of memory cells. The cell regions (CAR) may be spaced apart from each other in a first direction (D1) and a second direction (D2).

[0013] A core region (COR) may be provided between adjacent cell regions (CAR). A sense amplifier and a write driver may be provided in the core region (COR). A peripheral circuit region (POR) may be provided on one side of the cell regions (CAR). The peripheral circuit region (POR) may include a row decoder and a column decoder, etc.

[0014] FIG. 2 is an enlarged plan view of the boundary between the cell region and the core region of FIG. 1. FIG. 3a is a cross-sectional view along line A-A' of FIG. 2, FIG. 3b is a cross-sectional view along line B-B' of FIG. 2, FIG. 3c is a cross-sectional view along line C-C' of FIG. 2, and FIG. 3d is a cross-sectional view along line D-D' of FIG. 2. FIG. 4 is an enlarged cross-sectional view of region M of FIG. 3d.

[0015] Referring to FIG. 2, a substrate (100) including a cell region (CAR), a boundary region (BR), and a core region (COR) may be provided. The cell region (CAR) may be a region where a plurality of memory cells are provided. The boundary region (BR) may be interposed between the cell region (CAR) and the core region (COR). The boundary region (BR) may be a region for buffering process differences resulting from differences between the structure on the cell region (CAR) and the structure on the core region (COR). The boundary region (BR) may connect the structure on the cell region (CAR) and the structure on the core region (COR) to each other.

[0016] The substrate (100) may be a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, or a substrate of an epitaxial thin film obtained by performing selective epitaxial growth (SEG).

[0017] Hereinafter, the cell region (CAR) will be described in detail with reference to FIGS. 2 and FIGS. 3a through 3d. A device isolation film (ST) defining first active patterns (ACT1) may be provided on the cell region (CAR) of the substrate (100). The first active patterns (ACT1) may be formed by patterning the upper surface of the substrate (100). Each of the first active patterns (ACT1) may extend in a third direction (D3) parallel to the upper surface of the substrate (100). In other words, each of the first active patterns (ACT1) may have a major axis in the third direction (D3). The first active patterns (ACT1) may be arranged two-dimensionally along the first direction (D1) and the second direction (D2). The first active patterns (ACT1) may be spaced apart from each other in the third direction (D3).

[0018] Each of the first active patterns (ACT1) may have its width reduced as it moves in a direction perpendicular to the upper surface of the substrate (100) (i.e., the fourth direction (D4)). In other words, each of the first active patterns (ACT1) may have its width reduced as it moves away from the bottom surface of the substrate (100).

[0019] First and second trenches (TR1, TR2) may be defined between first active patterns (ACT1). A device isolation layer (ST) may fill the first and second trenches (TR1, TR2) between the first active patterns (ACT1). A first trench (TR1) may be defined between a pair of first active patterns (ACT1) adjacent to each other in a second direction (D2). A second trench (TR2) may be defined between a pair of first active patterns (ACT1) adjacent to each other in a third direction (D3).

[0020] The distance between a pair of first active patterns (ACT1) adjacent to each other in the second direction (D2) may be smaller than the distance between a pair of first active patterns (ACT1) adjacent to each other in the third direction (D3). Thus, the second trench (TR2) may be deeper than the first trench (TR1). In other words, the bottom of the second trench (TR2) may be lower than the bottom of the first trench (TR1) (see FIG. 3b).

[0021] The upper portion of each first active pattern (ACT1) may include a first source / drain region (SD1) and a pair of second source / drain regions (SD2). The first source / drain region (SD1) may be located between the pair of second source / drain regions (SD2). In other words, from a planar perspective, the second source / drain region (SD2), the first source / drain region (SD1), and the second source / drain region (SD2) may be arranged sequentially along a third direction (D3).

[0022] A pair of grooves (GRV) may be defined in each of the first active patterns (ACT1) (see FIG. 2c). Each groove (GRV) may be defined between the first source / drain region (SD1) and the second source / drain region (SD2). The groove (GRV) may extend downward from the upper surface of the first active pattern (ACT1) toward the bottom surface of the substrate (100), penetrating the upper part of the first active pattern (ACT1). The bottom of the groove (GRV) may be higher than the bottoms of the first and second trenches (TR1, TR2).

[0023] The upper portion of each first active pattern (ACT1) may further include a pair of channel regions (CH). In a planar view, the channel region (CH) may be interposed between the first source / drain region (SD1) and the second source / drain region (SD2). The channel region (CH) may be located below the groove (GRV) (see FIG. 3d). Thus, the channel region (CH) may be located lower than the first and second source / drain regions (SD1, SD2).

[0024] Gate electrodes (GE) may be provided across the first active patterns (ACT1) and the device isolation layer (ST). The gate electrodes (GE) may each be provided within the grooves (GRV). The gate electrodes (GE) may extend parallel to each other in a second direction (D2). A pair of gate electrodes (GE) may be provided on a pair of channel regions (CH) of the first active pattern (ACT1). In other words, from a planar perspective, the gate electrode (GE) may be interposed between the first source / drain region (SD1) and the second source / drain region (SD2). The upper surface of the gate electrode (GE) may be lower than the upper surface of the first active pattern (ACT1) (e.g., the upper surface of the first source / drain region (SD1) or the upper surface of the second source / drain region (SD2)).

[0025] Referring again to FIG. 3d, the upper part of the gate electrode (GE) may be adjacent to the first source / drain region (SD1) of the first active pattern (ACT1). The lower part of the gate electrode (GE) may be adjacent to the channel region (CH). The gate electrode (GE) may correspond to the word line of the memory cell.

[0026] Referring to FIGS. 2 and FIGS. 3a through 3d, a gate dielectric film (GI) may be interposed between a gate electrode (GE) and a first active pattern (ACT1). A gate capping film (GP) may be provided on the gate electrode (GE). The gate capping film (GP) may cover the upper surface of the gate electrode (GE). The upper surface of the gate capping film (GP) may co-plane with the upper surface of the first active pattern (ACT1).

[0027] The gate electrode (GE) may comprise a conductive metal nitride (e.g., titanium nitride or tantalum nitride) and / or a metallic material (e.g., titanium, tantalum, tungsten, copper, or aluminum). The gate dielectric film (GI) may comprise a silicon oxide film, a silicon nitride film, a silicon oxynitride film and / or a high dielectric constant material. As an example, the high dielectric constant material may comprise hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof. The gate capping film (GP) may comprise a silicon oxide film, a silicon nitride film, and / or a silicon oxynitride film.

[0028] A buffer film (IL) may be provided on a substrate (100). The buffer film (IL) may include first contact holes (CNH1) that expose first source / drain regions (SD1) of first active patterns (ACT1). In one embodiment of the present invention, the buffer film (IL) may include a first insulating film and a second insulating film that are sequentially stacked. The second insulating film may have a dielectric constant greater than that of the first insulating film. For example, the first insulating film may include a silicon oxide film, and the second insulating film may include a silicon oxynitride film.

[0029] Line structures (LST) extending parallel to each other in a first direction (D1) on the buffer film (IL) may be provided. The line structures (LST) may be arranged along a second direction (D2). In a planar view, the line structures (LST) may intersect perpendicularly with the gate electrodes (GE) (see FIG. 2). A pair of spacers (SP) may be provided on both sidewalls of each of the line structures (LST). The spacers (SP) may comprise silicon oxide, silicon nitride, and / or silicon oxynitride.

[0030] In one embodiment of the present invention, each spacer (SP) may include a first spacer, a second spacer, and a third spacer. The first spacer may directly cover the sidewall of the line structure (LST). The second spacer may be interposed between the first spacer and the third spacer. The second spacer may be made of an insulating material having a lower dielectric constant than that of the first and third spacers. For example, each of the first and third spacers may include a silicon nitride film, and the second spacer may include a silicon oxide film. For another example, the second spacer may be made of air, i.e., an air spacer.

[0031] Each line structure (LST) may include a sequentially stacked conductive pattern (CP), barrier pattern (BP), bit line (BL), and mask pattern (MP). The conductive pattern (CP) may include a contact portion (CNP) that fills a first contact hole (CNH1) and connects to a first source / drain region (SD1). More specifically, the contact portion (CNP) may extend toward the bottom surface of the substrate (100) by penetrating a buffer film (IL). The contact portion (CNP) may make direct contact with the first source / drain region (SD1).

[0032] The barrier pattern (BP) can suppress the diffusion of metallic material within the bit line (BL) into the conduction pattern (CP). The bit line (BL) can be electrically connected to the first source / drain region (SD1) through the barrier pattern (BP) and the conduction pattern (CP).

[0033] The conduction pattern (CP) may include a doped semiconductor material (doped silicon, doped germanium, etc.). The barrier pattern (BP) may include a conductive metal nitride (e.g., titanium nitride or tantalum nitride). The bit line (BL) may include a metallic material (e.g., titanium, tantalum, tungsten, copper, or aluminum).

[0034] A mask pattern (MP) may include a first mask pattern (MP1), a stopper pattern (STP), and a second mask pattern (MP2) sequentially stacked on a bit line (BL). The stopper pattern (STP) may be interposed between the first and second mask patterns (MP1, MP2). Each of the first mask pattern (MP1), the stopper pattern (STP), and the second mask pattern (MP2) may include silicon nitride or silicon oxynitride. For example, the first mask pattern (MP1), the stopper pattern (STP), and the second mask pattern (MP2) may include the same material (e.g., silicon nitride).

[0035] Referring again to FIG. 3b, a plurality of insulating fences (IFS) may be provided on the gate capping film (GP). Each insulating fence (IFS) may penetrate the buffer film (IL) and extend to the top of the gate capping film (GP).

[0036] Referring again to FIGS. 2 and FIG. 3b, insulating fences (IFS) can be arranged two-dimensionally along a first direction (D1) and a second direction (D2). Specifically, insulating fences (IFS) can be arranged along the second direction (D2) on a gate capping film (GP) extending in the second direction (D2). Insulating fences (IFS) and line structures (LST) can be arranged alternately along the second direction (D2). Insulating fences (IFS) arranged along the second direction (D2) can be vertically overlapped with the gate electrode (GE) underneath.

[0037] Referring to FIGS. 2 and FIGS. 3a through 3d, contacts (CNT) may be provided that penetrate the buffer film (IL) and connect to the second source / drain regions (SD2), respectively. Each contact (CNT) may fill a second contact hole (CNH2) formed by partially etching the upper portion of the second source / drain region (SD2). Referring again to FIG. 3a, the contact (CNT) may directly contact the second source / drain region (SD2) exposed by the second contact hole (CNH2). Additionally, the contact (CNT) may contact the sidewall of the spacer (SP) and the upper surface of the device isolation film (ST). The contact (CNT) may be spaced apart from the adjacent line structure (LST) by the spacer (SP). Each contact (CNT) may contain a doped semiconductor material (doped silicon, doped germanium, etc.).

[0038] Referring again to FIG. 2, contacts (CNTs) can be arranged two-dimensionally along a first direction (D1) and a second direction (D2). Specifically, contacts (CNTs) and line structures (LSTs) can be arranged alternately along the second direction (D2). Contacts (CNTs) and insulating fences (IFS) can be interposed between adjacent line structures (LSTs). Contacts (CNTs) and insulating fences (IFS) between adjacent line structures (LSTs) can be arranged alternately along the first direction (D1).

[0039] Landing pads (LP) connected to each of the contacts (CNT) may be provided on the contacts (CNT). The landing pads (LP) may be electrically connected to each of the second source / drain regions (SD2) through the contacts (CNT). The landing pads (LP) may be misaligned with the contacts (CNT) connected thereto. In other words, the landing pads (LP) may be horizontally offset from the center of the contacts (CNT) connected thereto (see FIG. 2 and FIG. 3a). The landing pads (LP) may comprise a metallic material (e.g., titanium, tantalum, tungsten, copper, or aluminum).

[0040] An insulation pattern (INP) may be provided on the mask patterns (MP). The insulation pattern (INP) on the cell region (CAR) may define the planar shape of the landing pads (LP). Adjacent landing pads (LP) may be separated from each other by the insulation pattern (INP).

[0041] Information storage elements (DS) may be provided on each of the landing pads (LP). Specifically, each information storage element (DS) may be electrically connected to a second source / drain region (SD2) through the landing pad (LP) and a contact (CNT). According to one embodiment, each information storage element (DS) may be a capacitor that stores data. For example, the information storage elements (DS) may include lower electrodes connected to each of the landing pads (LP), an upper electrode covering the lower electrodes, and a dielectric film interposed between the lower electrodes and the upper electrode. The upper electrode may be a common electrode covering the lower electrodes in common.

[0042] Each of the above-mentioned lower electrodes may have a hollow cylinder shape. Each of the above-mentioned lower electrodes may comprise a metal such as silicon or tungsten doped with impurities, or a conductive metal compound such as titanium nitride. The dielectric film (HDL) may comprise a high dielectric constant material, for example, hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof. The upper electrode may include doped silicon, Ru, RuO, Pt, PtO, Ir, IrO, SRO(SrRuO), BSRO((Ba,Sr)RuO), CRO(CaRuO), BaRuO, La(Sr,Co)O, Ti, TiN, W, WN, Ta, TaN, TiAlN, TiSiN, TaAlN, TaSiN, or a combination thereof.

[0043] The boundary region (BR) and the core region (COR) will be described in detail below with reference to FIGS. 2, 3d, and 3e. A third trench (TR3) may be defined between the cell region (CAR) and the core region (COR) of the substrate (100). In other words, a third trench (TR3) may be defined on the boundary region (BR) of the substrate (100). A device isolation film (ST) may fill the third trench (TR3).

[0044] At least one second active pattern (ACT2) may be provided on the core region (COR). For example, a third trench (TR3) may be defined between the first active pattern (ACT1) of the cell region (CAR) and the second active pattern (ACT2) of the core region (COR). In FIG. 2, the second active pattern (ACT2) is shown in a rectangular shape, but is not limited thereto and can be modified into any shape.

[0045] A core gate structure (CGS) may be provided on the core region (COR). The core gate structure (CGS) may include a core gate insulating film (CGI), a conduction pattern (CP), a barrier pattern (BP), a core gate electrode (CGE), and a first mask pattern (MP1) stacked sequentially on a second active pattern (ACT2). For example, the core gate structure (CGS) and the second active pattern (ACT2) may constitute a transistor of a sense amplifier in the core region (COR).

[0046] The components of the core gate structure (CGS) can be formed using substantially the same process as the components of the line structure (LST) on the cell region (CAR) described earlier. The components of the core gate structure (CGS) can be placed at substantially the same levels as the components of the line structure (LST). In other words, the core gate insulating film (CGI) can correspond to the buffer film (IL), and the core gate electrode (CGE) can correspond to the bit line (BL).

[0047] In one embodiment, one end of the core gate structure (CGS) may extend onto the device isolation layer (ST) of the boundary region (BR). In other words, at least a portion of the core gate structure (CGS) may be vertically overlapped with the device isolation layer (ST) of the boundary region (BR).

[0048] A sidewall spacer (SPC) may be provided on the sidewall of a core gate structure (CGS). As shown in FIG. 3d, the sidewall spacer (SPC) may be located on the device isolation film (ST) of the boundary region (BR). The sidewall spacer (SPC) may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0049] Referring to FIG. 2, one end (EN) of the line structure (LST) may extend onto the device isolation film (ST) of the boundary region (BR). A capping pattern (DML) may be connected to one end (EN) of the line structure (LST). The capping pattern (DML) may be provided on the device isolation film (ST) of the boundary region (BR). The capping pattern (DML) may extend from one end (EN) of the line structure (LST) toward the core region (COR) in the opposite direction of the first direction (D1). The capping pattern (DML) and the line structure (LST) connected thereto may be aligned in the first direction (D1). The line width of the capping pattern (DML) and the line width of the line structure (LST) connected thereto may be substantially the same as each other.

[0050] Referring again to FIGS. 2, FIGS. 3d, and FIGS. 3e, the capping pattern (DML) may include a stopper pattern (STP) and a second mask pattern (MP2). The conduction pattern (CP), barrier pattern (BP), and bit line (BL) may be omitted from the capping pattern (DML).

[0051] The stopper pattern (STP) can cover one end (EN) of the line structure (LST) on the boundary region (BR). The stopper pattern (STP) can extend from the line structure (LST) onto the core gate structure (CGS) while covering the upper surface of the device isolation film (ST) in the boundary region (BR). The stopper pattern (STP) can cover the sidewall spacer (SPC). An interlayer insulating film (ILD) may be interposed between the stopper pattern (STP) covering the sidewall spacer (SPC) and the capping pattern (DML).

[0052] A second mask pattern (MP2) may be provided on a stopper pattern (STP). The second mask pattern (MP2) may extend from a line structure (LST) through a capping pattern (DML) onto a core gate structure (CGS). In a planar view, the second mask pattern (MP2) may overlap with the line structure (LST) and the capping pattern (DML). The second mask pattern (MP2) on the core region (COR) may have a plate shape that overlaps with the core region (COR). In other words, the second mask pattern (MP2) on the core region (COR) may cover not only the core gate structure (CGS) but also the interlayer insulating film (ILD) surrounding the core gate structure (CGS).

[0053] In one embodiment, as shown in FIG. 2, the second mask pattern (MP2) may have a planar palm shape. Specifically, the second mask pattern (MP2) on the cell region (CAR) and boundary region (BR) may have a line shape extending in a first direction (D1). The second mask pattern (MP2) on the cell region (CAR) and boundary region (BR) may overlap with a line structure (LST) and a capping pattern (DML). The second mask pattern (MP2) on the core region (COR) may have a plate shape covering the entire core region (COR).

[0054] A recess region (RS) may be defined on the upper surface of the device isolation layer (ST) below the capping pattern (DML). The bottom of the recess region (RS) of the device isolation layer (ST) may be lower than the upper surface (STt) of the device isolation layer (ST) below the line structure (LST). The bottom of the recess region (RS) of the device isolation layer (ST) may be lower than the upper surface of the device isolation layer (ST) below the core gate structure (CGS).

[0055] The second mask pattern (MP2) of the capping pattern (DML) may extend into the recess region (RS) of the device isolation film (ST) along the stopper pattern (STP). The bottom surface of the second mask pattern (MP2) of the capping pattern (DML) may be lower than the bottom surface of the second mask pattern (MP2) of the line structure (LST). The bottom surface of the second mask pattern (MP2) of the capping pattern (DML) may be lower than the bottom surface of the second mask pattern (MP2) on the core region (COR).

[0056] The bottom surface (DMLb) of the capping pattern (DML) may be the same as the bottom of the recess region (RS) of the device isolation layer (ST). The bottom surface (DMLb) of the capping pattern (DML) may be lower than the bottom surface of the buffer layer (IL) of the line structure (LST). In other words, the bottom surface (DMLb) of the capping pattern (DML) may be lower than the top surface (STt) of the device isolation layer (ST) below the line structure (LST).

[0057] Referring again to FIG. 3e, a pair of spacers (SP) may be provided on both sidewalls of a capping pattern (DML). The pair of spacers (SP) may extend from both sidewalls of a line structure (LST) onto both sidewalls of the capping pattern (DML). A dummy contact (DCNT) may be provided between adjacent capping patterns (DML). The bottom of the dummy contact (DCNT) may be in contact with a device isolation film (ST). A dummy conductive film (DCL) may be provided on the dummy contact (DCNT).

[0058] Referring again to FIGS. 2, FIGS. 3d and FIGS. 3e, an insulating pattern (INP) may be provided on the second mask pattern (MP2). Although not illustrated, at least one metal wiring may be provided within the insulating pattern (INP). The metal wiring may electrically connect the bit line (BL) of the line structure (LST) and the core gate electrode (CGE) of the core gate structure (CGS) to each other.

[0059] With reference to FIG. 4, a capping pattern (DML) according to one embodiment of the present invention will be described in more detail. The capping pattern (DML) may be provided between the interlayer insulating film (ILD) of the core region (COR) and one end (EN) of the line structure (LST). The capping pattern (DML) may cap one end (EN) of the line structure (LST). In other words, the capping pattern (DML) may prevent the bit line (BL) from being exposed to an oxide environment near one end (EN) of the line structure (LST).

[0060] The capping pattern (DML) can extend toward the device isolation layer (ST) along one end (EN) of the line structure (LST). The lower portion of the capping pattern (DML) can be provided within the recess area (RS) of the device isolation layer (ST). The bottom surface (DMLb) of the capping pattern (DML) may be lower than the bottom surface of the line structure (LST). The bottom surface (DMLb) of the capping pattern (DML) may be lower than the top surface (STt) of the device isolation layer (ST) below the line structure (LST). This allows the capping pattern (DML) to more completely cap one end (EN) of the line structure (LST).

[0061] A sidewall spacer (SPC) is provided on the sidewall of the core gate structure (CGS), but the spacer may be omitted on one end (EN) of the line structure (LST). One end (EN) of the line structure (LST) may be directly covered by a capping pattern (DML). More specifically, one end (EN) of the line structure (LST) may be directly covered by a capping pattern (DML). More specifically, one end (EN) of the line structure (LST) may be directly covered by a stopper pattern (STP) of the capping pattern (DML). For example, since the stopper pattern (STP) contains silicon nitride, one end (EN) of the bit line (BL) may be prevented from being exposed to an oxide environment.

[0062] The recess region (RS) of the device isolation film (ST) may include an undercut region (UCR) extending downward from the line structure (LST). The undercut region (UCR) may be a space extending horizontally from the recess region (RS). The bottom surface (ILb) of the buffer film (IL) may be exposed by the undercut region (UCR). The capping pattern (DML) may include a lower protrusion (LPP) that fills the undercut region (UCR). The upper surface of the lower protrusion (LPP) may directly cover the bottom surface (ILb) of the buffer film (IL). The lower protrusion (LPP) may vertically overlap with at least a portion of the line structure (LST).

[0063] As shown in FIG. 4, the capping pattern (DML) according to the present embodiment can cover one end (EN) of the line structure (LST) in an L-shape. By doing so, the capping pattern (DML) can more completely cap the one end (EN) of the line structure (LST), thereby more effectively preventing the one end (EN) of the bit line (BL) from being exposed to an oxide environment.

[0065] FIGS. 5 and FIGS. 6 are each intended to illustrate a semiconductor device according to another embodiment of the present invention and are enlarged cross-sectional views of the M region of FIG. 3d. In this embodiment, detailed descriptions of technical features that overlap with those previously described with reference to FIG. 4 are omitted, and the differences are described in detail.

[0066] Referring to FIG. 5, the recess region (RS) of the device isolation film (ST) may include an inner wall (RSw) adjacent to one end (EN) of the line structure (LST). The inner wall (RSw) of the recess region (RS) may be vertically aligned with one end (EN) of the line structure (LST). The capping pattern (DML) may directly cover the one end (EN) of the line structure (LST) and the inner wall (RSw) of the recess region (RS).

[0067] Unlike the description above with reference to FIG. 4, the undercut region (UCR) of the recess region (RS) of the device isolation film (ST) in this embodiment may be omitted. The lower protrusion (LPP) of the capping pattern (DML) in this embodiment may be omitted.

[0068] Referring to FIG. 6, a sidewall spacer (SPC) on the sidewall of the core gate structure (CGS) may be omitted. A stopper pattern (STP) may directly cover the sidewall of the core gate structure (CGS). An interlayer insulating film (ILD) may be provided between the stopper pattern (STP) covering the sidewall of the core gate structure (CGS) and the capping pattern (DML).

[0070] FIGS. 7, 9, 11, 13, and 15 are plan views illustrating a method for manufacturing a semiconductor device according to embodiments of the present invention. FIGS. 8a, 10a, 12a, 14a, and 16a are cross-sectional views along line A-A' of FIGS. 7, 9, 11, 13, and 15, respectively. FIGS. 8b, 10b, 12b, 14b, and 16b are cross-sectional views along line B-B' of FIGS. 7, 9, 11, 13, and 15, respectively. FIGS. 8c, 10c, 12c, 14c, and 16c are cross-sectional views along line C-C' of FIGS. 7, 9, 11, 13, and 15, respectively. FIGS. 8d, FIGS. 10d, FIGS. 12d, FIGS. 14d, and FIGS. 16d are cross-sectional views along the line D-D' of FIGS. 7, FIGS. 9, FIGS. 11, FIGS. 13, and FIGS. 15, respectively. FIGS. 8e, FIGS. 10e, FIGS. 12e, FIGS. 14e, and FIGS. 16e are cross-sectional views along the line E-E' of FIGS. 7, FIGS. 9, FIGS. 11, FIGS. 13, and FIGS. 15, respectively. FIGS. 17 to 21 are cross-sectional views for explaining a method of forming the N region of FIG. 14d.

[0071] Referring to FIGS. 7 and FIGS. 8a through 8e, a substrate (100) comprising a cell region (CAR), a boundary region (BR), and a core region (COR) may be provided. By patterning the upper surface of the substrate (100), first active patterns (ACT1) may be formed on the cell region (CAR), and a second active pattern (ACT2) may be formed on the core region (COR).

[0072] Each of the first active patterns (ACT1) may extend in a third direction (D3) parallel to the upper surface of the substrate (100). The first active patterns (ACT1) may be arranged two-dimensionally along the first direction (D1) and the second direction (D2). The first active patterns (ACT1) may be spaced apart from each other in the third direction (D3).

[0073] First and second trenches (TR1, TR2) may be formed between first active patterns (ACT1). A first trench (TR1) may be formed between a pair of first active patterns (ACT1) adjacent to each other in a second direction (D2). A second trench (TR2) may be formed between a pair of first active patterns (ACT1) adjacent to each other in a third direction (D3).

[0074] A third trench (TR3) may be formed between the first active pattern (ACT1) of the cell region (CAR) and the second active pattern (ACT2) of the core region (COR). The third trench (TR3) may be formed on the boundary region (BR) and the core region (COR).

[0075] A device isolation layer (ST) can be formed to fill the first to third trenches (TR1-TR3). The device isolation layer (ST) can be formed to completely fill the first to third trenches (TR1-TR3) and cover the first and second active patterns (ACT1, ACT2). A planarization process can be performed on the device isolation layer (ST) until the upper surfaces of the first and second active patterns (ACT1, ACT2) are exposed.

[0076] Grooves (GRV) can be formed by patterning the first active patterns (ACT1) and the device isolation layer (ST) on the cell region (CAR). In a planar view, each of the grooves (GRV) may have a line shape extending in a second direction (D2).

[0077] Forming grooves (GRV) may include forming a hard mask pattern including openings, and etching the first active patterns (ACT1) and device isolation layer (ST) exposed to the hard mask pattern as an etching mask. The grooves (GRV) may be formed shallower than the first trench (TR1).

[0078] A gate dielectric film (GI), a gate electrode (GE), and a gate capping film (GP) can be sequentially formed within each groove (GRV). Specifically, a gate dielectric film (GI) can be conformally formed within the groove (GRV). The gate dielectric film (GI) may include a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and / or a high dielectric constant material.

[0079] A gate electrode (GE) can be formed by forming a conductive film that fills a groove (GRV) on a gate dielectric film (GI). The conductive film may include a conductive metal nitride and / or a metal material.

[0080] The gate dielectric film (GI) and the gate electrode (GE) can be recessed, and a gate capping film (GP) can be formed on the recessed gate electrode (GE). The upper surface of the gate capping film (GP) can co-plane with the upper surface of the first active pattern (ACT1).

[0081] An ion implantation process may be performed on the first active patterns (ACT1) to form a first source / drain region (SD1) and a pair of second source / drain regions (SD2) on the upper portion of the first active pattern (ACT1). The pair of second source / drain regions (SD2) may be spaced apart from each other in a third direction (D3) with the first source / drain region (SD1) in between. For example, the first and second source / drain regions (SD1, SD2) may be doped with the same impurity.

[0082] A channel region (CH) may be defined in a first active pattern (ACT1) located below a gate electrode (GE). In a planar view, the channel region (CH) may be interposed between a first source / drain region (SD1) and a second source / drain region (SD2). The gate electrode (GE) may be provided on the top surface and both sidewalls of the channel region (CH) (see FIG. 8b).

[0083] Referring to FIGS. 9 and FIGS. 10a through 10e, a buffer film (IL) may be formed on the front surface of a substrate (100). In other words, the buffer film (IL) may be formed on a cell region (CAR), a boundary region (BR), and a core region (COR). For example, the buffer film (IL) may be a multi-layer structure in which a silicon oxide film and a silicon oxynitride film are stacked. By patterning the buffer film (IL) on the cell region (CAR), first contact holes (CNH1) may be formed to expose first source / drain regions (SD1) of first active patterns (ACT1), respectively. When the first contact holes (CNH1) are formed, the upper portion of the first source / drain region (SD1) may be recessed. When the first contact holes (CNH1) are formed, the upper portion of the device isolation film (ST) around the first source / drain region (SD1) may be recessed.

[0084] A first conductive film (CL1), a barrier film (BAL), and a second conductive film (CL2) may be sequentially formed on a buffer film (IL). The first conductive film (CL1), the barrier film (BAL), and the second conductive film (CL2) may be formed on a cell region (CAR), a boundary region (BR), and a core region (COR).

[0085] The first conductive film (CL1) can fill the first contact holes (CNH1). In other words, the first conductive film (CL1) can come into contact with the first source / drain regions (SD1) of the first active patterns (ACT1). The first conductive film (CL1) filled in the first contact holes (CNH1) can form a contact portion (CNP). The first conductive film (CL1) can be vertically separated from the second source / drain regions (SD2) of the first active patterns (ACT1) by a buffer film (IL). The first conductive film (CL1) may include a doped semiconductor material.

[0086] A barrier film (BAL) may be formed to be interposed between a first conductive film (CL1) and a second conductive film (CL2). The barrier film (BAL) may include a conductive metal nitride. The second conductive film (CL2) may include a metal material. The barrier film (BAL) may prevent the metal material within the second conductive film (CL2) from diffusing into the first conductive film (CL1).

[0087] Referring to FIGS. 11 and FIGS. 12a through 12e, a first mask pattern (MP1) may be formed on a second conductive film (CL2). The first mask pattern (MP1) may be formed to completely cover a cell region (CAR). The edges of the first mask pattern (MP1) may overlap with a boundary region (BR). The first mask pattern (MP1) on the core region (COR) may define a core gate structure (CGS). Specifically, forming the first mask pattern (MP1) may include forming a first mask film on the second conductive film (CL2) and patterning the first mask film using photolithography.

[0088] The first mask pattern (MP1) can be used as an etching mask to etch the second conductive film (CL2), barrier film (BAL), first conductive film (CL1), and buffer film (IL) underneath. This allows the device isolation film (ST) in the region not covered by the first mask pattern (MP1) to be exposed (see FIG. 12d and FIG. 12e).

[0089] A buffer film (IL), a first conductive film (CL1), a barrier film (BAL), and a second conductive film (CL2) on a cell region (CAR) can be patterned by a first mask pattern (MP1) to form a plate structure (PLS). In a planar view, the plate structure (PLS) may have a rectangular plate shape. The plate structure (PLS) may overlap entirely with the cell region (CAR). The edges of the plate structure (PLS) may overlap with at least a portion of the boundary region (BR).

[0090] A buffer film (IL), a first conductive film (CL1), a barrier film (BAL), and a second conductive film (CL2) on a second active pattern (ACT2) may be patterned by a first mask pattern (MP1) to form a core gate structure (CGS). The core gate structure (CGS) may include a core gate insulating film (CGI), a conductive pattern (CP), a barrier pattern (BP), a core gate electrode (CGE), and a first mask pattern (MP1) sequentially stacked on the second active pattern (ACT2).

[0091] A sidewall spacer (SPC) may be formed on one end (EN) (or sidewall) of the boundary region (BR) of the plate structure (PLS). A sidewall spacer (SPC) may be formed on the sidewall of the core gate structure (CGS). Forming the sidewall spacer (SPC) may include forming a spacer film on the front surface of the substrate (100) and anisotropically etching the spacer film. The sidewall spacer (SPC) may include silicon oxide.

[0092] Referring to FIGS. 13 and FIGS. 14a through 14e, a plate structure (PLS) on a cell region (CAR) may be patterned to form line structures (LST) that extend parallel to each other in a first direction (D1). The line structures (LST) may extend from the cell region (CAR) to a boundary region (BR). A capping pattern (DML) may be formed on one end (EN) of the line structures (LST) on the boundary region (BR).

[0093] Specifically, forming a line structure (LST) and a capping pattern (DML) may include forming a stopper film and a second mask film on a substrate (100), forming a second mask pattern (MP2) from the second mask film using a photolithography process, and patterning a plate structure (PLS) using the second mask pattern (MP2) as an etching mask.

[0094] A stopper film, a first mask pattern (MP1), a second conductive film (CL2), a barrier film (BAL), and a first conductive film (CL1) can be sequentially patterned using a second mask pattern (MP2) on a cell region (CAR) as an etching mask, thereby forming a stopper pattern (STP), a first mask pattern (MP1), a bit line (BL), a barrier pattern (BP), and a conductive pattern (CP), respectively. The conductive pattern (CP), barrier pattern (BP), bit line (BL), and mask pattern (MP) sequentially stacked on a buffer film (IL) of the cell region (CAR) can form a line structure (LST). In other words, a plurality of line structures (LST) can be formed from a plate structure (PLS) by the second mask pattern (MP2) on the cell region (CAR). From a planar perspective, each bit line (BL) can extend by intersecting with the gate electrodes (GE).

[0095] The conduction pattern (CP) of the line structure (LST) may include contact portions (CNP) that each fill the first contact holes (CNH1). The conduction pattern (CP) may be connected to the first source / drain region (SD1) through the contact portions (CNP). In other words, the bit line (BL) may be electrically connected to the first source / drain region (SD1) through the conduction pattern (CP).

[0096] A second mask pattern (MP2) on the boundary region (BR) can form a capping pattern (DML). The capping pattern (DML) can cover one end (EN) of the line structure (LST). While the bit line (BL) is being patterned, the capping pattern (DML) can prevent the bit line (BL) from being exposed to an oxide environment.

[0097] The second mask pattern (MP2) on the core region (COR) may have a plate shape that overlaps the core region (COR) entirely. That is, the second mask pattern (MP2) may cover the upper surface of the core gate structure (CGS).

[0098] A pair of spacers (SP) may be formed on both sidewalls of each of the capping pattern (DML) covering the line structure (LST) and one end (EN) of the same (see FIG. 14a and FIG. 14e). Forming the spacers (SP) may include conformally forming a spacer film on the front surface of the substrate (100) and anisotropically etching the spacer film.

[0099] Referring to FIGS. 15 and FIGS. 16a through 16e, an etching process may be performed on the front surface of a substrate (100) using spacers (SP) and mask patterns (MP) as a mask to form second contact holes (CNH2) that expose second source / drain regions (SD2), respectively. Specifically, the second contact holes (CNH2) may extend below the upper surface of the substrate (100) by penetrating the buffer film (IL). When the second contact holes (CNH2) are formed, the upper portion of the second source / drain region (SD2) may be recessed. When the second contact holes (CNH2) are formed, the upper portion of the device isolation film (ST) around the second source / drain region (SD2) may be recessed. Second contact holes (CNH2) may also be formed on both sides of the capping pattern (DML) on the boundary region (BR) (see FIG. 16e).

[0100] Multiple insulating fences (IFS) may be formed between adjacent line structures (LST). Insulating fences (IFS) may also be formed between adjacent capping patterns (DML). The insulating fences (IFS) may not overlap with the second contact holes (CNH2) and may expose them.

[0101] A conductive material can be filled into the second contact holes (CNH2) to form contacts (CNT) within each of the second contact holes (CNH2). The contacts (CNT) can be connected to the second source / drain regions (SD2). Specifically, after forming the conductive material on the front surface of the substrate (100), the conductive material can be recessed so that the upper surface of the conductive material is lower than the upper surfaces of the insulating fences (IFS). Thus, the conductive material is separated by the insulating fences (IFS) so that contacts (CNT) can be formed in each of the second contact holes (CNH2). Between adjacent line structures (LST), the contacts (CNT) and the insulating fences (IFS) can be arranged alternately along the first direction (D1).

[0102] The conductive material filling the second contact holes (CNH2) may be a doped semiconductor material. For example, the conductive material may include doped polysilicon. The second contact holes (CNH2) may be filled with a doped semiconductor, and impurities within the semiconductor may be diffused into the second source / drain regions (SD2). The diffusion of the impurities may utilize a metallurgical process.

[0103] The conductive material filled within the second contact hole (CNH2) on the boundary region (BR) can form a dummy contact (DCNT). The dummy contact (DCNT) may be a dummy that contacts the upper surface of the device isolation film (ST).

[0104] Referring again to FIGS. 2 and FIGS. 3a through 3e, landing pads (LP) can be formed on the contacts (CNT) of the cell region (CAR). Specifically, a metal film can be formed on the contacts (CNT) and insulating fences (IFS). A plurality of landing pads (LP) can be formed by patterning the metal film. An insulating pattern (INP) can be formed by filling the space between the plurality of landing pads (LP) with an insulating material.

[0105] Information storage elements (DS) may each be formed on landing pads (LP). Forming the information storage elements (DS) may include forming a lower electrode on the landing pad (LP), forming a dielectric film covering the lower electrode, and forming an upper electrode on the dielectric film. Although not illustrated, stacked wiring layers (e.g., M1, M2, M3, M4...) may be formed on the information storage elements (DS).

[0107] With reference to FIGS. 17 to 21 below, a method for forming a capping pattern (DML) on the boundary region (BR) shown in FIG. 14d will be explained in more detail.

[0108] Referring to FIG. 17, the result of FIG. 12d may be provided. Specifically, the edge of a plate structure (PLS) may be provided on the device isolation film (ST) of the boundary region (BR). For example, one end (EN) of the plate structure (PLS) may be located on the device isolation film (ST) of the boundary region (BR). The edge of a core gate structure (CGS) may be provided on the device isolation film (ST) of the core region (COR). Sidewall spacers (SPC) may be provided on the one end (EN) of the plate structure (PLS) and on the sidewall of the core gate structure (CGS), respectively.

[0109] Referring to FIG. 18, a first etching mask pattern (COP) can be formed that covers a core region (COR) and exposes a boundary region (BR) and a cell region (CAR). The first etching mask pattern (COP) can be formed using a photolithography process. The first etching mask pattern (COP) can cover a core gate structure (CGS). The first etching mask pattern (COP) can expose a plate structure (PLS).

[0110] A first etching process can be performed using a first etching mask pattern (COP) to remove the sidewall spacer (SPC) on the plate structure (PLS). While the sidewall spacer (SPC) is being removed, the upper portion of the device isolation film (ST) on the boundary region (BR) may be etched together. As the upper portion of the device isolation film (ST) is etched, a recess region (RS) may be formed. The bottom of the recess region (RS) may be lower than the upper surface (STt) of the device isolation film (ST) below the plate structure (PLS). Meanwhile, the plate structure (PLS) may be protected by the first mask pattern (MP1) and may not be etched during the first etching process.

[0111] In one embodiment of the present invention, the first etching process may include a wet etching process for selectively etching silicon oxide. As an example, the wet etching process may use a buffered hydrofluoric acid solution (BHF) or a hydrofluoric acid solution (HF). During the first etching process, a recess region (RS) formed on the upper surface of the device isolation film (ST) may be further extended horizontally to form an undercut region (UCR). The undercut region (UCR) may be vertically superimposed with the plate structure (PLS). The undercut region (UCR) may expose the bottom surface (ILb) of the buffer film (IL).

[0112] In another embodiment of the present invention, the first etching process may include a dry etching process. Specifically, the first etching mask pattern (COP) may be formed in a slit shape that covers the core region (COR) and the cell region (CAR) while exposing only the boundary region (BR). All exposed films can be anisotropically etched using the dry etching process with the first etching mask pattern (COP). As described above with reference to FIG. 5, the end (EN) of the line structure (LST) and the inner wall (RSw) of the recess region (RS) can be vertically aligned. When using the anisotropic etching process, all residues that interfere with the first etching process around the device isolation film (ST) of the boundary region (BR) can be cleanly removed.

[0113] Referring to FIG. 19, the first etching mask pattern (COP) can be optionally removed. A stopper film (STL) can be conformally formed on the front surface of the substrate (100). The stopper film (STL) can cover one end (EN) of the plate structure (PLS). The stopper film (STL) can cover the upper surface of the device isolation film (ST) on the boundary region (BR). The stopper film (STL) can cover the core gate structure (CGS) and the sidewall spacer (SPC).

[0114] The stopper membrane (STL) can partially fill the recess region (RS) and the undercut region (UCR). For example, the stopper membrane (STL) can cover the bottom surface (ILb) of the exposed buffer membrane (IL). In one embodiment, the stopper membrane (STL) may comprise a silicon nitride film.

[0115] An interlayer insulating layer (ILD) may be formed on a stopper film (STL). The interlayer insulating layer (ILD) may fill the space between the core gate structure (CGS) and the plate structure (PLS). A planarization process may be performed on the interlayer insulating layer (ILD) until the top surface of the stopper film (STL) is exposed.

[0116] Referring to FIG. 20, a second etching mask pattern (SOP) can be formed that covers the core region (COR) and the cell region (CAR) while exposing only the boundary region (BR). For example, the second etching mask pattern (SOP) can expose the interlayer insulating film (ILD) on the recess region (RS).

[0117] A second etching process can be performed using a second etching mask pattern (SOP) to remove the interlayer insulating film (ILD) exposed by the second etching mask pattern (SOP). The second etching process may include a wet etching process that selectively etches silicon oxide. This allows all of the interlayer insulating film (ILD) within the recess region (RS) and the undercut region (UCR) to be removed. Only the stopper film (STL) may remain within the recess region (RS) and the undercut region (UCR).

[0118] Through the second etching process above, a stopper film (STL) covering one end (EN) of the plate structure (PLS) can be exposed. The oxide film (e.g., interlayer insulating film (ILD)) on the stopper film (STL) can be completely removed.

[0119] Referring to FIG. 21, the second etching mask pattern (SOP) can be selectively removed. A second mask film (MAL) can be formed on the stopper film (STL). For example, the second mask film (MAL) may include a silicon nitride film.

[0120] The second mask film (MAL) can completely fill the recess area (RS) and the undercut area (UCR). The second mask film (MAL) filling the undercut area (UCR) can form the lower protrusion (LPP) described earlier with reference to FIG. 4.

[0121] Referring again to FIGS. 13, 14d, and 14e, a second mask film (MAL) can be patterned to form a second mask pattern (MP2). A plate structure (PLS) can be patterned using the second mask pattern (MP2) as an etching mask to form a plurality of line structures (LST).

[0122] As a comparative example of the present invention, as shown in FIG. 17, when a sidewall spacer (SPC) remains on one end (EN) of a plate structure (PLS), the second conductive film (CL2) may be exposed to an oxide environment caused by the sidewall spacer (SPC) while patterning the plate structure (PLS). If the second conductive film (CL2) is exposed to an oxide environment while patterning, a process defect may occur in which the line width of the bit line (BL) becomes thin and the bit line (BL) cannot be extended to the boundary region (BR).

[0123] On the other hand, according to an embodiment of the present invention, the second mask film (MAL) and the stopper film (STL) corresponding to the capping pattern (DML) both comprise a silicon nitride film, and a separate oxide may not be formed around one end (EN) of the plate structure (PLS). Since the second mask film (MAL) and the stopper film (STL) completely cap one end (EN) of the plate structure (PLS), the second conductive film (CL2) can be prevented from being exposed to an oxide environment while patterning. Thus, the linewidth of the bit line (BL) can be prevented from becoming thin, and the bit line (BL) can be sufficiently extended to the boundary region (BR). Consequently, according to the present invention, the reliability of the semiconductor device can be improved.

[0125] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing its technical concept or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive.

Claims

Claim 1 A substrate comprising a cell region, a core region, and a boundary region between the cell region and the core region, wherein the cell region comprises a first active pattern and the core region comprises a second active pattern; a device isolation layer on the boundary region, wherein the device isolation layer fills a trench between the first active pattern and the second active pattern; and a line structure provided on the first active pattern and extending from the cell region to the boundary region. A semiconductor device comprising a capping pattern covering one end of the line structure on the boundary region, wherein the device isolation film includes a recess region formed adjacent to the one end of the line structure, the capping pattern extends along the one end of the line structure to the recess region, the bottom surface of the capping pattern is lower than the top surface of the device isolation film below the line structure, the capping pattern includes a stopper pattern and a mask pattern, the stopper pattern extends from the line structure through the device isolation film to the core region, the recess region includes a horizontally extended undercut region, and the stopper pattern extends below the bottom surface of the line structure within the undercut region. Claim 2 A semiconductor device according to claim 1, wherein the capping pattern includes a lower protrusion that fills the undercut region, and the lower protrusion is located below the line structure and vertically overlaps with at least a portion of the line structure. Claim 3 A semiconductor device according to claim 1, further comprising: a gate electrode provided within a groove above the first active pattern, wherein the gate electrode is interposed between a first source / drain region and a second source / drain region of the first active pattern; a contact on the second source / drain region; and an information storage element on the contact, wherein the first source / drain region is electrically connected to the line structure. Claim 4 In paragraph 3, the information storage element is a semiconductor device including a capacitor. Claim 5 A semiconductor device according to paragraph 3, further comprising a dummy contact provided on one side of the capping pattern. Claim 6 A semiconductor device according to claim 1, wherein the line structure extends in a first direction, the capping pattern extends in the first direction, and the capping pattern is aligned with the line structure in the first direction. Claim 7 A semiconductor device according to claim 1, further comprising: a core gate structure provided on the second active pattern; and a sidewall spacer provided on the boundary region and covering the sidewall of the core gate structure, wherein one end of the line structure is directly covered by the capping pattern instead of the sidewall spacer. Claim 8 In claim 7, the stopper pattern and the mask pattern are a semiconductor device extending from the line structure through the device isolation layer to the core gate structure. Claim 9 In claim 8, the stopper pattern and the mask pattern are a semiconductor device comprising silicon nitride. Claim 10 In claim 1, the line structure comprises a semiconductor device including a conductive pattern, a barrier pattern, and a bit line sequentially stacked on a buffer film of the cell region. Claim 11 A semiconductor device comprising a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, wherein the cell region includes a first active pattern and the core region includes a second active pattern; a device isolation layer on the boundary region, wherein the device isolation layer fills a trench between the first active pattern and the second active pattern; a line structure provided on the first active pattern and extending from the cell region to the boundary region; a core gate structure provided on the second active pattern; a sidewall spacer provided on the boundary region and covering a sidewall of the core gate structure; and a capping pattern provided on the boundary region and covering one end of the line structure, wherein the capping pattern comprises a material different from the sidewall spacer, wherein the capping pattern comprises a stopper pattern and a mask pattern, wherein the stopper pattern extends from the line structure through the device isolation layer to the core gate structure, and the bottom surface of the stopper pattern extends below the bottom surface of the line structure. Claim 12 A semiconductor device according to claim 11, wherein the sidewall spacer comprises silicon oxide and the capping pattern comprises silicon nitride. Claim 13 In claim 11, the bottom surface of the capping pattern is lower than the upper surface of the device isolation film below the line structure, for a semiconductor device. Claim 14 In claim 13, the capping pattern includes a lower protrusion extending downward from the line structure, and the lower protrusion is a semiconductor device that vertically overlaps with at least a portion of the line structure. Claim 15 In claim 11, the one end of the line structure is a semiconductor device that is capped by the capping pattern instead of the sidewall spacer. Claim 16 A substrate comprising a cell region, a core region, and a boundary region between the cell region and the core region, wherein the cell region comprises a first active pattern and the core region comprises a second active pattern, wherein the first active pattern has a major axis in a first direction and the first active pattern comprises a first source / drain region and a second source / drain region spaced apart from each other in the first direction; a gate electrode provided within a groove between the first and second source / drain regions of the first active pattern, wherein the gate electrode extends in a second direction; a gate dielectric film interposed between the gate electrode and the first active pattern; a gate capping film provided on the gate electrode to fill the groove; a device isolation film provided on the substrate to define the first active pattern and the second active pattern; a buffer film on the cell region; a line structure extending in a third direction that crosses the first active pattern and intersects the second direction on the buffer film, wherein the line structure extends from the cell region to the boundary region, and the line structure penetrates the buffer film and A first conductive pattern connected to a first source / drain region, a bit line on the first conductive pattern, and a first barrier pattern between the bit line and the first conductive pattern; a pair of spacers each provided on both sidewalls of the line structure; a contact connected to a second source / drain region; a landing pad on the contact; an information storage element on the landing pad; a core gate structure on the second active pattern, wherein the core gate structure includes a second conductive pattern corresponding to the first conductive pattern, a second barrier pattern corresponding to the first barrier pattern, and a core gate electrode corresponding to the bit line; and a sidewall spacer on the sidewall of the core gate structure;A semiconductor device comprising a capping pattern covering one end of the line structure on the boundary region, wherein the capping pattern includes a stopper pattern and a mask pattern, the stopper pattern extends from the line structure through the device isolation layer to the core gate structure, and the lowest surface of the stopper pattern extends below the bottom surface of the line structure. Claim 17 In claim 16, the above pair of spacers is a semiconductor device extending from the two side walls of the line structure onto the two side walls of the capping pattern. Claim 18 In claim 16, the above capping pattern is a semiconductor device comprising a sidewall spacer and a different material. Claim 19 In claim 16, the bottom surface of the capping pattern is lower than the upper surface of the device isolation film below the line structure, in a semiconductor device. Claim 20 In paragraph 16, the information storage element is a semiconductor device including a capacitor.

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