Semiconductor device and data storage system including the same

Abstract

A semiconductor device and a data storage system including the same are provided. The semiconductor device comprises: a first structure; a second structure comprising a stacking structure including at least three gate stacking groups stacked vertically on the first structure and an insulating structure covering at least a portion of the stacking structure; a memory vertical structure penetrating at least the stacking structure; and a separation structure penetrating at least the stacking structure and having an upper surface at a level higher than the upper surface of the memory vertical structure. Each of the gate stacking groups includes gate layers stacked spaced apart from each other in the vertical direction, and at a height level between the lowest gate layer and the highest gate layer among the gate layers of the stacking structure, the side of the memory vertical structure includes "N" memory side slope change portions, and the side of the separation structure includes "M" separation side slope change portions located at the same height level as "M" memory side slope change portions smaller than "N" among the "N" memory side slope change portions, wherein "N" is a natural number greater than 2 or greater than 2, and "M" is a natural number greater than 1.

Description

Technology Field

[0001] The present invention relates to a semiconductor device and a data system including the same. Background Technology

[0003] In electronic systems requiring data storage, there is a demand for semiconductor devices capable of storing high-capacity data. Accordingly, methods to increase the data storage capacity of semiconductor devices are being studied. For example, as one method to increase the data storage capacity of semiconductor devices, a semiconductor device including memory cells arranged in three dimensions instead of memory cells arranged in two dimensions is being proposed. The problem to be solved

[0005] One of the technical problems that the technical concept of the present invention aims to solve is to provide a semiconductor device capable of improving integration density and reliability.

[0006] One of the technical problems that the technical concept of the present invention aims to solve is to provide a data storage system including a semiconductor device. means of solving the problem

[0008] A semiconductor device according to one embodiment of the technical concept of the present invention is provided. The semiconductor device comprises: a first structure; a second structure comprising a stacked structure including at least three gate stacking groups stacked in a vertical direction on the first structure and an insulating structure covering at least a portion of the stacked structure; a memory vertical structure penetrating at least the stacked structure; and a separation structure penetrating at least the stacked structure. Each of the gate stacking groups comprises gate layers stacked spaced apart from each other in the vertical direction, and at a height level between the lowest gate layer and the highest gate layer among the gate layers of the stacked structure, the side of the memory vertical structure comprises "N" memory side slope change portions, and the side of the separation structure comprises "M" separation side slope change portions located at substantially the same height level as "M" memory side slope change portions smaller than "N" among the "N" memory side slope change portions, wherein "N" is 2 or a natural number greater than 2, and "M" is 1 or a natural number greater than 1.

[0009] A semiconductor device according to one embodiment of the technical concept of the present invention is provided. The semiconductor device comprises: a lower structure; a stacked structure comprising at least three gate stacked groups stacked vertically on the first structure and an insulating structure covering at least a portion of the stacked structure; a memory vertical structure penetrating at least the stacked structure; peripheral contact plugs; gate contact plugs; and a separation structure penetrating at least the stacked structure and having a line shape in a plane. Each of the above gate stacking groups includes gate layers that are stacked spaced apart from each other in the vertical direction, and at a height level between the lowest gate layer and the highest gate layer among the gate layers of the stacking structure, each side of the memory vertical structure and the side of the peripheral contact plug include "N" first slope change portions, and the side of the separation structure includes "M" second slope change portions located at substantially the same height level as "M" first slope change portions that are smaller than "N" among the "N" first slope change portions, and "N" and "M" are different natural numbers, and at a level higher than the highest gate layer, the side of the memory vertical structure, the side of the peripheral contact plug, the side of the separation structure and the side of each of the gate contact plugs include a first upper slope change portion disposed at substantially the same height level, and at a height level identical to the first slope change portion located at the lowest of the "N" first slope change portions, the side of the separation structure is substantially vertical.

[0010] A data storage system according to one embodiment of the technical concept of the present invention is provided. The system includes a main board; a semiconductor device on the main board; and a controller electrically connected to the semiconductor device on the main board. The semiconductor device includes: a lower structure; a stacked structure comprising at least three gate stacking groups stacked vertically on the first structure and an insulating structure covering at least a portion of the stacked structure; a memory vertical structure penetrating at least the stacked structure; peripheral contact plugs; gate contact plugs; and a separation structure penetrating at least the stacked structure and having a line shape in a plane. Each of the above gate stacking groups includes gate layers that are stacked spaced apart from each other in the vertical direction, and at a height level between the lowest gate layer and the highest gate layer among the gate layers of the stacking structure, each side of the memory vertical structure and the side of the peripheral contact plug include "N" first slope change portions, and the side of the separation structure includes "M" second slope change portions located at substantially the same height level as "M" first slope change portions that are smaller than "N" among the "N" first slope change portions, and "N" and "M" are different natural numbers, and at a level higher than the highest gate layer, the side of the memory vertical structure, the side of the peripheral contact plug, the side of the separation structure and the side of each of the gate contact plugs include a first upper slope change portion disposed at substantially the same height level, and at a height level identical to the first slope change portion located at the lowest of the "N" first slope change portions, the side of the separation structure is substantially vertical. Effects of the invention

[0012] According to embodiments of the technical concept of the present invention, since gate layers can be formed by stacking them in a vertical direction, the integration density of a semiconductor device can be improved. Accordingly, a semiconductor device capable of improving integration density and a data storage system including the same can be provided.

[0013] According to embodiments of the technical concept of the present invention, a method is provided to simultaneously perform some semiconductor processes for forming the memory vertical structure, the support vertical structure, the gate contact plugs, the peripheral contact plugs, and the separation structure while increasing the number of gate layers stacked in the vertical direction. Accordingly, productivity can be improved while increasing the integration density of the semiconductor device.

[0014] The various and beneficial advantages and effects of the present invention are not limited to those described above and will be more easily understood in the process of explaining specific embodiments of the present invention. Brief explanation of the drawing

[0016] FIG. 1 is a schematic perspective view showing a semiconductor device according to embodiments of the present invention. FIGS. 2a and 2b are schematic cross-sectional views showing a semiconductor device according to one embodiment of the present invention. FIGS. 3a to 3c are schematic partial enlarged views of a portion of a semiconductor device according to one embodiment of the present invention. FIGS. 4a and FIGS. 4b are schematic cross-sectional views showing a semiconductor device according to a modified embodiment of the present invention. FIGS. 5a and 5b are schematic partial enlarged views of a portion of a semiconductor device according to a modified embodiment of the present invention. FIGS. 6 and FIGS. 7 are schematic drawings showing a semiconductor device according to a modified embodiment of the present invention. FIG. 8 is a schematic cross-sectional view showing a semiconductor device according to a modified embodiment of the present invention. FIGS. 9a and 9b are process flow diagrams illustrating exemplary examples of a method for forming a semiconductor device according to one embodiment of the present invention. FIGS. 10a, FIGS. 10b, FIGS. 11a, and FIGS. 11b are cross-sectional views illustrating exemplary examples of a method for forming a semiconductor device according to an embodiment of the present invention. FIG. 12 is a schematic diagram showing a data storage system including a semiconductor device according to an exemplary embodiment of the present invention. FIG. 13 is a schematic perspective view of a data storage system including a semiconductor device according to an exemplary embodiment of the present invention. FIG. 14 is a cross-sectional view schematically illustrating a data storage system including a semiconductor device according to an exemplary embodiment of the present invention. Specific details for implementing the invention

[0017] Hereinafter, embodiments of the present invention will be described as follows with reference to the attached drawings.

[0018] A semiconductor device according to embodiments of the present invention will be described with reference to FIG. 1. FIG. 1 is a schematic perspective view showing a semiconductor device according to embodiments of the present invention.

[0019] Referring to FIG. 1, a semiconductor device (1) may include a first structure (LS) and a second structure (US) on the first structure (LS). The second structure (US) may include a plurality of memory structures (M1, M2). Although the number of the plurality of memory structures (M1, M2) is shown as two in FIG. 1, embodiments are not limited thereto and may be more than two. Each of the plurality of memory structures (M1, M2) may include separation structures (87), first regions (MCA) disposed between the separation structures (87), and second regions (SA) disposed on at least one side of the first regions (MCA).

[0020] The first regions (MCA) may be memory cell array regions or memory cell regions, and the second regions (SA) may be step regions.

[0021] Among the first regions (MCAs), the first region, i.e., the memory cell array region, disposed between a pair of separated structures (87) that are spaced apart from each other and parallel, can be defined as a memory block. Each of the plurality of memory structures (M1, M2) may further include a through region (TA) disposed between a pair of first regions among the first regions (MCAs). The semiconductor device (1) may further include peripheral contact plugs (111). At least some of the peripheral contact plugs (111) may penetrate the through region (TA).

[0022] Hereinafter, an exemplary example of the semiconductor device (1) will be described with reference to FIGS. 2a and FIG. 2b. FIG. 2a is a schematic cross-sectional view showing an area taken along the line I-I' of FIG. 1, and FIG. 2b is a schematic cross-sectional view showing an area taken along the line II-II' of FIG. 1.

[0023] Referring to FIG. 1, FIG. 2a, and FIG. 2b, the first structure (LS) of the semiconductor device (1) may include a pattern structure (23). The pattern structure (23) may include at least one silicon layer.

[0024] The pattern structure (23) may include a lower pattern layer (23a), a first intermediate pattern layer (23b1), a second intermediate pattern layer (23b2), and an upper pattern layer (23c). The first intermediate pattern layer (23b1) and the second intermediate pattern layer (23b2) may be spaced apart from each other on the first pattern layer (23a). The upper pattern layer (23c) may cover the first intermediate pattern layer (23b1) and the second intermediate pattern layer (23b2) on the first pattern layer (23a). The first pattern layer (23a) may have a thickness greater than the thickness of each of the first intermediate pattern layer (23b1), the second intermediate pattern layer (23b2), and the upper pattern layer (23c). At least one of the first pattern layer (23a), the first intermediate pattern layer (23b1), the second intermediate pattern layer (23b2), and the upper pattern layer (23c) may include a silicon layer. For example, the first pattern layer (23a), the first intermediate pattern layer (23b1), and the upper pattern layer (23c) may include a silicon layer, for example, a silicon layer having an N-type conductivity, and the second intermediate pattern layer (23b2) may include a material other than the silicon layer. For example, the second intermediate pattern layer (23b2) may include a plurality of layers stacked in sequence, for example, a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer stacked in sequence.

[0025] The first structure (LS) may further include a semiconductor substrate (5), peripheral circuits (9, 13) on the semiconductor substrate (5), peripheral pads (15) electrically connected to the peripheral circuits (9, 13), and a lower insulating structure (21) covering the peripheral circuits (9, 13) and the peripheral pads (15) on the semiconductor substrate (5). The peripheral circuits (9, 13) may include circuit elements (9), such as a transistor, comprising a peripheral gate (9a) disposed on an active region (7a) defined by a device isolation film (7s) within the semiconductor substrate (5), and peripheral source / drain (9b) disposed within the active region (7a) on both sides of the peripheral gate (9a), and circuit wiring (13) electrically connected to the circuit elements (9).

[0026] The first structure (LS) may further include a capping layer (17) formed on each of the surrounding pads (15) and an etch stop layer (19) formed on the capping layer (17). In an exemplary example, the capping layer (17) may be formed of a silicon layer, and the etch stop layer (19) may be formed of an insulating material, for example, silicon oxide or silicon nitride.

[0027] The above pattern structure (23) may be placed on the lower insulation structure (21). The peripheral pads (15) may include a ground pad (15g), a first peripheral pad (15a), a second peripheral pad (15b), and a third peripheral pad (15c).

[0028] In one example, a portion of the first pattern layer (23a) of the pattern structure (23) may extend downward and be electrically connected to the ground pad (15g). The ground pad (15g) may be grounded to the ground region (11) of the semiconductor substrate (5) through the circuit wiring (13).

[0029] The first structure (LS) may include an outer insulating layer (26o) disposed on the outside of the pattern structure (23), a first inner insulating layer (26i_1) penetrating the pattern structure (23), and second inner insulating layers (26i_2) penetrating the pattern structure (23).

[0030] In one example, the first inner insulating layer (26i_1) may be in a line shape in a plane. Each of the second inner insulating layers (26i_2) may be in a circular, elliptical, or polygonal shape.

[0031] The second structure (US) of the semiconductor device (1) may include a further stacked structure (GS) disposed within the first region (MCA) and extending from the first region (MCA) into the second region (SA). The stacked structure (GS) may include at least three stacked groups (GR1, GR2, GR3) stacked in the vertical direction (Z). For example, the stacked structure (GS) may include a lower stacked group (GR1), an intermediate stacked group (GR2) on the lower stacked group (GR1), and an upper stacked group (GR3) on the intermediate stacked group (GR2). The lower stacking group (GR1) may include alternately stacked lower interlayer insulating layers (32a) and lower gate layers (32g), the intermediate stacking group (GR2) may include alternately stacked intermediate interlayer insulating layers (44a) and intermediate gate layers (44g), and the upper stacking group (GR3) may include alternately stacked upper interlayer insulating layers (58a) and upper gate layers (58g).

[0032] In the embodiments, the lower gate layers (32g) stacked spaced apart from each other in the vertical direction (Z) may be defined as a lower gate stacking group, the intermediate gate layers (44g) stacked spaced apart from each other in the vertical direction (Z) may be defined as an intermediate gate stacking group, and the upper gate layers (55g) stacked spaced apart from each other in the vertical direction (Z) may be defined as an upper gate stacking group.

[0033] The lower, middle, and upper gate layers (32g, 44g, 58g) may include gate pads (GP) arranged in a stepped shape within the second region (SA). The gate pads (GP) are not limited to the stepped shape shown in FIG. 2a and may be arranged in various stepped shapes.

[0034] The thickness of each of the above gate pads (GP) may be greater than the thickness of each of the lower, middle, and upper gate layers (32g, 44g, 58g) in regions other than the gate pads (GP).

[0035] The second structure (US) may further include an intermediate insulating structure (36, 48, 62) covering at least a portion of the stacked structure (GS). The intermediate insulating structure (36, 48, 62) may include a first intermediate insulating layer (36) covering the gate pads (GP) of the lower gate layers (32g) on ​​the lower structure (LS), a second intermediate insulating layer (48) covering the gate pads (GP) of the intermediate gate layers (44g) on ​​the first intermediate insulating layer (36), and a third intermediate insulating layer (62) covering the gate pads (GP) of the upper gate layers (58g) on ​​the second intermediate insulating layer (48).

[0036] The second structure (US) may further include an upper insulating structure (68, 84, 90, 116) on the laminated structure (GS) and the intermediate insulating structure (36, 48, 62). The intermediate insulating structure (36, 48, 62) and the upper insulating structure (68, 84, 90, 116) may constitute an insulating structure.

[0037] The upper insulating structure (68, 84, 90, 116) may include a first upper insulating layer (68), a second upper insulating layer (84), a third upper insulating layer (90), and a fourth upper insulating layer (116) stacked in order.

[0038] The semiconductor device (1) may further include a memory vertical structure (71) that penetrates at least the stacked structure (GS) within the first region (MCA). A plurality of memory vertical structures (71) may be arranged. The memory vertical structure (71) may extend downward from the portion penetrating the stacked structure (GS) and extend into the pattern structure (23). For example, the memory vertical structure (71) may penetrate the upper pattern layer (23c) and the first intermediate pattern layer (23b1) in sequence and extend into the lower pattern layer (23a) to come into contact with the lower pattern layer (23a). The memory vertical structure (71) may extend upward from the portion penetrating the stacked structure (GS) and penetrate the first upper insulating layer (68). The upper surface of the memory vertical structure (71) may form a co-surface with the upper surface of the first upper insulating layer (68).

[0039] The semiconductor device (1) may further include a support vertical structure (81) that penetrates at least the stacked structure (GS) within the second region (SA). A plurality of the support vertical structures (81) may be arranged. The support vertical structures (81) may extend into the pattern structure (23). For example, the support vertical structures (81) may penetrate the upper pattern layer (23c) and the second intermediate pattern layer (23b2) in sequence and extend into the lower pattern layer (23a) to come into contact with the lower pattern layer (23a). The support vertical structures (81) may extend upward from the portion penetrating the stacked structure (GS) to penetrate the first upper insulating layer (68). The upper surface of the support vertical structures (81) may form a co-surface with the upper surface of the first upper insulating layer (68).

[0040] The separation structure (87) described in FIG. 1 may penetrate at least the stacked structure (GS). The separation structure (87) may extend downward from the portion penetrating the stacked structure (GS) to come into contact with the lower pattern layer (23a) of the pattern structure (23). The separation structure (87) may extend upward from the portion penetrating the stacked structure (GS) to penetrate the first and second upper insulating layers (68, 84). The upper surface of the separation structure (87) may form a co-surface with the upper surface of the second upper insulating layer (84).

[0041] The through-region (TA) described in FIG. 1 may be disposed on the first inner insulating layer (26i_1). The through-region (TA) may include lower, middle, and upper horizontal insulating layers (32d, 44d, 58d) located at substantially the same height level as the lower, middle, and upper gate layers (32g, 44g, 58g). Within the through-region (TA), the lower, middle, and upper interlayer insulating layers (32a, 44a, 58a) and the lower, middle, and upper horizontal insulating layers (32d, 44d, 58d) may be alternately and repeatedly stacked. The lower, middle, and upper horizontal insulating layers (32d, 44d, 58d) may be formed of silicon nitride, and the lower, middle, and upper interlayer insulating layers (32a, 44a, 58a) may be formed of silicon oxide.

[0042] The above peripheral contact plugs (111) can penetrate at least a portion of the second structure (US). The peripheral contact plugs (111) may include a first peripheral contact plug (111a), a second peripheral contact plug (111b), and a third peripheral contact plug (111c).

[0043] The first peripheral contact plug (111a) is spaced apart from the laminated structure (GS), penetrates the intermediate insulating structure (36, 48, 62), the outer insulating layer (26o), and the first, second, and third upper insulating layers (68, 84, 90), and can come into contact with the first peripheral pad (15a). The upper surface of the first peripheral contact plug (111a) can form a co-surface with the upper surface of the third upper insulating layer (90).

[0044] The second peripheral contact plug (111b) penetrates the lower, middle, and upper interlayer insulation layers (32a, 44a, 58a) and the lower, middle, and upper horizontal insulation layers (32d, 44d, 58d) within the penetration area (TA), penetrates the first inner insulation layer (26i_1) and the first, second, and third upper insulation layers (68, 84, 90), and can come into contact with the second peripheral pad (15b). The upper surface of the second peripheral contact plug (111b) may form a co-surface with the upper surface of the third upper insulation layer (90).

[0045] The third peripheral contact plug (111c) is spaced apart from the laminated structure (GS), penetrates the intermediate insulating structure (36, 48, 62) and the first, second, and third upper insulating layers (68, 84, 90), and can come into contact with the lower pattern layer (23a). The upper surface of the third peripheral contact plug (111c) can form a co-surface with the upper surface of the third upper insulating layer (90).

[0046] The lower surface of the above peripheral contact plugs (111) may be positioned at a lower level than the lower surface of the memory vertical structure (71), and the upper surface of the above peripheral contact plugs (111) may be positioned at a higher level than the upper surface of the memory vertical structure (71).

[0047] The semiconductor device (1) may further include gate contact plugs (106) that penetrate at least a portion of the second structure and are electrically connected to each of the gate layers (32g, 44g, 58g). Each of the gate contact plugs (106) may have a lower surface at a level lower than the lowest gate layer (32g_L) among the gate layers (32g, 44g, 58g) and an upper surface at a level higher than the uppermost gate layer (58g_U) among the gate layers (32g, 44g, 58g).

[0048] The gate contact plugs (106) may each contact the gate pads (GP). The gate contact plugs (106) may each contact the gate pads (GP) in a manner that penetrates the gate pads (GP). For example, one gate contact plug (106) may be electrically connected to one gate pad (GP) by penetrating it. Buffer insulation layers (103) may be disposed between the gate layers located at a lower level than the gate pads (GP) and the gate contact plugs (106). For example, when viewed with respect to one gate pad (GP) and the gate contact plug (106) in contact with each other, the buffer insulation layers (103) may be disposed between the gate layers at a lower level than the gate pad (GP) and the gate contact plug (106). The buffer insulation layers (103) may be formed of silicon oxide.

[0049] The gate contact plugs (106) may have a lower surface at a level lower than the lowest gate layer (38g_L) and an upper surface at a level higher than the upper gate layer (58g_U). The lower surface of the gate contact plugs (106) may be positioned at a level lower than the lower surface of the memory vertical structure (71), and the upper surface of the gate contact plugs (106) may be positioned at a level higher than the upper surface of the memory vertical structure (71).

[0050] The semiconductor device (1) may further include a bitline contact plug (119) electrically connected to the memory vertical structure (71) penetrating the upper insulating structure (68, 84, 90, 116), and upper contact plugs (120) penetrating the fourth upper insulating layer (116) and electrically connected to the surrounding contact plugs (111) respectively.

[0051] The semiconductor device (1) may further include a bit line (123) electrically connected to the memory vertical structure (71) through the bit line contact plug (119) on the fourth upper insulating layer (116), and peripheral wiring (124) electrically connected to the first and third peripheral contact plugs (111a, 111c), respectively, through the upper contact plugs (120). The second peripheral contact plug (111b) may be electrically connected to the bit line (123) through either of the upper contact plugs (120).

[0053] Hereinafter, with reference to FIG. 3a, the memory vertical structure (71) and the separation structure (87) described above will be explained in detail. FIG. 3a is a partial enlarged view of the area marked "A" in FIG. 2b.

[0054] Referring to FIG. 3a together with FIG. 1 to 2b, in one embodiment, at a height level between the lowest gate layer (32g_L) and the highest gate layer (58g_U), the side of the memory vertical structure (71) may include "N" memory side slope change portions (71s_1a, 71s_1b). The side of the separation structure (87) may include "M" separation side slope change portions (87s_1) located at substantially the same height level as "M" slope change portions (71s_1b) which are smaller than "N" among the "N" memory side slope change portions (71s_1a, 71s_1b).

[0055] The above "N" may be 2 or a natural number greater than 2, and the above "M" may be a natural number smaller than "N," for example, 1 or a natural number greater than 1. For example, the above "M" may be "N-1". For example, the above "N" may be 2 and the above "M" may be 1.

[0056] The above "M" separated side slope change sections (87s_1) can be placed at substantially the same height level as the memory side slope change section (71s_1b) which is located at a higher level than the lowest memory side slope change section (71s_1a) among the "N" memory side slope change sections (71s_1a, 71s_1b).

[0057] At a level higher than the uppermost gate layer (58g_U), the memory vertical structure (71) may include at least one upper side slope change portion (71s_2).

[0058] At a level higher than the uppermost gate layer (58g_U), the separation structure (87) may include at least one upper side slope change portion (87s_2). The upper side slope change portion (71s_2) of the memory vertical structure (71) and the upper side slope change portion (87s_2) of the separation structure (87) may be positioned at substantially the same height level.

[0059] In the embodiments, the "slope change portion" may be defined as a side portion having a third slope between the upper side portion of the first slope and the lower side portion of the second slope. Here, the third slope may be a gentler slope than each of the first slope and the second slope. Each of the first slope and the second slope may be a vertical or near-vertical slope. Each of the first slope and the second slope may be described as a steep slope, and the third slope may be described as a gentle slope. For example, the side of the memory vertical structure (71) may include a lower side portion (71sa) having a steep slope, a first middle side portion (71sb) having a steep slope on the lower side portion (71sa), a first memory side slope change portion (71s_1a) having a gentle slope between the lower side portion (71sa) and the first middle side portion (71sb), a second middle side portion (71sc) having a steep slope on the first middle side portion (71sb), a second memory side slope change portion (71s_1b) having a gentle slope between the first middle side portion (71sb) and the second middle side portion (71sc), an upper side portion (71sd) having a steep slope on the second middle side portion (71sc), and an upper side slope change portion (71s_2) having a gentle slope between the second middle side portion (71sc) and the upper side portion (71sd). Here, "steep slope" and "gentle slope" are terms indicating relative inclination, and steep slopes in different side sections may have different slopes, and gentle slopes in different slope change sections may have different slopes.

[0060] The side of the above-mentioned separation structure (87) may include a lower side portion (87sa) having a steep slope, an intermediate side portion (87sb) on the lower side portion (87sa), a separation side slope change portion (87s_1) having a slope gentler than the slope of the lower side portion (87sa) and the slope of the intermediate side portion (87sb) between the lower side portion (87sa) and the intermediate side portion (87sb), an upper side portion (87sc) on the intermediate side portion (87sb), and an upper slope change portion (87s_2) having a slope gentler than the slope of the intermediate side portion (87sb) and the slope of the upper side portion (87sc) between the intermediate side portion (87sb) and the upper side portion (87sc).

[0061] Therefore, even without separate explanation below, the "side slope change section" or "slope change section" can be understood as a section having a gentle slope between the steep slope of the upper side part located above the side slope change section and the steep slope of the lower side part located below the side slope change section.

[0062] In the embodiments, regarding "memory side slope change sections" and "separated side slope change sections," "memory side" and "separated side" are used to distinguish and describe the slope change sections of different components and may be replaced with other terms. For example, "memory side slope change sections" and "separated side slope change sections" may be described by being replaced with "first slope change sections" and "second slope change sections," respectively, or by being described by being replaced with "first side slope change sections" and "second side slope change sections," respectively.

[0063] At a height level between the lowest gate layer (32g_L) and the uppermost gate layer (58g_U), the "N" memory side slope change portions (71s_1a, 71s_1b) of the memory vertical structure (71) may be positioned between the gate stacking groups adjacent to each other in the vertical direction. For example, among the "N" memory side slope change portions (71s_1a, 71s_1b), the first memory side slope change portion (71s_1a) may be positioned at a height level between the lower gate stacking group including the lower gate layers (33g) and the intermediate gate stacking group including the intermediate gate layers (44g), and the second memory side slope change portion (71s_1b) may be positioned at a height level between the intermediate gate stacking group including the intermediate gate layers (44g) and the upper gate stacking group including the upper gate layers (58g).

[0064] At the same height level as the lowest memory side slope change part (71s_1a) among the above "N" memory side slope change parts (71s_1a, 71s_1b), the side of the separation structure (57) can be substantially vertical.

[0065] Each of the lower, middle, and upper gate layers (32g, 44g, 58g) may include a first layer (31a) and a second layer (31b). The first layer (31a) may cover the upper and lower surfaces of the second layer (31b) and extend between the memory vertical structure (71) and the second layer (31b).

[0066] In an exemplary example, the first layer (31a) may include a dielectric material, and the second layer (31b) may include a conductive material. For example, the first layer (31a) may include a high-k dielectric such as AlO, and the second layer (31b) may include a conductive material such as TiN, WN, Ti, or W.

[0067] In another example, the first layer (31a) may include a first conductive material (e.g., TiN or W, etc.), and the second layer (31b) may include a second conductive material different from the first conductive material (e.g., Ti or W, etc.).

[0068] In another example, each of the lower, middle, and upper gate layers (32g, 44g, 58g) may be formed of doft polysilicon, a metal-semiconductor compound (e.g., TiSi, TaSi, CoSi, NiSi, or WSi), a metal nitride (e.g., TiN, TaN, or WN), or a metal (e.g., Ti or W).

[0069] The memory vertical structure (71) may include a gap-fill insulating layer (73), a channel material layer (75) covering the outer surface and bottom surface of the gap-fill insulating layer (73), an information storage structure (72) covering the outer surface and bottom surface of the channel material layer (73), and a pad pattern (79) on the gap-fill insulating layer (73).

[0070] The information storage structure (72) may include a first dielectric layer (72b) covering the outer surface and bottom surface of the channel material layer (75), an information storage material layer (72d) covering the outer surface and bottom surface of the first dielectric layer (72b), and a second dielectric layer (72a) covering the outer surface and bottom surface of the information storage material layer (72d). The first dielectric layer (72b) may be in contact with the channel material layer (73), and the information storage material layer (72d) may be spaced apart from the channel material layer (73).

[0071] The gap-fill insulating layer (73) may include silicon oxide, for example, ALD silicon oxide that can be formed by an atomic layer deposition process, or silicon oxide with voids formed inside.

[0072] The first dielectric layer (72b) may comprise silicon oxide or silicon oxide doped with impurities. The second dielectric layer (72a) may comprise at least one of silicon oxide and a high dielectric. The information storage material layer (72d) may comprise a material capable of trapping charge, for example, silicon nitride.

[0073] The information storage material layer (72d) of the information storage structure (72) of the memory vertical structure (71) may include regions capable of storing information in a semiconductor device such as a flash memory device. The channel material layer (73) may include polysilicon. The pad pattern (79) may include at least one of doft polysilicon, metal nitride (e.g., TiN, etc.), metal (e.g., W, etc.), and metal-semiconductor compound (e.g., TiSi, etc.).

[0074] Among the above pattern structures (23), the first intermediate pattern layer (23b1) penetrates the information storage structure (72) of the memory vertical structure (71) and can come into contact with the channel material layer (73).

[0075] The bitline contact plug (119) may include a plug pattern (118b) and a conductive liner (118a) covering the side and bottom surfaces of the plug pattern (118b).

[0077] Next, with reference to FIG. 3b, the above-described peripheral contact plugs (111) will be described in detail. FIG. 3b is a partial enlarged view of the areas marked "B1" in FIG. 2b and "B2" in FIG. 2a. Below, the description will focus on one of the first and second peripheral contact plugs (111a, 111b) and the peripheral contact plug (111).

[0078] Referring to FIG. 3b together with FIG. 1 to 3a, at a height level between the lowest gate layer (33g_L) and the uppermost gate layer (58g_U), the side of the peripheral contact plug (111), like the side of the memory vertical structure (71), may include "N" peripheral contact side slope change portions (111s_1a, 111s_1b) positioned at substantially the same height level as the "N" memory side slope change portions (71s_1a, 71s_1b). At a level higher than the uppermost gate layer (58g_U), the peripheral contact plug (111) may include at least one upper side slope change portion (111s_2). The upper side slope change portion (71s_2) of the memory vertical structure (71) and the upper side slope change portion (111s_2) of the peripheral contact plug (111) can be positioned at substantially the same height level.

[0079] For example, the side of the peripheral contact plug (111) comprises a lower side portion (111sa), a first intermediate side portion (111sb) on the lower side portion (111sa), a first peripheral contact side slope change portion (111s_1a) having a slope gentler than the slope of the lower side portion (11sa) and the slope of the first intermediate side portion (111sb) between the lower side portion (11sa) and the first intermediate side portion (111sb), a second intermediate side portion (111sc) on the first intermediate side portion (11sb), a second peripheral contact side slope change portion (111s_1b) having a slope gentler than the slope of the first intermediate side portion (111sb) and the slope of the second intermediate side portion (111sc) between the first intermediate side portion (111sb) and the second intermediate side portion (111sc), and the second intermediate side It may include an upper side portion (111sd) on a portion (111sc), and an upper side slope change portion (111s_2) having a slope gentler than the slope of the second middle side portion (111sc) and the slope of the upper side portion (111sd) between the second middle side portion (111sc) and the upper side portion (111sd).

[0080] The above peripheral contact plug (111) may include a plug pattern (113b) and a conductive liner (113a) covering the side and bottom surfaces of the plug pattern (113b). The plug pattern (113b) may include a conductive material such as tungsten, and the conductive liner (113a) may include a conductive material such as Ti or TiN. Here, the conductive material may be replaced with various materials other than those mentioned.

[0081] The upper contact plug (120) may include a plug pattern (120b) and a conductive liner (120a) covering the side and bottom surfaces of the plug pattern (120b).

[0083] Next, with reference to FIG. 3c, the gate contact plugs (106) and the support vertical structure (81) described above will be described in detail. FIG. 3c is a partial enlarged view of the area marked "C" in FIG. 2a. Below, the description will focus on one of the gate contact plugs (106).

[0084] Referring to FIG. 3c together with FIG. 1 to 3b, at a height level between the lowest gate layer (33g_L) and the uppermost gate layer (58g_U), the side of the gate contact plug (106), like the side of the memory vertical structure (71), may include "N" gate contact side slope change portions (106s_1a, 106s_1b) positioned at substantially the same height level as the "N" memory side slope change portions (71s_1a, 71s_1b). At a level higher than the uppermost gate layer (58g_U), the gate contact plug (106) may include at least two upper side slope change portions (106s_2a, 103s_2b).

[0085] The first upper side slope change portion (106s_2a) located at the lower of the at least two upper side slope change portions (106s_2a, 103s_2b) of the gate contact plug (106) can be positioned at substantially the same height level as the upper side slope change portion (71s_2) of the memory vertical structure (71).

[0086] Among the at least two upper side slope change portions (106s_2a, 103s_2b) of the gate contact plug (106), the second upper side slope change portion (106s_2b) located at the top can be positioned at a higher level than the upper surface of the memory vertical structure (71).

[0087] The gate contact plug (106) may include a plug pattern (108b) and a conductive liner (108a) covering the side and bottom surfaces of the plug pattern (108b). The plug pattern (108b) may include a conductive material such as tungsten, and the conductive liner (108a) may include a conductive material such as Ti or TiN.

[0088] The gate contact plug (106) may include a horizontal extension portion (106p) that extends horizontally at the portion in contact with the gate pad (GP). When gate layers are located at a lower level than the gate pad (GP) in contact with the gate contact plug (106), the buffer insulation layers (103) may be disposed between the gate layers located at a lower level than the gate pad (GP) and the gate contact plug (106) as described above, and the buffer insulation layers (103) may overlap with the horizontal extension portion (106p).

[0089] At a height level between the lowest gate layer (33g_L) and the uppermost gate layer (58g_U), the side of the support vertical structure (81), like the side of the memory vertical structure (71), may include "N" support side slope change sections (87s_1a, 87s_1b) located at substantially the same height level as the "N" memory side slope change sections (71s_1a, 71s_1b). At a level higher than the uppermost gate layer (58g_U), the support vertical structure (87) may include an upper side slope change section (87s_2) located at substantially the same height level as the upper side slope change section (71s_2) of the memory vertical structure (71).

[0090] In one embodiment, the support vertical structure (87) may be formed of substantially the same material layers as the memory vertical structure (71). For example, the support vertical structure (87) may include a gap-fill insulating layer (73'), a channel material layer (75') covering the outer and bottom surfaces of the gap-fill insulating layer (73'), and an information storage structure (72') covering the outer and bottom surfaces of the channel material layer (73'). The information storage structure (72') may include a first dielectric layer (72b') covering the outer and bottom surfaces of the channel material layer (75'), an information storage material layer (72d') covering the outer and bottom surfaces of the first dielectric layer (72b'), and a second dielectric layer (72a') covering the outer and bottom surfaces of the information storage material layer (72d').

[0092] As described above, at a level higher than the uppermost gate layer (58g_U), the side of the memory vertical structure (71), the side of each of the peripheral contact plugs (111), the side of the separation structure (87), and the side of each of the gate contact plugs (106) may include a first upper slope change portion (71s_2, 87s_2, 111s_2, 106s_2a) positioned at substantially the same height level, and the side of each of the gate contact plugs (106) may include a second upper slope change portion (106s_2b) positioned at a level higher than the first upper slope change portion (71s_2, 87s_2, 111s_2, 106s_2a).

[0094] Next, a semiconductor device according to a modified embodiment of the present invention will be described with reference to FIGS. 4a and 4b. FIG. 4a is a schematic cross-sectional view showing an area taken along the line I-I' of FIG. 1, and FIG. 4b is a schematic cross-sectional view showing an area taken along the line II-II' of FIG. 1. In describing a semiconductor device according to a modified embodiment of the present invention with reference to FIGS. 4a and 4b, the description will focus on the components that are modified or replaced among the components of the semiconductor device (1) described above, and the description of components that are substantially identical to the components described above, components that can be easily understood from the components described above, or components that can be easily understood from the drawings described above will be omitted.

[0095] Referring to FIGS. 4a and 4b, the semiconductor device (1') may include a first structure (LS) and a second structure (US) on the first structure (LS). The stacked structure (GS) comprising at least three stacked groups (GR1, GR2, GR3) described in FIGS. 2a and 2b may be replaced with a stacked structure (GS') comprising at least four stacked groups (GR1, GR2a, GR2b, GR3).

[0096] The above four stacking groups (GR1, GR2a, GR2b, GR3) may include a lower stacking group (GR1), a first intermediate stacking group (GR2a) on the lower stacking group (GR1), a second intermediate stacking group (GR2b) on the first intermediate stacking group (GR2a), and an upper stacking group (GR3) on the second intermediate stacking group (GR2b). The lower stacking group (GR1) may include alternately stacked lower interlayer insulating layers (32a) and lower gate layers (32g), the first intermediate stacking group (GR2a) may include alternately stacked first intermediate interlayer insulating layers (44a1) and first intermediate gate layers (44g1), the second intermediate stacking group (GR2b) may include alternately stacked second intermediate interlayer insulating layers (44a2) and second intermediate gate layers (44g2), and the upper stacking group (GR3) may include alternately stacked upper interlayer insulating layers (58a) and upper gate layers (58g).

[0097] In the embodiments, the lower gate layers (32g) stacked spaced apart from each other are defined as a lower gate stacking group, the first intermediate gate layers (44g1) stacked spaced apart from each other are defined as a first intermediate gate stacking group, the second intermediate gate layers (44g2) stacked spaced apart from each other are defined as a second intermediate gate stacking group, and the upper gate layers (55g) stacked spaced apart from each other are defined as an upper gate stacking group.

[0098] In the embodiments, the terms "lower, first intermediate, second intermediate, and upper" are used to distinguish gate stacking groups from one another and may be replaced with other terms. For example, the terms "lower, first intermediate, second intermediate, and upper" may be replaced with the terms "first, second, third, and fourth," respectively.

[0099] As described in FIGS. 1 to 2b, the lower, first intermediate, second intermediate, and upper gate layers (32g, 44g1, 44g2, 58g) may include gate pads (GP) arranged in a stepped shape within the second region (SA).

[0100] The second structure (US) may further include an intermediate insulating structure (36, 48a, 48b, 62) that covers at least a portion of the laminated structure (GS'). The above intermediate insulating structure (36, 48a, 48b, 62) may include a first intermediate insulating layer (36) covering the gate pads (GP) of the lower gate layers (32g) on ​​the lower structure (LS), a second intermediate insulating layer (48a) covering the gate pads (GP) of the first intermediate gate layers (44g1) on the first intermediate insulating layer (36), a third intermediate insulating layer (48b) covering the gate pads (GP) of the second intermediate gate layers (44g2) on the second intermediate insulating layer (48a), and a fourth intermediate insulating layer (62) covering the gate pads (GP) of the upper gate layers (58g) on ​​the third intermediate insulating layer (48b).

[0101] The second structure (US) may further include an upper insulating structure (68, 84, 90, 116) comprising the same first to fourth upper insulating layers (68, 84, 90, 116) as described in FIG. 2a and 2b.

[0102] The penetration region (TA) described in FIG. 1 may include lower, first intermediate, second intermediate, and upper horizontal insulating layers (32d, 44d1, 44d2, 58d) located at substantially the same height level as the lower, first intermediate, second intermediate, and upper gate layers (32g, 44g1, 44g2, 58g).

[0103] The semiconductor device (1) may further include a memory vertical structure (171) penetrating at least the stacked structure (GS') within a first region (MCA), a support vertical structure (181) penetrating at least the stacked structure (GS) within a second region (SA), and a separation structure (287) penetrating at least the stacked structure (GS). The semiconductor device (1) may further include peripheral contact plugs (211) including a first peripheral contact plug (211a), a second peripheral contact plug (211b), and a third peripheral contact plug (211c).

[0105] Hereinafter, with reference to FIG. 5a, the memory vertical structure (171) and the separation structure (287) described above will be explained in detail. FIG. 5a is a partial enlarged view of the area marked "A1" in FIG. 4b.

[0106] Referring to FIG. 5a together with FIG. 4a and 4b, the sides of the memory vertical structure (171) may each include side portions (171sa, 171sb1, 171sb2, 171sc, 171sd) having a steep slope, and side slope change portions having a relatively gentle slope that are positioned between adjacent side portions among the side portions (171sa, 171sb1, 171sb2, 171sc, 171sd). In the side of the memory vertical structure (171), the side slope change portions may include "n" memory side slope change portions (171s_1a, 171s_1ab, 171s_b) positioned at a height level between the lowest gate layer (32g_L) and the highest gate layer (58g_U), and at least one upper side slope change portion (171s_2) positioned at a level higher than the highest gate layer (58g_U).

[0107] The side of the separation structure (287) may each include side portions (287sa, 287sb, 287sc, 287sd) having a steep slope, and side slope change portions having a relatively gentle slope that are positioned between adjacent side portions among the side portions (287sa, 287sb, 287sc, 287sd). On the side of the separation structure (287), the side slope change portions may include “m” separation side slope change portions (287s_1a, 287s_1b) positioned at a height level between the lowest gate layer (32g_L) and the uppermost gate layer (58g_U), and at least one upper side slope change portion (287s_2) positioned at a level higher than the uppermost gate layer (58g_U). The upper side slope change portion (171s_2) on the side of the memory vertical structure (171) and the upper side slope change portion (287s_2) on the side of the separation structure (287) can be positioned at substantially the same height level.

[0108] The “m” separation side slope change portions (287s_1a, 287s_1b) on the side of the separation structure (287) positioned at a height level between the lowermost gate layer (32g_L) and the uppermost gate layer (58g_U) may be positioned at substantially the same height level as the “m” memory side slope change portions (171s_1ab, 171s_b) that are smaller than “n” among the “n” memory side slope change portions (171s_1a, 171s_1ab, 171s_b). For example, the “m” separated side slope change sections (287s_1a, 287s_1b) may be placed at substantially the same height level as the “m” memory side slope change sections (171s_1ab, 171s_b) which are located at a higher level than the side slope change section (171s_1a) located at the lowest among the “n” memory side slope change sections (171s_1a, 171s_1ab, 171s_b).

[0109] The above "n" and "m" may each be natural numbers, and "n" may be greater than "m". For example, "n" may be 3 or a natural number greater than 3, and "m" may be "n-1". For example, "n" may be 3 and "m" may be 2.

[0110] Next, with reference to FIG. 5b, we will describe one of the peripheral contact plugs (211) described above. FIG. 5b is a magnified view of the area marked "B2a" in FIG. 4a.

[0111] With reference to FIG. 5b, together with FIG. 4a, FIG. 4b and FIG. 5a, the sides of the peripheral contact plug (211) may each include side portions (211sa, 211sb1, 211sb2, 211sc, 211sd) having a steep slope, and side slope change portions having a relatively gentle slope that are positioned between adjacent side portions among the side portions (211sa, 211sb1, 211sb2, 211sc, 211sd). On the side of the above peripheral contact plug (211), the side slope change portions may include “n” peripheral contact side slope change portions (211s_1a, 211s_1ab, 211s_b) positioned at a height level between the lowest gate layer (32g_L) and the highest gate layer (58g_U), and at least one upper side slope change portion (211s_2) positioned at a level higher than the highest gate layer (58g_U).

[0112] The above "n" peripheral contact side slope change portions (211s_1a, 211s_1ab, 211s_b) can be placed at substantially the same height level as the above "n" memory side slope change portions (171s_1a, 171s_1ab, 171s_b) described in FIG. 5a.

[0113] The upper side slope change portion (211s_2) of the side of the above peripheral contact plug (211) can be positioned at substantially the same height level as the upper side slope change portion (171s_2) of the side of the memory vertical structure (171).

[0115] Next, a semiconductor device according to a modified embodiment of the present invention will be described with reference to FIGS. 6 and 7. FIG. 6 is a schematic cross-sectional view showing an area taken along the line II-II' of FIG. 1, and FIG. 7 is a partial enlarged view of the area marked 'A2' in FIG. 6. In describing a semiconductor device according to a modified embodiment of the present invention with reference to FIGS. 6 and 7, the description will focus on a modified example of the separation structure (287) described in FIGS. 4b and 5a.

[0116] Referring to FIGS. 6 and 7, the separation structure (287) described in FIGS. 4b and 5a may be replaced with the separation structure (387) of FIGS. 6 and 7. For example, the sides of the separation structure (387) may each include side sections (387sa, 387sb, 387sc) having a steep slope and side slope change sections having a relatively gentle slope that are positioned between adjacent side sections among the side sections (387sa, 387sb, 387sc). On the side of the separation structure (387), the side slope change portions may include "n-2" separation side slope change portions (387s_1) positioned at a height level between the lowest gate layer (32g_L) and the highest gate layer (58g_U), and at least one upper side slope change portion (387s_2) positioned at a level higher than the highest gate layer (58g_U). The upper side slope change portion (171s_2) on the side of the memory vertical structure (171) and the upper side slope change portion (387s_2) on the side of the separation structure (387) may be positioned at substantially the same height level.

[0117] As described with reference to FIG. 5a, when the side of the memory vertical structure (171) placed at a height level between the lowest gate layer (32g_L) and the highest gate layer (58g_U) includes "n" memory side slope change portions (171s_1a, 171s_1ab, 171s_b), the "n-2" may be 1 or a natural number greater than 1, and the "n" may be 3 or a natural number greater than 3.

[0118] The above "n-2" separated side slope change sections (387s_1) can be placed at substantially the same height level as the intermediate memory side slope change section (171s_ab) located between the lower memory side slope change section (171s_1a) located at the bottom and the upper memory side slope change section (171s_1b) located at the top among the "n" memory side slope change sections (171s_1a, 171s_1ab, 171s_b).

[0120] In the semiconductor device (1) described in FIGS. 2a and 2b, the peripheral circuits (9, 13) may be placed below the stacked structure (GS). However, the technical concept of the present invention is not limited thereto. For example, the peripheral circuits (9, 13) may be placed on the stacked structure (GS). Accordingly, an exemplary example in which the peripheral circuits (9, 13) are placed on the stacked structure (GS) will be described with reference to FIG. 8. FIG. 8 is a schematic cross-sectional view showing a modified example of a semiconductor device according to an embodiment of the present invention.

[0121] Referring to FIG. 8, the semiconductor device (1") may include a first chip structure (CH1) and a second chip structure (CH2) bonded to the first chip structure (CH1). The second chip structure (CH2) may include the pattern structure (23), the insulating layers (26o, 26i_2), the stacked structure (GS), the intermediate insulating structure (36, 48, 62), and the upper insulating structure (68, 84, 90, 116) as described above. The second chip structure (CH2) may further include a lower insulating structure (221) corresponding to the lower insulating structure (21) in FIG. 2a. The second chip structure (CH2) may further include gate contact plugs (106) that penetrate the gate pads (GP) of the gate layers (32g, 44g, 58g) within a step region (SA) and are electrically connected to the gate pads (GP). There is. The second chip structure (CH2) may further include the memory vertical structure (71 in FIG. 2a), the support vertical structure (81 in FIG. 2a), the peripheral contact plugs (111), the separation structures (87 in FIG. 2b), the upper contact plugs (120 in FIG. 2a), the bitline contact plug (119 in FIG. 2a), the bitline (123 in FIG. 2a), and the peripheral wiring (124 in FIG. 2a) as described above.

[0122] The second chip structure (CH2) may further include gate connection plugs (121) disposed on the gate contact plugs (106) and gate wiring (126) on the gate connection plugs (121).

[0123] The second chip structure (CH2) may further include first junction patterns (155) and a first junction insulating layer (150) surrounding the sides of the first junction patterns (155). The first junction patterns (155) may be electrically connected to the bit line (123), the gate wiring (126), and the peripheral wiring (124). The first junction patterns (155) may include a metallic material such as copper.

[0124] The first chip structure (CH1) may include components similar to the substructure (LS) described above. For example, the first chip structure (CH1) may include a semiconductor substrate (305), a peripheral circuit (313) below the semiconductor substrate (305), second junction patterns (315) electrically connected to the peripheral circuit (311, 313) and joined to the first junction patterns (155), and a second junction insulating layer (321) joined to the first junction insulating layer (150).

[0125] The first chip structure (CH1) may further include an insulating layer (360) on the semiconductor substrate (305), an input / output pad (380) disposed on the insulating layer (360), and an input / output connection pattern (370) that penetrates the semiconductor substrate (305) and the insulating layer (360) and electrically connects the input / output pad (380) and the peripheral circuits (311, 313).

[0127] Next, FIGS. 9a, 9b, 10a, 10b, 11a, and 11b will describe exemplary examples of a method for forming a semiconductor device according to an embodiment of the present invention. FIGS. 9a and 9b are process flow diagrams showing exemplary examples of a method for forming a semiconductor device according to an embodiment of the present invention, and FIGS. 10a, 10b, 11a, and 11b are cross-sectional views for explaining exemplary examples of a method for forming a semiconductor device according to an embodiment of the present invention. In FIGS. 10a, 10b, 11a, and 11b, FIGS. 10a and 11b are schematic cross-sectional views showing regions taken along the line I-I' of FIG. 1, and FIGS. 10b and 11b are schematic cross-sectional views showing regions taken along the line II-II' of FIG. 1.

[0128] Referring to FIG. 1, FIG. 9a, FIG. 10a, and FIG. 10b, a substructure (LS) can be formed (S10). The substructure (LS) may be referred to as a first structure. The substructure (LS) may include a semiconductor substrate (5), a device isolation film (7s) defining a peripheral active region (7a) on the semiconductor substrate (5), peripheral circuits (9, 13) formed on the semiconductor substrate (5), peripheral pads (15) electrically connected to the peripheral circuits (9, 13), and a lower insulating structure (21) covering the peripheral circuits (9, 13) and the peripheral pads (15) on the semiconductor substrate (5). The peripheral circuits (9, 13) may include circuit elements (9), such as a transistor including a peripheral gate (9b) and a peripheral source / drain (9a), and circuit wiring (13) electrically connected to the circuit elements (9). The above peripheral pads (15) can be electrically connected to the circuit wiring (13).

[0129] The above peripheral pads (15) may include first to third peripheral pads (15a, 15b, 15c). In an exemplary example, each of the above peripheral pads (15) may include a conductive material, such as a metallic material such as tungsten.

[0130] The above substructure (LS) may further include a capping layer (17) formed on each of the surrounding pads (15) and an etch stop layer (19) formed on the capping layer (17). In an exemplary example, the capping layer (17) may be formed of a silicon layer, and the etch stop layer (19) may be formed of an insulating material, for example, silicon oxide or silicon nitride.

[0131] Forming the lower structure (LS) may further include forming a pattern structure (23) and insulation layers (26i_1, 26i_2, 26o) on the lower insulation structure (21). The insulation layers (26i_1, 26i_2, 26o) may include an outer insulation layer (26o) disposed on the outside of the pattern structure (23), a first inner insulation layer (26i_1) penetrating the pattern structure (23), and second inner insulation layers (26i_2) penetrating the pattern structure (23).

[0132] The pattern structure (23) may include a plurality of pattern layers that can be stacked in sequence. For example, the pattern structure (23) may include a lower pattern layer (23a), intermediate pattern layers (23b) spaced apart from each other on the lower pattern layer (23a), and an upper pattern layer (23c) on the intermediate pattern layers (23b). At least one of the lower pattern layer (23a), intermediate pattern layers (23b), and upper pattern layer (23c) may be a silicon layer. For example, the lower pattern layer (23a) and the upper pattern layer (23c) may be silicon layers, for example, silicon layers having an N-type conductivity, and the intermediate pattern layers (23b) may be a material layer different from the silicon layer, for example, a silicon oxide layer and / or a silicon nitride layer.

[0133] A first mold group (30m) can be formed (S15). Forming the first mold group (30m) may include forming first interlayer insulating layers (32a) and first sacrificial gate layers (32b) that are alternately and repeatedly stacked, patterning the first interlayer insulating layers (32a) and the first sacrificial gate layers (32b) to form a stepped shape, and forming pad layers (34) on the stepped portions of the first sacrificial gate layers (32b). Among the first interlayer insulating layers (32a) and the first sacrificial gate layers (32b), the lowest layer and the highest layer may be the first interlayer insulating layers. The first interlayer insulating layers (32a) may be formed of silicon oxide. The first sacrificial gate layers (32b) and the pad layers (34) may be formed of silicon nitride or polysilicon.

[0134] A first intermediate insulating layer (36) covering the first sacrificial gate layers (32b) formed in a stepped shape on the lower structure (LS) and the pad layers (34) can be formed.

[0135] The lower sacrificial vertical structures (39a, 39b, 39c, 39d) can be formed (S20). The lower sacrificial vertical structures (39a, 39b, 39c, 39d) can each be formed in the area where the memory vertical structure (71), the support vertical structure (81), the gate contact plugs (106), and the peripheral contact plugs (111) described in FIGS. 2A and 2B are to be placed. The lower sacrificial vertical structures (39a, 39b, 39c, 39d) can be formed simultaneously.

[0136] Referring to FIG. 1, FIG. 9a, FIG. 9b, FIG. 11a, and FIG. 11b, a second mold group (42m) can be formed (S25). Forming the second mold group (42m) may include forming second interlayer insulating layers (44a) and second sacrificial gate layers (44b) that are alternately and repeatedly stacked, patterning the second interlayer insulating layers (44a) and the second sacrificial gate layers (44b) to form a stepped shape, and forming pad layers (46) on the stepped portions of the second sacrificial gate layers (44b). Among the second interlayer insulating layers (44a) and the second sacrificial gate layers (44b), the lowest layer and the highest layer may be the second interlayer insulating layers. The second interlayer insulating layers (44a) may be formed of silicon oxide. The second sacrificial gate layers (44b) and the pad layers (46) may be formed of silicon nitride or polysilicon.

[0137] Step-shaped portions of the second sacrificial gate layers (44b) formed on the first intermediate insulating layer (36) and a second intermediate insulating layer (48) covering the pad layers (46) can be formed.

[0138] Intermediate sacrificial vertical structures (51a, 51b, 51c, 51d) that are in contact with the lower sacrificial vertical structures (39a, 39b, 39c, 39d), respectively, and lower sacrificial separation structures (52) that penetrate the first and second mold groups (30m, 42m) can be formed (S30). The lower sacrificial separation structures (52) can be spaced apart from the lower pattern layer (23a) and can be in contact with the upper pattern layer (23c). The lower sacrificial separation structures (52) can be spaced apart from the intermediate pattern layers (23b).

[0139] A third mold group (56m) can be formed (S35). Forming the third mold group (56m) may include forming third interlayer insulating layers (58a) and third sacrificial gate layers (58b) that are alternately and repeatedly stacked, patterning the third interlayer insulating layers (58a) and the third sacrificial gate layers (58b) to form a stepped shape, and forming pad layers (60) on the stepped portions of the third sacrificial gate layers (58b). Among the third interlayer insulating layers (58a) and the third sacrificial gate layers (58b), the lowest layer and the highest layer may be the third interlayer insulating layers. The third interlayer insulating layers (58a) may be formed of silicon oxide. The third sacrificial gate layers (58b) and the pad layers (60) may be formed of silicon nitride or polysilicon.

[0140] A third intermediate insulating layer (62) covering the third sacrificial gate layers (58b) formed in a stepped shape on the second intermediate insulating layer (48) and the pad layers (60) can be formed.

[0141] Upper sacrificial vertical structures (64a, 64b, 64c, 64d) in contact with the intermediate sacrificial vertical structures (51a, 51b, 51c, 51d) and upper sacrificial separation structures (65) penetrating the third mold group (56m) and in contact with the lower sacrificial separation structures (52) can be formed.

[0142] The lower sacrifice vertical structures (39a, 39b, 39c, 39d), the intermediate sacrifice vertical structures (51a, 51b, 51c, 51d), and the upper sacrifice vertical structures (64a, 64b, 64c, 64d) may form sacrifice vertical structures (66a, 66b, 66c, 66d), and the lower sacrifice separation structures (52) and the upper sacrifice separation structures (65) may form sacrifice separation structures (67).

[0143] The above sacrificial vertical structures (66a, 66b, 66c, 66d) may each be formed in an area where the memory vertical structure (71), the support vertical structure (81), the gate contact plugs (106), and the peripheral contact plugs (111) are to be placed. For example, the sacrificial vertical structures (66a, 66b, 66c, 66d) may include a memory sacrificial vertical structure (66a) for forming the memory vertical structure (71), a support sacrificial vertical structure (66b) for forming the support vertical structure (81), peripheral contact sacrificial vertical structures (66c) for forming the peripheral contact plugs (111), and a gate contact sacrificial vertical structure (66d) for forming the gate contact plug (106).

[0146] Referring to FIG. 1, FIG. 9b, FIG. 2a and FIG. 2b, a first upper insulating layer (68) can be formed on the sacrificial vertical structures (66a, 66b, 66c, 66d), the third mold group (56m), and the third intermediate insulating layer (62).

[0147] While forming holes penetrating the first upper insulating layer (68), the memory sacrifice vertical structure (66a in FIG. 11a) and the support sacrifice vertical structure (66b in FIG. 11a) are respectively exposed, and the exposed memory sacrifice vertical structure (66a in FIG. 11a) and the exposed support sacrifice vertical structure (66b in FIG. 11a) are removed to form a memory vertical hole and a support vertical hole, and a memory vertical structure (71) and a support vertical structure (81) can be formed within the memory vertical hole and the support vertical hole, respectively.

[0148] A second upper insulating layer (84) can be formed on the first upper insulating layer (68). Preliminary gate contact plugs can be formed (S50). Forming the above-mentioned preliminary gate contact plugs involves forming holes that penetrate the second upper insulating layer (84) and the first upper insulating layer (68) in sequence and expose the gate contact sacrificial vertical structure (66d in FIG. 11a), removing the gate contact sacrificial vertical structure (66d in FIG. 11a) exposed by the holes to form preliminary gate contact holes, partially etching the sacrificial gate layers (32b, 44b, 58b) and the pad layers (34, 56, 60) exposed by the preliminary gate contact holes to form spaces, and forming buffer insulating layers (103) that fill the partially etched spaces of the sacrificial gate layers (32b, 44b, 58b) that do not contact the pad layers (34, 56, 60), and the pad layers (34, The sacrificial gate layers (32b, 44b, 58b) in contact with 56, 60) may include forming a material layer that partially fills the partially etched spaces.

[0149] Separation trenches can be formed (S55). Forming the separation trenches may include exposing the sacrificial separation structures (67 in FIG. 11b) while forming openings that penetrate the first and second upper insulation layers (68, 84) in turn, and removing the exposed sacrificial separation structures (67 in FIG. 11b).

[0150] In one embodiment, the intermediate pattern layer below the first region (MCA) among the intermediate pattern layers (20b) may be exposed while forming a sacrificial spacer on the sidewalls of the separation trenches, the exposed intermediate pattern layer below the first region (MCA) may be removed, the exposed intermediate pattern layer may form a first intermediate pattern layer (20b1) in the space, and the sacrificial spacer may be removed. The intermediate pattern layer below the second region (SA) among the intermediate pattern layers (20b) may remain and be referred to as a second intermediate pattern layer (20b2).

[0151] The sacrificial gate layers (32b, 44b, 58b in FIG. 11a and FIG. 11b) within the first to third mold groups (30m, 42m, 56m in FIG. 11a and FIG. 11b) can be replaced with gate layers (32g, 44g, 58g) (S60). For example, the sacrificial gate layers (32b, 44b, 58b in FIG. 11a and FIG. 11b) within the separation trenches exposed by the separation trenches can be etched to form empty spaces, and the gate layers (32g, 44g, 58g) can be formed within the empty spaces.

[0152] During the process of etching the sacrificial gate layers (32b, 44b, 58b in FIG. 11a and FIG. 11b) to form empty spaces, the memory vertical structure (71) and the support vertical structure (81) can act as supports to prevent the interlayer insulating layers (32a, 44a, 58a) from bending or deforming.

[0153] In an embodiment, within the penetration region (TA), a portion of the sacrificial gate layers (32b, 44b, 58b in FIG. 11b) may remain and be formed into horizontal insulating layers (32d, 44d, 58d).

[0154] A third upper insulating layer (90) can be formed on the second upper insulating layer (84). Separation structures (87) can be formed (S65). The separation structures (87) can be formed within separation trenches. Gate contact plugs (106) and peripheral contact plugs (111) can be formed (S70). Forming the gate contact plugs (106) and the peripheral contact plugs (111) may include forming holes penetrating the third upper insulating layer (90) to expose the reserve gate contact plugs and holes penetrating the first to third upper insulating layers (68, 84, 90) to expose the peripheral contact sacrificial vertical structures (66c in FIG. 11a and FIG. 11b), removing the exposed reserve gate contact plugs and the exposed peripheral contact sacrificial vertical structures (66c in FIG. 11a and FIG. 11b), respectively, to form gate contact holes and peripheral contact holes, and filling the gate contact holes and peripheral contact holes, respectively, with a conductive material. The buffer insulating layers (103) may remain while removing the exposed reserve gate contact plugs.

[0155] A fourth upper insulating layer (116) can be formed on the third upper insulating layer (90). A wiring process can be carried out (S75). The wiring process may include forming a bitline contact plug (119) that penetrates the first to fourth upper insulating layers (68, 84, 90, 116) and is electrically connected to the memory vertical structure (71), and upper contact plugs (120) that penetrate the fourth upper insulating layer (116) and are electrically connected to the peripheral contact plugs (111), and forming a bitline (123) and peripheral wiring (124).

[0157] FIG. 12 is a schematic diagram showing a data storage system including a semiconductor device according to an exemplary embodiment of the present invention.

[0158] Referring to FIG. 12, a data storage system (1000) according to an exemplary embodiment of the present invention may include a semiconductor device (1100) and a controller (1200) electrically connected to the semiconductor device (1100). The data storage system (1000) may be a storage device including the semiconductor device (1100) or an electronic device including the storage device. For example, the data storage system (1000) may be a solid state drive device (SSD), a Universal Serial Bus (USB), a computing system, a medical device, or a communication device including the semiconductor device (1100).

[0159] In an embodiment, the data storage system (1000) may be an electronic system that stores data.

[0160] The semiconductor device (1100) may be a semiconductor device according to any one of the embodiments described above with reference to FIGS. 1 to 8, or a semiconductor device manufactured by the semiconductor device formation method described with reference to FIGS. 9a to 11b. The semiconductor device (1100) may include a first structure (1100F) and a second structure (1100S) on the first structure (1100F).

[0161] The first structure (1100F) may be a peripheral circuit structure including a decoder circuit (1110), a page buffer (1120), and a logic circuit (1130). For example, the first structure (1100F) may include the peripheral circuit (9 in FIG. 2a) described above.

[0162] The second structure (1100S) may be a memory cell structure comprising a bit line (BL), a common source line (CSL), word lines (WL), first and second gate upper lines (UL1, UL2), first and second gate lower lines (LL1, LL2), and memory cell strings (CSTR) between the bit line (BL) and the common source line (CSL).

[0163] The pattern structure (23) described above may include a silicon layer having an N-type conductivity, and the silicon layer having an N-type conductivity may be the common source line (CSL).

[0164] In the second structure (1100S) above, each memory cell string (CSTR) may include lower transistors (LT1, LT2) adjacent to the common source line (CSL), upper transistors (UT1, UT2) adjacent to the bit line (BL), and a plurality of memory cell transistors (MCT) disposed between the lower transistors (LT1, LT2) and the upper transistors (UT1, UT2). The number of the lower transistors (LT1, LT2) and the number of the upper transistors (UT1, UT2) may vary depending on the embodiments.

[0165] In exemplary embodiments, the upper transistors (UT1, UT2) may include string select transistors, and the lower transistors (LT1, LT2) may include ground select transistors. The gate lower lines (LL1, LL2) may each be gate electrodes of the lower transistors (LT1, LT2). The word lines (WL) may be gate electrodes of memory cell transistors (MCT), and the gate upper lines (UL1, UL2) may each be gate electrodes of the upper transistors (UT1, UT2).

[0166] The gate layers (32g, 44g, 58g) described above may comprise the gate lower lines (LL1, LL2), the word lines (WL), and the gate upper lines (UL1, UL2).

[0167] In exemplary embodiments, the lower transistors (LT1, LT2) may include a lower erase control transistor (LT1) and a ground select transistor (LT2) connected in series. The upper transistors (UT1, UT2) may include a string select transistor (UT1) and an upper erase control transistor (UT2) connected in series. At least one of the lower erase control transistor (LT1) and the upper erase control transistor (UT1) may be used for an erase operation to delete data stored in the memory cell transistors (MCT) using the Gate Induced Drain Leakage (GIDL) phenomenon.

[0168] The above common source line (CSL), the first and second gate lower lines (LL1, LL2), word lines (WL), and the first and second gate upper lines (UL1, UL2) can be electrically connected to the decoder circuit (1110) through first connecting wires (1115) extending from the first structure (1100F) to the second structure (1100S).

[0169] The bit lines (BL) may be electrically connected to the page buffer (1120) through second connecting wires (1125) extending from the first structure (1100F) to the second structure (1100S). The bit lines (BL) may be the bit lines (123) described above.

[0170] In the first structure (1100F), the decoder circuit (1110) and the page buffer (1120) can perform control operations on at least one selected memory cell transistor among the plurality of memory cell transistors (MCT). The decoder circuit (1110) and the page buffer (1120) can be controlled by a logic circuit (1130). The semiconductor device (1000) can communicate with the controller (1200) through the input / output pad (1101) which is electrically connected to the logic circuit (1130). The input / output pad (1101) can be electrically connected to the logic circuit (1130) through an input / output connection wire (1135) that extends from the first structure (1100F) to the second structure (1100S).

[0171] The controller (1200) may include a processor (1210), a NAND controller (1220), and a host interface (1230). According to embodiments, the data storage system (1000) may include a plurality of semiconductor devices (1100), and in this case, the controller (1200) may control the plurality of semiconductor devices (1000).

[0172] The processor (1210) can control the overall operation of the data storage system (1000), including the controller (1200). The processor (1210) can operate according to a predetermined firmware and can access the semiconductor device (1100) by controlling the NAND controller (1220). The NAND controller (1220) may include a NAND interface (1221) that handles communication with the semiconductor device (1100). Through the NAND interface (1221), control commands for controlling the semiconductor device (1100), data to be written to the memory cell transistors (MCT) of the semiconductor device (1100), data to be read from the memory cell transistors (MCT) of the semiconductor device (1100), etc., may be transmitted. The host interface (1230) may provide a communication function between the data storage system (1000) and an external host. When a control command is received from an external host through the host interface (1230), the processor (1210) can control the semiconductor device (1100) in response to the control command.

[0174] FIG. 13 is a schematic perspective view of a data storage system including a semiconductor device according to an exemplary embodiment of the present invention.

[0175] Referring to FIG. 13, a data storage system (2000) according to an exemplary embodiment of the present invention may include a main board (2001), a controller (2002) mounted on the main board (2001), one or more semiconductor packages (2003), and a DRAM (2004). The semiconductor package (2003) and the DRAM (2004) may be connected to the controller (2002) by wiring patterns (2005) formed on the main board (2001).

[0176] The main board (2001) may include a connector (2006) comprising a plurality of pins that are coupled to an external host. The number and arrangement of the plurality of pins in the connector (2006) may vary depending on the communication interface between the data storage system (2000) and the external host. In exemplary embodiments, the data storage system (2000) may communicate with the external host according to any one of interfaces such as USB (Universal Serial Bus), PCI-Express (Peripheral Component Interconnect Express), SATA (Serial Advanced Technology Attachment), and M-Phy for UFS (Universal Flash Storage). In exemplary embodiments, the data storage system (2000) may operate by power supplied from the external host through the connector (2006). The data storage system (2000) may further include a Power Management Integrated Circuit (PMIC) that distributes power supplied from the external host to the controller (2002) and the semiconductor package (2003).

[0177] The above controller (2002) can write data to the semiconductor package (2003) or read data from the semiconductor package (2003), and can improve the operating speed of the data storage system (2000).

[0178] The above DRAM (2004) may be a buffer memory to mitigate the speed difference between the semiconductor package (2003), which is a data storage space, and an external host. The DRAM (2004) included in the data storage system (2000) may also function as a type of cache memory and may provide a space for temporarily storing data during control operations for the semiconductor package (2003). When the DRAM (2004) is included in the data storage system (2000), the controller (2002) may further include a DRAM controller for controlling the DRAM (2004) in addition to a NAND controller for controlling the semiconductor package (2003).

[0179] The semiconductor package (2003) may include first and second semiconductor packages (2003a, 2003b) spaced apart from each other. The first and second semiconductor packages (2003a, 2003b) may each be a semiconductor package comprising a plurality of semiconductor chips (2200). Each of the semiconductor chips (2200) may include a semiconductor device according to any one of the embodiments described above with reference to FIGS. 1 to 8, or a semiconductor device manufactured by the semiconductor device forming method described with reference to FIGS. 9a to 11b.

[0180] Each of the first and second semiconductor packages (2003a, 2003b) may include a package substrate (2100), semiconductor chips (2200) on the package substrate (2100), adhesive layers (2300) disposed on the lower surface of each of the semiconductor chips (2200), a connecting structure (2400) electrically connecting the semiconductor chips (2200) and the package substrate (2100), and a molding layer (2500) covering the semiconductor chips (2200) and the connecting structure (2400) on the package substrate (2100).

[0181] The above package substrate (2100) may be a printed circuit board including package upper pads (2130). Each of the above semiconductor chips (2200) may include an input / output pad (2210).

[0182] In exemplary embodiments, the connection structure (2400) may be a bonding wire that electrically connects the input / output pad (2210) and the package upper pads (2130). Accordingly, in each of the first and second semiconductor packages (2003a, 2003b), the semiconductor chips (2200) may be electrically connected to each other by a bonding wire and may be electrically connected to the package upper pads (2130) of the package substrate (2100). According to embodiments, in each of the first and second semiconductor packages (2003a, 2003b), the semiconductor chips (2200) may be electrically connected to each other by a connection structure including a through silicon via (TSV) instead of the connection structure (2400) in a bonding wire manner.

[0183] In exemplary embodiments, the controller (2002) and the semiconductor chips (2200) may be included in a single package. For example, the controller (2002) and the semiconductor chips (2200) may be mounted on a separate interposer substrate different from the main substrate (2001), and the controller (2002) and the semiconductor chips (2200) may be connected to each other by wiring formed on the interposer substrate.

[0184] FIG. 14 is a schematic cross-sectional view of a semiconductor package according to an exemplary embodiment of the present invention. FIG. 14 illustrates an exemplary embodiment of the semiconductor package (2003) of FIG. 13 and conceptually shows a region of the semiconductor package (2003) of FIG. 13 cut along the cutting line V-V'.

[0185] Referring to FIG. 14, in a semiconductor package (2003), the package substrate (2100) may be a printed circuit board. The package substrate (2100) may include a package substrate body portion (2120), package upper pads (2130) disposed on the upper surface of the package substrate body portion (2120), lower pads (2125) disposed on the lower surface of the package substrate body portion (2120) or exposed through the lower surface, and internal wiring (2135) electrically connecting the upper pads (2130) and the lower pads (2125) inside the package substrate body portion (2120). The upper pads (2130) may be electrically connected to connection structures (2400). The lower pads (2125) may be connected to wiring patterns (2005) of the main board (2010) of the data storage system (2000) through conductive connection portions (2800).

[0186] Each of the semiconductor chips (2200) may include a semiconductor substrate (3010) and a first structure (3100) and a second structure (3200) that are sequentially stacked on the semiconductor substrate (3010). The first structure (3100) may include a peripheral circuit region including peripheral wiring (3110). The second structure (3200) may include a common source line (3205), a gate stacking structure (3210) on the common source line (3205), memory channel structures (3220) and separation structures (3230) penetrating the gate stacking structure (3210), bit lines (3240) electrically connected to the memory channel structures (3220), and gate contact plugs (106 in FIG. 2a) electrically connected to the word lines (WL) of the gate stacking structure (3210). The first structure (3100) may include the first structure (1100F) of FIG. 12, and the second structure (3200) may include the second structure (1100S) of FIG. 12.

[0187] Each of the above semiconductor chips (2200) may include a through-wire (3245) that is electrically connected to the peripheral wiring (3110) of the first structure (3100) and extends into the second structure (3200). The through-wire (3245) may penetrate the gate stacking structure (3210) and may be further disposed outside the gate stacking structure (3210).

[0188] Each of the above semiconductor chips (2200) may further include an input / output connection wire that is electrically connected to the peripheral wiring (3110) of the first structure (3100) and extends into the second structure (3200), and an input / output pad (2210) that is electrically connected to the input / output connection wire.

[0189] In FIG. 14, the enlarged portion of the semiconductor device (1) indicated by reference numeral 1 is intended to explain that the semiconductor chips (2200) of FIG. 14 may be modified to include a cross-sectional structure as in FIG. 2a. Accordingly, each of the semiconductor chips (2200) may include a semiconductor device (1) according to any one of the embodiments described above with reference to FIG. 1 to 8, or a semiconductor device (1) manufactured by the semiconductor device formation method described with reference to FIG. 9a to 16b.

[0190] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing its technical concept or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0192] 1: Semiconductor device LS: First structure US: Structure 2 5: Semiconductor substrate 7a: Active area 15: Peripheral pad 17: Capping layer 19: Etching stop layer 21: Lower insulation structure 23: Pattern structure 23a: Lower pattern layer 23b1: First intermediate pattern layer 23b2: Second intermediate pattern layer 23c: Upper pattern layer 26o: Outer insulation layer 26i_1: First inner insulation layer 26i_2: Second inner insulating layer 32b: First gate mold layers 32g: First gate layers 32d: First horizontal insulation layers 44a: Second interlayer insulation layers 44g: Second gate layers 44d: Second horizontal insulation layers 58a: Third interlayer insulation layers 58g: Third gate layers 58d: Third horizontal insulation layers 68: First upper insulation layer 71: Memory vertical structure 81: Vertical support structure 84: Second upper insulation layer 87: Separation structure 90: Third upper insulation layer 103: Buffer insulation layer 106: Gate contact plug 111: Peripheral contact plug 71s_1a, 71s_1b, 71s_2, 81s_1a, 81s_1b, 81s_2, 87s_1, 87s_2, 106s_1a, 106s_1b, 106s_2, 111s_1a, 111s_1b, 111s_2: Gradient change cattails 116: 4th upper insulation layer 119: Bitline contact plug 120: Upper contact plug 123: Bit line 124: Peripheral Wiring GR1: 1st Lamination Group GR2: 2nd stacking group GR3: 3rd stacking group GR: Laminated structure GP: Gate pads

Claims

Claim 1 A first structure; a second structure comprising a stacked structure including at least three gate stacked groups stacked vertically on the first structure and an insulating structure covering at least a portion of the stacked structure; a memory vertical structure penetrating at least the stacked structure; and a separation structure penetrating at least the stacked structure and having an upper surface at a level higher than the upper surface of the memory vertical structure. A semiconductor device comprising gate contact plugs, wherein each of the gate stacking groups comprises gate layers stacked apart from each other in the vertical direction, the gate contact plugs are connected to the gate layers, and at a height level between the lowest gate layer and the highest gate layer among the gate layers of the stacking structure, the side of the memory vertical structure comprises "N" memory side slope change portions, and the side of the separation structure comprises "M" separation side slope change portions located at the same height level as "M" memory side slope change portions smaller than "N" among the "N" memory side slope change portions, wherein "N" is a natural number greater than 2 or greater than 2, and "M" is a natural number greater than 1 or greater than 1, and at a level higher than the highest gate layer, the side of one of the gate contact plugs comprises at least two upper slope change portions disposed at different levels. Claim 2 A semiconductor device according to claim 1, wherein the "N" memory side slope change portions and the "M" separation side slope change portions each have a first slope between an upper side portion and a lower side portion, and the first slope is a gentler slope than the slope of the upper side portion and the slope of the lower side portion. Claim 3 A semiconductor device according to claim 1, wherein the gate stacking groups include a first gate stacking group, a second gate stacking group, and a third gate stacking group that are stacked sequentially in the vertical direction, wherein "N" is 2 and "M" is 1, and one of the separated side slope change parts is positioned at the same height level as the memory side slope change part located at the upper of the two memory side slope change parts. Claim 4 A semiconductor device according to claim 1, wherein the gate stacking groups include a first gate stacking group, a second gate stacking group, a third gate stacking group and a fourth gate stacking group that are stacked sequentially in the vertical direction, wherein "N" is 3 and "M" is 2, and the two separated side slope change portions are positioned at the same height level as the two memory side slope change portions that are positioned at a higher level than the memory side slope change portion located at the lowest of the three memory side slope change portions. Claim 5 A semiconductor device according to claim 1, wherein the gate stacking groups include a first gate stacking group, a second gate stacking group, a third gate stacking group and a fourth gate stacking group that are stacked sequentially in the vertical direction, wherein "N" is 3 and "M" is 1, and the separated side slope change portion is disposed at the same height level as an intermediate memory side slope change portion located between the lowest lower memory side slope change portion and the upper upper memory side slope change portion among the three memory side slope change portions. Claim 6 A semiconductor device according to claim 1, further comprising a peripheral contact plug penetrating at least a portion of the second structure, wherein the peripheral contact plug is spaced apart from the gate layers of the stacked structure, and at a height level between the lowest gate layer and the highest gate layer, the side of the peripheral contact plug comprises "N" peripheral contact side slope change portions disposed at the same height level as the "N" memory side slope change portions. Claim 7 A semiconductor device according to claim 1, further comprising gate contact plugs, wherein the gate layers are stacked in the vertical direction within a first region of the second structure and include gate pads that extend from the first region of the second structure into a second region of the second structure and are arranged in a stepped manner within the second region of the second structure, wherein the gate contact plugs penetrate the gate pads and are electrically connected to the gate pads, and each of the gate contact plugs has a lower surface at a level lower than the lowest gate layer and an upper surface at a level higher than the uppermost gate layer, and at a height level between the lowest gate layer and the uppermost gate layer, the side of one of the gate contact plugs comprises "N" gate contact side slope change portions disposed at the same height level as the "N" memory side slope change portions. Claim 8 A substructure; a stacked structure comprising at least three gate stacking groups stacked vertically on the substructure and an insulating structure covering at least a portion of the stacked structure; a memory vertical structure penetrating at least the stacked structure; peripheral contact plugs; gate contact plugs; and at least including a separation structure penetrating the stacked structure and having a line shape in a plane, wherein each of the gate stacking groups includes gate layers stacked spaced apart from each other in the vertical direction, and at a height level between the lowest gate layer and the highest gate layer among the gate layers of the stacked structure, the side of each of the memory vertical structure and the side of the peripheral contact plug include "N" first slope change portions, and the side of the separation structure includes "M" second slope change portions located at the same height level as "M" first slope change portions smaller than "N" among the "N" first slope change portions, wherein "N" and "M" are different natural numbers, and at a level higher than the highest gate layer, the side of the memory vertical structure, the side of the peripheral contact plug, the side of the separation structure and the side of each of the gate contact plugs include a first upper slope change portion disposed at the same height level, and the same as the first slope change portion located at the lowest of the "N" first slope change portions A semiconductor device comprising, at a height level, a side of the separation structure is vertical, and at a level higher than the top gate layer, a second upper slope change portion which is positioned at a level higher than the first upper slope change portion, wherein the side of each of the gate contact plugs is positioned at a level higher than the first upper slope change portion. Claim 9 A semiconductor device according to claim 8, wherein the gate layers are stacked in the vertical direction within a first region of the upper structure and include gate pads that extend from the first region of the upper structure into a second region of the upper structure and are arranged in a stepped manner within the second region of the upper structure, and the gate contact plugs are each electrically connected to the gate pads, and at a level higher than the top gate layer, the side of each of the gate contact plugs further includes a second upper slope change portion at a level higher than the first upper slope change portion, and the first slope change portions, the second slope change portion, the first upper slope change portion and the second upper slope change portion each have a third slope between the upper side portion of the first slope and the lower side portion of the second slope, and the third slope is a gentler slope than each of the first slope and the second slope. Claim 10 A main board; a semiconductor device on the main board; and a controller electrically connected to the semiconductor device on the main board, wherein the semiconductor device comprises: a lower structure; a stacked structure comprising at least three gate stacking groups stacked vertically on the lower structure and an insulating structure covering at least a portion of the stacked structure; a memory vertical structure penetrating at least the stacked structure; peripheral contact plugs; and gate contact plugs. and at least a separation structure penetrating the stacked structure and having a line shape in a plane, wherein each of the gate stacking groups comprises gate layers stacked spaced apart from each other in the vertical direction, and at a height level between the lowest gate layer and the highest gate layer among the gate layers of the stacked structure, the side of each of the memory vertical structure and the side of the peripheral contact plug comprises "N" first slope change portions, and the side of the separation structure comprises "M" second slope change portions located at the same height level as "M" first slope change portions smaller than "N" among the "N" first slope change portions, wherein "N" and "M" are different natural numbers, and at a level higher than the highest gate layer, the side of the memory vertical structure, the side of the peripheral contact plug, the side of the separation structure and the side of each of the gate contact plugs comprise a first upper slope change portion disposed at the same height level, and at the same height as the first slope change portion located at the lowest of the "N" first slope change portions A data storage system comprising, at a level, the side of the separation structure is vertical, and at a level higher than the top gate layer, the side of each of the gate contact plugs further comprises a second upper slope change portion positioned at a level higher than the first upper slope change portion.

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