Display apparatus

Abstract

The present invention provides a display device for reducing the possibility of defects in a display device, comprising a first substrate including a rectangular unit area and a first subpixel, a second subpixel, and a third subpixel spaced apart from each other and emitting different colors, wherein the unit area includes a virtual octagon having sides that coincide with the center of the unit area and are spaced apart from the boundary of the unit area, the first to third subpixels are located within the virtual octagon, and the boundaries of at least two of the first to third subpixels each contact one or more sides of the virtual octagon.

Description

Technology Field

[0001] The present invention relates to a display device, and more specifically, to a display device capable of reducing the possibility of defects occurring during the manufacturing process. Background Technology

[0002] A display device has multiple pixels. For a full-color display device, the multiple pixels can emit light of different colors. To this end, at least some of the pixels of the display device have a color conversion unit. Accordingly, light of a first color generated from the light-emitting unit of some pixels passes through the corresponding color conversion unit, is converted into light of a second color, and is emitted externally. The problem to be solved

[0003] However, these conventional display devices had a problem in that there was a high possibility of defects occurring during the manufacturing process.

[0004] The present invention aims to solve various problems, including those mentioned above, by providing a display device capable of reducing the possibility of defects occurring during the manufacturing process. However, these problems are exemplary and do not limit the scope of the present invention. means of solving the problem

[0005] According to one aspect of the present invention, a display device is provided comprising a first substrate including a rectangular unit area and a first subpixel, a second subpixel, and a third subpixel spaced apart from each other and emitting different colors on the unit area, wherein the unit area includes a virtual octagon having sides that coincide with the center of the unit area and are spaced apart from the boundary of the unit area, and the first to third subpixels are located within the virtual octagon, and the boundaries of at least two of the first to third subpixels each touch one or more sides of the virtual octagon.

[0006] In one embodiment, the boundary of the first subpixel may be the first side of the virtual octagon, two sides of the virtual octagon adjacent to one side centered on the first side, and two sides of the virtual octagon adjacent to the other side of the first side.

[0007] In one embodiment, the boundary of the second subpixel may be in contact with the second side of the virtual octagon parallel to the first side, and two sides of the virtual octagon adjacent to one side of the second side, and the boundary of the third subpixel may be in contact with the second side and two sides of the virtual octagon adjacent to the other side of the second side.

[0008] In one embodiment, the boundary of the second subpixel is in contact with the second side of the virtual octagon parallel to the first side, two sides of the virtual octagon adjacent to one side of the second side, and two sides of the virtual octagon adjacent to the other side of the second side, and the third subpixel may be located between the first subpixel and the second subpixel.

[0009] In one embodiment, the virtual octagon has a third side and a fourth side perpendicular to the first side, and the boundary of the third subpixel can be in contact with the third side and the fourth side.

[0010] In one embodiment, the first to third subpixels are each provided in multiple quantities, and the unit area includes sub-unit areas that divide the virtual octagon into four parts, and on the first sub-unit area, a first subpixel whose boundary touches the first side of the virtual octagon, a second subpixel whose boundary touches the second side of the virtual octagon perpendicular to the first side, and a third subpixel disposed adjacent to the center of the virtual octagon are disposed, and the first to third subpixels disposed on the second sub-unit area are symmetrical to the first to third subpixels on the first sub-unit area with respect to a first center line extending in a first direction and passing through the center of the virtual octagon, and the first to third subpixels disposed on the third sub-unit area are symmetrical to the first to third subpixels on the first sub-unit area with respect to the center of the virtual octagon The first to third subpixels arranged on the fourth sub-unit area, which are point-symmetric, can be symmetric with respect to the first to third subpixels on the first sub-unit area with respect to a second center line that extends in a second direction perpendicular to the first direction and passes through the center of the virtual octagon.

[0011] In one embodiment, the first to third subpixels are each provided in multiple numbers, and the first side of the virtual octagon, the second side parallel to the first side, the third side perpendicular to the first side, and the fourth side may each be in contact with the boundary of any one of the first subpixels, the boundary of any one of the second subpixels, and the boundary of any one of the third subpixels.

[0012] In one embodiment, the plurality of first subpixels may be spaced apart along the diagonal direction of the unit area.

[0013] The above unit area has mutually spaced virtual first to third vertical lines passing through the virtual octagon in a first direction and virtual first to third horizontal lines passing through the virtual octagon in a second direction and virtual first to third horizontal lines passing through the virtual octagon in a second direction, wherein the first vertical line and the first horizontal line pass only through the first subpixel, the second vertical line and the second horizontal line pass only through the second subpixel, and the third vertical line and the third horizontal line pass only through the third subpixel.

[0014] In one embodiment, the display device further comprises a bank layer disposed on the unit area and including a first hole corresponding to the first subpixel, a second hole corresponding to the second subpixel, a third hole corresponding to the third subpixel, and auxiliary holes, a first quantum dot layer located within the first hole, and a second quantum dot layer located within the second hole, wherein at least some of the auxiliary holes may be along the first to third vertical lines or the first to third horizontal lines.

[0015] In one embodiment, some of the auxiliary holes may be placed in an area between two adjacent subpixels among the first to third subpixels.

[0016] In one embodiment, some of the auxiliary holes may be arranged along the boundary of the unit area.

[0017] In one embodiment, the first subpixel has a rectangular shape in which the major axis coincides with the first diagonal connecting the vertices of the unit area, the center of the second subpixel overlaps with the second diagonal connecting the vertices of the unit area, and the boundary of the second subpixel touches the first side of the virtual octagon, the center of the third subpixel overlaps with the second diagonal, and the boundary of the third subpixel touches the second side of the virtual octagon parallel to the first side.

[0018] In one embodiment, the boundary of the first subpixel is in contact with the third side of the virtual octagon and the fourth side of the virtual octagon parallel to the third side, and the third side and the fourth side may be perpendicular to the first diagonal.

[0019] In one embodiment, an imaginary line connecting the center of the second subpixel and the center of the third subpixel may be parallel to the second diagonal.

[0020] In one embodiment, a virtual line connecting the center of the second subpixel and the center of the third subpixel may intersect the second diagonal.

[0021] In one embodiment, the display device further comprises a pixel defining film disposed on the first substrate and having a first opening that exposes the central portion of the pixel electrode of the first subpixel, a second opening that exposes the central portion of the pixel electrode of the second subpixel, a third opening that exposes the central portion of the pixel electrode of the third subpixel, and a fourth opening having a center located on each vertex of the unit area; wherein the boundary of the first subpixel overlaps with the first opening, the boundary of the second subpixel overlaps with the second opening, and the boundary of the third subpixel overlaps with the third opening.

[0022] In one embodiment, the display device further comprises: a plurality of auxiliary electrodes disposed on the first substrate; a light-emitting layer disposed on the pixel electrode of the first subpixel, the pixel electrode of the second subpixel, and the pixel electrode of the third subpixel; an intermediate layer having contact holes that overlap with each of the fourth openings; and a counter electrode located on the intermediate layer; wherein the fourth openings and the contact holes expose a portion of each of the auxiliary electrodes, and the counter electrode can come into contact with the auxiliary electrodes through the fourth openings and the contact holes.

[0023] In one embodiment, the display device comprises a plurality of auxiliary wires disposed on the first substrate, a light-emitting layer disposed on the pixel electrode of the first subpixel, the pixel electrode of the second subpixel, and the pixel electrode of the third subpixel, and further comprises an intermediate layer having contact holes that overlap with each of the fourth openings, and a counter electrode located on the intermediate layer, wherein the fourth openings and the contact holes expose a portion of each of the auxiliary wires, and the counter electrode can come into contact with the auxiliary wires through the fourth openings and the contact holes.

[0024] In one embodiment, the area of ​​the first subpixel is larger than the area of ​​the second subpixel and the third subpixel, and the area of ​​the second subpixel may be equal to or larger than the area of ​​the third subpixel.

[0025] In one embodiment, the display device comprises a first substrate including a rectangular unit area, and a first subpixel, a second subpixel, and a third subpixel spaced apart from each other and emitting different colors on the unit area, wherein the first subpixel and the second subpixel are arranged along a first direction, and the second subpixel and the third subpixel may be arranged along a second direction perpendicularly intersecting the first direction.

[0026] In one embodiment, the pixel defining film is further included, disposed on the first substrate and having a first opening that exposes the central portion of the pixel electrode of the first subpixel, a second opening that exposes the central portion of the pixel electrode of the second subpixel, a third opening that exposes the central portion of the pixel electrode of the third subpixel, and a fourth opening that is inscribed with two adjacent sides of the unit area, wherein the first opening and the fourth opening may be disposed along the second direction.

[0027] In one embodiment, the display device includes first subpixels, second subpixels, and third subpixels that emit different colors and are spaced apart from each other on the first substrate, and when the first subpixels, second subpixels, and third subpixels are arranged in a matrix, each row of the matrix includes all of the first subpixels, second subpixels, and third subpixels, wherein the first subpixels and the third subpixels are spaced apart by one column, and each column of the matrix includes all of the first subpixels, second subpixels, and third subpixels, wherein the first subpixels and the second subpixels are spaced apart by one row.

[0028] In one embodiment, the spacing between first subpixels arranged in one row may be the same as the spacing between first subpixels arranged in one column.

[0029] Other aspects, features, and advantages other than those described above will become clear from the following drawings, claims, and detailed description of the invention. Effects of the invention

[0030] According to one embodiment of the present invention as described above, a display device capable of reducing the possibility of defects occurring during the manufacturing process can be implemented. Of course, the scope of the present invention is not limited by this effect. Brief explanation of the drawing

[0031] FIG. 1 is a cross-sectional view schematically illustrating a part of a display device according to one embodiment of the present invention. FIG. 2 is an equivalent circuit diagram of a pixel provided by a display device according to one embodiment of the present invention. FIG. 3 is a plan view schematically illustrating a part of the display device of FIG. 1 according to one embodiment. FIG. 4 is a plan view schematically illustrating a pixel defining film of the display device of FIG. 1. FIGS. 5a to 5c are cross-sectional views of a display device along the line II-II' of FIG. 3. FIGS. 6 to 8 are plan views schematically illustrating parts of the display device of FIG. 1 according to embodiments. FIG. 9 is a plan view schematically illustrating a part of the display device of FIG. 1 according to one embodiment. FIG. 10 is a plan view schematically illustrating a pixel defining film of the display device of FIG. 9. FIG. 11 is a plan view schematically illustrating a part of the display device of FIG. 1 according to one embodiment. FIG. 12 is a plan view schematically illustrating a part of the display device of FIG. 1 according to one embodiment. FIG. 13 is a plan view schematically illustrating the bank layer of the display device of FIG. 12. FIG. 14 is a cross-sectional view along the line III-III' of FIG. 12. FIG. 15 is a plan view schematically illustrating a part of the display device of FIG. 1 according to one embodiment, and FIG. 16 is a plan view schematically illustrating a bank layer of the display device of FIG. 15. FIGS. 17 to 19 are plan views schematically illustrating parts of the display device of FIG. 1 according to embodiments. FIG. 20 is a plan view schematically illustrating the bank layer of the display device of FIG. 19. FIG. 21 is a plan view schematically illustrating a part of the display device of FIG. 1 according to one embodiment. FIG. 22 is a plan view schematically illustrating a pixel defining film of the display device of FIG. 21. FIGS. 23 and 24 are plan views schematically illustrating parts of the display device of FIG. 1 according to embodiments. Specific details for implementing the invention

[0032] The present invention is capable of various modifications and may have various embodiments; specific embodiments are illustrated in the drawings and described in detail in the detailed description. The effects and features of the present invention, and the methods for achieving them, will become clear by referring to the embodiments described below in detail together with the drawings. However, the present invention is not limited to the embodiments disclosed below but can be implemented in various forms.

[0033] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. When describing with reference to the drawings, identical or corresponding components are given the same reference numerals, and redundant descriptions thereof will be omitted.

[0034] In this specification, terms such as first, second, etc. are used not in a limiting sense, but for the purpose of distinguishing one component from another.

[0035] In this specification, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0036] In this specification, terms such as "include" or "have" mean that the features or components described in the specification exist, and do not preclude the possibility that one or more other features or components may be added.

[0037] In this specification, when a part such as a film, region, or component is described as being on or above another part, it includes not only cases where it is immediately above the other part, but also cases where another film, region, or component is interposed therein.

[0038] In this specification, when it is stated that a membrane, region, component, etc. is connected, it includes cases where the membrane, region, or component is directly connected, or / or cases where other membranes, regions, or components are interposed between them to form an indirect connection. For example, when it is stated that a membrane, region, or component, etc. is electrically connected in this specification, it indicates cases where the membrane, region, or component, etc. are directly electrically connected, and / or cases where other membranes, regions, or components are interposed between them to form an indirect electrical connection.

[0039] In this specification, "A and / or B" indicates the case where it is A, B, or both A and B. And, "at least one of A and B" indicates the case where it is A, B, or both A and B.

[0040] In this specification, the x-axis, y-axis, and z-axis are not limited to three axes in an orthogonal coordinate system and may be interpreted in a broader sense that includes them. For example, the x-axis, y-axis, and z-axis may be orthogonal to each other, but they may also refer to different directions that are not orthogonal to each other.

[0041] Where any embodiment in this specification can be implemented differently, a specific process sequence may be performed differently from the order described. For example, two processes described consecutively may be performed substantially simultaneously or proceed in the reverse order of the order described.

[0042] In the drawings, the size of components may be exaggerated or reduced for convenience of explanation. For example, the size and thickness of each component shown in the drawings are depicted arbitrarily for convenience of explanation, so the present invention is not necessarily limited to what is illustrated.

[0043] FIG. 1 is a cross-sectional view schematically illustrating a part of a display device according to one embodiment of the present invention. For reference, FIG. 1 may be understood as a cross-section taken along line I-I' of FIG. 3.

[0044] The display device according to the present embodiment comprises a first substrate (100), a first subpixel (PX1), a second subpixel (PX2), a third subpixel (PX3) disposed on the first substrate (100), and a second substrate (400).

[0045] The first substrate (100) may include glass, metal, or polymer resin. The first substrate (100) may include polymer resins such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. Of course, the first substrate (100) may have a multilayer structure including two layers each containing such polymer resins and a barrier layer containing an inorganic material (such as silicon oxide, silicon nitride, silicon oxynitride, etc.) interposed between the layers, and various modifications are possible.

[0046] A first pixel electrode (311), a second pixel electrode (321), and a third pixel electrode (331) are located on the first substrate (100). Of course, in addition to the first pixel electrode (311), the second pixel electrode (321), and the third pixel electrode (331), a first thin-film transistor (210), a second thin-film transistor (220), and a third thin-film transistor (230) electrically connected to them may also be located on the first substrate (100). That is, as illustrated in FIG. 1, the first pixel electrode (311) may be electrically connected to the first thin-film transistor (210), the second pixel electrode (321) may be electrically connected to the second thin-film transistor (220), and the third pixel electrode (331) may be electrically connected to the third thin-film transistor (230). The first pixel electrode (311), the second pixel electrode (321), and the third pixel electrode (331) may be located on the planarization layer (140) described later, which is located on the first substrate (100).

[0047] The first thin-film transistor (210) may include a first semiconductor layer (211) comprising amorphous silicon, polycrystalline silicon, an organic semiconductor material, or an oxide semiconductor material, a first gate electrode (213), a first source electrode (215a), and a first drain electrode (215b). The first gate electrode (213) may include various conductive materials and may have various layered structures, for example, may include a Mo layer and an Al layer. In this case, the first gate electrode (213) may have a Mo / Al / Mo layered structure. Alternatively, the first gate electrode (213) may include a TiNx layer, an Al layer, and / or a Ti layer. The first source electrode (215a) and the first drain electrode (215b) may also include various conductive materials and may have various layered structures, for example, may include a Ti layer, an Al layer, and / or a Cu layer. In this case, the first source electrode (215a) and the first drain electrode (215b) may have a layered structure of Ti / Al / Ti.

[0048] In order to ensure insulation between the first semiconductor layer (211) and the first gate electrode (213), a gate insulating film (121) containing inorganic materials such as silicon oxide, silicon nitride, and / or silicon oxynitride may be interposed between the first semiconductor layer (211) and the first gate electrode (213). Additionally, an interlayer insulating film (131) containing inorganic materials such as silicon oxide, silicon nitride, and / or silicon oxynitride may be disposed on the upper portion of the first gate electrode (213), and the first source electrode (215a) and the first drain electrode (215b) may be disposed on such an interlayer insulating film (131). Insulating films containing inorganic materials in this manner may be formed through CVD (chemical vapor deposition) or ALD (atomic layer deposition). This is also true for the embodiments and variations thereof described below.

[0049] A buffer layer (110) containing an inorganic material such as silicon oxide, silicon nitride and / or silicon oxynitride may be interposed between the first thin-film transistor (210) of this structure and the first substrate (100). This buffer layer (110) may serve to increase the smoothness of the upper surface of the first substrate (100) or to prevent or minimize the penetration of impurities from the first substrate (100) into the first semiconductor layer (211) of the first thin-film transistor (210).

[0050] The second thin-film transistor (220) located in the second subpixel (PX2) may include a first semiconductor layer (221), a second gate electrode (223), a second source electrode (225a), and a second drain electrode (225b). The third thin-film transistor (230) located in the third subpixel (PX3) may include a third semiconductor layer (231), a third gate electrode (233), a third source electrode (235a), and a third drain electrode (235b). Since the structure of the second thin-film transistor (220) and the structure of the third thin-film transistor (230) are identical or similar to the structure of the first thin-film transistor (210) located in the first subpixel (PX1), a description thereof is omitted.

[0051] And a planarization layer (140) may be disposed on the first thin-film transistor (210). For example, when an organic light-emitting diode including a first pixel electrode (311) is disposed on the first thin-film transistor (210) as shown in FIG. 1, the planarization layer (140) can serve to generally planarize the upper surface of the protective film covering the first thin-film transistor (210). This planarization layer (140) may include organic materials such as acrylic, BCB (Benzocyclobutene), or HMDSO (hexamethyldisiloxane). Although the planarization layer (140) is shown as a single layer in FIG. 1, various variations are possible, such as it being a multi-layer.

[0052] An organic light-emitting diode may be positioned in the first subpixel (PX1), having a first pixel electrode (311), a counter electrode (305), and an intermediate layer (303) interposed between them and including a light-emitting layer. The first pixel electrode (311) is electrically connected to the first thin-film transistor (210) by contacting either the first source electrode (215a) or the first drain electrode (215b) through a contact hole formed in the planarization layer (140), etc., as shown in FIG. 1. The first pixel electrode (311) includes a transparent conductive layer formed of a transparent conductive oxide such as ITO, In2O3, or IZO, and a reflective layer formed of a metal such as Al or Ag. For example, the first pixel electrode (311) may have a three-layer structure of ITO / Ag / ITO.

[0053] An organic light-emitting element having a second pixel electrode (321), a counter electrode (305), and an intermediate layer (303) interposed between them and including a light-emitting layer may be located in the second subpixel (PX2). Additionally, an organic light-emitting element having a third pixel electrode (331), a counter electrode (305), and an intermediate layer (303) interposed between them and including a light-emitting layer may be located in the third subpixel (PX3). The second pixel electrode (321) is electrically connected to the second thin-film transistor (220) by contacting either the second source electrode (225a) or the second drain electrode (225b) through a contact hole formed in the planarization layer (140), etc. The third pixel electrode (331) is electrically connected to the third thin-film transistor (230) by contacting either the third source electrode (235a) or the third drain electrode (235b) through a contact hole formed in the planarization layer (140), etc. The description of the first pixel electrode (311) described above may be applied to the second pixel electrode (321) and the third pixel electrode (331).

[0054] As described above, the intermediate layer (303) including the light-emitting layer may be positioned not only on the first pixel electrode (311) of the first subpixel (PX1) but also on the second pixel electrode (321) of the second subpixel (PX2) and the third pixel electrode (331) of the third subpixel (PX3). This intermediate layer (303) may have a shape that is integral across the first pixel electrode (311), the second pixel electrode (321), and the third pixel electrode (331). In this case, the intermediate layer (303) may have a contact hole (303H) for electrically contacting the opposing electrode (305) and the auxiliary electrode (341), as shown in FIG. 5a. If necessary, the intermediate layer (303) may be patterned and positioned on the first pixel electrode (311), the second pixel electrode (321), and the third pixel electrode (331). In addition to the light-emitting layer, the intermediate layer (303) may also include a hole injection layer, a hole transport layer, and / or an electron transport layer as necessary. Some of the layers included in the intermediate layer (303) may have a shape that is integral across the first pixel electrode (311) to the third pixel electrode (331), while other layers may be patterned and positioned on the first pixel electrode (311), the second pixel electrode (321), and the third pixel electrode (331).

[0055] The light-emitting layer including the intermediate layer (303) can emit light of a wavelength belonging to a first wavelength band. The first wavelength band may be, for example, 450 nm to 495 nm.

[0056] The counter electrode (305) on the intermediate layer (303) may also have a shape that is integral across the first pixel electrode (311) to the third pixel electrode (331). The counter electrode (305) may include a transparent conductive layer formed of ITO, In2O3, or IZO, and may also include a semipermeable film containing a metal such as Al, Li, Mg, Yb, or Ag. For example, the counter electrode (305) may be a semipermeable film containing MgAg, AgYb, Yb / MgAg, or Li / MgAg.

[0057] A pixel defining film (150) may be disposed on the upper portion of the flattening layer (140). This pixel defining film (150) has openings corresponding to each pixel. That is, the pixel defining film (150) covers the edges of each of the first pixel electrode (311), the second pixel electrode (321), and the third pixel electrode (331), and has a first opening (151) that exposes the central portion of the first pixel electrode (311), a second opening (152) that exposes the central portion of the second pixel electrode (321), and a third opening (153) that exposes the central portion of the third pixel electrode (331). In this way, the pixel defining film (150) can serve to define subpixels. Additionally, as illustrated in FIG. 1, the pixel defining film (150) serves to prevent arcs from occurring at the edges of the first pixel electrode (311), the second pixel electrode (321), and the third pixel electrode (331) by increasing the distance between the edges of the first pixel electrode (311), the second pixel electrode (321), and the third pixel electrode (331) and the opposing electrode (305). Such a pixel defining film (150) may include, for example, an organic material such as polyimide or HMDSO (hexamethyldisiloxane).

[0058] As illustrated in FIG. 5a, the pixel defining film (150) may further include fourth openings (155) for the opposing electrode (305) and the auxiliary electrode (134) to come into contact. When viewed in a planar view, the contact hole (303H) of the intermediate layer (303) may overlap with the fourth opening (155) of the pixel defining film (150). The opposing electrode (305) receives additional power through the auxiliary electrode (134) to improve the reduction in brightness of pixels at intermediate points in a large-area display device.

[0059] The second substrate (400) is positioned on top of the first substrate (100) so that the first pixel electrode (311), the second pixel electrode (321), and the third pixel electrode (331), etc., are interposed between the second substrate (400) and the first substrate (100). The second substrate (400) may include glass or a polymer resin. The second substrate (400) may include a polymer resin such as, for example, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. Of course, the second substrate (400) may have various variations, such as having a multilayer structure including two layers each containing such a polymer resin and a barrier layer containing an inorganic material (such as silicon oxide, silicon nitride, silicon oxynitride) interposed between the layers. This second substrate (400) may have flexible or bendable properties.

[0060] A bank layer (500) is located on the lower surface (400b) of the second substrate (400) facing the direction (-z direction) of the first substrate (100). That is, the bank layer (500) is located between the second substrate (400) and the first substrate (100). The bank layer (500) includes first holes (501), second holes (502), third holes (503), and auxiliary holes (510).

[0061] The first hole (501) of the bank layer (500) corresponds to the first opening (151) of the pixel defining film (150), the second hole (502) of the bank layer (500) corresponds to the second opening (152) of the pixel defining film (150), and the third hole (503) of the bank layer (500) corresponds to the third opening (153) of the pixel defining film (150). That is, when viewed from a direction perpendicular to the upper surface (400a) of the second substrate (400) (z-axis direction), the first hole (501) of the bank layer (500) overlaps with the first opening (151) that exposes the first pixel electrode (311) of the pixel defining film (150), the second hole (502) of the bank layer (500) overlaps with the second opening (152) that exposes the second pixel electrode (321) of the pixel defining film (150), and the third hole (503) of the bank layer (500) overlaps with the third opening (153) that exposes the third pixel electrode (331) of the pixel defining film (150). Accordingly, when viewed from a direction perpendicular to the upper surface (400a) of the second substrate (400) (z-axis direction), the shape of the edge of each of the first hole (501) to the third hole (503) of the bank layer (500) may be identical or similar to the shape of the edge of the corresponding first opening (151) to the third opening (153) of the pixel defining film (150). Accordingly, the first hole (501) of the bank layer (500) corresponds to the first pixel electrode (311), the second hole (502) of the bank layer (500) corresponds to the second pixel electrode (321), and the third hole (503) of the bank layer (500) corresponds to the third pixel electrode (331).

[0062] The bank layer (500) can be formed from various materials, such as inorganic materials like silicon oxide, silicon nitride and / or silicon oxynitride. If necessary, the bank layer (500) may include a photoresist material, thereby allowing the bank layer (500) to be easily formed through processes such as exposure and development.

[0063] A first quantum dot layer (415) may be located within the first holes (501) of the bank layer (500). This first quantum dot layer (415) may overlap with the first pixel electrode (311) when viewed from a direction perpendicular to the upper surface (400a) of the second substrate (400) (z-axis direction). The first quantum dot layer (415) can convert light of a wavelength belonging to a first wavelength band passing through the first quantum dot layer (415) into light of a wavelength belonging to a second wavelength band. The second wavelength band may be, for example, 630 nm to 780 nm. Of course, the present invention is not limited thereto, and the wavelength band to which the wavelength to which the first quantum dot layer (415) converts belongs and the wavelength band to which the wavelength after conversion belongs may be modified differently.

[0064] The first quantum dot layer (415) may have a form in which quantum dots are dispersed within a resin. In this embodiment, the embodiments described below and variations thereof, the quantum dots refer to crystals of a semiconductor compound and may include any material capable of emitting light of various emission wavelengths depending on the size of the crystals. The diameter of these quantum dots may be, for example, approximately 1 nm to 10 nm.

[0065] Quantum dots can be synthesized by wet chemical processes, organometallic chemical vapor deposition (MOCVD), molecular beam epitaxy, or similar processes. A wet chemical process is a method of growing quantum dot crystals after mixing an organic solvent and a precursor material. In the case of wet chemical processes, the organic solvent naturally acts as a dispersant coordinated to the surface of the quantum dot crystals during crystal growth and controls crystal growth, making it easier than vapor deposition methods such as Metal Organic Chemical Vapor Deposition (MOCVD) or Molecular Beam Epitaxy (MBE). Furthermore, wet chemical processes are low-cost processes that allow for the control of quantum dot particle growth.

[0066] These quantum dots may include group III-VI semiconductor compounds, group II-VI semiconductor compounds, group III-V semiconductor compounds, group I-III-VI semiconductor compounds, group IV-VI semiconductor compounds, group IV elements or compounds, or any combination thereof.

[0067] Examples of group III-VI semiconductor compounds may include binary compounds such as GaS, GaSe, Ga2Se3, GaTe, InS, InSe, In2Se3, or InTe, ternary compounds such as InGaS3 or InGaSe3, or any combination thereof. Examples of group II-VI semiconductor compounds may include binary compounds such as CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnO, HgS, HgSe, HgTe, MgSe, or MgS, or CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, MgZnSe, or MgZnS It may include ternary compounds such as etc., quaternary compounds such as CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe, or HgZnSTe, or any combination thereof.

[0068] Examples of III-V semiconductor compounds may include binary compounds such as GaN, GaP, GaAs, GaSb, AlN, AlP, AlAs, AlSb, InN, InP, InAs, or InSb; ternary compounds such as GaNP, GaNAs, GaNSb, GaPAs, GaPSb, AlNP, AlNAs, AlNSb, AlPAs, AlPSb, InGaP, InNP, InAlP, InNAs, InNSb, InPAs, InPSb, or GaAlNP; quaternary compounds such as GaAlNAs, GaAlNSb, GaAlPAs, GaAlPSb, GaInNP, GaInNAs, GaInNSb, GaInPAs, GaInPSb, InAlNP, InAlNAs, InAlNSb, InAlPAs, or InAlPSb; or any combination thereof. Meanwhile, III-V semiconductor compounds may further include a Group II element. Examples of III-V semiconductor compounds containing additional group II elements may include InZnP, InGaZnP, or InAlZnP.

[0069] Examples of group I-III-VI semiconductor compounds may include ternary compounds such as AgInS, AgInS2, CuInS, CuInS2, CuGaO2, AgGaO2, or AgAlO2, or any combination thereof.

[0070] Examples of group IV-VI semiconductor compounds may include binary compounds such as SnS, SnSe, SnTe, PbS, PbSe, or PbTe; ternary compounds such as SnSeS, SnSeTe, SnSTe, PbSeS, PbSeTe, PbSTe, SnPbS, SnPbSe, or SnPbTe; quaternary compounds such as SnPbSSe, SnPbSeTe, or SnPbSTe; or any combination thereof.

[0071] Group IV elements or compounds may include single-element compounds such as Si or Ge, binary compounds such as SiC or SiGe, or any combination thereof.

[0072] Each element contained in polyelement compounds, such as binary, ternary, and quaternary compounds, can exist within the particle at a uniform or non-uniform concentration.

[0073] Meanwhile, quantum dots can have a single structure in which the concentration of each element contained within the quantum dot is uniform, or a core-shell dual structure. For example, the material contained in the core and the material contained in the shell may be different from each other. The shell of the quantum dot can serve as a protective layer to maintain semiconductor properties by preventing chemical degradation of the core, and / or as a charging layer to impart electrophoretic properties to the quantum dot. The shell can be a single layer or a multilayer. The interface between the core and the shell may have a concentration gradient in which the concentration of elements present in the shell decreases towards the center.

[0074] Examples of the shell of a quantum dot include oxides of metals or nonmetals, semiconductor compounds, or combinations thereof. Examples of oxides of metals or nonmetals may include binary compounds such as SiO2, Al2O3, TiO2, ZnO, MnO, Mn2O3, Mn3O4, CuO, FeO, Fe2O3, Fe3O4, CoO, Co3O4, or NiO, ternary compounds such as MgAl2O4, CoFe2O4, NiFe2O4, or CoMn2O4, or any combination thereof. Examples of semiconductor compounds may include group III-VI semiconductor compounds, group II-VI semiconductor compounds, group III-V semiconductor compounds, group I-III-VI semiconductor compounds, group IV-VI semiconductor compounds, or any combination thereof as described above. For example, the semiconductor compound may include CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnSeS, ZnTeS, GaAs, GaP, GaSb, HgS, HgSe, HgTe, InAs, InP, InGaP, InSb, AlAs, AlP, AlSb, or any combination thereof.

[0075] Quantum dots can have a full width of half maximum (FWHM) of the emission wavelength spectrum of about 45 nm or less, specifically about 40 nm or less, and more specifically about 30 nm or less, and color purity or color reproducibility can be improved in this range. In addition, since the light emitted through these quantum dots is emitted in all directions, the wide viewing angle can be improved.

[0076] In addition, the shape of the quantum dots can specifically be spherical, pyramidal, multi-arm, or cubic, and can be in the form of nanoparticles, nanotubes, nanowires, nanofibers, or nanoplate particles.

[0077] By controlling the size of these quantum dots, the energy band gap can be controlled, allowing light of various wavelengths to be obtained from the quantum dot emissive layer. Therefore, by using quantum dots of different sizes, a light-emitting device that emits light of various wavelengths can be realized. Specifically, the size of the quantum dots can be selected to emit red, green, and / or blue light. Additionally, the size of the quantum dots can be configured to emit white light by combining light of various colors.

[0078] The first quantum dot layer (415) may include a scatterer. Incident light can be scattered by the scatterer included in the first quantum dot layer (415), thereby allowing the incident light to be efficiently converted by quantum dots within the first quantum dot layer (415). The scatterer is not particularly limited as long as it is a material capable of partially scattering transmitted light by forming an optical interface between the scatterer and the transparent resin, such as a metal oxide particle or an organic particle. Examples of metal oxides for the scatterer include titanium oxide (TiO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), indium oxide (In2O3), zinc oxide (ZnO), or tin oxide (SnO2), and examples of organic materials for the scatterer include acrylic resin or urethane resin. The scatterer can scatter light in various directions regardless of the angle of incidence without substantially changing the wavelength of the incident light. Through this, the scatterer can improve the side visibility of the display device. In addition, the scattering body included in the first quantum dot layer (415) can increase the light conversion efficiency by increasing the probability that incident light incident on the first quantum dot layer (415) meets the quantum dots.

[0079] Any material that is transparent and has excellent dispersion characteristics toward scatterers can be used as the resin included in the first quantum dot layer (415). For example, polymer resins such as acrylic resin, imide resin, epoxy resin, BCB (Benzocyclobutene), or HMDSO (hexamethyldisiloxane) can be used as the material for forming the first quantum dot layer (415). This material for forming the first quantum dot layer (415) can be positioned within the first hole (501) of the bank layer (500) overlapping with the first pixel electrode (311) through an inkjet printing method.

[0080] A second quantum dot layer (425) may be located within the second holes (502) of the bank layer (500). This second quantum dot layer (425) may overlap with the second pixel electrode (321) when viewed from a direction perpendicular to the upper surface (400a) of the second substrate (400) (z-axis direction). The second quantum dot layer (425) can convert light of a wavelength belonging to a first wavelength band passing through the second quantum dot layer (425) into light of a wavelength belonging to a third wavelength band. The third wavelength band may be, for example, 495 nm to 570 nm. Of course, the present invention is not limited thereto, and the wavelength band to which the wavelength to which the second quantum dot layer (425) converts belongs and the wavelength band to which the wavelength after conversion belongs may be modified differently.

[0081] The second quantum dot layer (425) may have a form in which quantum dots are dispersed within a resin. In this embodiment, the embodiments described below, and variations thereof, the quantum dots refer to crystals of a semiconductor compound and may include any material capable of emitting light of various emission wavelengths depending on the size of the crystals. The diameter of these quantum dots may be, for example, approximately 1 nm to 10 nm. Since the description of the quantum dots included in the first quantum dot layer (415) described above may apply to the quantum dots included in the second quantum dot layer (425), the description of the quantum dots included in the second quantum dot layer (425) is omitted.

[0082] The second quantum dot layer (425) may include a scatterer. Incident light can be scattered by the scatterer included in the second quantum dot layer (425), thereby allowing the incident light to be efficiently converted into quantum dots within the second quantum dot layer (425). The scatterer is not particularly limited as long as it is a material capable of partially scattering transmitted light by forming an optical interface between the scatterer and the transparent resin, for example, it may be a metal oxide particle or an organic particle. The metal oxide or organic material for the scatterer is as described above. The scatterer can scatter light in various directions regardless of the angle of incidence without substantially changing the wavelength of the incident light. Through this, the scatterer can improve the side visibility of the display device. In addition, the scatterer included in the second quantum dot layer (425) can increase the light conversion efficiency by increasing the probability that the incident light incident on the second quantum dot layer (425) meets the quantum dots.

[0083] Any material that is transparent and has excellent dispersion characteristics toward scatterers can be used as the resin included in the second quantum dot layer (425). For example, polymer resins such as acrylic resin, imide resin, epoxy resin, BCB (Benzocyclobutene), or HMDSO (hexamethyldisiloxane) can be used as the material for forming the second quantum dot layer (425). This material for forming the second quantum dot layer (425) can be positioned within the second hole (502) of the bank layer (500) overlapping with the second pixel electrode (321) through an inkjet printing method.

[0084] In the third subpixel (PX3), light of a wavelength belonging to the first wavelength band generated in the intermediate layer (303) including the light-emitting layer is emitted to the outside through the second substrate (400) without wavelength conversion. Therefore, the third subpixel (PX3) does not have a quantum dot layer. Thus, a light-transmitting layer (435) containing a light-transmitting resin may be located within the third hole (503) of the bank layer (500) that overlaps with the third pixel electrode (331). The light-transmitting layer (435) may include acrylic, BCB (Benzocyclobutene), or HMDSO (hexamethyldisiloxane). In addition, the light-transmitting layer (435) may also include a scatterer. Of course, depending on the case, the light-transmitting layer (435) may not exist within the third hole (503) of the bank layer (500), unlike what is shown in FIG. 1.

[0085] To protect the first quantum dot layer (415), the second quantum dot layer (425), and the light-transmitting layer (435), a protective layer (600) may be positioned in contact with the first substrate (100) direction surface of the first quantum dot layer (415), the second quantum dot layer (425), and the light-transmitting layer (435), as illustrated in FIGS. 1 and 4. This protective layer (600) may include an inorganic material such as silicon oxide or silicon nitride. For example, the protective layer (600) may have a two-layer structure including a silicon oxide layer and a silicon nitride layer.

[0086] As described above, the first quantum dot layer (415) and the second quantum dot layer (425) can be formed by an inkjet printing method. That is, after forming a bank layer (500) having a first hole (501), a second hole (502), and a third hole (503) on a second substrate (400), a material for forming the first quantum dot layer (415) can be dotted into the first hole (501) by an inkjet printing method, and a material for forming the second quantum dot layer (425) can be dotted into the second hole (502) by an inkjet printing method to form the first quantum dot layer (415) and the second quantum dot layer (425).

[0087] At this time, during the process of depositing the material for forming the first quantum dot layer (415) using an inkjet printing method, the material may not be located within the first hole (501), and during the process of depositing the material for forming the second quantum dot layer (425), the material may not be located within the second hole (502). In such cases, to reduce the probability that the material for forming the first quantum dot layer (415) is located within the second hole (502) or the third hole (503) and to reduce the probability that the material for forming the second quantum dot layer (425) is located within the first hole (501) or the third hole (503), the display device according to some embodiments may have auxiliary holes (510) in the bank layer (500) as shown in FIG. 13, FIG. 16 and FIG. 20.

[0088] FIG. 2 is an equivalent circuit diagram of a pixel provided by a display device according to one embodiment of the present invention.

[0089] Referring to FIG. 2, each pixel can be implemented by a pixel circuit (PC) connected to a scan line (SL) and a data line (DL), and an organic light-emitting diode (OLED) connected to the pixel circuit (PC). The pixel circuit (PC) may include a driving thin-film transistor (T1), a switching thin-film transistor (T2), a sensing thin-film transistor (T3), and a storage capacitor (Cst).

[0090] A scan line (SL) is connected to the gate electrode (G2) of a switching thin-film transistor (T2), a data line (DL) is connected to the source electrode (S2), and the first electrode (CE1) of a storage capacitor (Cst) can be connected to the drain electrode (D2).

[0091] Accordingly, the switching thin-film transistor (T2) can supply the data voltage of the data line (DL) to the first node (N) in response to the scan signal (Sn) from the scan line (SL) of each pixel.

[0092] The gate electrode (G1) of the driving thin-film transistor (T1) is connected to the first node (N), the source electrode (S1) is connected to a driving voltage line (PL) that transmits a driving voltage (ELVDD), and the drain electrode (D1) can be connected to a pixel electrode of an organic light-emitting diode (OLED).

[0093] Accordingly, the driving thin-film transistor (T1) can control the amount of current flowing through the organic light-emitting diode (OLED) according to its source-gate voltage (Vgs), that is, the voltage between the driving voltage (ELVDD) and the first node (N).

[0094] A sensing control line (SSL) may be connected to the gate electrode (G3) of a sensing thin-film transistor (T3), the source electrode (S3) may be connected to a second node (S), and the drain electrode (D3) may be connected to a reference voltage line (RL). In one embodiment, the sensing thin-film transistor (T3) may be controlled by the scan line (SL) instead of the sensing control line (SSL).

[0095] The sensing thin-film transistor (T3) can function to sense the potential of the first electrode (e.g., pixel electrode) of the organic light-emitting diode (OLED). The sensing thin-film transistor (T3) can supply a pre-charging voltage from the reference voltage line (RL) to the second node (S) in response to a sensing signal (SSn) from the sensing control line (SSL), or supply the voltage of the first electrode (e.g., pixel electrode) of the organic light-emitting diode (OLED) to the reference voltage line (RL) during the sensing period.

[0096] A storage capacitor (Cst) may have a first electrode (CE1) connected to a first node (N) and a second electrode (CE2) connected to a second node (S). The storage capacitor (Cst) can charge the difference voltage between the voltages supplied to the first and second nodes (N, S), respectively, and supply it as the driving voltage of a driving thin-film transistor (T1). For example, the storage capacitor (Cst) can charge the difference voltage between the data voltage (Dm) and the pre-charging voltage (Vpre) supplied to the first and second nodes (N, S), respectively.

[0097] The bias electrode (BSM) is formed to correspond to the driving thin-film transistor (T1) and can be connected to the source electrode (S3) of the sensing thin-film transistor (T3). Since the bias electrode (BSM) receives voltage linked to the potential of the source electrode (S3) of the sensing thin-film transistor (T3), the driving thin-film transistor (T1) can be stabilized. In one embodiment, the bias electrode (BSM) may not be connected to the source electrode (S3) of the sensing thin-film transistor (T3) but may be connected to a separate bias wiring.

[0098] The second electrode (e.g., cathode) of the organic light-emitting diode (OLED) can be provided with a common voltage (ELVSS). The organic light-emitting diode (OLED) can emit light by receiving a driving current from a driving thin-film transistor (T1).

[0099] FIG. 2 illustrates a case where signal lines (SL, SSL, DL), a reference voltage line (RL), and a driving voltage line (PL) are provided for each pixel, but the present invention is not limited thereto. For example, at least one of the signal lines (SL, SSL, DL), or / and the reference voltage line (RL) and the driving voltage line (PL) may be shared among neighboring pixels.

[0100] In addition, the pixel circuit (PC) is not limited to the number and circuit design of the thin-film transistors and storage capacitors described with reference to FIG. 2, and the number and circuit design can be varied.

[0101] FIG. 3 is a plan view schematically illustrating a part of the display device of FIG. 1 according to one embodiment.

[0102] FIG. 3 is a diagram for explaining the arrangement of the first subpixel (PX1), the second subpixel (PX2), and the third subpixel (PX3) when viewed from a direction (z direction) perpendicular to the upper surface (400a) of the second substrate (400).

[0103] Referring to FIG. 3, the first substrate (100) has a unit area (UA) having a square shape. Although FIG. 3 shows the unit area (UA) having a square shape, the unit area (UA) may have a rectangular or rhombus shape.

[0104] A unit area (UA) may include a virtual octagon (VO) having sides that coincide with the center of the unit area (UA) and are spaced inward from the boundary of the unit area (UA). In one embodiment, the first side (S1) of the virtual octagon (VO) may be parallel to one boundary of the unit area (UA). When each side of the virtual octagon (VO) is defined as the second through eighth sides in a clockwise direction with respect to the first side (S1), the third, fifth, and seventh sides may each be parallel to the remaining boundaries of the unit area (UA).

[0105] The first subpixel (PX1), the second subpixel (PX2), and the third subpixel (PX3) are placed on the unit area (UA) and may be located within a virtual octagon (VO).

[0106] The boundary of the first subpixel (PX1) may be in contact with the first side (S1) of the virtual octagon (VO), the second and third sides of the virtual octagon (VO) adjacent to the first side (S1) in a clockwise direction, and the seventh and eighth sides of the virtual octagon (VO) adjacent to the first side (S1) in a counterclockwise direction. In other words, the boundary of the first subpixel (PX1) may be in contact with five sides of the virtual octagon (VO) centered on the first side (S1).

[0107] The second subpixel (PX2) may be in contact with a part of the fifth side of the virtual octagon (VO) parallel to the first side (S1), and with the sixth and eighth sides of the virtual octagon (VO) adjacent to the fifth side in a clockwise direction. The third subpixel (PX3) may be in contact with a part of the fifth side of the virtual octagon (VO) parallel to the first side (S1), and with the fourth and third sides of the virtual octagon (VO) adjacent to the fifth side in a counterclockwise direction. For example, the second subpixel (PX2) and the third subpixel (PX3) may each be in contact with three sides of the virtual octagon (VO).

[0108] In one embodiment, the first subpixel (PX1) may emit light belonging to a second wavelength band, the second subpixel (PX2) may emit light of a third wavelength band, and the third subpixel (PX3) may emit light of a first wavelength band. For example, the first wavelength band may be 450 nm to 495 nm, the second wavelength band may be 630 nm to 780 nm, and the third wavelength band may be 495 nm to 570 nm. At this time, the area of ​​the first subpixel (PX1) may be equal to or larger than the area of ​​the second subpixel (PX2) and the area of ​​the third subpixel (PX3), respectively, and the area of ​​the second subpixel (PX2) may be equal to or larger than the area of ​​the third subpixel (PX3). That is, the color combination of the display device can be optimized by adjusting the area ratio within the virtual octagon (VO) of the first subpixel (PX1), the second subpixel (PX2), and the third subpixel (PX3).

[0109] FIG. 4 is a plan view schematically illustrating a pixel defining film of the display device of FIG. 1, and FIG. 5a to 5c are cross-sectional views of the display device along line II-II' of FIG. 4. FIG. 5a to 5c are illustrated with the second substrate (400), the first quantum dot layer (415), the second quantum dot layer (425), the light-transmitting layer (435), the bank layer (500), and the protective layer (600) omitted for convenience of illustration.

[0110] Referring to FIG. 4, as described above, the pixel defining film (150) may further include a first opening (151), a second opening (152), and a third opening (153) that define a subpixel, and a fourth opening (155) for the opposing electrode (305, see FIG. 1) and an auxiliary electrode (134, see FIG. 1) to come into contact.

[0111] In one embodiment, the boundary of the first subpixel (PX1, see FIG. 3) may be the same or similar to the boundary of the first aperture (151), the boundary of the second subpixel (PX2, see FIG. 3) may be the same or similar to the boundary of the second aperture (152), and the boundary of the third subpixel (PX3, see FIG. 3) may be the same or similar to the boundary of the third aperture (153).

[0112] As described above, based on the first side (S1) of the virtual octagon (VO) parallel to one side boundary of the unit area (UA), each side of the virtual octagon (VO) can be defined as the second to eighth sides along a clockwise direction. At this time, the boundary of the first opening (151) may be in contact with the first side (S1) of the virtual octagon (VO), the second and third sides of the virtual octagon (VO) adjacent to one side of the first side (S1), and the eighth and seventh sides of the virtual octagon (VO) adjacent to the other side of the first side (S1). In other words, the boundary of the first opening (151) may be in contact with five sides of the virtual octagon (VO) centered on the first side (S1).

[0113] The fourth opening (155) may be positioned to overlap with each vertex of the unit area (UA). For example, the center of the fourth opening (155) may be positioned to overlap with each vertex of the unit area (UA). The fourth opening (155) may expose a portion of the auxiliary electrode (341) located below the pixel definition film (150).

[0114] Referring to FIGS. 5a and 5b, the auxiliary electrode (341) may be disposed between the planarization layer (140) and the pixel definition film (150). In one embodiment, the auxiliary electrode (341) may be disposed on the same layer as the first pixel electrode (311), the second pixel electrode (321), and the third pixel electrode (331). In one embodiment, the auxiliary electrode (341) includes a transparent conductive layer formed of a transparent conductive oxide such as ITO, In2O3, or IZO, and a reflective layer formed of a metal such as Al or Ag. For example, the auxiliary electrode (341) may have a three-layer structure of ITO / Ag / ITO.

[0115] As described above, the intermediate layer (303) may have a shape that is integral across the first pixel electrode (311, see FIG. 1), the second pixel electrode (321, see FIG. 3), and the third pixel electrode (331). Additionally, the intermediate layer (303) may have a shape that is integral across adjacent unit regions (UA). The intermediate layer (303) may have a contact hole (303H) that overlaps with the fourth opening (155). In one embodiment, the contact hole (303H) may be located overlapping with each vertex of the unit region (UA). The contact hole (303H) may expose a portion of the auxiliary electrode (341).

[0116] The counter electrode (305) can be electrically connected to the auxiliary electrode (341) through the contact hole (303H) and the fourth opening (155) of the intermediate layer (303). The auxiliary electrode (341) supplies additional power to the counter electrode (305) to improve the reduction in brightness of pixels at intermediate points in a large-area display device.

[0117] As illustrated in FIG. 5b, the auxiliary electrode (341) can be electrically connected to an auxiliary wiring (217) disposed between the interlayer insulating film (131) and the planarization layer (140). For example, the auxiliary wiring (217) can be disposed on the same layer as the first source electrode (215a) and the first drain electrode (215b) of the first thin-film transistor (210). The auxiliary wiring (217) can supply additional power to the auxiliary electrode (341).

[0118] In another embodiment, as shown in FIG. 5c, the auxiliary electrode (341) may be omitted. For example, the flattening layer (140) may have an opening or hole that overlaps with the fourth opening (155), and the opposing electrode (305) may come into direct contact with the auxiliary wiring (217) through the opening or hole of the flattening layer (140).

[0119] Each of the four sides of the virtual octagon (VO) facing each vertex of the unit area (UA) can be defined by being spaced apart from the center of the fourth opening (155) by a predetermined distance. Accordingly, by forming the boundary of the virtual octagon (VO) to be in contact with the boundary of the first opening (151) to the third opening (153), space is secured to prevent adjacent subpixels from being damaged by the laser drilling process for forming the contact hole (303H), and the aperture ratio of the pixel can be optimized.

[0120] FIGS. 6 to 8 are plan views schematically illustrating parts of the display device of FIG. 1 according to embodiments.

[0121] FIGS. 6 to 8 are plan views illustrating various embodiments similar to FIG. 3, but with different shapes of the virtual octagon (VO) and arrangements of the first subpixel (PX1), second subpixel (PX2), and third subpixel (PX3). Hereinafter, redundant descriptions of identical or corresponding components will be omitted.

[0122] Referring to FIG. 6, the lengths of each side of the virtual octagon (VO) may differ. For example, the length of the first side (S1) of the virtual octagon (VO) parallel to one side boundary of the unit area (UA) and the length of the second side (S2) facing one vertex of the unit area (UA) may differ from each other. In one embodiment, as shown in FIG. 6, the lengths of the first side (S1), the third side, the fifth side, and the seventh side may be equal to or longer than the lengths of the second side (S2), the fourth side, the sixth side, and the eighth side. In another embodiment, the lengths of the first side (S1), the third side, the fifth side, and the seventh side may be shorter than the lengths of the second side (S2), the fourth side, the sixth side, and the eighth side.

[0123] In the corresponding area between the first subpixel (PX1) and the second subpixel (PX2), a partition is located that separates the first opening (151) and the second opening (152) in the pixel defining film (150). In one embodiment, the partition may pass through the center of a virtual octagon (VO). In another embodiment, it may be located spaced apart from a first center line (CL1) that extends in the second direction (x direction) from the center of the virtual octagon (VO) in the first direction (y direction) or in the opposite direction (-y direction) of the first direction (y direction).

[0124] In one embodiment, a partition separating the second opening (152) and the third opening (153) in the pixel defining film (150) is located in the area between the second subpixel (PX2) and the third subpixel (PX3), and the extension of the partition may pass through the center of the virtual octagon (VO). In another embodiment, the partition may be located spaced apart from the second center line (CL2), which extends in the first direction (y direction) from the center of the virtual octagon (VO), in the second direction (x direction) or in the opposite direction (-x direction). In this way, by adjusting the area ratio of the first subpixel (PX1), the second subpixel (PX2), and the third subpixel (PX3) within the virtual octagon (VO), the color combination of the display device can be optimized.

[0125] Referring to FIG. 7, in one embodiment, the boundary of the first subpixel (PX1) is parallel to the boundary of the unit area (UA) and may be in contact with the first side (S1) of the virtual octagon (VO) extended in the first direction (y direction), and the second, third, fourth, and fifth sides adjacent to the first side (S1) in a clockwise direction. The boundary of the second subpixel (PX2) may be in contact with the first side (S1) of the virtual octagon (VO), and the eighth and seventh sides adjacent to the first side (S1) in a counterclockwise direction. The boundary of the third subpixel (PX3) may be in contact with the fifth side of the virtual octagon (VO), and the sixth and seventh sides adjacent to the fifth side in a clockwise direction. In other words, the arrangement of the first subpixel (PX1), the second subpixel (PX2), and the third subpixel (PX3) shown in FIG. 7 may be the arrangement of the first subpixel (PX1), the second subpixel (PX2), and the third subpixel (PX3) shown in FIG. 6 rotated 90 degrees clockwise.

[0126] In another embodiment, the arrangement of the first subpixel (PX1), the second subpixel (PX2), and the third subpixel (PX3) may be rotated 180 degrees clockwise or 270 degrees clockwise from the arrangement of the first subpixel (PX1), the second subpixel (PX2), and the third subpixel (PX3) shown in FIG. 6.

[0127] In another embodiment, the arrangement of the first subpixel (PX1), the second subpixel (PX2), and the third subpixel (PX3) may be symmetrical to the arrangement of the first subpixel (PX1), the second subpixel (PX2), and the third subpixel (PX3) shown in FIG. 6 with respect to a straight line extending in the first direction (y direction) through the center of the virtual octagon (VO).

[0128] In another embodiment, the arrangement of the first subpixel (PX1), the second subpixel (PX2), and the third subpixel (PX3) may be symmetrical to the arrangement of the first subpixel (PX1), the second subpixel (PX2), and the third subpixel (PX3) shown in FIG. 6 with respect to a straight line extending in the second direction (x direction) through the center of the virtual octagon (VO).

[0129] Referring to FIG. 8, the boundary of the first subpixel (PX1) may be in contact with the first side (S1) of the virtual octagon (VO), and the eighth, seventh, sixth, and fifth sides adjacent to the first side (S1) in a counterclockwise direction. The boundary of the third subpixel (PX3) may be in contact with the first side (S1) of the virtual octagon (VO), and the second, third, fourth, and fifth sides adjacent to the first side (S1) in a clockwise direction. The second subpixel (PX2) may be located between the first subpixel (PX1) and the third subpixel (PX3).

[0130] In other words, the partition separating the first opening (151) defining the boundary of the first subpixel (PX1) and the second opening (152) defining the boundary of the second subpixel (PX2) can divide a virtual octagon (VO) along the first direction (y direction). Likewise, the partition separating the second opening (152) defining the boundary of the second subpixel (PX2) and the third opening (153) defining the boundary of the third subpixel (PX3) can divide a virtual octagon (VO) along the first direction (y direction).

[0131] In one embodiment, the boundary of the second subpixel (PX2) may be in contact with the first side (S1) of the virtual octagon (VO) and the fifth side parallel to the first side (S1). In another embodiment, the boundary of the second subpixel (PX2) may not be in contact with any side of the virtual octagon (VO).

[0132] In FIG. 8, the second subpixel (PX2) is interposed between the first subpixel (PX1) and the third subpixel (PX3), but the first subpixel (PX1) may be arranged to be interposed between the second subpixel (PX2) and the third subpixel (PX3), or the third subpixel (PX3) may be arranged to be interposed between the first subpixel (PX1) and the second subpixel (PX2). Additionally, the arrangement of the first subpixel (PX1), the second subpixel (PX2), and the third subpixel (PX3) may be rotated 90 degrees clockwise, 180 degrees clockwise, or 270 degrees clockwise.

[0133] FIG. 9 is a plan view schematically illustrating a part of the display device of FIG. 1 according to one embodiment, and FIG. 10 is a plan view schematically illustrating a pixel defining film of the display device of FIG. 9.

[0134] Referring to FIG. 9, the unit area (UA) may have a virtual octagon (VO) and a first sub-area (SUA1), a second sub-area (SUA2), a third sub-area (SUA3), and a fourth sub-area (SUA4) that divide the virtual octagon (VO) into four parts. For example, the unit area (UA) may be divided into a first sub-area (SUA1), a second sub-area (SUA2), a third sub-area (SUA3), and a fourth sub-area (SUA4) by a first center line (CL1) that passes through the center of the virtual octagon (VO) and extends in a second direction (x direction), and a second center line (CL2) that passes through the center of the virtual octagon (VO) and extends in a first direction (y direction). The first sub-region (SUA1), the second sub-region (SUA2), the third sub-region (SUA3), and the fourth sub-region (SUA4) may each include a first sub-pixel (PX1), a second sub-pixel (PX2), and a third sub-pixel (PX3).

[0135] In one embodiment, the first side (S1) of a virtual octagon (VO) parallel to the boundary of a unit area (UA) may be divided equally by a first sub-area (SUA1) and a second sub-area (SUA2). Parts of the eighth and seventh sides adjacent to the first side (S1) in a counterclockwise direction may be located in the first sub-area (SUA1).

[0136] In one embodiment, a first subpixel (PX1) placed on a first sub-region (SUA1) may be positioned to be in contact with the seventh side of a virtual octagon (VO), and a third subpixel (PX3) may be positioned to be in contact with the first side (S1) of a virtual octagon (VO). A second subpixel (PX2) may be positioned adjacent to the center of the virtual octagon (VO) so as to be spaced apart from the first subpixel (PX1) and the third subpixel (PX3).

[0137] The arrangement of the first subpixel (PX1), the second subpixel (PX2), and the third subpixel (PX3) placed on the second sub-region (SUA2) can be symmetrical with respect to the second center line (CL2) and the arrangement of the first subpixel (PX1), the second subpixel (PX2), and the third subpixel (PX3) placed on the first sub-region (SUA1).

[0138] The arrangement of the first subpixel (PX1), the second subpixel (PX2), and the third subpixel (PX3) placed on the third sub-region (SUA3) can be line-symmetric with respect to the first center line (CL1) and the arrangement of the first subpixel (PX1), the second subpixel (PX2), and the third subpixel (PX3) placed on the first sub-region (SUA1).

[0139] The arrangement of the first subpixel (PX1), the second subpixel (PX2), and the third subpixel (PX3) placed on the fourth sub-region (SUA4) can be point-symmetric with respect to the center of the virtual octagon (VO) with respect to the arrangement of the first subpixel (PX1), the second subpixel (PX2), and the third subpixel (PX3) placed on the first sub-region (SUA1).

[0140] Referring to FIG. 10, the pixel defining film (150) may include first openings (151) corresponding to first subpixels (PX1), second openings (152) corresponding to second subpixels (PX2), third openings (153) corresponding to third subpixels (PX3), and fourth openings (155).

[0141] The first sub-region (SUA1), the second sub-region (SUA2), the third sub-region (SUA3), and the fourth sub-region (SUA4) may each have a first opening (151), a second opening (152), and a third opening (153).

[0142] A first opening (151) placed on the first sub-region (SUA1) may be positioned to be in contact with the seventh side of the virtual octagon (VO), and a third opening (153) may be positioned to be in contact with the first side (S1) of the virtual octagon (VO). A second opening (152) may be positioned adjacent to the center of the virtual octagon (VO) so as to be spaced apart from the first opening (151) and the third opening (153).

[0143] The arrangement of the first opening (151), the second opening (152), and the third opening (153) placed on the second sub-region (SUA2) can be symmetrical with respect to the second centerline (CL2) and the arrangement of the first opening (151), the second opening (152), and the third opening (153) placed on the first sub-region (SUA1).

[0144] The arrangement of the first opening (151), the second opening (152), and the third opening (153) placed on the third sub-region (SUA3) can be symmetric with respect to the first centerline (CL1) and the arrangement of the first opening (151), the second opening (152), and the third opening (153) placed on the first sub-region (SUA1).

[0145] The arrangement of the first opening (151), the second opening (152), and the third opening (153) placed on the fourth sub-region (SUA4) can be point-symmetric with respect to the center of the virtual octagon (VO) with respect to the arrangement of the first opening (151), the second opening (152), and the third opening (153) placed on the first sub-region (SUA1).

[0146] The fourth opening (155) may be positioned overlapping each vertex of the unit area (UA). In one embodiment, the center of the fourth opening (155) may be located overlapping each vertex of the unit area (UA). Thus, two sub-unit areas may be positioned between adjacent fourth openings (155).

[0147] FIG. 11 is a plan view schematically illustrating a part of the display device of FIG. 1 according to one embodiment.

[0148] Referring to FIG. 11, the unit area (UA) includes a virtual octagon (VO), and a plurality of first subpixels (PX1), second subpixels (PX2), and third subpixels (PX3) may be arranged within the virtual octagon (VO).

[0149] In one embodiment, the first subpixels (PX1), the second subpixels (PX2), and the third subpixel (PX3) may form a 3x3 matrix having three columns and three rows within a virtual octagon (VO). The first subpixel (PX1) located at (1M, 1N) may be in contact with the first side (S1) of the virtual octagon (VO), and the eighth and seventh sides adjacent to the first side (S1) in a counterclockwise direction. The second subpixel (PX2) located at (1M, 2N) may be in contact with the first side (S1) of the virtual octagon (VO). The third subpixel (PX3) located at (1M, 3N) may be in contact with the first side (S1) of the virtual octagon (VO), and the second and third sides adjacent to the first side (S1) in a clockwise direction.

[0150] The third subpixel (PX3) located at (2M, 1N) may be in contact with the seventh side of the virtual octagon (VO). The first subpixel (PX1) located at (2M, 2N) may not be in contact with any side of the virtual octagon (VO). The second subpixel (PX2) located at (2M, 3N) may be in contact with the third side of the virtual octagon (VO).

[0151] The second subpixel (PX2) located at (3M, 1N) can be in contact with the 5th, 6th, and 7th sides of the virtual octagon (VO). The third subpixel (PX3) located at (3M, 2N) can be in contact with the 5th side of the virtual octagon (VO). The first subpixel (PX1) located at (3M, 3N) can be in contact with the 3rd, 4th, and 5th sides of the virtual octagon (VO).

[0152] Any row forming the matrix may include all of the first subpixel (PX1), the second subpixel (PX2), and the third subpixel (PX3). Likewise, any column forming the matrix may include all of the first subpixel (PX1), the second subpixel (PX2), and the third subpixel (PX3). Both the second subpixel (PX2) and the third subpixel (PX3) may be arranged along each side of a virtual octagon (VO) parallel to each boundary of the unit area (UA). Thus, the phenomenon in which mixed colors of R / B, R / G, or G / B are visible at the boundary of the unit area (UA) when the display device is driven in black and white can be reduced.

[0153] FIG. 12 is a plan view schematically illustrating a part of the display device of FIG. 1 according to one embodiment, and FIG. 13 is a plan view schematically illustrating a bank layer of the display device of FIG. 12. FIG. 14 is a cross-sectional view along line III-III' of FIG. 12.

[0154] Referring to FIG. 12, the first substrate (100) has a unit area (UA) having a rectangular shape. Within the unit area (UA), a virtual octagon (VO) may be included, which has sides that coincide with the center of the unit area (UA) and are spaced inward from the boundary of the unit area (UA). In one embodiment, the first side (S1) of the virtual octagon (VO) may be parallel to one side boundary of the unit area (UA). When each side of the virtual octagon (VO) is defined as the second to eighth sides in a clockwise direction with respect to the first side (S1), the third, fifth, and seventh sides may each be parallel to the remaining boundaries of the unit area (UA).

[0155] A unit area (UA) may have virtual first vertical lines (VL1) to third vertical lines (VL3) that pass through a virtual octagon (VO) in a first direction (y direction) and are spaced apart from each other, and virtual first horizontal lines (HL1) to third horizontal lines (HL3) that pass through a virtual octagon (VO) in a second direction (x direction) and are spaced apart from each other.

[0156] The boundary of the first subpixel (PX1) may be in contact with the first side (S1) of the virtual octagon (VO), the second side adjacent clockwise from the first side (S1), and the eighth side adjacent counterclockwise from the first side (S1). At this time, the first subpixel (PX1) may overlap with one of the first vertical line (VL1), the second vertical line (VL2), and the third vertical line (VL3), and may not overlap with the others. Similarly, the first subpixel (PX1) may overlap with one of the first horizontal line (HL1), the second horizontal line (HL2), and the third horizontal line (HL3), and may not overlap with the others. For example, as shown in FIG. 12, the first subpixel (PX1) may overlap with the second vertical line (VL2) and the first horizontal line (HL1), and may not overlap with the remaining vertical lines and horizontal lines.

[0157] The boundary of the second subpixel (PX2) may be in contact with the fifth side parallel to the first side (S1) of the virtual octagon (VO), and the sixth and seventh sides adjacent to the fifth side in a clockwise direction. At this time, the second subpixel (PX2) may overlap with one of the first vertical line (VL1), the second vertical line (VL2), and the third vertical line (VL3), and not overlap with the others. Similarly, the second subpixel (PX2) may overlap with one of the first horizontal line (HL1), the second horizontal line (HL2), and the third horizontal line (HL3), and not overlap with the others. For example, as shown in FIG. 12, the second subpixel (PX2) may overlap with the first vertical line (VL1) and the third horizontal line (HL3), and not overlap with the remaining vertical and horizontal lines.

[0158] The boundary of the third subpixel (PX3) may be adjacent to the fourth side in a clockwise direction from the third side and the second side of the virtual octagon (VO). In this case, the third subpixel (PX3) may overlap with one of the first vertical line (VL1), the second vertical line (VL2), and the third vertical line (VL3), and not overlap with the others. Similarly, the third subpixel (PX3) may overlap with one of the first horizontal line (HL1), the second horizontal line (HL2), and the third horizontal line (HL3), and not overlap with the others. For example, as shown in FIG. 12, the third subpixel (PX3) may overlap with the third vertical line (VL3) and the second horizontal line (HL2), and not overlap with the remaining vertical lines and horizontal lines.

[0159] In other words, one vertical line and one horizontal line can be arranged to pass through only one subpixel. In one embodiment, the second vertical line (VL2) and the first horizontal line (HL1) may correspond to the movement line of the spray nozzle for forming the first quantum dot layer (415) by inkjet printing. The first vertical line (VL1) and the third horizontal line (HL3) may correspond to the movement line of the spray nozzle for forming the second quantum dot layer (425) by inkjet printing. The third vertical line (VL3) and the second horizontal line (HL2) may correspond to the movement line of the spray nozzle for forming the light-transmitting layer (435) by inkjet printing. Thus, mixing of colors in each subpixel due to mis-detection can be prevented when forming the first quantum dot layer (415), the second quantum dot layer (425), and the light-transmitting layer (435).

[0160] Referring to FIGS. 13 and 14, the bank layer (500) includes first holes (501), second holes (502), third holes (503) and auxiliary holes (510).

[0161] The first hole (501) of the bank layer (500) corresponds to the first opening (151) of the pixel defining film (150), the second hole (502) of the bank layer (500) corresponds to the second opening (152) of the pixel defining film (150), and the third hole (503) of the bank layer (500) corresponds to the third opening (153) of the pixel defining film (150). That is, when viewed from a direction perpendicular to the upper surface (400a) of the second substrate (400) (z-axis direction), the first hole (501) of the bank layer (500) overlaps with the first opening (151) that exposes the first pixel electrode (311) of the pixel defining film (150), the second hole (502) of the bank layer (500) overlaps with the second opening (152) that exposes the second pixel electrode (321) of the pixel defining film (150), and the third hole (503) of the bank layer (500) overlaps with the third opening (153) that exposes the third pixel electrode (331) of the pixel defining film (150). Accordingly, when viewed from a direction perpendicular to the upper surface (400a) of the second substrate (400) (z-axis direction), the shape of the edge of each of the first hole (501) to the third hole (503) of the bank layer (500) may be identical or similar to the shape of the edge of the corresponding first opening (151) to the third opening (153) of the pixel defining film (150). Accordingly, the first hole (501) of the bank layer (500) corresponds to the first pixel electrode (311), the second hole (502) of the bank layer (500) corresponds to the second pixel electrode (321), and the third hole (503) of the bank layer (500) corresponds to the third pixel electrode (331).

[0162] Auxiliary holes (510) may be placed between adjacent subpixels. In one embodiment, a first auxiliary hole (510a) may be placed between adjacent second holes (502) along a first vertical line (VL1). A second auxiliary hole (510b) may be placed between adjacent first holes (501) along a second vertical line (VL2). A third auxiliary hole (510c) may be placed between adjacent third holes (503) along a third vertical line (VL3). Fourth auxiliary holes (510d) may be placed along a boundary extending in the first direction (y direction) of a unit area (UA). When no material is present within the auxiliary holes (510), the protective layer (600) may be in contact with the inner and bottom surfaces of the auxiliary holes (510), as illustrated in FIG. 14.

[0163] In the process of dotting a material for forming a first quantum dot layer (415) using an inkjet printing method, the material may not be located within the first hole (501), and in the process of dotting a material for forming a second quantum dot layer (425), the material may not be located within the second hole (502). In such cases, to reduce the probability that the material for forming the first quantum dot layer (415) is located within the second hole (502) or the third hole (503), and to reduce the probability that the material for forming the second quantum dot layer (425) is located within the first hole (501) or the third hole (503), the display device according to the present embodiment has a bank layer (500) having auxiliary holes (510).

[0164] Accordingly, during the process of dotting a material for forming a first quantum dot layer (415) using an inkjet printing method, even if the material is not located within the first hole (501), the material is positioned within the auxiliary hole (510), thereby reducing the probability that the material is located in the second hole (502) or the third hole (503). Additionally, during the process of dotting a material for forming a second quantum dot layer (425) using an inkjet printing method, even if the material is not located within the second hole (502), the material is positioned within the auxiliary hole (510), thereby reducing the probability that the material is located in the first hole (501) or the third hole (503).

[0165] FIG. 15 is a plan view schematically illustrating a part of the display device of FIG. 1 according to one embodiment, and FIG. 16 is a plan view schematically illustrating a bank layer of the display device of FIG. 15.

[0166] In FIG. 15, the unit area (UA) may have virtual first vertical lines (VL1) to third vertical lines (VL3) that pass through the virtual octagon (VO) in the first direction (y direction) and are spaced apart from each other, and virtual first horizontal lines (HL1) to third horizontal lines (HL3) that pass through the virtual octagon (VO) in the second direction (x direction) and are spaced apart from each other, similar to FIG. 12.

[0167] The boundary of the first subpixel (PX1) may be in contact with the first side (S1) of the virtual octagon (VO), and the second and third sides adjacent to the first side (S1) in a clockwise direction. At this time, the first subpixel (PX1) may overlap with one of the first vertical line (VL1), the second vertical line (VL2), and the third vertical line (VL3), and may not overlap with the others. Similarly, the first subpixel (PX1) may overlap with one of the first horizontal line (HL1), the second horizontal line (HL2), and the third horizontal line (HL3), and may not overlap with the others. For example, as shown in FIG. 12, the first subpixel (PX1) may overlap with the third vertical line (VL3) and the first horizontal line (HL1), and may not overlap with the remaining vertical and horizontal lines.

[0168] The boundary of the second subpixel (PX2) may be tangent to the seventh side of the virtual octagon (VO). In this case, the second subpixel (PX2) may overlap with one of the first vertical line (VL1), the second vertical line (VL2), and the third vertical line (VL3), and not overlap with the others. Similarly, the second subpixel (PX2) may overlap with one of the first horizontal line (HL1), the second horizontal line (HL2), and the third horizontal line (HL3), and not overlap with the others. For example, as shown in FIG. 12, the second subpixel (PX2) may overlap with the first vertical line (VL1) and the second horizontal line (HL2), and not overlap with the remaining vertical and horizontal lines.

[0169] The boundary of the third subpixel (PX3) may be tangent to the fifth side of the virtual octagon (VO). In this case, the third subpixel (PX3) may overlap with one of the first vertical line (VL1), the second vertical line (VL2), and the third vertical line (VL3), and not overlap with the others. Similarly, the third subpixel (PX3) may overlap with one of the first horizontal line (HL1), the second horizontal line (HL2), and the third horizontal line (HL3), and not overlap with the others. For example, as shown in FIG. 12, the third subpixel (PX3) may overlap with the second vertical line (VL2) and the third horizontal line (HL3), and not overlap with the remaining vertical lines and horizontal lines.

[0170] In other words, one vertical line and one horizontal line may be arranged to pass through only one subpixel. In one embodiment, the third vertical line (VL3) and the first horizontal line (HL1) may correspond to the movement line of the spray nozzle for forming the first quantum dot layer (415) by inkjet printing. The first vertical line (VL1) and the first horizontal line (HL1) may correspond to the movement line of the spray nozzle for forming the second quantum dot layer (425) by inkjet printing. The second vertical line (VL2) and the third horizontal line (HL3) may correspond to the movement line of the spray nozzle for forming the light-transmitting layer (435) by inkjet printing.

[0171] Referring to FIG. 16, the bank layer (500) includes first holes (501), second holes (502), third holes (503) and auxiliary holes (520).

[0172] The first hole (501) of the bank layer (500) corresponds to the first opening (151) of the pixel defining film (150), the second hole (502) of the bank layer (500) corresponds to the second opening (152) of the pixel defining film (150), and the third hole (503) of the bank layer (500) corresponds to the third opening (153) of the pixel defining film (150). That is, when viewed from a direction perpendicular to the upper surface (400a) of the second substrate (400) (z-axis direction), the first hole (501) of the bank layer (500) overlaps with the first opening (151) that exposes the first pixel electrode (311) of the pixel defining film (150), the second hole (502) of the bank layer (500) overlaps with the second opening (152) that exposes the second pixel electrode (321) of the pixel defining film (150), and the third hole (503) of the bank layer (500) overlaps with the third opening (153) that exposes the third pixel electrode (331) of the pixel defining film (150). Accordingly, when viewed from a direction perpendicular to the upper surface (400a) of the second substrate (400) (z-axis direction), the shape of the edge of each of the first hole (501) to the third hole (503) of the bank layer (500) may be identical or similar to the shape of the edge of the corresponding first opening (151) to the third opening (153) of the pixel defining film (150). Accordingly, the first hole (501) of the bank layer (500) corresponds to the first pixel electrode (311), the second hole (502) of the bank layer (500) corresponds to the second pixel electrode (321), and the third hole (503) of the bank layer (500) corresponds to the third pixel electrode (331).

[0173] Auxiliary holes (520) may be placed between adjacent subpixels. In one embodiment, the first auxiliary hole (520a) may be placed overlapping the boundary of a unit area (UA) parallel to the second direction (x direction). The second auxiliary hole (520b) may be placed overlapping the boundary of a unit area (UA) parallel to the first direction (y direction). The third auxiliary hole (520c) may be placed overlapping the first horizontal line (HL1). The fourth auxiliary hole (520d) may be placed along the second direction (x direction) in the area between the first hole (501) and the second hole (502). The fifth auxiliary hole (520e) may be placed along the second direction (x direction) in the area between the first hole (501) and the third hole (503). The fifth auxiliary hole (520e) may be placed overlapping the second horizontal line (HL2). The sixth auxiliary hole (520f) may be placed along the second direction (x direction) in the area between the second hole (502) and the third hole (503). The seventh auxiliary hole (520g) may be placed in the area between the second hole (502) and the third hole (503) and may be placed overlapping the intersection of the first vertical line (VL1) and the third horizontal line (HL3). In other embodiments, some of the auxiliary holes (520) may be omitted or additionally added, and their shapes may be modified.

[0174] By arranging the first subpixel (PX1), the second subpixel (PX2), and the third subpixel (PX3) in this manner, the aperture ratio of the subpixels is increased, and color mixing caused by misalignment or overflow of the first quantum dot layer (415), the second quantum dot layer (425), and the light-transmitting layer (435) can be prevented.

[0175] FIGS. 17 to 19 are plan views schematically illustrating a part of the display device of FIG. 1 according to embodiments, and FIG. 20 is a plan view schematically illustrating a bank layer of the display device of FIG. 19.

[0176] Referring to FIG. 17, the unit area (UA) may include a virtual octagon (VO) and a virtual first diagonal (DL1) and a second diagonal (DL2) that pass through the center of the virtual octagon (VO) and connect the vertices of the unit area (UA).

[0177] The first subpixel (PX1) and the second subpixel (PX2) may have their centers overlap with the first diagonal (DL1). For example, as shown in FIG. 17, the first subpixel (PX1) may have a rectangular shape in which the major axis overlaps with the first diagonal (DL1), or a rectangular shape in which the minor axis overlaps with the first diagonal (DL1). Similarly, the second subpixel (PX2) may have a rectangular shape in which the major axis overlaps with the first diagonal (DL1), or a rectangular shape in which the minor axis overlaps with the first diagonal (DL1). The third subpixel (PX3) may have a rectangular shape in which the major axis overlaps with the second diagonal (DL2).

[0178] When defining the second to eighth sides clockwise based on the first side (S1) of a virtual octagon (VO) parallel to one side of a unit area (UA), the boundary of the first subpixel (PX1) may be in contact with the fourth side, and the boundary of the second subpixel (PX2) may be in contact with the eighth side. The boundary parallel to the short side of the third subpixel (PX3) may be in contact with the second and sixth sides of the virtual octagon (VO). For example, the first subpixel (PX1), the second subpixel (PX2), and the third subpixel (PX3) may be arranged in an X shape within the virtual octagon (VO).

[0179] In another embodiment, the first subpixel (PX1) may have a circular, elliptical, or polygonal shape that is in contact with the fourth side, and the second subpixel (PX2) may have a circular, elliptical, or polygonal shape that is in contact with the eighth side. Likewise, the third subpixel (PX3) may have an elliptical or polygonal shape in which the major axis overlaps with the second diagonal (DL2).

[0180] The distance from the center of the third subpixel (PX3) to the center of the first subpixel (PX1) and the distance from the center of the third subpixel (PX3) to the center of the second subpixel (PX2) may be the same or different. The shortest distance from the center of the third subpixel (PX3) to the boundary of the first subpixel (PX1) and the shortest distance from the center of the third subpixel (PX3) to the boundary of the second subpixel (PX2) may be the same or different.

[0181] Referring to FIG. 18, one axis of the first subpixel (PX1) may be parallel to the first diagonal (DL1) but spaced apart. Similarly, one axis of the second subpixel (PX2) may be parallel to the first diagonal (DL1) but spaced apart. That is, the center of at least one of the first subpixel (PX1) and the second subpixel (PX2) may not be located on the first diagonal (DL1). Therefore, a straight line connecting the center of the first subpixel (PX1) and the center of the second subpixel (PX2) may intersect the first diagonal (DL1).

[0182] Referring to FIGS. 19 and 20, the third subpixel (PX3) has a long axis that overlaps with the second diagonal (DL2), similar to FIG. 17, but the boundary of the third subpixel (PX3) may not touch the second side and the sixth side.

[0183] Similar to FIGS. 12 and 15, the unit area (UA) may have virtual first vertical lines (VL1) to third vertical lines (VL3) spaced apart and passing through a virtual octagon (VO) in a first direction (y direction), and virtual first horizontal lines (HL1) to third horizontal lines (HL3) spaced apart and passing through a virtual octagon (VO) in a second direction (x direction).

[0184] At this time, the first subpixel (PX1), the second subpixel (PX2), and the third subpixel (PX3) may each overlap with any one of the first vertical line (VL1), the second vertical line (VL2), and the third vertical line (VL3), and may not overlap with the others. Likewise, the first subpixel (PX1), the second subpixel (PX2), and the third subpixel (PX3) may each overlap with any one of the first horizontal line (HL1), the second horizontal line (HL2), and the third horizontal line (HL3), and may not overlap with the others. For example, as illustrated in FIG. 12, the first subpixel (PX1) may overlap with the third vertical line (VL3) and the third horizontal line (HL3) and not overlap with the remaining vertical lines and horizontal lines, the second subpixel (PX2) may overlap with the second vertical line (VL2) and the second horizontal line (HL2) and not overlap with the remaining vertical lines and horizontal lines, and the third subpixel (PX3) may overlap with the first vertical line (VL1) and the first horizontal line (HL1) and not overlap with the remaining vertical lines and horizontal lines. In other words, one vertical line and one horizontal line may be arranged to pass through only one subpixel.

[0185] The bank layer (500) includes first holes (501), second holes (502), third holes (503) and auxiliary holes (510).

[0186] The first hole (501) of the bank layer (500) corresponds to the first opening (151) of the pixel defining film (150), the second hole (502) of the bank layer (500) corresponds to the second opening (152) of the pixel defining film (150), and the third hole (503) of the bank layer (500) corresponds to the third opening (153) of the pixel defining film (150). That is, when viewed from a direction perpendicular to the upper surface (400a) of the second substrate (400) (z-axis direction), the first hole (501) of the bank layer (500) overlaps with the first opening (151) that exposes the first pixel electrode (311) of the pixel defining film (150), the second hole (502) of the bank layer (500) overlaps with the second opening (152) that exposes the second pixel electrode (321) of the pixel defining film (150), and the third hole (503) of the bank layer (500) overlaps with the third opening (153) that exposes the third pixel electrode (331) of the pixel defining film (150). Accordingly, when viewed from a direction perpendicular to the upper surface (400a) of the second substrate (400) (z-axis direction), the shape of the edge of each of the first hole (501) to the third hole (503) of the bank layer (500) may be identical or similar to the shape of the edge of the corresponding first opening (151) to the third opening (153) of the pixel defining film (150). Accordingly, the first hole (501) of the bank layer (500) corresponds to the first pixel electrode (311), the second hole (502) of the bank layer (500) corresponds to the second pixel electrode (321), and the third hole (503) of the bank layer (500) corresponds to the third pixel electrode (331).

[0187] Auxiliary holes (530) may be placed between adjacent subpixels. In one embodiment, a first auxiliary hole (530a) may be placed between adjacent second holes (502) along a first vertical line (VL1). A second auxiliary hole (530b) may be placed between adjacent third holes (503) along a second vertical line (VL2). A third auxiliary hole (530c) may be placed between adjacent first holes (501) along a third vertical line (VL3). Fourth auxiliary holes (530d) may be placed along the first direction (y direction) boundary of a unit area (UA). As described above, these auxiliary holes (530) can serve to limit the position of the material dotted in the wrong location when the material for forming the first quantum dot layer (415) or the material for forming the second quantum dot layer (425) is dotted by inkjet printing and the material is not located within the intended opening.

[0188] FIG. 21 is a plan view schematically illustrating a part of the display device of FIG. 1 according to one embodiment. FIG. 22 is a plan view schematically illustrating a pixel defining film of the display device of FIG. 21.

[0189] The unit area (UA) of FIG. 21 does not include a virtual octagon, and differs from FIG. 3 in that the fourth opening (155) of the pixel defining film (150) overlapping with the contact hole (303H) of the intermediate layer (303) is located within the unit area (UA) rather than at the vertex of the unit area (UA). Below, redundant descriptions regarding identical components will be omitted, and the explanation will focus on the differences.

[0190] Referring to FIG. 21, the first substrate (100) includes a plurality of unit regions (UA), and a first subpixel (PX1), a second subpixel (PX2), and a third subpixel (PX3) may be disposed on each unit region (UA). The unit region (UA) may include an empty region (VA) where subpixels are not disposed.

[0191] In one embodiment, the second subpixel (PX2) and the third subpixel (PX3) may be arranged alternately along the first direction (y direction), and the second subpixel (PX2) and the first subpixel (PX1) may be arranged alternately along the second direction (x direction).

[0192] An empty region (VA) may be located between adjacent first subpixels (PX1) along the first direction (y direction). Similarly, an empty region (VA) may be located between adjacent third subpixels (PX3) along the second direction (x direction).

[0193] The area of ​​the first subpixel (PX1) may be equal to or larger than the area of ​​the second subpixel (PX2) and the area of ​​the third subpixel (PX3), respectively, and the area of ​​the second subpixel (PX2) may be equal to or larger than the area of ​​the third subpixel (PX3). That is, the color combination of the display device can be optimized by adjusting the area ratio of the first subpixel (PX1), the second subpixel (PX2), and the third subpixel (PX3).

[0194] Referring to FIG. 22, the pixel defining film (150) may include first openings (151) corresponding to first subpixels (PX1), second openings (152) corresponding to second subpixels (PX2), third openings (153) corresponding to third subpixels (PX3), and fourth openings (155) for the opposing electrode (305, see FIG. 1) and auxiliary electrode (134, see FIG. 1) to come into contact.

[0195] The empty area (VA) may be an area that overlaps with the fourth opening (155). The fourth opening (155) may be located inside the boundary of the unit area (UA). In one embodiment, the fourth opening (155) may be positioned to be in contact with two intersecting boundaries of the unit area (UA).

[0196] In one embodiment, the third opening (153) and the fourth opening (155) may be alternately arranged in the first M row, the second opening (152) and the first opening (151) may be alternately arranged in the second M row, the third opening (153) and the second opening (152) may be alternately arranged in the first N column, and the fourth opening (155) and the first opening (151) may be alternately arranged in the second N column.

[0197] In one embodiment, the boundary of the fourth opening (155) may be adjacent to the boundary of the unit area (UA). In one embodiment, the distance (d1) between the boundary of the fourth opening (155) and the boundary of the first opening (151) adjacent in the first direction (y direction) relative to the fourth opening (155), the distance (d2) between the boundary of the fourth opening (155) and the boundary of the third opening (153) adjacent in the second direction (x direction) relative to the fourth opening, the distance (d3) between the boundary of the fourth opening (155) and the boundary of the first opening (151) adjacent in the opposite direction (-y direction) relative to the fourth opening (155), and the distance (d4) between the boundary of the fourth opening (155) and the boundary of the third opening (153) adjacent in the opposite direction (-x direction) relative to the fourth opening (155) relative to the fourth opening (155) may be the same. By arranging the first to fourth apertures (151, 152, 153, 155) in this manner, the brightness of the subpixels can be maintained constant even in the center of the high-resolution display device, and the aperture ratio of each subpixel can be improved.

[0198] FIGS. 23 and 24 are plan views schematically illustrating parts of the display device of FIG. 1 according to embodiments.

[0199] Referring to FIG. 23, the first substrate (100) has a first unit area (UA1), a second unit area (UA2), a third unit area (UA3), and a fourth unit area (UA4), and the first unit area (UA1) to the fourth unit area (UA4) can form a single repeating area (RA).

[0200] A first subpixel (PX1), a second subpixel (PX2), and a third subpixel (PX) may be arranged on each of the first unit area (UA1) to the fourth unit area (UA4). Each of the first unit area (UA1) to the fourth unit area (UA4) may include an empty area (VA) where subpixels are not arranged. As described above, the empty area (VA) may be an area corresponding to the fourth opening (155) of the pixel defining film (150, see FIG. 5a).

[0201] In one embodiment, regions corresponding to the first subpixels (PX1), second subpixels (PX2), and third subpixels (PX3), and an empty region (VA) within a repeating region (RA) may be arranged to form a 4x4 matrix. For example, the third subpixel (PX3), second subpixel (PX2), first subpixel (PX1), and empty region (VA) may be arranged along the first M row, the first subpixel (PX1), empty region (VA), third subpixel (PX3), and second subpixel (PX2) may be arranged along the second M row, the second subpixel (PX2), third subpixel (PX3), empty region (VA), and first subpixel (PX1) may be arranged along the third M row, and the empty region (VA), first subpixel (PX1), second subpixel (PX2), and third subpixel (PX3) may be arranged along the fourth M row. Each row includes a first subpixel (PX1), a second subpixel (PX2), and a third subpixel (PX3), and the first subpixel (PX1) and the third subpixel (PX3) may be spaced apart by one column interval by an empty area (VA). Likewise, along the 1N column, the 3rd subpixel (PX3), the 1st subpixel (PX1), the 2nd subpixel (PX2) and the empty area (VA) are arranged, along the 2N column, the 2nd subpixel (PX2), the empty area (VA), the 3rd subpixel (PX3) and the 1st subpixel (PX1) are arranged, along the 3rd column, the 1st subpixel (PX1), the 3rd subpixel (PX3), the empty area (VA) and the 2nd subpixel (PX2) are arranged, and along the 4th column, the empty area (VA), the 2nd subpixel (PX2), the 1st subpixel (PX1), and the 3rd subpixel (PX3) may be arranged. Each column includes a first subpixel (PX1), a second subpixel (PX2), and a third subpixel (PX3), and the first subpixel (PX1) and the second subpixel (PX2) may be spaced apart by one row interval by an empty area (VA).

[0202] Two subpixels emitting a first color, one subpixel emitting a second color, and another subpixel emitting a third color may be arranged to surround an empty area (VA). Additionally, the first subpixel (PX1), the second subpixel (PX2), and the third subpixel (PX3) may all be arranged at either side boundary of the repeating area (RA) to reduce the phenomenon in which mixed colors of R / B, R / G, or G / B are visible when the display device is driven in black and white.

[0203] Referring to FIG. 24, the first substrate (100) may include a plurality of repeating regions. In one embodiment, the spacing (HI1) between first subpixels (PX1) arranged in one row is the same as the spacing (VI1) between first subpixels (PX1) arranged in one column, the spacing (HI2) between second subpixels (PX2) arranged in one row is the same as the spacing (VI2) between second subpixels (PX2) arranged in one column, and the spacing (HI3) between third subpixels (PX3) arranged in one row may be the same as the spacing (VI3) between third subpixels (PX3) arranged in one column.

[0204] The present invention has been described with reference to the embodiments illustrated in the drawings, but this is merely illustrative, and those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of the present invention should be determined by the technical spirit of the appended claims. Explanation of the symbols

[0205] 100: First substrate 110: Buffer layer 121: Gate insulating film 131: Interlayer insulating film 134: Auxiliary electrode 140: Planarization layer 150: Pixel defining layer 151, 152, 153, 155: 1st to 4th apertures 210: 1st thin-film transistor 220: 2nd thin-film transistor 230: Third thin-film transistor 303: Intermediate layer 303H: Contact hole 305: Counter electrode 311, 321, 331: 1st to 3rd pixel electrodes 341: Auxiliary electrode 400: Second substrate 415: 1st quantum dot layer 425: 2nd quantum dot layer 500: Bank layer 501, 502, 503: 1st to 3rd holes 510, 520, 530: Auxiliary Halls 600: Protection Layer

Claims

Claim 1 A display device comprising: a first substrate including a plurality of unit regions arranged in a first direction and a second direction intersecting the first direction and having a rectangular shape; and a unit pixel disposed in each of the plurality of unit regions; wherein each of the plurality of unit regions includes a virtual octagon having sides that coincide with the center of the corresponding unit region and are spaced apart from the boundaries of the unit regions adjacent to the corresponding unit region; and each of the plurality of unit pixels includes a first subpixel, a second subpixel, and a third subpixel located within the virtual octagon and emitting different colors, and the boundaries of at least two of the first to third subpixels each touch one or more sides of the virtual octagon. Claim 2 A display device according to claim 1, wherein the boundary of the first subpixel is in contact with the first side of the virtual octagon, two sides of the virtual octagon adjacent to one side centered on the first side, and two sides of the virtual octagon adjacent to the other side of the first side. Claim 3 A display device according to claim 2, wherein the boundary of the second subpixel is in contact with the second side of the virtual octagon parallel to the first side and two sides of the virtual octagon adjacent to one side of the second side, and the boundary of the third subpixel is in contact with the second side and two sides of the virtual octagon adjacent to the other side of the second side. Claim 4 A display device according to claim 2, wherein the boundary of the second subpixel is in contact with the second side of the virtual octagon parallel to the first side, two sides of the virtual octagon adjacent to one side of the second side, and two sides of the virtual octagon adjacent to the other side of the second side, and the third subpixel is located between the first subpixel and the second subpixel. Claim 5 A display device according to claim 4, wherein the virtual octagon has a third side and a fourth side perpendicular to the first side, and the boundary of the third subpixel is in contact with the third side and the fourth side. Claim 6 In claim 1, the first to third sub-pixels are each provided in a plurality, and each of the plurality of unit regions includes sub-unit regions that divide the virtual octagon into four parts, and on the first sub-unit region, a first sub-pixel whose boundary touches the first side of the virtual octagon, a second sub-pixel whose boundary touches the second side of the virtual octagon perpendicular to the first side, and a third sub-pixel disposed adjacent to the center of the virtual octagon are disposed, and the first to third sub-pixels disposed on the second sub-unit region are symmetrical to the first to third sub-pixels on the first sub-unit region with respect to a first center line extending in a first direction and passing through the center of the virtual octagon, and the first to third sub-pixels disposed on the third sub-unit region are symmetrical to the first sub-pixels on the first sub-unit region with respect to the center of the virtual octagon A display device in which the first to third subpixels arranged on the fourth sub-unit area are point-symmetric with the third subpixel, and are symmetric with the first to third subpixels on the first sub-unit area with respect to a second center line that extends in a second direction perpendicular to the first direction and passes through the center of the virtual octagon. Claim 7 A display device according to claim 1, wherein each of the first to third subpixels is provided in multiple numbers, and the first side of the virtual octagon, the second side parallel to the first side, the third side perpendicular to the first side, and the fourth side each touch the boundary of any one of the first subpixels, the boundary of any one of the second subpixels, and the boundary of any one of the third subpixels. Claim 8 A display device according to claim 7, wherein the plurality of first subpixels are spaced apart along the diagonal direction of the corresponding unit area. Claim 9 A display device according to claim 1, wherein each of the plurality of unit regions has a virtual first to third vertical line that passes through the virtual octagon in a first direction and is spaced apart from each other, and a virtual first to third horizontal line that passes through the virtual octagon in a second direction and is spaced apart from each other, wherein the first vertical line and the first horizontal line pass only through the first subpixel, the second vertical line and the second horizontal line pass only through the second subpixel, and the third vertical line and the third horizontal line pass only through the third subpixel. Claim 10 A display device according to claim 9, further comprising: a bank layer disposed on the plurality of unit regions and including a first hole corresponding to the first subpixel, a second hole corresponding to the second subpixel, a third hole corresponding to the third subpixel, and auxiliary holes; a first quantum dot layer located within the first hole; and a second quantum dot layer located within the second hole; wherein at least some of the auxiliary holes are disposed along the first to third vertical lines or the first to third horizontal lines. Claim 11 A display device according to claim 10, wherein some of the auxiliary holes are disposed in the area between two adjacent subpixels among the first subpixel to the third subpixel. Claim 12 A display device according to claim 10, wherein some of the auxiliary holes are arranged along the boundaries of the plurality of unit regions. Claim 13 A display device according to claim 1, wherein the first subpixel has a rectangular shape in which the major axis coincides with the first diagonal connecting the vertices of the unit area, the center of the second subpixel overlaps with the second diagonal connecting the vertices of the unit area, the boundary of the second subpixel touches the first side of the virtual octagon, the center of the third subpixel overlaps with the second diagonal, and the boundary of the third subpixel touches the second side of the virtual octagon parallel to the first side. Claim 14 A display device according to claim 13, wherein the boundary of the first subpixel is in contact with the third side of the virtual octagon and the fourth side of the virtual octagon parallel to the third side, and the third side and the fourth side are perpendicular to the first diagonal. Claim 15 A display device according to claim 13, wherein the imaginary line connecting the center of the second subpixel and the center of the third subpixel is parallel to the second diagonal. Claim 16 A display device according to claim 13, wherein the imaginary line connecting the center of the second subpixel and the center of the third subpixel intersects the second diagonal. Claim 17 A display device according to claim 1, further comprising: a pixel defining film disposed on the first substrate and having a first opening that exposes the central portion of the pixel electrode of the first subpixel, a second opening that exposes the central portion of the pixel electrode of the second subpixel, a third opening that exposes the central portion of the pixel electrode of the third subpixel, and a fourth opening having a center located on each vertex of the unit area; wherein the boundary of the first subpixel overlaps with the first opening, the boundary of the second subpixel overlaps with the second opening, and the boundary of the third subpixel overlaps with the third opening. Claim 18 A display device according to claim 17, further comprising: a plurality of auxiliary electrodes disposed on the first substrate; an intermediate layer having contact holes that overlap each of the fourth openings, the light-emitting layer disposed on the pixel electrode of the first subpixel, the pixel electrode of the second subpixel, and the pixel electrode of the third subpixel; and a counter electrode located on the intermediate layer, wherein the fourth openings and the contact holes expose a portion of each of the auxiliary electrodes, and the counter electrode contacts the auxiliary electrodes through the fourth openings and the contact holes. Claim 19 A display device according to claim 17, further comprising: a plurality of auxiliary wires disposed on the first substrate; an intermediate layer having contact holes that overlap each of the fourth openings, the light-emitting layer disposed on the pixel electrode of the first subpixel, the pixel electrode of the second subpixel, and the pixel electrode of the third subpixel; and a counter electrode located on the intermediate layer, wherein the fourth openings and the contact holes expose a portion of each of the auxiliary wires, and the counter electrode contacts the auxiliary wires through the fourth openings and the contact holes. Claim 20 A display device according to claim 1, wherein the area of ​​the first subpixel is larger than the area of ​​the second subpixel and the third subpixel, and the area of ​​the second subpixel is equal to or larger than the area of ​​the third subpixel. Claim 21 A display device comprising: a first substrate including a rectangular unit area divided into 2×2 sub-unit areas arranged to form a matrix along a first direction and a second direction intersecting the first direction; and a first sub-pixel, a second sub-pixel, and a third sub-pixel spaced apart from each other and emitting different colors on the unit area, wherein the first sub-pixel, the second sub-pixel, and the third sub-pixel are arranged in a one-to-one correspondence with each other in three different sub-unit areas. Claim 22 A display device according to claim 21, further comprising: a pixel defining film disposed on the first substrate and having a first opening that exposes the central portion of the pixel electrode of the first subpixel, a second opening that exposes the central portion of the pixel electrode of the second subpixel, a third opening that exposes the central portion of the pixel electrode of the third subpixel, and a fourth opening that is inscribed with two adjacent sides of the unit area; wherein the fourth opening is disposed in one sub-unit area excluding the three sub-unit areas in which the first subpixel, the second subpixel, and the third subpixel are disposed. Claim 23 A display device comprising: a first substrate; and first subpixels, second subpixels, and third subpixels spaced apart from each other and emitting different colors, wherein the first subpixels, second subpixels, and third subpixels are arranged in a matrix, and each row of the matrix has the first subpixel, second subpixel, and third subpixel arranged in a repeating sequence, wherein adjacent first subpixels and third subpixels are spaced apart by one column, and each column of the matrix has the first subpixel, third subpixel, and second subpixel arranged in a repeating sequence, wherein adjacent first subpixels and second subpixels are spaced apart by one row. Claim 24 A display device according to paragraph 23, wherein the spacing between first subpixels arranged in any row is the same as the spacing between first subpixels arranged in any column.

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