Power supply switch circuit and operating method thereof

Abstract

A power switch circuit and a method of operating the same may be disclosed. The power switch circuit may include a switch circuit comprising a first switch that switches supplying a first power voltage to a power terminal of a power amplifier, and a second switch that switches supplying a second power voltage to the power terminal; and a switch control unit that controls the switch circuit such that when the first switch is turned off and the second switch is turned on, the first and second switches are set to a state that is simultaneously on for a first period.

Description

Technology Field

[0001] This description relates to a power switch circuit and a method of operation thereof. Background Technology

[0002] As wireless communication standards evolve, multiple communication standards such as 2G, Wi-Fi, Bluetooth, 3G, 4G, and 5G are being used in a single device (e.g., a smartphone). As multiple communication standards are used in a single device, a power amplifier that outputs a transmission signal is also used for each communication standard. In other words, in order to output a signal suitable for multiple communication standards, multiple power amplifiers corresponding to multiple communication standards may be required.

[0003] Power amplifiers operate by receiving power from an external source, and generally, a separate Power Supply IC (Integrated Circuit) is used to supply power to a single power amplifier. For example, four Power Supply ICs are used to operate four power amplifiers. Among multiple communication standards, when one standard is in use, other standards may not be used simultaneously. For example, when the 4G communication standard is in use, the 3G communication standard may not be in use. Accordingly, it is necessary to effectively utilize Power Supply ICs corresponding to unused communication standards for other communication standards. The problem to be solved

[0004] According to at least one embodiment among the embodiments, a power switch circuit and a method of operation thereof are provided for switching at least two power voltages to supply power amplifiers.

[0005] According to at least one embodiment among the embodiments, a power switch circuit that stably supplies power voltage to a power amplifier and a method of operating the same are provided. means of solving the problem

[0006] According to one aspect, a power switch circuit may be provided. The power switch circuit may include a switch circuit comprising a first switch for switching to supply a first power voltage to a power terminal of a power amplifier, and a second switch for switching to supply a second power voltage to the power terminal, and a switch control unit for controlling the switch circuit such that when the first switch is turned off and the second switch is turned on, the first and second switches are set to a state that is simultaneously on for a first period.

[0007] The switch control unit above can delay the turn-off of the first switch during the first period to maintain the turn-on of the first switch.

[0008] During the first period above, the first power supply voltage and the second power supply voltage can be supplied simultaneously to the power terminal.

[0009] After the first period mentioned above, the first switch is set to an off state and the second switch is set to an on state, and the second power voltage can be supplied to the power terminal.

[0010] The switch control unit may include a delay circuit that delays a first logic signal controlling the first switch and a second logic signal controlling the second switch.

[0011] The above delay circuit may include a first delay circuit comprising a first delay element that delays the first logic signal and a first NAND gate that receives the first logic signal and the signal delayed by the first delay element, a second delay element that delays the second logic signal, and a second delay circuit comprising a second NAND gate that receives the second logic signal and the signal delayed by the second delay element.

[0012] The first and second delay elements may each include a resistor and a capacitor, and the first and second logic signals may be delayed in correspondence with a time constant value determined by the resistor and the capacitor.

[0013] The switch control unit may further include a logic circuit that generates the first and second logic signals, and a buffer circuit that converts a driving control signal for driving the first and second switches using the output signal of the delay circuit.

[0014] The above logic circuit may include a first NAND gate that receives a first bit for controlling the first switch and a second bit for controlling the second switch, a second NAND gate that receives the first bit and the output of the first NAND gate and outputs the first logic signal, and a third NAND gate that receives the second bit and the output of the first NAND gate and outputs the second logic signal.

[0015] Each of the first and second switches may include a p-type transistor and an n-type transistor connected in parallel with each other.

[0016] The above p-type transistor and the above n-type transistor can be turned on simultaneously and turned off simultaneously.

[0017] According to another aspect, a method of operation of a power switch circuit for selecting at least one of a first power supply voltage and a second power supply voltage and supplying it to a power terminal of a power amplifier may be provided. The method of operation may include the step of, in a first period, turning on a first switch that switches the first power supply voltage and turning off a second switch that switches the second power supply voltage to supply the first power supply voltage to the power terminal; in a second period, maintaining the turned-on state of the first switch and turning on the second switch to supply the first power supply voltage and the second power supply voltage simultaneously to the power terminal; and after the second period, turning off the first switch and maintaining the turned-on state of the second switch to supply the second power supply voltage to the power terminal.

[0018] In the second period above, the logic signal controlling the turn-off of the first switch may be delayed during the second period.

[0019] The logic signal can be delayed for the second period by means of a capacitor and a resistor that generate an RC time constant.

[0020] In the second period above, a voltage between the first power supply voltage and the second power supply voltage can be supplied to the power terminal.

[0021] Each of the first and second switches may include a p-type transistor and an n-type transistor connected in parallel with each other. Effects of the invention

[0022] According to at least one of the embodiments, the number of power circuits can be reduced by selectively providing a power voltage to a power amplifier through a power switch circuit.

[0023] According to at least one of the embodiments, the power voltage can be supplied continuously without interruption during the switching of the power switch circuit.

[0024] According to at least one of the embodiments, by configuring the switches of the power switch circuit with a p-type transistor and an n-type transistor connected in parallel with each other, the turn-on resistance can be kept low even over a wide input voltage range. Brief explanation of the drawing

[0025] FIG. 1 is a block diagram showing a transmitter system according to one embodiment. FIG. 2 is a diagram showing the connection relationship between a power switch circuit and a power amplifier according to one embodiment. Figure 3 is a diagram showing the internal configuration of the power switch circuit of Figure 2. FIG. 4 is a diagram showing a logic table according to one embodiment. FIG. 5 is a drawing specifically showing the internal configuration of a switch control unit according to one embodiment. FIG. 6 is a diagram showing a logic circuit according to one embodiment. Figure 7 shows the input / output logic table of the logic circuit of Figure 6. FIG. 8a shows a delay circuit according to one embodiment, and FIG. 8b is a graph showing the input / output signal timing of the delay circuit according to one embodiment. FIG. 9 shows an operation timing graph of a power switch circuit according to one embodiment. FIG. 10 is a diagram showing a power switch circuit according to another embodiment. FIG. 11 shows the turn-on resistance (R) of the transistor according to the power supply voltage (VCC). ON It is a graph representing ). Specific details for implementing the invention

[0026] Embodiments of the present invention are described below with reference to the attached drawings so that those skilled in the art can easily implement them. However, the present invention may be embodied in various different forms and is not limited to the embodiments described herein. Furthermore, in order to clearly explain the present invention in the drawings, parts unrelated to the explanation have been omitted, and similar parts throughout the specification are denoted by similar reference numerals.

[0027] Throughout the specification, when a part is described as being "coupled" with another part, this includes not only cases where they are "directly or physically coupled," but also cases where they are "indirectly or non-contact coupled" with another element in between.

[0028] Throughout the specification, when a part is described as being "connected" to another part, this includes not only cases where they are "directly or physically connected," but also cases where they are "indirectly or non-contactually connected" with other elements in between, or cases where they are "electrically connected."

[0029] Throughout the specification, RF signals may have a format according to any other wireless and wired protocols designated as Wi-Fi (IEEE 802.11 family, etc.), WiMAX (IEEE 802.16 family, etc.), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G and later, but are not limited thereto.

[0030] Furthermore, when it is stated that a part "includes" a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components.

[0031] FIG. 1 is a block diagram showing a transmitter system (1000) according to one embodiment.

[0032] As shown in FIG. 1, a transmitter system (1000) according to one embodiment may include first and second power circuits (100a, 100b), first and second power switch circuits (200a, 200b), and first to fourth power amplifiers (300a to 300d). FIG. 1 shows, as an example, a case in which the transmitter system (100) is composed of four power amplifiers and two associated power switch circuits, but the number of power amplifiers and power switch circuits may be changed.

[0033] The first power circuit (100a) generates and outputs a first power voltage (VCC1). According to one embodiment, the first power voltage (VCC1) may be applied to the power terminals of the first power amplifier (300a), the second power amplifier (300b), or the third power amplifier (300c). To support the APT mode (Average Power Tracking mode), the value of the first power voltage (VCC1) may vary according to the envelope of the signal input to the first power amplifier (300a), the second power amplifier (300b), or the third power amplifier (300c).

[0034] The second power circuit (100b) generates and outputs a second power voltage (VCC2). According to one embodiment, the second power voltage (VCC2) may be applied to the power terminals of the second power amplifier (300b), the third power amplifier (300c), or the fourth power amplifier (300d). To support the APT mode (Average Power Tracking mode), the value of the second power voltage (VCC2) may vary according to the envelope of the signal input to the second power amplifier (300b), the third power amplifier (300c), or the fourth power amplifier (300d).

[0035] Meanwhile, the first and second power circuits (100a, 100b) can each be implemented as a PM IC (Power Management Integrated Circuit).

[0036] The first power switch circuit (200a) receives a first power voltage (VCC1) from the first power circuit (100a) and receives a second power voltage (VCC2) from the second power circuit (100b). The first power switch circuit (200a) can select one of the received first and second power voltages (VCC1, VCC2) and output it to the power terminal of the second power amplifier (300b). For example, if the first power amplifier (300a) is not operating, the first power switch circuit (200a) can select the first power voltage (VCC1) and output it to the power terminal of the second power amplifier (300b). And, if the fourth power amplifier (300d) is not operating, the first power switch circuit (200a) can select the second power voltage (VCC2) and output it to the power terminal of the second power amplifier (300b).

[0037] The second power switch circuit (200b) receives a first power voltage (VCC1) from the first power circuit (100a) and receives a second power voltage (VCC2) from the second power circuit (100b). The second power switch circuit (200b) can select one of the received first and second power voltages (VCC1, VCC2) and output it to the power terminal of the third power amplifier (300c). For example, if the first power amplifier (300a) is not operating, the second power switch circuit (200b) can select the first power voltage (VCC1) and output it to the power terminal of the third power amplifier (300c). And, if the fourth power amplifier (300d) is not operating, the second power switch circuit (200b) can select the second power voltage (VCC2) and output it to the power terminal of the third power amplifier (300c).

[0038] The first power amplifier (300a) operates by receiving the first power voltage (VCC1) from the first power circuit (100a) and amplifies and outputs an input RF (radio frequency) signal. The input RF signal of the first power amplifier (300a) may be an RF signal for a first communication standard.

[0039] The second power amplifier (300b) operates by receiving a power voltage selected by the first power switch circuit (200a) (i.e., the first power voltage (VCC1) or the second power voltage (VCC2)) and amplifies and outputs an input RF signal. The input RF signal of the second power amplifier (300b) may be an RF signal for the second communication standard.

[0040] The third power amplifier (300c) operates by receiving a power voltage selected by the second power switch circuit (200b) (i.e., the first power voltage (VCC1) or the second power voltage (VCC2)) and amplifies and outputs an input RF signal. The input RF signal of the third power amplifier (300c) may be an RF signal for the third communication standard.

[0041] The fourth power amplifier (300d) operates by receiving the second power voltage (VCC2) from the second power circuit (100b) and amplifies and outputs an input RF (radio frequency) signal. The input RF signal of the fourth power amplifier (300d) may be an RF signal for the fourth communication standard.

[0042] Here, the first to fourth communication standards may be different communication standards and may be any one of 2G, WiFi, Bluetooth, 3G, 4G, and 5G. Meanwhile, the first to fourth communication standards may be communication standards that define different bands among 5G communication standards.

[0043] According to this embodiment, the number of power circuits can be reduced by sharing the power voltage through a power switch circuit. Generally, when there are four power amplifiers, four power circuits are used, but in FIG. 1, the number of power circuits can be reduced to two by using a power switch circuit. Below, the specific configuration and operation method of power switch circuits, such as the first and second power switch circuits (200a, 200b), will be described.

[0044] FIG. 2 is a diagram showing the connection relationship between a power switch circuit (200) and a power amplifier (300) according to one embodiment.

[0045] The power switch circuit (200) receives a first power voltage (VCC1) and a second power voltage (VCC2) as inputs, and selects one of the first and second power voltages (VCC1, VCC20) and outputs it to the power terminal (T_VCC) of the power amplifier (300). The power switch circuit (200) may be the first power switch circuit (200a) or the second power switch circuit (200b) of FIG. 1.

[0046] In FIGS. 1 and 2, the power switch circuit (200) is shown as receiving two power voltages, but it can receive at least two power voltages. At this time, the power switch circuit (200) can select one of the at least two power voltages.

[0047] The power amplifier (300) includes an input terminal (RFin), an output terminal (Rout), and a power supply terminal (T_VCC). An RF signal is input through the input terminal (RFin), and an amplified signal is output through the output terminal (Rout). A power supply voltage (VCC1 or VCC2) is applied through the power supply terminal (T_VCC), and the power amplifier (300) is operated by the applied power supply voltage (VCC1 or VCC2). The power amplifier (300) can be implemented as a transistor. If the power amplifier (300) is implemented as a Bipolar Junction Transistor (BJT), the input terminal (RFin) may be the base and the power supply terminal (T_VCC) may be the collector or emitter. Meanwhile, if the power amplifier (300) is implemented as a Field Effect Transistor (FET), the input terminal (RFin) may be the gate and the power supply terminal (T_VCC) may be the drain or source.

[0048] Meanwhile, the power switch circuit (200) and the power amplifier (300) of FIG. 2 can be combined to be implemented as a single power amplifier module.

[0049] Figure 3 is a diagram showing the internal configuration of the power switch circuit (200) of Figure 2.

[0050] As shown in FIG. 3, a power switch circuit (200) according to one embodiment may include a switch circuit (210) and a switch control unit (220). The switch circuit (210) includes a first switch (SW1) and a second switch (SW2). The first switch (SW1) switches to supply a first power voltage (VCC1) to the power terminal (T_VCC) of the power amplifier (300), and the second switch (SW2) switches to supply a second power voltage (VCC2) to the power terminal (T_VCC) of the power amplifier (300). The first switch (SW1) may be connected between the first power circuit (100a) and the power terminal (T_VCC) of the power amplifier (300), and the second switch (SW2) may be connected between the second power circuit (100b) and the power terminal (T_VCC) of the power amplifier (300).

[0051] The switch control unit (220) receives a bit signal (digital signal) from the outside and can generate a switching control signal (SW_CTRL) that switches the switch circuit (210) in response to the input bit signal. The generated switching control signal (SW_CTRL) is output to the switch circuit (210). Here, the bit signal input from the outside may be 2 bits. The switching control signal (SW_CTRL) includes a first switching control signal (SW1_CTRL) that controls the first switch (SW1) and a second switching control signal (SW2_CTRL) that controls the second switch (SW2).

[0052] When the first switching control signal (SW1_CTRL) is an ON control signal and the second switching control signal (SW2_CTRL) is an OFF control signal, the first switch (SW1) is turned ON and the second switch (SW2) is turned OFF. Accordingly, the first power supply voltage (VCC1) is applied to the power terminal (T_VCC) of the power amplifier (300) through the first switch (SW1).

[0053] When the first switching control signal (SW1_CTRL) is an OFF control signal and the second switching control signal (SW2_CTRL) is an ON control signal, the first switch (SW1) is turned off and the second switch (SW2) is turned on. Accordingly, the second power supply voltage (VCC2) is applied to the power terminal (T_VCC) of the power amplifier (300) through the second switch (SW2).

[0054] The first switching control signal (SW1_CTRL) and the second switching control signal (SW2_CTRL) may not simultaneously become ON control signals. That is, the case where the first and second switches (SW1, SW2) are turned on simultaneously may be prevented. Referring to FIG. 4 below, even when the bit signal is 11, the first and second switching control signals (SW1_CTRL, SW2_CTRL) may become OFF control signals. When the first and second switches (SW1, SW2) are turned on simultaneously, a current path may be formed from the first power circuit (100a) to the second power circuit (100b) or from the second power circuit (100b) to the first power circuit (100a). Accordingly, the first power circuit (100a) or the second power circuit (100b) may be damaged. To prevent this, according to one embodiment, the first and second switches (SW1, SW2) may not be turned on simultaneously.

[0055] FIG. 4 is a diagram showing a logic table according to one embodiment.

[0056] In FIG. 4, bit1 and bit2 are external bit signals input to the switch control unit (220). As shown in FIG. 4, when the external bit signal is 00 and 11, both the first and second switching control signals (SW1_CTRL, SW2_CTRL) are OFF control signals, and both the first and second switches (SW1, SW2) are in a turned-off state. The switch control unit (220) may include a logic circuit having a logic table as shown in FIG. 4, which will be explained in more detail below.

[0057] A power switch circuit (200) according to one embodiment can generate a switching control signal to instantaneously overlap two power voltages (VCC1, VCC2) when changing from a first power voltage (VCC1) that was applied to a power terminal (T_VCC) to a second power voltage (VCC2) that is applied to a power terminal (T_VCC). Additionally, the power switch circuit (200) can generate a switching control signal to instantaneously overlap two power voltages (VCC1, VCC2) when changing from a second power voltage (VCC2) that was applied to a power terminal (T_VCC) to a first power voltage (VCC1) that is applied to a power terminal (T_VCC). That is, the power switch circuit (200) generates a control signal so that when switching between two power voltages, the power voltage can be supplied to the power terminal (T_VCC) of the power amplifier (300) without interruption. This can be explained from the perspective of a switch as follows. Meanwhile, when the first switch (SW1) changes from a turned-on state to a turned-off state and the second switch (SW2) changes from a turned-off state to a turned-on state, the switch control unit (220) delays the turning off of the first switch (SW1) to create a period during which the first switch (SW1) and the second switch (SW2) are simultaneously turned on (hereinafter referred to as the "overlapping on period"). Also, when the second switch (SW2) changes from a turned-on state to a turned-off state and the first switch (SW1) changes from a turned-off state to a turned-on state, the switch control unit (220) delays the turning off of the second switch (SW2) to create an overlapping on period. Through this overlapping on period, the power supply voltage can be supplied to the power amplifier without interruption. In the absence of an overlapping on period, the power supply voltage is interrupted, causing the power amplifier (300) to turn off, and thus a call drop may occur in the electronic device containing the power amplifier (300). Accordingly, when an overlapping on period is set as in one embodiment, call drops can be prevented.

[0058] Meanwhile, in one embodiment, the switch control unit (220) may not generate an overlapping on period, which is a period during which the first switch (SW1) and the second switch (SW2) are turned on simultaneously, when one switch (SW1 or SW2) is turned on while both the first and second switches (SW1, SW2) are in an off state (bit signal 00, 11).

[0059] The first and second switches (SW1, SW2) can be implemented as p-type transistors or n-type transistors. If the first and second switches (SW1, SW2) are p-type transistors, the ON control signal may have a low voltage level (e.g., 0V or a negative voltage) and the OFF control signal may have a high voltage level (e.g., 3V). If the first and second switches (SW1, SW2) are n-type transistors, the ON control signal may have a high voltage level (e.g., 3V) and the OFF control signal may have a low voltage level (e.g., 0V or a negative voltage).

[0060] FIG. 5 is a drawing specifically showing the internal configuration of a switch control unit (220) according to one embodiment.

[0061] As shown in FIG. 5, a switch control unit (220) according to one embodiment may include a logic circuit (221), a delay circuit (222), and a buffer circuit (223). FIG. 5 shows, as an example, the case where the first and second transistors (SW1, SW2) are p-type transistors, but they may be n-type transistors. In FIG. 5, the voltage of the power terminal (T_VCC) is V OUT It is represented as follows. In the following, the voltage supplied by the power switch circuit (200) to the power terminal (T_VCC) is referred to as the 'power terminal voltage (V OUT It is called )'.

[0062] The logic circuit (221) receives external bit signals (bit1, bit2) and receives a logic signal (V) corresponding to the bit signals (bit1, bit2). LOG1 , V LOG2 Generates and outputs the first bit signal (bit1) and the first logic signal (V LOG1 ) is used to control the first switch (SW1), and the second bit signal (bit2) and the second logic signal (V LOG2 ) is used to control the second switch (SW2).

[0063] FIG. 6 is a diagram showing a logic circuit (221) according to one embodiment.

[0064] As shown in FIG. 6, a logic circuit (221) according to one embodiment may include a first NAND gate (610), a second NAND gate (620), and a third NAND gate (630).

[0065] The first NAND gate (610) receives the first bit signal (bit1) and the second bit signal (bit2) as inputs. The second NAND gate (620) receives the first bit signal (bit1) and the output of the first NAND gate (610) as inputs, and the first logic signal (V LOG1 It outputs ). And, the third NAND gate (630) receives the second bit signal (bit2) and the output of the first NAND gate (610) as inputs, and the second logic signal (V LOG2 Prints ).

[0066] FIG. 7 shows the input / output logic table of the logic circuit (221) of FIG. 6.

[0067] As shown in FIG. 7, the logic circuit (221) has four states corresponding to two bit signals. The first logic signal (V LOG1 When ) is 1, it means a High level, in which case the first switch (SW1) is turned off. And the first logic signal (V LOG1When ) is 0, it means a low level, in which case the first switch (SW1) is turned on. As explained below, the first and second logic signals (V LOG1 ) is inverted by the NAND gate of the delay circuit (222). Accordingly, the first and second logic signals (V LOG1 , V LOG2 At the high level of ), the first and second switches (SW1, SW) are turned off, and the first and second logic signals (V LOG1 , V LOG2 At the low level of ), the first and second switches (SW1, SW) are turned on. That is, at bit signal 01, the first logic signal (V LOG1 ) becomes a low level, and the first switch (SW1) is turned on. Then, at bit signal 10, the second logic signal (V LOG2 ) becomes a low level, and the second switch (SW2) is turned on. In the remaining cases, the first and second logic signals (V LOG1 , V LOG2 ) becomes a High level, and both the first and second switches (SW1, SW2) are turned off.

[0068] The delay circuit (222) receives the first and second logic signals (V) from the logic circuit (221). LOG1 , V LOG2 Receiving ) as input, and causing an overlapping ON period to occur when switching between the first switch (SW1) and the second switch (SW2), a delay signal (V DEL1 , V DEL2 Outputs ). The first delay signal (V DEL1 ) is the first logic signal (V LOG1 Corresponds to ), and the second delay signal (V DEL2 ) is the second logic signal (V LOG2 It corresponds to ).

[0069] FIG. 8a shows a delay circuit (222) according to one embodiment, and FIG. 8b is a graph showing the input / output signal timing of the delay circuit (222) according to one embodiment.

[0070] As shown in FIG. 8a, the delay circuit (222) may include a first delay circuit (222_a) and a second delay circuit (222_b).

[0071] The first delay circuit (222_a) is the first logic signal (V LOG1 ) receives input and the first delay signal (V DEL1 It outputs ). The first delay circuit (222_a) may include a NAND gate (810) and a delay element (820). The delay element (820) may include a resistor (R) and a capacitor (C). In the first delay circuit (222_a), A and B represent the input terminals of the NAND gate (810), and Y represents the output terminal of the NAND gate (810). At the input terminal (A) of the NAND gate (810), a first logic signal (V LOG1 ) is input. The capacitor (C) is connected between the input terminal (B) of the NAND gate (810) and ground. At one end of the resistor (R), the first logic signal (V LOG1 ) is input, and the other end of the resistor (R) is connected to the input terminal (B) of the NAND gate (810). Here, the delay element (820) is the first logic signal (V LOG1 After delaying the signal for a predetermined amount of time, it is output to the input terminal (B) of the NAND gate (810). The RC time constant value is determined by the value of the resistor (R) and the value of the capacitor (C), and the signal is delayed by this RC time constant value. Meanwhile, the delay element (820) is a device that delays the signal and can be implemented not only by the resistor (R) and the capacitor (C) but also by other methods.

[0072] Referring to FIG. 8b, at time t1, the first logic signal (V LOG1) changes from the Low level to the High level (i.e., V LOG1 (This changes from 0 to 1). That is, at time t1, the first switch (SW1) changes from the turned-on state to the turned-off state. At this time, the input terminal (A) changes immediately from the low level to the high level, but the input terminal (B) changes from the low level to the high level after being delayed by a predetermined time (Δt) by the delay element (820). Accordingly, due to the operating characteristics of the NAND gate (outputting low only when both inputs are high, and outputting high for all others), the output terminal (Y) of the NAND gate (810) changes from the high level to the low level after a predetermined delay time (Δt). Accordingly, when the first switch (SW1) changes from the ON state to the OFF state, the turn-off of the first switch (SW1) is delayed by a predetermined delay time (Δt).

[0073] At time t2, since both input terminals (A, B) of the NAND gate (810) are at a high level, the output terminal (Y) of the NAND gate (810) becomes a low level.

[0074] Meanwhile, at time t3, the first logic signal (V LOG1 ) changes from High level to Low level (V LOG1(This changes from 1 to 0). That is, at time t3, the first switch (SW1) changes from the turn-off state to the turn-on state. At this time, the input terminal (A) changes immediately from the High level to the Low level, but the input terminal (B) changes from the Low level to the High level after being delayed for a predetermined amount of time by the delay element (820). Accordingly, due to the operating characteristics of the NAND gate (outputting High when only one of the two inputs is Low), the output terminal (Y) of the NAND gate (810) changes immediately from the Low level to the High level without any delay time.

[0075] In other words, the first delay circuit (222_a) is the first logic signal (V LOG1 The output signal (V) only when ) changes from a low level to a high level DEL1 Causes a delay of ) and the first logic signal (V LOG1 When ) changes from a High level to a Low level, an output signal is generated immediately without delay. The first logic signal (V LOG1 The case where ) changes from a low level to a high level is when the first switch (SW1) changes from turn-on to turn-off, and the first switch (SW1) is turned off after a delay of a predetermined time. And, the first logic signal (V LOG1 When ) changes from a high level to a low level, it is when the first switch (SW1) changes from off to on, and the first switch (SW1) is turned on immediately without delay.

[0076] The second delay circuit (222_b) is the second logic signal (V LOG2 ) receives input and the second delay signal (V DEL2 ) outputs. As shown in FIG. 8a, the second delay circuit (222_b) outputs the second logic signal (V LOG2Except for receiving ), the internal configuration is identical to the first delay circuit (222_a), so redundant descriptions are omitted. The second delay circuit (222_b) receives the second logic signal (V LOG2 It causes a delay in the output signal only when ) changes from a low level to a high level, and the second logic signal (V LOG2 When ) changes from a high level to a low level, it generates an output signal immediately without delay.

[0077] Due to such a delay circuit (222), when switching between the first switch (SW1) and the second switch (SW2) changes, an overlapping turn-on period may occur, which is a period during which the first and second switches (SW1, SW2) are turned on simultaneously. For example, when the first switch (SW1) changes from the turned-on state to the turned-off state, it is turned off with a delay of RC time constant, and the second switch (SW2) is turned on immediately without delay. Accordingly, the first and second switches (SW1, SW2) are turned on simultaneously for the RC time constant. Here, the RC time constant may correspond to the overlapping turn-on period. The overlapping turn-on period generated by the delay circuit (222) will be explained in more detail with reference to FIG. 9 below.

[0078] The buffer circuit (223) receives the first and second delay signals (V) from the delay circuit (222). DEL1 , V DEL2 It receives ) as input, and the switching drive signal (V SW1 , V SW2 ) outputs. The buffer circuit (223) outputs the first delay signal (V DEL1 ) is the first switching driving signal (V SW1 Converts to ) and the second delay signal (V DEL2 ) is the second switching drive signal (V SW2 Converts to ). The first delay signal (V DEL1 ) and the second delay signal (V DEL2Since ) is a logic signal and the current level is low, the buffer circuit (223) is the first delay signal (V DEL1 ) and the second delay signal (V DEL2 ) each are first switching driving signals (V) with a high current level SW1 ) and the second switching drive signal (V SW2 It converts to ). The specific configuration and operation of the buffer circuit (223) are known to those skilled in the art to which the present invention belongs, so a specific description is omitted. The first and second switching driving signals (V SW1 , V SW2 ) corresponds to the first and second switching control signals (SW1_CTRL, SW2_CTRL) described in FIGS. 3 and 4.

[0079] Since the first and second switches (SW1, SW2) are p-type transistors, the first and second switching driving signals (V SW1 , V SW2 When ) is a low voltage (e.g., 0V or a negative (-) voltage), the first and second switches (SW1, SW2) are turned on. And, the first and second switching drive signals (V SW1 , V SW2 When the voltage is high (e.g., 3V), the first and second switches (SW1, SW2) are turned off. Accordingly, the buffer circuit (223) delays the signal (V DEL1 , V DEL2 Outputs a high voltage when ) is at a low level and the delay signal (V DEL1 , V DEL2 It can be implemented as an inverter buffer so that a low voltage can be output when ) is at a high level.

[0080] FIG. 9 shows an operation timing graph of a power switch circuit (200) according to one embodiment. In FIG. 9, a first logic signal (V) according to external bit signals (bit1, bit2) LOG1 ), second logic signal (V LOG2 ), first switching drive signal (V SW1), second switching drive signal (V SW2 ), and power terminal voltage (V OUT It represented ).

[0081] When first and second bit signals (bit1, bit2) such as 910 and 920 are input, the logic circuit (221) receives a first logic signal (V such as 930). LOG1 ) and a second logic signal such as 940 (V LOG2 Prints ).

[0082] In the first period (TD1), the first logic signal (V LOG1 ) is at a high level and the second logic signal (V LOG2 ) is also at a high level. In this case, the first and second switching drive signals (V SW1 , V SW2 All of them are at high voltages, and the first and second switches (SW1, SW2) are in the off state. Accordingly, the power switch circuit (200) has a power terminal voltage (V OUT ) does not apply both power supply voltages (VCC1, VCC2).

[0083] In the second period (TD2), the first logic signal (V LOG1 ) is at a low level and the second logic signal (V LOG2 ) is at a high level. In this case, the first switching drive signal (V SW1 ) is a low voltage and the second switching drive signal (V SW2 ) is a high voltage, the first switch (SW1) is turned on, and the second switch (SW2) remains turned off. Accordingly, the power terminal voltage (V OUT ) becomes the first power supply voltage (VCC1).

[0084] In the third period (TD3), the first logic signal (V LOG1 ) is at a high level and the second logic signal (V LOG2 ) is at a low level. That is, when considering the second period (TD2) and the third period (TD3) together, the first logic signal (V LOG1) changes from a low level to a high level. As described in FIGS. 8a and 8b above, the delay circuit (222) causes a delay in the output signal when the logic signal changes from a low level to a high level (changes from 0 to 1). The first logic signal (V LOG1 Since ) changes from a low level to a high level, the first delay circuit (222_a) causes a delay in the output signal. Accordingly, the first switching driving signal (V SW1 Since ) changes from a low voltage to a high voltage after a predetermined delay time (Δt), the turn-off of the first switch (SW1) is delayed. In the third period (TD3), the second switching drive signal (V SW2 Since the voltage changes immediately from high to low without any delay, the second switch (SW2) is immediately turned on. That is, during the third period (TD3), an overlapping on period occurs in which both the first and second switches (SW1, SW2) are in the turned-on state. Accordingly, the first power supply voltage (VCC1) and the second power supply voltage (VCC2) are simultaneously applied to the power terminal (T_VCC), and the power terminal voltage (V OUT ) is set to a voltage between the first power supply voltage (VCC1) and the second power supply voltage (VCC2). Meanwhile, during the third period (TD3), after a predetermined delay time (Δt), the first switch (SW1) is turned off and the second switch (SW2) remains turned on, so the power terminal voltage (V OUT ) becomes the second power supply voltage (VCC2).

[0085] In the fourth period (TD4), the first logic signal (V LOG1 ) is at a high level and the second logic signal (V LOG2 ) is also at a high level. That is, when considering the third period (TD3) and the fourth period (TD4) together, the second logic signal (V LOG2) changes from a low level to a high level. As described in FIGS. 8a and 8b above, the delay circuit (222) causes a delay in the output signal when the logic signal changes from a low level to a high level (changes from 0 to 1). The second logic signal (V LOG2 Since ) changes from a low level to a high level, the second delay circuit (222_b) causes a delay in the output signal. Accordingly, the second switching drive signal (V SW2 Since ) changes from a low voltage to a high voltage after a predetermined delay time (Δt), the turn-off of the second switch (SW2) is delayed. Due to the turn-off delay of the second switch (SW2), the power terminal voltage (V OUT ) is maintained at the second power supply voltage (VCC2) for a predetermined delay time (Δt).

[0086] In the 5th period (TD5), the 1st logic signal (V LOG1 ) is at a low level and the second logic signal (V LOG2 ) is at a high level. That is, the second logic signal (V LOG2 Since ) is at a low level immediately before the 5th period (TD5) and at a high level during the 5th period (TD5), the 2nd logic signal (V LOG1 ) changes from a low level to a high level at the start of the fifth period (TD5). As described in FIGS. 8a and 8b above, the delay circuit (222) causes a delay in the output signal when the logic signal changes from a low level to a high level (changes from 0 to 1). The second logic signal (V LOG2 Since ) changes from a low level to a high level, the second delay circuit (222_b) causes a delay in the output signal. Accordingly, the second switching drive signal (V SW2 Since ) changes from a low voltage to a high voltage after a predetermined delay time (Δt), the turn-off of the second switch (SW2) is delayed. In the fifth period (TD5), the first switching drive signal (VSW1 Since the voltage changes immediately from high to low without any delay, the first switch (SW1) is immediately turned on. That is, during the fifth period (TD5), an overlapping on period occurs in which both the first and second switches (SW1, SW2) are in the turned-on state. Accordingly, the first power supply voltage (VCC1) and the second power supply voltage (VCC2) are simultaneously applied to the power terminal (T_VCC), and the power terminal voltage (V OUT ) is set to a voltage between the first power supply voltage (VCC1) and the second power supply voltage (VCC2). Meanwhile, during the fifth period (TD5), after a predetermined delay time (Δt), the second switch (SW2) is turned off and the first switch (SW1) remains turned on, so the power terminal voltage (V OUT ) becomes the first power supply voltage (VCC1).

[0087] In the 6th period (TD6), the first logic signal (V LOG1 ) is at a high level and the second logic signal (V LOG2 ) is also at a high level. That is, when considering the 5th period (TD5) and the 6th period (TD6) together, the 1st logic signal (V LOG1 ) changes from a low level to a high level. As described in FIGS. 8a and 8b above, the delay circuit (222) causes a delay in the output signal when the logic signal changes from a low level to a high level (changes from 0 to 1). The first logic signal (V LOG1 Since ) changes from a low level to a high level, the first delay circuit (222_a) causes a delay in the output signal. Accordingly, the first switching driving signal (V SW1 Since ) changes from a low voltage to a high voltage after a predetermined delay time (Δt), the turn-off of the first switch (SW1) is delayed. Due to the turn-off delay of the first switch (SW1), the power terminal voltage (V OUT ) is maintained at the first power supply voltage (VCC1) for a predetermined delay time (Δt).

[0088] In this way, the power switch circuit (200) according to the embodiment can supply the first and second power voltages (VCC1, VCC2) simultaneously to the power terminal (T_VCC) for a predetermined period of time when changing from the first power voltage (VCC1) to the second power voltage (VCC2) and supplying to the power terminal (T_VCC). That is, when the first switch (SW1) is changed to turn off and the second switch (SW2) is changed to turn on (for example, the third period (TD3) of FIG. 9), an overlapping on period in which the first switch (SW1) and the second switch (SW2) are simultaneously turned on can be set. In addition, the power switch circuit (200) according to the embodiment can supply the first and second power voltages (VCC1, VCC2) simultaneously to the power terminal for a predetermined period of time even when changing from the second power voltage (VCC2) to the first power voltage (VCC1) and supplying to the power terminal (T_VCC). That is, when the first switch is turned on and the second switch is turned off (for example, the fifth period (TD5) of FIG. 9), an overlapping on period can be set in which the first switch (SW1) and the second switch (SW2) are turned on simultaneously. According to this embodiment, when the switching between the first switch (SW1) and the second switch (SW2) is changed, the power amplifier (300) can be prevented from turning off by continuously supplying the power voltage without interruption.

[0089] FIG. 10 is a drawing showing a power switch circuit (200') according to another embodiment.

[0090] As shown in FIG. 10, a power switch circuit (200') according to another embodiment may include a switch circuit (210') and a switch control unit (220').

[0091] A switch circuit (210') according to another embodiment may include a first switch (SW1') and a second switch (SW2'). The first and second switches (SW1', SW2') are each composed of a p-type transistor and an n-type transistor connected in parallel with each other. That is, the first switch (SW1') includes a p-type transistor and an n-type transistor connected in parallel with each other, and the second switch (SW2') also includes a p-type transistor and an n-type transistor connected in parallel with each other. In the first switch (SW1'), the drain of the n-type transistor and the source of the p-type transistor are connected to each other and connected to a first power supply voltage (VCC1). Also, in the first switch (SW1), the source of the n-type transistor and the drain of the p-type transistor are connected to each other and connected to a power terminal (T_VCC). In the second switch (SW2'), the drain of the n-type transistor and the source of the p-type transistor are connected to each other and connected to a second power supply voltage (VCC2). And in the second switch (SW2), the source of the n-type transistor and the drain of the p-type transistor are connected to each other and connected to the power terminal (T_VCC).

[0092] As described above, the first and second power supply voltages (VCC1, VCC2) can vary according to the input RF signal envelope of the power amplifier (300) to support the APT mode. Accordingly, the first and second power supply voltages (VCC1, VCC2) can have a wide voltage range. It is necessary to keep the switch turn-on resistance low even with power supply voltages having a wide voltage range; to this end, in FIG. 10, the first and second switches (SW1', SW2') are composed of an n-type transistor and a p-type transistor connected in a parallel structure.

[0093] FIG. 11 shows the turn-on resistance (R) of the transistor according to the power supply voltage (VCC). ON It is a graph representing ).

[0094] In FIG. 11, 1110 represents the turn-on resistance of a p-type transistor (e.g., PMOS) according to the power supply voltage (VCC), and 1120 represents the turn-on resistance of an n-type transistor (e.g., NMOS) according to the power supply voltage (VCC). Referring to 1110, the turn-on resistance of the p-type transistor increases as the power supply voltage (VCC) decreases. That is, if the switch is configured using only p-type transistors as in FIG. 5, the turn-on resistance may be high at low power supply voltages (VCC). As a result, a high voltage drop occurs across the switch, leading to higher power consumption. Meanwhile, referring to 1120, the turn-on resistance of the n-type transistor increases as the power supply voltage (VCC) increases. That is, if the switch is configured using only n-type transistors, the turn-on resistance may be high at high power supply voltages (VCC).

[0095] To maintain a low turn-on resistance over a wide power supply voltage range, as shown in FIG. 10, the first and second switches (SW1', SW2') can be configured with an n-type transistor and a p-type transistor connected in a parallel structure. In FIG. 11, 1130 represents the turn-on resistance according to the power supply voltage (VCC) when the switches are configured with an n-type transistor and a p-type transistor connected in parallel. Referring to 1130, the turn-on resistance can be maintained at a low level over a wide power supply voltage (input voltage). Here, when the switches (SW1', SW2') are configured with a p-type transistor and an n-type transistor, the n-type transistor mainly operates when the power supply voltage (input voltage) is low, and the p-type transistor mainly operates when the power supply voltage is high.

[0096] As shown in FIG. 10, a switch control unit (220') according to another embodiment may include a logic circuit (221), a delay circuit (222), a buffer circuit (223), a first inverter (224a), and a second inverter (224b). Since the switch control unit (220') according to another embodiment is identical to the switch control unit (220) of FIG. 5 except that the first and second inverters (224a, 224b) are added, a redundant description is omitted.

[0097] The first inverter (224a) is the first switching drive signal (V SW1 ) receives an inverted switching drive signal ( Outputs ). The first switch driving signal (V SW1 ) is input to the p-type transistor control terminal of the first switch (SW1'), and the inverted switching driving signal ( ) is input to the n-type transistor control terminal of the first switch (SW1'). Accordingly, at the first switch (SW1'), the p-type transistor and the n-type transistor are turned on and turned off simultaneously.

[0098] The second inverter (224b) is the second switching drive signal (V SW2 ) receives an inverted switching drive signal ( Outputs ). Second switch driving signal (V SW2 ) is input to the p-type transistor control terminal of the second switch (SW2'), and the inverted switching drive signal ( ) is input to the n-type transistor control terminal of the second switch (SW2'). Accordingly, at the second switch (SW2'), the p-type transistor and the n-type transistor are turned on and turned off simultaneously.

[0099] Although embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements by those skilled in the art using the basic concept of the present invention as defined in the following claims also fall within the scope of the present invention. Explanation of the symbols

[0100] 1000: Transmitter system 100a: First power circuit 100b: Second power circuit 200: Power switch circuit 300: Power amplifier 210: Switch circuit 220: Switch control unit 221: Logic Circuit 222: Delay circuit 223: Buffer circuit

Claims

Claim 1 A power switch circuit comprising a first switch for switching to supply a first power supply voltage to a power terminal of a power amplifier, and a second switch for switching to supply a second power supply voltage to the power terminal; and a switch control unit for controlling the switch circuit such that when the first switch is switched from turn-on to turn-off and the second switch is switched from turn-off to turn-on, the first and second switches are set to an ON state simultaneously during a first period so that the first power supply voltage and the second power supply voltage are supplied simultaneously to the power terminal. Claim 2 In claim 1, the switch control unit is a power switch circuit that delays the turn-off of the first switch during the first period and maintains the turn-on of the first switch. Claim 3 A power switch circuit according to claim 1, wherein during the first period, the first power supply voltage and the second power supply voltage are simultaneously supplied to the power terminal. Claim 4 A power switch circuit according to claim 1, wherein after the first period, the first switch is set to an off state and the second switch is set to an on state, and the second power voltage is supplied to the power terminal. Claim 5 In claim 1, the switch control unit comprises a power switch circuit including a delay circuit that delays a first logic signal controlling the first switch and a second logic signal controlling the second switch. Claim 6 In claim 5, the delay circuit comprises a first delay circuit including a first delay element that delays the first logic signal and a first NAND gate that receives the first logic signal and the signal delayed by the first delay element, and a second delay circuit including a second delay element that delays the second logic signal and a second NAND gate that receives the second logic signal and the signal delayed by the second delay element. Claim 7 In claim 6, the first and second delay elements each include a resistor and a capacitor, and the first and second logic signals are delayed in a power switch circuit corresponding to a time constant value determined by the resistor and the capacitor. Claim 8 In claim 5, the switch control unit further comprises a power switch circuit including a logic circuit that generates the first and second logic signals, and a buffer circuit that converts a driving control signal for driving the first and second switches using the output signal of the delay circuit. Claim 9 In claim 8, the logic circuit comprises a first NAND gate receiving a first bit for controlling the first switch and a second bit for controlling the second switch, a second NAND gate receiving the first bit and the output of the first NAND gate and outputting the first logic signal, and a third NAND gate receiving the second bit and the output of the first NAND gate and outputting the second logic signal. Claim 10 In claim 1, each of the first and second switches is a power switch circuit comprising a p-type transistor and an n-type transistor connected in parallel with each other. Claim 11 In claim 10, the power switch circuit in which the p-type transistor and the n-type transistor are simultaneously turned on and simultaneously turned off. Claim 12 A method of operation of a power switch circuit for selecting at least one of a first power supply voltage and a second power supply voltage and supplying it to a power terminal of a power amplifier, comprising: a step of, in a first period, turning on a first switch that switches the first power supply voltage and turning off a second switch that switches the second power supply voltage to supply the first power supply voltage to the power terminal; a step of, in a second period, maintaining the turned-on state of the first switch and turning on the second switch to supply the first power supply voltage and the second power supply voltage simultaneously to the power terminal; and, after the second period, turning off the first switch and maintaining the turned-on state of the second switch to supply the second power supply voltage to the power terminal. Claim 13 In paragraph 12, the logic signal controlling the turn-off of the first switch during the second period is a method of operation that is delayed during the second period. Claim 14 In paragraph 13, the operation method in which the logic signal is delayed for the second period by means of a capacitor and a resistor generating an RC time constant. Claim 15 In claim 12, a method of operation in which, during the second period, a voltage between the first power supply voltage and the second power supply voltage is supplied to the power terminal. Claim 16 In claim 12, the method of operation wherein each of the first and second switches comprises a p-type transistor and an n-type transistor connected in parallel with each other.

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