Power supply switch circuit

Abstract

A power switch circuit may be disclosed. The power switch circuit may include a first switch that switches supplying a first power voltage to a power terminal of a power amplifier, a control voltage generator that generates a first control voltage higher than the first power voltage by comparing a first voltage, which is the voltage of the power terminal, with a predetermined first reference voltage, and a switch controller that generates a switching driving signal to control the first switch using the first control voltage.

Description

Technology Field

[0001] This description relates to a power switch circuit. Background Technology

[0002] As wireless communication standards evolve, multiple communication standards such as 2G, Wi-Fi, Bluetooth, 3G, 4G, and 5G are being used in a single device (e.g., a smartphone). As multiple communication standards are used in a single device, a power amplifier that outputs a transmission signal is also used for each communication standard. In other words, in order to output a signal suitable for multiple communication standards, multiple power amplifiers corresponding to multiple communication standards may be required.

[0003] Power amplifiers operate by receiving power from an external source, and generally, a separate Power Supply IC (Integrated Circuit) is used to supply power to a single power amplifier. For example, four Power Supply ICs are used to operate four power amplifiers. Among multiple communication standards, when one standard is in use, other standards may not be used simultaneously. For example, when the 4G communication standard is in use, the 3G communication standard may not be in use. Accordingly, it is necessary to effectively utilize Power Supply ICs corresponding to unused communication standards for other communication standards. The problem to be solved

[0004] According to at least one embodiment of the embodiments, a power switch circuit is provided that switches at least two power voltages and supplies them to a power amplifier.

[0005] According to at least one embodiment of the embodiments, a power switch circuit is provided that stably supplies a power voltage to a power amplifier. means of solving the problem

[0006] According to one aspect, a power switch circuit may be provided. The power switch circuit may include a first switch that switches supplying a first power voltage to a power terminal of a power amplifier, a control voltage generator that generates a first control voltage higher than the first power voltage by comparing a first voltage, which is the voltage of the power terminal, with a predetermined first reference voltage, and a switch controller that generates a switching drive signal to control the first switch using the first control voltage.

[0007] The above power switch circuit may further include a second switch that switches supplying a second power voltage to the power terminal, and the control voltage generator may generate a second control voltage higher than the second power voltage by comparing the first voltage with a predetermined second reference voltage, and the switch controller may generate a switching drive signal that controls the second switch using the second control voltage.

[0008] The control voltage generator may include a comparator that compares the first voltage and the first reference voltage, an oscillator that generates a waveform corresponding to the output of the comparator, and a charge pump that receives the first power supply voltage and a predetermined second voltage as inputs and operates through the waveform to generate the first control voltage.

[0009] The first control voltage may correspond to the sum of the first power supply voltage and the second voltage.

[0010] The charge pump above can perform a charge pumping operation until the first voltage becomes the first reference voltage.

[0011] The above switch controller may include a buffer circuit that receives the first control voltage and generates the switching driving signal having the first control voltage.

[0012] The first power supply voltage may vary according to the envelope of the RF (Radio Frequency) signal input to the power amplifier.

[0013] The first reference voltage may be a voltage lower than the first power supply voltage, and the second reference voltage may be a voltage lower than the second power supply voltage.

[0014] According to another aspect, a power switch circuit may be provided. The power switch circuit may include a first switch connected between a first power circuit outputting a first voltage and a power terminal of a power amplifier, a second switch connected between a second power circuit outputting a second voltage and the power terminal, a control voltage generator that generates a first control voltage higher than the first voltage and a second control voltage higher than the second voltage using the voltage of the power terminal, the first voltage, and the second voltage, and a switch controller that generates a first switching drive signal for controlling the first switch using the first control voltage and a second switching drive signal for controlling the second switch using the second control voltage.

[0015] The control voltage generator may include a first control voltage generator that generates the first control voltage using the voltage of the power terminal, the first voltage, and a predetermined first reference voltage, and a second control voltage generator that generates the second control voltage using the voltage of the power terminal, the second voltage, and a predetermined second reference voltage.

[0016] The first control voltage generator may include a first comparator that compares the voltage of the power terminal with the first reference voltage, a first oscillator that generates a waveform in response to the output of the first comparator, and a first charge pump that receives the first voltage and a predetermined third voltage as inputs and operates in response to the output of the first oscillator to generate the first control voltage.

[0017] The second control voltage generator may include a second comparator that compares the voltage of the power terminal with the second reference voltage, a second oscillator that generates a waveform in response to the output of the second comparator, and a second charge pump that receives the second voltage and a predetermined fourth voltage as inputs and operates in response to the output of the second oscillator to generate the second control voltage.

[0018] The first control voltage may correspond to the sum of the first voltage and the third voltage, and the second control voltage may correspond to the sum of the second voltage and the fourth voltage.

[0019] The first charge pump can perform a charge pumping operation until the voltage of the power terminal becomes the first reference voltage, and the second charge pump can perform a charge pumping operation until the voltage of the power terminal becomes the second reference voltage.

[0020] The switch controller may include a buffer circuit that receives the first control voltage and the second control voltage as inputs and generates the first switching driving signal having the first control voltage and the second switching driving signal having the second control voltage.

[0021] The first and second voltages above may vary according to the envelope of the RF (Radio Frequency) signal input to the power amplifier.

[0022] The first reference voltage is a voltage lower than the first voltage, and the second reference voltage may be a voltage lower than the second voltage. Effects of the invention

[0023] According to at least one of the embodiments, the number of power circuits can be reduced by selectively providing a power voltage to a power amplifier through a power switch circuit.

[0024] According to at least one of the embodiments, by generating a control voltage of a switch using the voltage supplied to the power terminal of a power amplifier, a stable power voltage can be supplied to the power amplifier. Brief explanation of the drawing

[0025] FIG. 1 is a block diagram showing a transmitter system according to one embodiment. FIG. 2 is a diagram showing the connection relationship between a power switch circuit and a power amplifier according to one embodiment. FIG. 3 is a diagram showing the internal configuration of a power switch circuit according to one embodiment. FIG. 4 is a diagram showing a logic table according to one embodiment. FIG. 5 is a diagram showing a control voltage generator according to one embodiment. FIG. 6a is a diagram showing the internal configuration of a first control voltage generator according to one embodiment, and FIG. 6b is a diagram showing the internal configuration of a second control voltage generator according to one embodiment. FIG. 7 is a diagram showing the internal configuration of a switch circuit and the internal configuration of a switch controller according to one embodiment. FIG. 8 is a diagram showing a logic circuit according to one embodiment. Figure 9 shows the input / output logic table of the logic circuit of Figure 8. Specific details for implementing the invention

[0026] Embodiments of the present invention are described below with reference to the attached drawings so that those skilled in the art can easily implement them. However, the present invention may be embodied in various different forms and is not limited to the embodiments described herein. Furthermore, in order to clearly explain the present invention in the drawings, parts unrelated to the explanation have been omitted, and similar parts throughout the specification are denoted by similar reference numerals.

[0027] Throughout the specification, when a part is described as being "coupled" with another part, this includes not only cases where they are "directly or physically coupled," but also cases where they are "indirectly or non-contact coupled" with another element in between.

[0028] Throughout the specification, when a part is described as being "connected" to another part, this includes not only cases where they are "directly or physically connected," but also cases where they are "indirectly or non-contactually connected" with other elements in between, or cases where they are "electrically connected."

[0029] Throughout the specification, RF (Radio Frequency) signals may have a format according to Wi-Fi (IEEE 802.11 family, etc.), WiMAX (IEEE 802.16 family, etc.), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G and any other wireless and wired protocols designated thereafter, but are not limited thereto.

[0030] Furthermore, when it is stated that a part "includes" a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components.

[0031] FIG. 1 is a block diagram showing a transmitter system (1000) according to one embodiment.

[0032] As shown in FIG. 1, a transmitter system (1000) according to one embodiment may include first and second power circuits (100a, 100b), first and second power switch circuits (200a, 200b), and first to fourth power amplifiers (300a to 300d). FIG. 1 shows, as an example, a case in which the transmitter system (1000) is composed of four power amplifiers and two associated power switch circuits, but the number of power amplifiers and power switch circuits may be changed.

[0033] The first power circuit (100a) generates and outputs a first power voltage (VCC1). According to one embodiment, the first power voltage (VCC1) may be applied to the power terminals of the first power amplifier (300a), the second power amplifier (300b), or the third power amplifier (300c). To support the APT mode (Average Power Tracking mode), the value of the first power voltage (VCC1) may vary according to the envelope of the RF signal input to the first power amplifier (300a), the second power amplifier (300b), or the third power amplifier (300c).

[0034] The second power circuit (100b) generates and outputs a second power voltage (VCC2). According to one embodiment, the second power voltage (VCC2) may be applied to the power terminals of the second power amplifier (300b), the third power amplifier (300c), or the fourth power amplifier (300d). To support the APT mode (Average Power Tracking mode), the value of the second power voltage (VCC2) may vary according to the envelope of the RF signal input to the second power amplifier (300b), the third power amplifier (300c), or the fourth power amplifier (300d).

[0035] Meanwhile, the first and second power circuits (100a, 100b) can each be implemented as a PM IC (Power Management Integrated Circuit).

[0036] The first power switch circuit (200a) can receive a first power voltage (VCC1) from the first power circuit (100a) and a second power voltage (VCC2) from the second power circuit (100b). The first power switch circuit (200a) can select one of the received first and second power voltages (VCC1, VCC2) and output (supply) it to the power terminal of the second power amplifier (300b). For example, if the first power amplifier (300a) is not operating, the first power switch circuit (200a) can select the first power voltage (VCC1) and output it to the power terminal of the second power amplifier (300b). And, if the fourth power amplifier (300d) is not operating, the first power switch circuit (200a) can select the second power voltage (VCC2) and output it to the power terminal of the second power amplifier (300b).

[0037] The second power switch circuit (200b) receives a first power voltage (VCC1) from the first power circuit (100a) and receives a second power voltage (VCC2) from the second power circuit (100b). The second power switch circuit (200b) can select one of the received first and second power voltages (VCC1, VCC2) and output (supply) it to the power terminal of the third power amplifier (300c). For example, if the first power amplifier (300a) is not operating, the second power switch circuit (200b) can select the first power voltage (VCC1) and output it to the power terminal of the third power amplifier (300c). And, if the fourth power amplifier (300d) is not operating, the second power switch circuit (200b) can select the second power voltage (VCC2) and output it to the power terminal of the third power amplifier (300c).

[0038] The first power amplifier (300a) operates by receiving the first power voltage (VCC1) from the first power circuit (100a) and amplifies and outputs an input RF (radio frequency) signal. The input RF signal of the first power amplifier (300a) may be an RF signal for a first communication standard.

[0039] The second power amplifier (300b) operates by receiving a power voltage selected by the first power switch circuit (200a) (i.e., the first power voltage (VCC1) or the second power voltage (VCC2)) and amplifies and outputs an input RF signal. The input RF signal of the second power amplifier (300b) may be an RF signal for the second communication standard.

[0040] The third power amplifier (300c) operates by receiving a power voltage selected by the second power switch circuit (200b) (i.e., the first power voltage (VCC1) or the second power voltage (VCC2)) and amplifies and outputs an input RF signal. The input RF signal of the third power amplifier (300c) may be an RF signal for the third communication standard.

[0041] The fourth power amplifier (300d) operates by receiving the second power voltage (VCC2) from the second power circuit (100b) and amplifies and outputs an input RF (radio frequency) signal. The input RF signal of the fourth power amplifier (300d) may be an RF signal for the fourth communication standard.

[0042] Here, the first to fourth communication standards may be different communication standards and may be any one of 2G, WiFi, Bluetooth, 3G, 4G, and 5G. Meanwhile, the first to fourth communication standards may be communication standards that define different bands among 5G communication standards.

[0043] According to this embodiment, the number of power circuits can be reduced by sharing the power voltage through a power switch circuit. Generally, when there are four power amplifiers, four power circuits are used, but in FIG. 1, the number of power circuits can be reduced to two by using a power switch circuit. Below, the specific configuration and operation method of power switch circuits, such as the first and second power switch circuits (200a, 200b), will be described.

[0044] FIG. 2 is a diagram showing the connection relationship between a power switch circuit (200) and a power amplifier (300) according to one embodiment.

[0045] The power switch circuit (200) receives a first power voltage (VCC1) and a second power voltage (VCC2) as inputs, and selects one of the received first and second power voltages (VCC1, VCC2) and outputs it to the power terminal (T_VCC) of the power amplifier (300). Here, the power switch circuit (200) may be the first power switch circuit (200a) or the second power switch circuit (200b) of FIG. 1.

[0046] In FIGS. 1 and 2, the power switch circuit (200) is shown as receiving two power voltages, but it can receive at least two power voltages. At this time, the power switch circuit (200) can select one of the at least two power voltages.

[0047] The power amplifier (300) includes an input terminal (RFin), an output terminal (RFout), and a power supply terminal (T_VCC). An RF signal is input at the input terminal (RFin), and an amplified signal is output at the output terminal (Rout). A power supply voltage (VCC1 or VCC2) is applied to the power supply terminal (T_VCC), and the power amplifier (300) is operated by the applied power supply voltage (VCC1 or VCC2). The power amplifier (300) can be implemented as a transistor. If the power amplifier (300) is implemented as a Bipolar Junction Transistor (BJT), the input terminal (RFin) may be the base and the power supply terminal (T_VCC) may be the collector or emitter. Meanwhile, if the power amplifier (300) is implemented as a Field Effect Transistor (FET), the input terminal (RFin) may be the gate and the power supply terminal (T_VCC) may be the drain or source.

[0048] Meanwhile, the power switch circuit (200) and the power amplifier (300) of FIG. 2 can be combined to be implemented as a single power amplifier module.

[0049] FIG. 3 is a diagram showing the internal configuration of a power switch circuit (200) according to one embodiment.

[0050] As shown in FIG. 3, a power switch circuit (200) according to one embodiment may include a switch circuit (210), a switch controller (220), and a control voltage generator (230).

[0051] The switch circuit (210) may include a first switch (SW1) and a second switch (SW2). The first switch (SW1) may switch to supply a first power supply voltage (VCC1) to the power terminal (T_VCC) of the power amplifier (300), and the second switch (SW2) may switch to supply a second power supply voltage (VCC2) to the power terminal (T_VCC) of the power amplifier (300). The first switch (SW1) may be connected between the first power circuit (100a) and the power terminal (T_VCC) of the power amplifier (300), and the second switch (SW2) may be connected between the second power circuit (100b) and the power terminal (T_VCC) of the power amplifier (300). Meanwhile, in FIG. 3, the voltage of the power terminal (T_VCC) is V T It is represented as such, and below, the voltage of the power terminal (T_VCC) is referred to as 'power terminal voltage (V T It is called )'.

[0052] The switch controller (220) receives a bit signal (digital signal) from the outside and a switching driving signal (V) that switches the switch circuit (210) in response to the input bit signal. SW It can generate the generated switching drive signal (V SW ) is output to the switch circuit (210). Here, as an example, the bit signal input from the outside may be 2 bits. Switching driving signal (V SW ) is a first switching driving signal (V) that controls the first switch (SW1). SW1 A second switching driving signal (V) that controls ) and the second switch (SW2)SW2 It may include ). The switch controller (220) receives a first control voltage (V) from the control voltage generator (230). C1 ) is received as input, and the first control voltage (V C1 Using ), the first switching driving signal (V SW1 ) can be generated. And the switch controller (220) can generate a second control voltage (V) from the control voltage generator (230). C2 ) receives the input and the second control voltage (V C2 Using ), the second switching driving signal (V SW1 Can generate ).

[0053] First switching drive signal (V SW1 ) is the ON driving signal and the second switching driving signal (V SW2 When the signal is OFF, the first switch (SW1) is turned on and the second switch (SW2) is turned off. Accordingly, the first power supply voltage (VCC1) is applied to the power terminal (T_VCC) of the power amplifier (300) through the first switch (SW1).

[0054] First switching drive signal (V SW1 ) is the OFF driving signal and the second switching driving signal (V SW2 When ) is an ON driving signal, the first switch (SW1) is turned off and the second switch (SW2) is turned on. Accordingly, the second power supply voltage (VCC2) is applied to the power terminal (T_VCC) of the power amplifier (300) through the second switch (SW2).

[0055] FIG. 4 is a diagram showing a logic table according to one embodiment.

[0056] In FIG. 4, bit1 and bit2 are external bit signals input to the switch controller (220). As shown in FIG. 4, when the external bit signal is 00 and 11, the first and second switching driving signals (V SW1 , V SW2) All may be OFF driving signals, and the first and second switches (SW1, SW2) may both be in the OFF state. The switch controller (220) may include a logic circuit having a logic table as shown in FIG. 4, which will be explained in more detail below.

[0057] As shown in FIG. 3, the control voltage generator (230) receives a first power supply voltage (VCC1) from the first power supply circuit (100a) and a second power supply voltage (VCC2) from the second power supply circuit (100b). The control voltage generator (230) also receives a first excess voltage (ΔV1), a second excess voltage (ΔV2), and a power terminal voltage (V T ), first reference voltage (V REF1 ), and the second reference voltage (V REF1 ) is also received as input. The control voltage generator (230) receives the first power supply voltage (VCC1), the first excess voltage (ΔV1), and the power terminal voltage (V T ), and the first reference voltage (V REF1 Using ), the first control voltage (V C1 ) generates. The control voltage generator (230) generates the second power supply voltage (VCC2), the second excess voltage (ΔV2), and the power terminal voltage (V T ), and the second reference voltage (V REF2 Using ), the second control voltage (V C2 Generates the first and second control voltages (V) generated in the control voltage generator (230). C1 , V C2 ) is input to the switch controller (220). The first control voltage (V C1 ) may be a control voltage (e.g., gate voltage) for switching the first switch (SW1), and a second control voltage (V C2 ) may be a control voltage (e.g., gate voltage) for switching the second switch (SW2).

[0058] FIG. 5 is a drawing showing a control voltage generator (230) according to one embodiment.

[0059] As shown in FIG. 5, the control voltage generator (230) may include a first control voltage generator (230a) and a second control voltage generator (230b).

[0060] The first control voltage generator (230a) has a first power supply voltage (VCC1), a first excess voltage (ΔV1), and a power terminal voltage (V T ), and the first reference voltage (V REF1 It receives ) as input, and uses them to provide a first control voltage (V C1 ) generates. To explain in more detail, the first control voltage generator (230a) generates the input power terminal voltage (V T ) and the first reference voltage (V REF1 By comparing ) and operating the internal charge pump according to the comparison result, the first control voltage (V C1 Generates ). Here, the first control voltage (V C1 ) may be the sum of the first power supply voltage (VCC1) and the first excess voltage (ΔV1) (VCC1+ΔV1). The first excess voltage (ΔV1) is an arbitrarily set voltage and may be 3V as an example. The first excess voltage (ΔV1) may be implemented through a regulator such as a Low Dropout (LDO). The first reference voltage (V REF1 ) is an arbitrarily set voltage and may be the actual voltage to be supplied to the power terminal (T_VCC) through the power switch circuit (200) (i.e., a voltage that takes into account the voltage drop of the first switch (SW1), etc.). The first reference voltage (V REF1 ) may be a voltage slightly lower than the first power supply voltage (VCC1). As an example, the first reference voltage (V REF1 ) may be a voltage (VCC1 - 0.2V) that is 0.2V lower than the first power supply voltage (VCC1).

[0061] The second control voltage generator (230b) has a second power supply voltage (VCC2), a second excess voltage (ΔV2), and a power terminal voltage (V T ), and the second reference voltage (V REF2 It receives ) as input, and uses them to provide a second control voltage (V C2 ) generates. To explain in more detail, the second control voltage generator (230b) generates the input power terminal voltage (V T ) and the second reference voltage (V REF2 By comparing ) and operating the internal charge pump according to the comparison result, the second control voltage (V C2 Generates ). Here, the second control voltage (V C2 ) may be the sum of the second power supply voltage (VCC2) and the second excess voltage (ΔV2) (VCC2+ΔV2). The second excess voltage (ΔV2) is an arbitrarily set voltage, and as an example, may be 3V. The second excess voltage (ΔV2) may also be implemented through a regulator such as a Low Dropout (LDO). The second excess voltage (ΔV2) may be the same voltage as the first excess voltage (ΔV1). The second reference voltage (V REF2 ) is an arbitrarily set voltage and may be the actual voltage to be supplied to the power terminal (T_VCC) through the power switch circuit (200) (i.e., a voltage that takes into account the voltage drop of the second switch (SW2), etc.). The second reference voltage (V REF2 ) may be a voltage slightly lower than the second power supply voltage (VCC2). As an example, the second reference voltage (V REF2 ) can be a voltage 0.2V lower than the second power supply voltage (VCC2) (VCC2 - 0.2V).

[0062] FIG. 6a is a drawing showing the internal configuration of a first control voltage generator (230a) according to one embodiment, and FIG. 6b is a drawing showing the internal configuration of a second control voltage generator (230b) according to one embodiment.

[0063] As shown in FIG. 6a, a first control voltage generator (230a) according to one embodiment may include a comparator (231a), an oscillator (232a), and a charge pump (233a).

[0064] The first reference voltage (V) is applied to the non-inverting terminal (+) of the comparator (231a). REF1 ) is input, and the power terminal voltage (V) is input to the inversion terminal (-) of the comparator (231a). T ) is input. The comparator (231a) is the first reference voltage (V REF1 ) and power terminal voltage (V T Compares the first reference voltage (V REF1 ) is the power terminal voltage (V T If it is higher than ), the comparator (231a) outputs a High signal. And, the power terminal voltage (V T ) is the first reference voltage (V REF1 If it is higher than ), the comparator (231a) outputs a low signal. Meanwhile, if the first switch (SW1) is an n-type transistor, the comparator (231a) can start a comparison operation when the enable signal of the first switch (SW1) is input. And, if the first switch (SW1) is a p-type transistor, the comparator (231a) can start a comparison operation when the disable signal of the first switch (SW1) is input.

[0065] The oscillator (232a) receives the output of the comparator (231a) and generates a square wave in response to the output of the comparator (231a). When the output of the comparator (231a) is a High signal, the oscillator (232a) operates and generates a square wave. When the output of the comparator (231a) is a Low signal, the oscillator (232a) does not operate and does not generate a square wave. That is, the oscillator (232a) [receives] the power terminal voltage (V T ) is the first reference voltage (V REF1It performs operations until it becomes ) and generates and outputs a square wave.

[0066] The charge pump (233a) receives the output of the oscillator (232a) and receives the first power supply voltage (VCC1) and the first excess voltage (ΔV1). When a square wave is input from the oscillator (232a), the charge pump (233a) performs an operation. Accordingly, the charge pump (233a) receives a voltage (VCC1+ΔV1) corresponding to the sum of the first power supply voltage (VCC1) and the first excess voltage (ΔV1) as the first control voltage (V C1 ) output as. In other words, the charge pump (233a) outputs the power terminal voltage (VT) as the first reference voltage (V REF1 The charge pumping operation continues until it reaches ). The charge pump (233a) uses the square wave input from the oscillator (232a) to perform the first control voltage (V C1 The specific method for generating ) is known to those skilled in the art to which the present invention belongs, so a specific description is omitted.

[0067] Here, the first control voltage (V C1 The relationship between ) and the first power supply voltage (VCC1) can satisfy the following mathematical equation 1.

[0068]

[0069] As shown in Equation 1, the first control voltage (V C1 ) can be set to a voltage higher than the first power supply voltage (VCC1) by a first excess voltage (ΔV1). The first control voltage (V C1 Since ) is the voltage used to switch the first switch (SW1), the first switch (SW1) can be sufficiently turned on or turned off. For example, if the first switch (SW1) is implemented as an n-type transistor, the first switching driving signal (V SW1The voltage of ) must be set higher than the first power supply voltage (VCC1) so that the first switch (SW1) can sufficiently perform a turn-on operation. And when the first switch (SW1) is implemented as a p-type transistor, the first switching driving signal (V SW1 The voltage of ) must be set higher than the first power supply voltage (VCC1) so that the first switch (SW1) can sufficiently perform a turn-off operation. Accordingly, the first control voltage generating unit (230a) according to the embodiment generates a first control voltage (VC1) higher than the first power supply voltage (VCC1) and outputs it to the switch controller (220).

[0070] As shown in FIG. 6b, a second control voltage generator (230b) according to one embodiment may include a comparator (231b), an oscillator (232b), and a charge pump (233b).

[0071] The non-inverting terminal (+) of the comparator (231b) has a second reference voltage (V REF2 ) is input, and the power terminal voltage (V) is input to the inverting terminal (-) of the comparator (231b). T ) is input. The comparator (231b) is the second reference voltage (V REF2 ) and power terminal voltage (V T Compares the second reference voltage (V REF2 ) is the power terminal voltage (V T If it is higher than ), the comparator (231b) outputs a High signal. And, the power terminal voltage (V T ) is the second reference voltage (V REF2 If it is higher than ), the comparator (231a) outputs a Low signal. Meanwhile, if the second switch (SW2) is an n-type transistor, the comparator (231b) can start a comparison operation when the enable signal of the second switch (SW2) is input. And, if the second switch (SW2) is a p-type transistor, the comparator (231b) can start a comparison operation when the disable signal of the second switch (SW2) is input.

[0072] The oscillator (232b) receives the output of the comparator (231b) and generates a square wave in response to the output of the comparator (231b). When the output of the comparator (231b) is a high signal, the oscillator (232b) operates and generates a square wave. When the output of the comparator (231a) is a low signal, the oscillator (232b) does not operate and does not generate a square wave. That is, the oscillator (232b) [in response to] the power terminal voltage (V T ) is the second reference voltage (V REF It performs operations until it becomes ) and generates and outputs a square wave.

[0073] The charge pump (233b) receives the output of the oscillator (232b) and receives the second power supply voltage (VCC2) and the second excess voltage (ΔV2). When a square wave is input from the oscillator (232b), the charge pump (233b) performs an operation. Accordingly, the charge pump (233b) receives a voltage (VCC2+ΔV2) corresponding to the sum of the second power supply voltage (VCC2) and the second excess voltage (ΔV2) as the second control voltage (V C2 ) output as . In other words, the charge pump (233b) outputs the power terminal voltage (VT) as the second reference voltage (V REF2 The charge pumping operation continues until it reaches ). The charge pump (233b) uses the square wave input from the oscillator (232b) to obtain the second control voltage (V C2 The specific method for generating ) is known to those skilled in the art to which the present invention belongs, so a specific description is omitted.

[0074] Here, the second control voltage (V C2 The relationship between ) and the second power supply voltage (VCC2) can satisfy the following mathematical equation 2.

[0075]

[0076] As shown in Equation 2, the second control voltage (VC2 ) can be set to a voltage higher than the second power supply voltage (VCC2) by the second excess voltage (ΔV2). The second control voltage (V C2 Since ) is the voltage used to switch the second switch (SW2), the second switch (SW2) can be sufficiently turned on or off. For example, if the second switch (SW2) is implemented as an n-type transistor, the second switching driving signal (V SW2 The voltage of ) must be set higher than the second power supply voltage (VCC2) so that the second switch (SW2) can sufficiently perform a turn-on operation. And when the second switch (SW2) is implemented as a p-type transistor, the second switching driving signal (V SW2 The voltage of ) must be set higher than the second power supply voltage (VCC1) so that the second switch (SW2) can sufficiently perform a turn-off operation. Accordingly, the second control voltage generating unit (230b) according to the embodiment generates a second control voltage (VC2) higher than the second power supply voltage (VCC2) and outputs it to the switch controller (220).

[0077] FIG. 7 is a diagram showing the internal configuration of a switch circuit (210) and the internal configuration of a switch controller (220) according to one embodiment.

[0078] As shown in FIG. 7, the switch controller (220) may include a logic circuit (221) and a buffer circuit (222).

[0079] The logic circuit (221) receives external bit signals (bit1, bit2) and, in response to the bit signals (bit1, bit2), receives a logic signal (V LOG1 , V LOG2 Generates and outputs the first bit signal (bit1) and the first logic signal (V LOG1 ) is used to control the first switch (SW1), and the second bit signal (bit2) and the second logic signal (V LOG2 ) is used to control the second switch (SW2).

[0080] FIG. 8 is a diagram showing a logic circuit (221) according to one embodiment.

[0081] As shown in FIG. 8, a logic circuit (221) according to one embodiment may include a first NAND gate (810), a second NAND gate (820), and a third NAND gate (830).

[0082] The first NAND gate (810) receives the first bit signal (bit1) and the second bit signal (bit2) as inputs. The second NAND gate (820) receives the first bit signal (bit1) and the output of the first NAND gate (810) as inputs, and the first logic signal (V LOG1 It outputs ). And, the third NAND gate (830) receives the second bit signal (bit2) and the output of the first NAND gate (810) as inputs, and the second logic signal (V LOG2 Prints ).

[0083] FIG. 9 shows the input / output logic table of the logic circuit (221) of FIG. 8.

[0084] As shown in FIG. 9, the logic circuit (221) can generate and output four states corresponding to two bit signals. The first logic signal (V LOG1 When ) is 1, it means a High level, in which case the first switch (SW1) can be turned off. And the first logic signal (V LOG1 When ) is 0, it means a low level, in which case the first switch (SW1) can be turned on. Accordingly, the first and second logic signals (V LOG1 , V LOG2 At the high level of ), the first and second switches (SW1, SW2) are turned off, and the first and second logic signals (V LOG1 , V LOG2At the low level of ), the first and second switches (SW1, SW2) are turned on. That is, at bit signal 01, the first logic signal (V LOG1 Since ) becomes a low level, the first switch (SW1) is turned on. And at bit signal 10, the second logic signal (V LOG2 Since ) becomes a low level, the second switch (SW2) is turned on. In the remaining cases, the first and second logic signals (V LOG1 , V LOG2 Since ) becomes a High level, both the first and second switches (SW1, SW2) are turned off.

[0085] The buffer circuit (222) receives the first and second logic signals (V) from the logic circuit (221). LOG1 , V LOG2 It receives ) as input, and the switching drive signal (V SW1 , V SW2 It can generate and output ). The buffer circuit (222) can generate and output the first logic signal (V LOG1 ) is the first switching driving signal (V SW1 Converts to ) and the second logic signal (V LOG2 ) is the second switching drive signal (V SW2 Converts to ). The first logic signal (V LOG1 ) and the second logic signal (V LOG2 Since ) is a logic signal, the current level is low. Accordingly, the buffer circuit (222) is the first logic signal (V LOG1 ) and the second logic signal (V LOG2 ) each are first switching driving signals (V) with a high current level SW1 ) and the second switching drive signal (V SW2 It converts to ). Meanwhile, the buffer circuit (222) may further include a level shifter circuit in addition to the buffer to increase the voltage level as well as the current level. According to one embodiment, the buffer circuit (222) receives a first control voltage (V) from the control voltage generator (230). C1It receives ) as input, and the first control voltage (V C1 Using ), the first switching driving signal (V SW1 Generates the first switching drive signal (V SW1 When ) has a high voltage level, the first switching driving signal (V SW1 ) is the first control voltage (V C1 ) may be. And the buffer circuit (222) receives the second control voltage (V) from the control voltage generator (230). C2 It receives ) as input, and the second control voltage (V C2 Using ), the second switching driving signal (V SW2 Generates the second switching drive signal (V SW2 When ) has a high voltage level, the second switching driving signal (V SW2 ) is the second control voltage (V C2 ) may be. When the first and second switches (SW1, SW2) are implemented as n-type transistors, the buffer circuit (222) is an ON driving signal, and the first and second control voltages (V C1 , V C2 The first and second switching driving signals (V) each having ) SW1 , V SW2 It can output ). In this case, the first and second switches (SW1, SW2) are turned on. When the first and second switches (SW1, SW2) are implemented as p-type transistors, the buffer circuit (222) uses the first and second control voltages (V) as an OFF driving signal. C1 , V C2 The first and second switching driving signals (V) each having ) SW1 , V SW2 ) can output. In this case, the first and second switches (SW1, SW2) are turned off. The buffer circuit (222) outputs the first and second control voltages (V C1 , V C2 Using ), the first and second switching driving signals (V SW1 , V SW2The method of generating ) is known to those skilled in the art to which the present invention belongs, so a specific description is omitted.

[0086] As shown in FIG. 7, in the switch circuit (210), the first and second switches (SW1, SW2) can each be implemented as transistors (211, 212). As one example, the transistor (211) can be implemented as an n-type or p-type Field Effect Transistor (FET), and the second transistor (212) can also be implemented as an n-type or p-type FET.

[0087] The first terminal of the transistor (211) is connected to the first power circuit (100a) to receive the first power voltage (VCC1), and the second terminal of the transistor (211) is connected to the power terminal (T_VCC). The control terminal of the transistor (211) receives the first switching driving signal (V) from the buffer circuit (222). SW1 ) is received as input. The first terminal of the transistor (212) is connected to the second power circuit (100b) to receive the second power voltage (VCC2) as input (supply), and the second terminal of the transistor (212) is connected to the power terminal (T_VCC). The control terminal of the transistor (212) receives the second switching drive signal (V) from the buffer circuit (222). SW2 Receives ) as input.

[0088] When the transistor (211) is an n-type transistor, for turning on the transistor (211), the buffer circuit (220) provides a first switching drive signal (V SW1 As the first control voltage (V C1 ) can output. And if the transistor (212) is an n-type transistor, for turning on the transistor (212), the buffer circuit (220) can output a second switching drive signal (V SW2 As the second control voltage (V C2It can output ). Through this, the n-type transistors (211, 212) can be sufficiently turned ON. If the control voltage of the n-type transistors (211, 212) is lower than the voltage of the first terminal or the voltage of the second terminal, the n-type transistors (211, 212) operate in the turn-off region, and the ON resistance may increase. To solve this problem, the control voltage generator (230) provides first and second control voltages (V1, V2) that are each higher than the first and second power supply voltages (VCC1, VCC2). C1 , V C2 ) generates. The buffer circuit (222) generates the first and second control voltages (V C1 , V C2 ) is generated as the control voltage of each n-type transistor (211, 212). That is, the first control voltage (V C1 ) may be the ON control voltage of the n-type transistor (211), and the second control voltage (V C2 ) can be the ON control voltage of the n-type transistor (212).

[0089] When the transistor (211) is a p-type transistor, for turning off the transistor (211), the buffer circuit (220) provides a first switching drive signal (V SW1 As the first control voltage (V C1 ) can output. And if the transistor (212) is a p-type transistor, for turning off the transistor (212), the buffer circuit (220) can output a second switching drive signal (V SW2 As the second control voltage (V C2It can output ). Through this, the p-type transistors (211, 212) can be sufficiently turned off. If the control voltage of the p-type transistors (211, 212) is lower than the voltage of the first terminal or the voltage of the second terminal, the p-type transistors (211, 212) are not sufficiently turned off, and leakage current may occur. To solve this problem, the control voltage generator (230) provides first and second control voltages (V1, V2) that are each higher than the first and second power supply voltages (VCC1, VCC2). C1 , V C2 ) generates. The buffer circuit (222) generates the first and second control voltages (V C1 , V C2 ) is generated as the control voltage of each p-type transistor (211, 212). That is, the first control voltage (V C1 ) may be the OFF control voltage of the p-type transistor (211), and the second control voltage (V C2 ) can be the OFF control voltage of the p-type transistor (212).

[0090] Although embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements by those skilled in the art using the basic concept of the present invention as defined in the following claims also fall within the scope of the present invention. Explanation of the symbols

[0091] 1000: Transmitter system 100a: First power circuit 100b: Second power circuit 200: Power switch circuit 300: Power amplifier 210: Switch circuit 220: Switch controller 230: Control voltage generator 221: Logic Circuit 222: Buffer circuit

Claims

Claim 1 A power switch circuit comprising: a first switch for switching to supply a first power supply voltage to a power terminal of a power amplifier; a control voltage generator for comparing a first voltage, which is a voltage at the power terminal, with a predetermined first reference voltage and generating a first control voltage higher than the first power supply voltage in response to the comparison result; and a switch controller for generating a switching driving signal to control the first switch using the first control voltage. Claim 2 A power switch circuit according to claim 1, further comprising a second switch for switching the supply of a second power supply voltage to the power terminal, wherein the control voltage generator compares the first voltage with a predetermined second reference voltage and generates a second control voltage higher than the second power supply voltage in response to the comparison result, and the switch controller generates a switching driving signal for controlling the second switch using the second control voltage. Claim 3 In claim 1, the control voltage generator comprises a power switch circuit including a comparator that compares the first voltage and the first reference voltage, an oscillator that generates a waveform corresponding to the output of the comparator, and a charge pump that receives the first power supply voltage and a predetermined second voltage as inputs and operates through the waveform to generate the first control voltage. Claim 4 In paragraph 3, the first control voltage is a power switch circuit corresponding to the sum of the first power supply voltage and the second voltage. Claim 5 In paragraph 3, the charge pump is a power switch circuit that performs a charge pumping operation until the first voltage becomes the first reference voltage. Claim 6 In claim 1, the switch controller comprises a power switch circuit including a buffer circuit that receives the first control voltage and generates the switching driving signal having the first control voltage. Claim 7 In claim 1, the first power supply voltage is a power switch circuit that varies according to the envelope of an RF (Radio Frequency) signal input to the power amplifier. Claim 8 A power switch circuit according to paragraph 2, wherein the first reference voltage is a voltage lower than the first power supply voltage, and the second reference voltage is a voltage lower than the second power supply voltage. Claim 9 A power switch circuit comprising: a first switch connected between a first power circuit outputting a first voltage and a power terminal of a power amplifier; a second switch connected between a second power circuit outputting a second voltage and the power terminal; a control voltage generator that generates a first control voltage higher than the first voltage and a second control voltage higher than the second voltage using a voltage at the power terminal, the first voltage, and the second voltage; and a switch controller that generates a first switching driving signal for controlling the first switch using the first control voltage and a second switching driving signal for controlling the second switch using the second control voltage. Claim 10 In claim 9, the power switch circuit comprises a first control voltage generator that generates the first control voltage using the voltage of the power terminal, the first voltage, and a predetermined first reference voltage, and a second control voltage generator that generates the second control voltage using the voltage of the power terminal, the second voltage, and a predetermined second reference voltage. Claim 11 In claim 10, the first control voltage generator comprises a power switch circuit including a first comparator that compares the voltage of the power terminal with the first reference voltage, a first oscillator that generates a waveform in response to the output of the first comparator, and a first charge pump that receives the first voltage and a predetermined third voltage and operates in response to the output of the first oscillator to generate the first control voltage. Claim 12 In claim 11, the second control voltage generator comprises a second comparator that compares the voltage of the power terminal with the second reference voltage, a second oscillator that generates a waveform in response to the output of the second comparator, and a second charge pump that receives the second voltage and a predetermined fourth voltage as inputs and operates in response to the output of the second oscillator to generate the second control voltage, thereby forming a power switch circuit. Claim 13 In claim 12, the power switch circuit wherein the first control voltage corresponds to the sum of the first voltage and the third voltage, and the second control voltage corresponds to the sum of the second voltage and the fourth voltage. Claim 14 In claim 12, the power switch circuit wherein the first charge pump performs a charge pumping operation until the voltage of the power terminal becomes the first reference voltage, and the second charge pump performs a charge pumping operation until the voltage of the power terminal becomes the second reference voltage. Claim 15 In claim 9, the power switch circuit comprises a buffer circuit that receives the first control voltage and the second control voltage as inputs and generates the first switching driving signal having the first control voltage and the second switching driving signal having the second control voltage. Claim 16 In claim 9, the first and second voltages are power switch circuits that vary according to the envelope of the RF (Radio Frequency) signal input to the power amplifier. Claim 17 A power switch circuit according to claim 10, wherein the first reference voltage is a voltage lower than the first voltage, and the second reference voltage is a voltage lower than the second voltage.

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